Wired communication receiver with dc level displacement

Abstract

The invention relates to a wired communication receiver with DC level displacement. A receiver for wired communication includes a DC level shift circuit and an analog-to-digital converter circuit. The DC level shift circuit receives the first signal and generates a second signal. The direct current level shift circuit comprises a capacitor, and the direct current level shift circuit transmits a first common mode voltage in a first voltage domain to a first end of the capacitor and transmits a second common mode voltage in a second voltage domain to a second end of the capacitor before receiving the first signal. The DC level shift circuit stops transmitting the first common-mode voltage and the second common-mode voltage to the capacitor. The analog-to-digital converter circuit generates a digital signal according to the second signal.

Description

Technical Field

[0001] The present invention relates to a receiver, and more particularly to a receiver that utilizes passive circuits to perform DC level shifting. Background Art

[0002] In applications related to wired communication, the transmitter and receiver in the electronic device will send and receive data through the same endpoint. In order to increase the connection distance, the transmitter usually uses higher power to send data, which increases the overall power consumption. In the prior art, circuits such as source followers are usually used to perform level conversion to reduce the signal level processed by the receiver, thereby reducing the overall power consumption. However, in actual applications, the multiple active components in the source follower will still introduce additional power consumption, and the mismatch between these active components will cause nonlinear distortion to the output of the source follower. Summary of the invention

[0003] In some implementations, one of the purposes of the present invention is (but not limited to) to provide a receiver that can utilize a passive circuit to implement a DC level shift, so as to improve the deficiencies of the prior art.

[0004] In some embodiments, the receiver includes a DC level shift circuit and an analog-to-digital converter circuit. The DC level shift circuit is used to receive a first signal and generate a second signal. The DC level shift circuit includes a capacitor, and the DC level shift circuit is also used to transmit a first common-mode voltage in a first voltage domain to a first end of the capacitor and transmit a second common-mode voltage in a second voltage domain to a second end of the capacitor before receiving the first signal, and when the DC level shift circuit receives the first signal, the DC level shift circuit stops transmitting the first common-mode voltage and the second common-mode voltage to the capacitor. The analog-to-digital converter circuit is used to generate a digital signal according to the second signal.

[0005] The features, implementation and efficacy of the present invention are described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic diagram of a communication system is drawn according to some embodiments of the present invention;

[0007] Figure 2A According to some embodiments of the present invention, Figure 1 A schematic diagram of a DC level shifting circuit in FIG.

[0008] Figure 2B According to some embodiments of the present invention, Figure 2A A schematic diagram of waveforms of multiple control signals in FIG.

[0009] Figure 3A According to some embodiments of the present invention, Figure 1 A schematic diagram of a DC level shift circuit and an analog-to-digital converter circuit in FIG. 1 ; and

[0010] Figure 3B According to some embodiments of the present invention, Figure 3A Schematic diagram of waveforms of multiple control signals in . DETAILED DESCRIPTION

[0011] All words used herein have their usual meanings. The definitions of the above words in commonly used dictionaries and the use examples of any of the words discussed herein in the content of this case are only examples and should not limit the scope and meaning of this case. Similarly, this case is not limited to the various embodiments shown in this specification.

[0012] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuit" may be a device composed of at least one transistor and / or at least one active and passive element connected in a certain manner to process signals.

[0013] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. In this article, the words first, second, third, etc. are used to describe and distinguish each element. Therefore, the first element in this article can also be called the second element without departing from the original intention of the case. For ease of understanding, similar elements in the various drawings will be designated with the same reference numerals.

[0014] Figure 1 A schematic diagram of a communication system 100 is drawn according to some embodiments of the present invention. In some embodiments, the communication system 100 can be applied to a wired communication, such as an Ethernet system, but the present invention is not limited thereto. The communication system 100 includes a transmitter 110 and a receiver 120. The transmitter 110 can output a data signal SD1 to other devices (not shown) through an endpoint 101 through a network cable (not shown). The receiver 120 can receive a data signal SD2 from other devices through the same endpoint 101 through the same network cable. In some embodiments, the data signal SD1 and the data signal SD2 can be, but are not limited to, signals transmitted by an Ethernet network, and are transmitted through a network cable having a plurality of twisted-pair cables.

[0015] In some embodiments, the receiver 120 includes a hybrid circuit 122, a filter circuit 124, a DC (direct current) level shift circuit 126, and an analog-to-digital converter circuit 128. The hybrid circuit 122 is used to receive the data signal SD2 and generate a signal S1 accordingly. In some embodiments, the hybrid circuit 122 can be used to eliminate the echo caused by the transmitter 110. For example, the hybrid circuit 122 can include a first resistor and a second resistor (not shown). The first resistor can convert the signal on the terminal 101 into a first current signal, and the second resistor can convert the signal on the negative output terminal of the transmitter 110 into a second current signal. By setting the resistance values ​​of the first resistor and the second resistor, the first current signal and the second current signal can be offset at the input terminal of the filter circuit 124, thereby reducing the influence of the echo on the data signal SD2 and generating the signal S1 accordingly. The above configuration method of the hybrid circuit 122 is used for example, and the present case is not limited thereto.

[0016] The filter circuit 124 generates a signal S2 according to the signal S1. For example, the filter circuit 124 may perform a low pass filter on the signal S1 to generate the signal S2. The DC level shift circuit 126 is used to receive the signal S2 and generate the signal S3. In some embodiments, in order to be applicable to data transmission over a longer distance, the transmitter 110 transmits the data signal SD1 at a higher power. For example, the transmitter 110 operates in a first voltage domain, wherein the highest voltage in the first voltage domain may be approximately, but not limited to, 3.3 volts. Under this condition, in order to process the echo from the transmitter 110, the mixing circuit 122 and the filter circuit 124 also operate in the first voltage domain. In order to reduce the overall power consumption of the receiver 120, other circuits of the receiver 120 may operate in a lower second voltage domain, wherein the highest voltage in the second voltage domain (which is lower than the highest voltage in the first voltage domain) may be approximately, but not limited to, 0.9 volts.

[0017] The DC level shift circuit 126 receives the signal S2 and generates a signal S3. In some embodiments, the DC level shift circuit 126 can adjust the common mode level of the signal S2 to generate the signal S3. In some embodiments, the DC level shift circuit 126 can be a passive circuit. In some embodiments, the passive circuit can be a circuit that does not provide a voltage gain. For example, the DC level shift circuit 126 can include a capacitor (e.g., Figure 2A or Figure 3AThe DC level shift circuit 126 includes a capacitor C) and several switches, wherein the switches are used to transmit (or transfer) signals without amplifying the transmitted signals. Before receiving the signal S2, the DC level shift circuit 126 transmits the common mode voltage VCM1 of the first voltage domain to the first end of the aforementioned capacitor, and transmits the common mode voltage VCM2 of the second voltage domain to the second end of the aforementioned capacitor. When the DC level shift circuit 126 receives the signal S2, the DC level shift circuit 126 stops transmitting the common mode voltage VCM1 and the common mode voltage VCM2 to the capacitor. In some embodiments, the common mode voltage VCM1 may be higher than the common mode voltage VCM2, but the present case is not limited to this. For example, as mentioned above, the highest voltage of the first voltage domain may be approximately 3.3 volts, and the highest voltage of the second voltage domain may be approximately 0.9 volts. Under this condition, the common mode voltage VCM1 may be approximately 1.65 volts, and the common mode voltage VCM2 may be approximately 0.5 volts. The voltage values ​​mentioned above are only for example, and the present case is not limited to this. The analog-to-digital converter circuit 128 is used to convert the signal S3 into a digital signal SD3, and provide the digital signal SD3 to a digital circuit (not shown) in the system for subsequent signal processing. In some embodiments, the analog-to-digital converter circuit 128 can be various types of analog-to-digital converter circuits, such as, but not limited to, a successive approximation register (SAR) analog-to-digital converter circuit.

[0018] In some related technologies, a source follower is disposed in a receiver to perform a level shift of a signal. However, the source follower is an active circuit that provides voltage gain, which generates additional power consumption and nonlinear distortion. Compared to the above technology, in some embodiments of the present case, the DC level shift circuit 126 is a passive circuit, which can have lower power consumption and reduce the impact of nonlinear distortion.

[0019] Figure 2A According to some embodiments of the present invention, Figure 1Schematic diagram of the DC level shifting circuit 126 in FIG. In some embodiments, the DC level shifting circuit 126 includes a capacitor C, a switch 201, a switch 202, a switch 203, and a switch 204. A first end of the switch 201 receives a signal S2, a second end of the switch 201 is coupled to the first end of the capacitor C, and a control end of the switch 201 receives a control signal CKS. A first end of the switch 202 is coupled to the first end of the capacitor C, a second end of the switch 202 receives a common mode voltage VCM1, and a control end of the switch 202 receives a control signal CKR. A first end of the switch 203 is coupled to the second end of the capacitor C to receive a signal S3, a second end of the switch 203 is used to output the signal S3, and a control end of the switch 203 receives the control signal CKS. A first end of the switch 204 is coupled to the second end of the capacitor C, a second end of the switch 204 receives the common mode voltage VCM2, and a control end of the switch 204 receives the control signal CKR.

[0020] By means of the above configuration, the switch 201 can be turned on according to the control signal CKS to transmit the signal S2 to the first end of the capacitor C. The switch 202 can be turned on according to the control signal CKR to transmit the common mode voltage VCM1 to the first end of the capacitor C. The switch 203 can be turned on according to the control signal CKS to output the signal S3 from the second end of the capacitor C to the Figure 1 The switch 204 can be turned on according to the control signal CKR to transmit the common mode voltage VCM2 to the second end of the capacitor C.

[0021] Figure 2B According to some embodiments of the present invention, Figure 2ASchematic diagram of the waveforms of the control signal CKS and the control signal CKR in . In some embodiments, the phases of the control signal CKS and the control signal CKR are opposite to each other. For example, during period T1, the control signal CKR has an enable level (for example, but not limited to, a high level), and the control signal CKS has a disable level (for example, but not limited to, a low level). Under this condition, the switch 201 and the switch 203 are not turned on according to the control signal CKS, and the switch 202 and the switch 204 are turned on according to the control signal CKR, thereby transmitting the common mode voltage VCM1 and the common mode voltage VCM2 to the first end and the second end of the capacitor C respectively. In this way, the levels of the first end and the second end of the capacitor C will be the common mode voltage VCM1 and the common mode voltage VCM2 respectively during period T1. During period T2, the control signal CKR is switched to the disable level, and the control signal CKS is switched to the enable level. Under this condition, switch 202 and switch 204 are not conducting according to the control signal CKR, thereby stopping the transmission of the common-mode voltage VCM1 and the common-mode voltage VCM2 to the capacitor C. On the other hand, switch 201 and switch 203 can be turned on according to the control signal CKS. Switch 201 can transmit signal S2 to the first end of capacitor C during period T2. In some embodiments, the common-mode level of signal S2 is set to be the same as the common-mode voltage VCM1, so that the DC level difference between the first end and the second end of capacitor C does not change during period T2. In this way, the circuit behavior of capacitor C during period T2 is equivalent to a battery, so that capacitor C can transmit the AC component in signal S2 to the second end of capacitor C. This AC component can be superimposed on the level on the second end of capacitor C (i.e., the common-mode voltage VCM2) to form a signal S3, and switch 203 can output signal S3 to Figure 1 Analog-to-digital converter circuit 128 .

[0022] In other words, before the DC level shifting circuit 126 receives the signal S2 (i.e., before the switch 201 and the switch 203 are turned on), the switch 202 and the switch 204 are turned on to reset the first end and the second end of the capacitor C to the common mode voltage VCM1 and the common mode voltage VCM2, respectively. After the DC level shifting circuit 126 starts to receive the signal S2 (i.e., when the switch 201 and the switch 203 are turned on), the switch 202 and the switch 204 are turned off to stop transmitting the common mode voltage VCM1 and the common mode voltage VCM2 to the capacitor C. In this way, by means of the device characteristics of the capacitor C, the level shifting can be completed without using an active circuit. In some embodiments, since the switch 201 and the switch 202 process the signal of the first voltage domain (e.g., the signal S2 and the common mode voltage VCM1), and the signal of the first voltage domain has a higher voltage level, each of the switch 201 and the switch 202 can be implemented by an input / output (I / O) transistor with a higher withstand voltage. In some embodiments, since the switch 203 and the switch 204 process signals in the second voltage domain (e.g., the signal S3 and the common mode voltage VCM2), and the signals in the second voltage domain have a lower voltage level, each of the switch 203 and the switch 204 can be implemented by a core transistor suitable for a low voltage environment. Figure 1 The analog-to-digital converter circuit 128 processes the signal S3 in the second voltage domain. At least a portion of the circuit in the analog-to-digital converter circuit 128 may also be implemented by core transistors to reduce overall power consumption.

[0023] Figure 3A According to some embodiments of the present invention, Figure 1 Schematic diagram of the DC level shift circuit 126 and the analog-to-digital converter circuit 128 in FIG. In this example, the analog-to-digital converter circuit 128 may be a SAR analog-to-digital converter circuit, which includes a sampling switch 301, a capacitor array circuit 302, a comparator circuit 303, and a control logic circuit 304.

[0024] The sampling switch 301 can be turned on according to the control signal CKS to transmit the signal S2 to the capacitor array circuit 302. In other words, the capacitor array circuit 302 can sample the signal S2 according to the control signal CKS. The capacitor array circuit 302 includes a plurality of capacitors (not shown) and a plurality of switches (not shown), wherein the plurality of switches can be controlled by the control logic circuit 304 to selectively transmit the reference voltage VREF or the ground voltage GND to the capacitors. The DC level shift circuit 126 can transmit the signal S2 (hereinafter referred to as the signal S2') sampled by the capacitor array circuit 302 to the first end of the capacitor C according to the control signal CKC to generate the signal S3. The comparator circuit 303 can receive the signal S3 from the DC level shift circuit 126 to generate the decision signal SD. The control logic circuit 304 can execute the SAR algorithm according to the decision signal SD to sequentially switch the plurality of switches in the capacitor array circuit 302 and sequentially generate the plurality of bits in the digital signal SD3.

[0025] The DC level shift circuit 126 includes a capacitor C, a switch 311, a switch 312, and a switch 313. A first end of the switch 311 is coupled to the capacitor array circuit 302 to receive the signal S2', a second end of the switch 311 is coupled to the first end of the capacitor C, and a control end of the switch 311 receives a control signal CKC. A first end of the switch 312 is coupled to the first end of the capacitor C, a second end of the switch 312 receives a common mode voltage VCM1, and a control end of the switch 312 receives a control signal CKS. A first end of the switch 313 is coupled to the second end of the capacitor C, a second end of the switch 313 receives a common mode voltage VCM2, and a control end of the switch 313 receives a control signal CKS. In some embodiments, to avoid affecting the operation of the analog-to-digital converter circuit 128, the capacitance value of the capacitor C may be set to be greater than the capacitance value of the capacitor array circuit 302 (e.g., Figure 3A For example, the capacitance of the capacitor C may be set to be greater than or equal to 1.5 times the capacitance of the capacitor array circuit 302, but the present invention is not limited thereto.

[0026] By the above configuration, the switch 311 can be turned on according to the control signal CKC to transmit the signal S2' to the first end of the capacitor C. The switch 312 can be turned on according to the control signal CKS to transmit the common mode voltage VCM1 to the first end of the capacitor C. The switch 313 can be turned on according to the control signal CKS to transmit the common mode voltage VCM2 to the second end of the capacitor C.

[0027] Figure 3B According to some embodiments of the present invention, Figure 3ASchematic diagram of the waveforms of the control signal CKS and the control signal CKC in FIG. In some embodiments, the phases of the control signal CKS and the control signal CKC are opposite to each other. For example, during period T1, the control signal CKS has an enable level (for example, but not limited to, a high level), and the control signal CKC has a disable level (for example, but not limited to, a low level). Under this condition, the switch 311 is not turned on according to the control signal CKC, and the sampling switch 301, the switch 312 and the switch 313 are turned on according to the control signal CKS. Under this condition, the capacitor array circuit 302 can sample the signal S2 to generate the signal S2', and the switch 312 and the switch 313 can transmit the common mode voltage VCM1 and the common mode voltage VCM2 to the first end and the second end of the capacitor C, respectively. In this way, the levels of the first end and the second end of the capacitor C will be the common mode voltage VCM1 and the common mode voltage VCM2, respectively, during period T1. During period T2, the control signal CKS is switched to the disable level, and the control signal CKC is switched to the enable level. Under this condition, the sampling switch 301, the switch 312 and the switch 313 are turned off according to the control signal CKS, thereby stopping the transmission of the signal S2 to the capacitor array circuit 302 and stopping the transmission of the common mode voltage VCM1 and the common mode voltage VCM2 to the first end and the second end of the capacitor C. On the other hand, the switch 311 is turned on according to the control signal CKC to transmit the signal S2' to the first end of the capacitor C. Based on the same Figure 2B The capacitor C can generate a signal S3 and transmit the signal S3 to the comparator circuit 303. Thus, the control logic circuit 304 can generate a digital signal SD3 according to the decision signal SD provided by the comparator circuit 303.

[0028] In other words, before the DC level shift circuit 126 receives the signal S2′ (i.e., when the switch 311 is not turned on), the switch 312 and the switch 313 are turned on to reset the first end and the second end of the capacitor C to the common mode voltage VCM1 and the common mode voltage VCM2, respectively. After the DC level shift circuit 126 starts to receive the signal S2′ (i.e., when the switch 311 is turned on), the switch 312 and the switch 313 are turned off to stop transmitting the common mode voltage VCM1 and the common mode voltage VCM2 to the capacitor C. In some embodiments, since the sampling switch 301, the plurality of switches in the capacitor array circuit 302, the switch 311, and the switch 312 process signals in the first voltage domain (e.g., the signal S2, the signal S2′, and the common mode voltage VCM1), each of the sampling switch 301, the plurality of switches in the capacitor array circuit 302, the switch 311, and the switch 312 can be implemented by the aforementioned input / output (I / O) transistors. In some embodiments, since the switch 313, the comparator circuit 303 and the control logic circuit 304 process signals of the second voltage domain (e.g., the signal S3, the common mode voltage VCM2 and the decision signal SD), each of the switch 313, the comparator circuit 303 and the control logic circuit 304 can be implemented by the aforementioned core transistors, thereby reducing more power consumption.

[0029] In summary, the receiver provided in some embodiments of the present invention can utilize passive circuits to perform DC level shifting to reduce the impact of nonlinear distortion and reduce power consumption.

[0030] Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. Those with ordinary knowledge in the technical field may make changes to the technical features of the present case based on the explicit or implicit contents of the present case. All these changes may fall within the scope of patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be subject to the scope of the patent application defined in this specification.

[0031]

Explanation of symbols

[0032] 100: Communication System

[0033] 101: Endpoint

[0034] 110: Transmitter

[0035] 120: Receiver

[0036] 122: Hybrid Circuit

[0037] 124:Filter circuit

[0038] 126: DC level shift circuit

[0039] 128:Analog-to-digital converter circuit

[0040] 201~204: switch

[0041] 301: Sampling switch

[0042] 302: Capacitor array circuit

[0043] 303: Comparator circuit

[0044] 304: Control logic circuit

[0045] 311~313: Switch

[0046] C: Capacitor

[0047] CKC, CKR, CKS: control signal

[0048] Ceq: equivalent capacitance value

[0049] GND: Ground voltage

[0050] S1~S3,S2':Signal

[0051] SD: Decision Signal

[0052] SD1, SD2: data signal

[0053] SD3: Digital signal

[0054] T1,T2: Period

[0055] VCM1, VCM2: common mode voltage

[0056] VREF: reference voltage.

Claims

1. A receiver for wired communication, comprising: A DC level shift circuit is used to receive a first signal and generate a second signal. The DC level shift circuit includes a capacitor, and the DC level shift circuit is further used to transmit a first common mode voltage in a first voltage domain to a first end of the capacitor and transmit a second common mode voltage in a second voltage domain to a second end of the capacitor before receiving the first signal, and when the DC level shift circuit receives the first signal, the DC level shift circuit stops transmitting the first common mode voltage and the second common mode voltage to the capacitor; and An analog-to-digital converter circuit is used to generate a digital signal according to the second signal.

2. The receiver for wired communication as claimed in claim 1, wherein the DC level shifting circuit further comprises: a first switch, configured to be turned on according to a first control signal to transmit the first signal to the first end of the capacitor; a second switch, configured to be turned on according to a second control signal to transmit the first common mode voltage to the first end of the capacitor; a third switch, configured to be turned on according to the first control signal to output the second signal from the second end of the capacitor; and a fourth switch, configured to be turned on according to the second control signal to transmit the second common mode voltage to the first end of the capacitor.

3. The receiver for wired communication as claimed in claim 2, wherein each of the first switch and the second switch is implemented by an input-output transistor, and each of the third switch and the fourth switch is implemented by a core transistor.

4. The receiver for wired communication as claimed in claim 1, wherein the DC level shifting circuit is a passive circuit. 5 . The receiver for wired communication as claimed in claim 1 , wherein a highest voltage in the first voltage domain is higher than a highest voltage in the second voltage domain. 6 . The receiver for wired communication as claimed in claim 1 , wherein the first common mode voltage is higher than the second common mode voltage.

7. A receiver for wired communication as described in claim 1, wherein the analog-to-digital converter circuit includes a capacitor array circuit, the capacitor array circuit samples the first signal according to a first control signal, and the DC level shift circuit is used to transmit the first signal sampled by the capacitor array circuit to the first end of the capacitor according to a second control signal to generate the second signal.

8. The receiver for wired communication as claimed in claim 7, wherein the DC level shifting circuit further comprises: a first switch, configured to be turned on according to the second control signal to transmit the sampled first signal to the first end of the capacitor; a second switch, configured to be turned on according to the first control signal to transmit the first common mode voltage to the first end of the capacitor; and A third switch is configured to be turned on according to the first control signal to transmit the second common mode voltage to the second end of the capacitor.

9. The receiver for wired communication according to claim 1, further comprising: A filter circuit is used to generate the first signal according to a third signal.

10. The receiver for wired communication according to claim 9, further comprising: A mixing circuit is used for receiving a data signal and eliminating an echo caused by a transmitter to generate the third signal.

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