Device based on multi-level signal vertical interconnection

Abstract

The invention provides a device based on multi-level signal vertical interconnection. The device realizes signal vertical interconnection among multiple layers of subsystem board cards through fuzz button type connectors. According to the use requirements of different types of signals such as power supply, radio frequency, data, control and the like in each functional module in the assembly, the cascade architecture is divided into seven layers in total according to the sequence from the rear end to the antenna, and the different layers are vertically coupled and crimped by mainly utilizing welding-free fuzz button connectors of vibrating needles on the two sides to be matched with structural members. A traditional signal link plane sequential connection mode is converted into a vertical interconnection mode in a three-dimensional space, the vertical space above the corresponding connector area is fully utilized for hardware layout, the system channel integration degree is remarkably improved, and the design requirements of a light, thin and small array plane system are met.

Description

Technical Field

[0001] The present application relates to the technical field of active phased arrays, and in particular to a device based on multi-level vertical signal interconnection. Background Art

[0002] The connection of RF, power supply, data and other signals in the front-end components of traditional phased array equipment is completed by various types of cables and matching connectors. This planar series connection method is relatively stable, but it occupies a large space and is difficult to adapt to the high-density integration requirements of the future array channel scale becoming larger and larger, the number of connections increasing, and the module size becoming smaller and smaller.

[0003] To this end, it is necessary to adopt a three-dimensional vertical mutual understanding signal transmission method to reduce the overall spatial size of the link. This is also the difficulty and trend in the development of thin and lightweight phased array RF systems. Summary of the invention

[0004] The present application provides a device based on multi-level signal vertical interconnection, which can be used to solve the technical problem of large overall space of the current transmission mode link.

[0005] The present application provides a device based on multi-level signal vertical interconnection, the device comprising:

[0006] The device is divided into 7 layers in order from the back end to the antenna. Layer 1 is the back cover, which is responsible for the power supply, clock, and data transmission of the module; Layer 2 is the optical module layer, which is used to convert the high-speed electrical signal in the module into a high-speed optical signal; Layer 3 is the power supply layer, which is used to supply power to multiple types of power supplies in the digital subsystem; Layer 4 is the digital subsystem layer, and the main chip is used for digital-analog sampling and wave control instruction generation; Layer 5 is the balun layer, which is mainly responsible for the conversion between intermediate frequency single-ended signals and differential signals; Layer 6 is the frequency conversion layer, and the frequency conversion subsystem is used to realize the conversion between RF signals and intermediate frequency signals; Layer 7 is the component layer, which is used to power the TR component and issue wave control instructions;

[0007] Different layers are connected vertically by solder-free button connectors with spring pins on both sides and structural parts.

[0008] Furthermore, the interconnection relationship between different layers is as follows:

[0009] Power supply between layer 1 and layer 7; power supply signal type: +28V; the interface area at layer 1 matches the component power supply pad; the interface area at layer 7 matches the rear cover power supply pad and is larger than other layers. Layer 1 and layer 7 are connected through the first connector; the height of the first connector is the structural connection length from layer 1 to layer 7, which can be segmented, and the number of connectors is 4;

[0010] Power is supplied between layer 1 and layer 6, and layer 1 and layer 6 are connected through a second connector; power supply signal types: +8V, +5V, -40V, -5V, +15V, +2.5V, single-core current does not exceed 5A, the number and type of pins at the two locations can be different, and they are in the form of a button distribution; the interface area at layer 1 matches the component power supply pad; the height of the second connector is the structural connection length from layer 1 to layer 6, the connector can be segmented, and the number of connectors is 2;

[0011] Signals are transmitted between layer 1 and layer 2, and layer 1 and layer 2 are connected through the fourth connector; power supply signal type: multi-core low-frequency signal, including single-ended, low-speed clock differential signal, with an isolation of not less than 70dB; the interface area at layer 1 matches the component power supply pad;

[0012] Power is supplied between layer 1 and layer 2; the power supply signal type is +8V; the interface area at layer 1 matches the component power supply pad; the interface area at layer 2 completely coincides with the projection position of the sixth connector when vertically interconnected, and a sequential crimping positioning and installation method is adopted;

[0013] An optical fiber interface is set between layer 1 and layer 2; the optical fiber interface is a standard MT interface, and a floating MT socket is installed on the rear cover in a blind-plug manner;

[0014] Power is supplied between layer 2 and layer 3, and layer 2 and layer 3 are connected through the sixth connector; power supply signal type: +8V; when vertically interconnected with the fourth connector, the projection position completely overlaps, and a sequential crimping positioning and installation method is adopted;

[0015] Signals are transmitted between layer 2 and layer 4, and layer 2 and layer 4 are connected through the seventh connector; multi-core TTL low-frequency signals, low-speed differential signals, and high-speed differential signals are used;

[0016] Power is supplied between layer 3 and layer 4, and layer 3 and layer 4 are connected through an eighth connector; power supply signal types include 0.85V, 0.85V, 0.9V, 0.925V, 1.2V, 1.8V, 2.5V, and 3.3V;

[0017] Layer 4 and layer 5 are mixed for transmission, and layer 4 and layer 5 are connected through the ninth connector; signal types include differential signal, single-ended control signal, and 3.3V power supply;

[0018] Signals are transmitted between layer 5 and layer 6, and layer 5 and layer 6 are connected through the tenth connector and the eleventh connector; the signal type includes TTL low-frequency signals, a total of two groups;

[0019] Signals transmitted between layer 5 and layer 6; Signal type: multi-core RF signal;

[0020] Layer 6 and layer 7 are mixed; Layer 6 and layer 7 are connected through the twelfth connector; Signal types are RF signal and single-ended control signal; The connector adopts a cross-shaped structure with elastic needles and buttons on both sides, the RF signal port is arranged in the center, and the 4 pins of the cross are arranged with single-ended signal ports; The entire twelfth connector is a whole without segmentation;

[0021] Signal transmission between layer 1 and layer 6; the signal type is RF signal, the interface area at layer 1 matches the component power supply pad to ensure the button crimping requirements, the connector height is the structural connection length from layer 1 to layer 6, and can be set to segment;

[0022] The rear cover plate completes the aggregation and spacing transformation of the button pads of some connectors in the module through the PCB board, and completes the crimping with the array motherboard through the single-sided welded button connector.

[0023] The present invention converts the traditional planar sequential connection mode of the signal link into a vertical interconnection mode in a three-dimensional space by using a solder-free button connector with spring pins on both sides, making full use of the vertical space above the corresponding connector area for hardware layout, significantly improving the system channel integration, and meeting the design requirements of a lightweight and miniaturized array system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of multi-layer vertical interconnection of modules within a system provided in an embodiment of the present application;

[0025] Figure 2 This is a schematic diagram of the structure of a cross-shaped mixed signal connector provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0027] The following first introduces the embodiments of the present application in conjunction with the accompanying drawings.

[0028] A device based on multi-level signal vertical interconnection, which realizes the vertical interconnection of signals between multi-layer subsystem boards through a button-shaped connector. According to the usage requirements of different types of signals such as power supply, RF, data, and control in each functional module within the component, the device is divided into 7 layers in order from the back end to the antenna, such as Figure 1As shown, layer 1 is the back cover, which is responsible for the transmission of the module's external power supply, clock, and data signals; layer 2 is the optical module layer, which is used to convert the high-speed electrical signal in the module into a high-speed optical signal; layer 3 is the power supply layer, which is used to power multiple types of power supplies for the digital subsystem; layer 4 is the digital subsystem layer, and the main chip is used for digital-analog sampling and wave control instruction generation; layer 5 is the balun layer, which is mainly responsible for the conversion between intermediate frequency single-ended signals and differential signals; layer 6 is the frequency conversion layer, and the frequency conversion subsystem is used to realize the conversion between RF signals and intermediate frequency signals; layer 7 is the component layer, which is used to realize power supply to TR components and issue wave control instructions;

[0029] Different layers are connected by vertical coupling and crimping using solder-free button connectors with spring pins on both sides and structural parts;

[0030] The interconnection interface relationship includes:

[0031] (1) Power supply between layer 1 and layer 7;

[0032] Power supply signal type: +28V, 4 places in total, single-core current does not exceed 5A, and the total contact resistance is not higher than 100mΩ; the interface area at layer 1 matches the component power supply pad to ensure the button crimping requirements; the interface area at layer 7 matches the rear cover power supply pad, and the area is larger than other layers, and the size is appropriately enlarged. The channel part that runs through the shell ensures the size constraint of 4mm×8mm. Layer 1 and layer 7 are connected through the first connector 1; the height of the first connector 1 is the structural connection length from layer 1 to layer 7, and the assembly complexity needs to be considered and can be segmented;

[0033] (2) Power supply is provided between layer 1 and layer 6, and layer 1 and layer 6 are connected via a second connector 2;

[0034] Power supply signal type: +8V, +5V, -40V, -5V, +15V, +2.5V, 2 places in total, single core current does not exceed 5A, the number and type of pins at the two places can be different, and they are in the form of button distribution, allowing different button types to be set according to the single core current requirements; the interface area at layer 1 matches the component power supply pad to ensure the button crimping requirements; the interface area at layer 6 is 4.5mm×22mm, and the height of the second connector 2 is the structural connection length from layer 1 to layer 6. The assembly complexity needs to be considered, and the connector can be segmented;

[0035] (3) Signal transmission between layer 1 and layer 2, layer 1 and layer 2 are connected via a fourth connector 4;

[0036] Power supply signal type: multi-core low-frequency signal, including single-ended, low-speed clock differential signal, isolation not less than 70dB; the interface area at layer 1 matches the component power supply pad, and the interface area at layer 2 is 7mm×14mm; the fourth connector height is 7mm;

[0037] (4) Power supply between layer 1 and layer 2;

[0038] Power supply signal type: +8V, 6 cores in total; the interface area at layer 1 matches the component power supply pad; the interface area at layer 2 is 6mm×8mm, and the projection position completely coincides with the sixth connector 6 when vertically interconnected, and the positioning and installation method of sequential crimping is adopted, and the connector height is 7mm;

[0039] (5) An optical fiber interface is provided between layer 1 and layer 2;

[0040] Standard MT interface, using a MT socket with a floating amount of not less than ±0.5mm installed on the rear cover in a blind-mating manner, with a connector height of 7mm;

[0041] (6) Power supply between layer 2 and layer 3, layer 2 and layer 3 are connected via a sixth connector 6;

[0042] Power supply signal type: +8V, 6 cores in total; Layer 2 interface area 6mm×8mm, completely overlapped with the projection position of the fourth connector 4 when vertically interconnected, using sequential crimping positioning and installation method; Layer 3 interface area 6mm×8mm, the sixth connector 6 height 5mm;

[0043] (7) Signal transmission between layer 2 and layer 4, layer 2 and layer 4 are connected via a seventh connector 7;

[0044] Adopt multi-core TTL low-frequency signal matching resistance 50Ω, low-speed differential signal, high-speed differential signal, where the isolation between differential signals is not less than 50dB; layer 2 interface area is 7mm×37mm, layer 4 interface area is 7mm×37mm, and the seventh connector 7 height is 15mm;

[0045] (8) Power supply between layer 3 and layer 4, layer 3 and layer 4 are connected via an eighth connector 8;

[0046] The power supply signal types include 0.85V, 0.85V, 0.9V, 0.925V, 1.2V, 1.8V, 2.5V, and 3.3V; the layer 3 interface area is 7mm×37mm, the layer 4 interface area is 7mm×37mm, and the eighth connector 8 is 8mm high.

[0047] (9) Layer 4 and layer 5 are mixed for transmission, and layer 4 and layer 5 are connected via a ninth connector 9;

[0048] Signal types include differential signals, single-ended control signals (matching resistance 50Ω), and 3.3V power supply; the matching resistance of each pair of differential PN pins is 100Ω, and the ground wire is used to achieve an isolation of no less than 65dB between differential pairs; the amplitude and phase consistency requirements are that the amplitude difference between differential pairs does not exceed 1dB, the delay does not exceed 2.7ps (5°@5GHz), and the standing wave ratio is not higher than 1.2, giving priority to ensuring the balance and consistency between differential pairs. The interface area of ​​layer 4 is 9mm×45mm, the interface area of ​​layer 5 is 9mm×45mm, and the height of the ninth connector is 13mm;

[0049] (10) Signals are transmitted between layer 5 and layer 6, and layer 5 and layer 6 are connected via a tenth connector 10 and an eleventh connector 11;

[0050] Signal types include TTL low-frequency signals, two groups in total; the interface area of ​​layer 5 is two groups of 16mm×7mm, the interface area of ​​layer 6 is two groups of 16mm×7mm, and the connector height does not exceed 7mm;

[0051] (11) Signal transmission between layer 5 and layer 6;

[0052] Signal type: multi-core RF signal (DC-5GHz); layer 5 interface area: 16mm×7mm, layer 6 interface area: 16mm×7mm, connector height not exceeding 7mm;

[0053] (12) Layer 6 and layer 7 are mixed; layer 6 and layer 7 are connected by a twelfth connector 12;

[0054] Signal type: RF signal, single-ended control signal; the connector adopts a cross-shaped structure with pins and buttons on both sides, the RF signal port is arranged in the center, and the 4 pins of the cross are arranged with single-ended signal ports; the entire twelve connectors are a whole without segmentation, and the size and installation requirements of the connector are as follows Figure 2 shown.

[0055] (13) Signal transmission between layer 1 and layer 6

[0056] Signal type: RF signal, the interface area at layer 1 matches the component power supply pad to ensure the button crimping requirements, the interface area at layer 6 is 4.5mm×22mm, and the connector height is the structural connection length from layer 1 to layer 6. The assembly complexity needs to be considered and can be completed in sections;

[0057] (14) Rear cover

[0058] The rear cover plate completes the aggregation and spacing transformation of the button pads of some connectors in the module through the PCB board (to ensure the floating amount), and completes the crimping with the array motherboard through the single-sided welded button connector.

[0059] In the design of this scheme, the first connector 1 and the second connector 2 are powered by large current and need to penetrate multiple layers, and the required height is relatively high. They should try to adopt a locking form that is conformal to the shell or installed with the help of structural parts such as the shell; the connection form of the thirteenth connector 13 is similar to 2. The first connector 1, the second connector 2, the third connector 3, the fourth connector 4, the fifth connector 5, and the thirteenth connector 13 all have crimping requirements on the module cover plate of layer 1. A connector form with double-sided spring needles and buttons is selected. In order to ensure the crimping stability between PCB circuit boards, a product form in which the connector is embedded in a support frame is adopted. At the same time, auxiliary structural parts such as positioning pins and mounting screw holes are arranged within the available range of each connector.

[0060] In this device, non-adjacent cross-layer transmission states are allowed to occur between two connected layers.

[0061] The present invention is described below in conjunction with a specific embodiment. The design parameters of each connector involved in the vertical interconnection between each level are:

[0062] (1) Layer 1 → Layer 7, including 4 +28V / 96A power supply signals, the total contact resistance is not higher than 100mΩ, the interface information area at layer 7 is 4mm×8mm, and the connector height is 53mm;

[0063] (2) Layer 1 → Layer 6, including 2 power supply signals of +8 V / 24 A, +5 V / 30 A, -40 V / 0.8 A, -5 V / 5.2 A, +15 V / 0.2 A, and +2.5 V / 4.4 A. The interface area at layer 6 is 4.5 mm × 22 mm, and the connector height is 43 mm.

[0064] (3) Layer 1 → Layer 2, including 32-core low-frequency signals, including 24-core single-ended (100Mbps), 2 pairs of 1GHz low-speed clocks (can be processed as digital differential signals, with an isolation of no less than 70dB) + 4-core ground. The interface area at layer 2 is 7mm×14mm, and the connector height is 7mm;

[0065] (4) Layer 1 → Layer 2, including 6-core +8V / 12A power supply signal, the interface area at layer 2 is 6mm×8mm, completely overlapping with the projection position of connector (6), and the connector height is 7mm;

[0066] (5) Layer 1 → Layer 2, including 1 standard MT interface (12 receive 12 transmit) + 1 standard MT interface (4 receive 4 transmit), using a MT socket with a floating amount of not less than ±0.5mm installed on the rear cover in a blind-mating manner, connector height: 7mm;

[0067] (6) Layer 2 → Layer 3, including 6-core +8V / 10A power supply signal, layer 2 interface area 6mm×8mm, completely overlaps with the projection position of the fourth connector 4, layer 3 interface area 6mm×8mm, connector height 5mm;

[0068] (7) Layer 2 → Layer 4, including 4-core sampling clock + 24-core TTL low-frequency signal (matching resistance 50Ω) + 8 pairs of 6.25 Gbps differential signal + 12 pairs of 25 Gbps high-speed differential signal (isolation not less than 50 dB), layer 2 interface area 7mm × 37mm, layer 4 interface area 7mm × 37mm, connector height 15mm;

[0069] (8) Layer 3 → Layer 4, including 0.85V / 30A, 0.85V / 13A, 0.85V / 8A, 0.9V / 3A, 0.9V / 3A, 0.925V / 3A, 1.2V / 5A, 1.8V / 8A, 1.8V / 3A, 1.8V / 3A, 2.5V / 5A, 3.3V / 4A power supply signals. The above power supplies with the same voltage cannot be merged. The interface area of ​​layer 3 is 7mm×37mm, the interface area of ​​layer 4 is 7mm×37mm, and the connector height is 8mm;

[0070] (9) Layer 4 → Layer 5, including 16 pairs of 5GHz differential signals (excluding ground) + 92 cores of single-ended control signals (matching resistance 50Ω) + 2 cores of 3.3V power supply. The matching resistance of each pair of differential PN pins is 100Ω, and the differential pair isolation is not less than 65dB. The amplitude difference between differential pairs does not exceed 1dB, the delay does not exceed 2.7ps (5°@5GHz), and the standing wave ratio is not higher than 1.2. Priority is given to ensuring the balance and consistency between differential pairs. The interface area of ​​layer 4 is 9mm×45mm, the interface area of ​​layer 5 is 9mm×45mm, and the connector height is 13mm;

[0071] (10) Layer 5 → Layer 6, including 2 groups of 40-core TTL low-frequency signals, the interface area of ​​layer 5 is 16 mm × 7 mm, the interface area of ​​layer 6 is 16 mm × 7 mm, and the connector height is 7 mm;

[0072] (11) Layer 5 → Layer 6, including 8-core RF signals (DC-5GHz), layer 5 interface area 16mm×7mm, layer 6 interface area 16mm×7mm, connector height 7mm;

[0073] (12) Layer 6 → Layer 7, the connector is a whole without segmentation, the size and installation of the connector are Figure 2 Constraints match;

[0074] (13) Layer 1 → Layer 6, including 4-core RF signals (1 core 100 MHz + 2 cores DC-10 GHz + 1 core DC-5 GHz). The interface area at layer 6 is 4 mm × 10.25 mm, and the connector height is 43 mm.

[0075] (14) Rear cover

[0076] The rear cover plate completes the aggregation and spacing transformation of the button pads of some connectors in the module through a PCB board (to ensure the floating amount), and then completes the crimping with the array motherboard through a single-sided welded button connector.

[0077] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0078] The above-described embodiments of the present application do not constitute a limitation on the protection scope of the present application.

Claims

1. A device based on multi-level signal vertical interconnection, characterized in that: The device comprises: The device is divided into 7 layers in order from the back end to the antenna. Layer 1 is the back cover, which is responsible for the power supply, clock, and data transmission of the module; Layer 2 is the optical module layer, which is used to convert the high-speed electrical signal in the module into a high-speed optical signal; Layer 3 is the power supply layer, which is used to supply power to multiple types of power supplies in the digital subsystem; Layer 4 is the digital subsystem layer, and the main chip is used for digital-analog sampling and wave control instruction generation; Layer 5 is the balun layer, which is mainly responsible for the conversion between intermediate frequency single-ended signals and differential signals; Layer 6 is the frequency conversion layer, and the frequency conversion subsystem is used to realize the conversion between RF signals and intermediate frequency signals; Layer 7 is the component layer, which is used to power the TR component and issue wave control instructions; Different layers are connected vertically by solder-free button connectors with spring pins on both sides and structural parts.

2. The device according to claim 1, characterized in that The interconnection relationship between different layers is as follows: Power is supplied between layer 1 and layer 7; power supply signal type: +28V; the interface area at layer 1 matches the component power supply pad; the interface area at layer 7 matches the rear cover power supply pad and is larger than that of other layers; layer 1 and layer 7 are connected via a first connector (1); the height of the first connector (1) is the structural connection length from layer 1 to layer 7, and it can be segmented, and the number of connectors is 4; Power is supplied between layer 1 and layer 6, and layer 1 and layer 6 are connected via a second connector (2); power supply signal types: +8V, +5V, -40V, -5V, +15V, +2.5V, single-core current does not exceed 5A, the number and type of pins at the two locations can be different, and they are in a button-shaped distribution form; the interface area at layer 1 matches the component power supply pad; the height of the second connector (2) is the structural connection length from layer 1 to layer 6, the connector can be segmented, and the number of connectors is 2; Signals are transmitted between layer 1 and layer 2, and layer 1 and layer 2 are connected via a fourth connector (4); power supply signal type: multi-core low-frequency signal, including single-ended, low-speed clock differential signal, with an isolation of not less than 70 dB; the interface area at layer 1 matches the component power supply pad; Power is supplied between layer 1 and layer 2; the power supply signal type is +8V; the interface area at layer 1 matches the component power supply pad; the interface area at layer 2 completely coincides with the projection position of the sixth connector (6) when vertically interconnected, and a sequential crimping positioning and installation method is adopted; An optical fiber interface is set between layer 1 and layer 2; the optical fiber interface is a standard MT interface, and a floating MT socket is installed on the rear cover in a blind-plug manner; Power is supplied between layer 2 and layer 3, and layer 2 and layer 3 are connected via a sixth connector (6); power supply signal type: +8V; when vertically interconnected with the fourth connector (4), the projection position completely overlaps, and a sequential crimping positioning and installation method is adopted; Signals are transmitted between layer 2 and layer 4, and layer 2 and layer 4 are connected via a seventh connector (7); multi-core TTL low-frequency signals, low-speed differential signals, and high-speed differential signals are used; Power is supplied between layer 3 and layer 4, and layer 3 and layer 4 are connected via an eighth connector (8); power supply signal types include 0.85V, 0.85V, 0.9V, 0.925V, 1.2V, 1.8V, 2.5V, and 3.3V; Layer 4 and layer 5 are mixed for transmission, and layer 4 and layer 5 are connected via a ninth connector (9); signal types include differential signals, single-ended control signals, and 3.3V power supply; Signals are transmitted between layer 5 and layer 6, and layer 5 and layer 6 are connected via a tenth connector (10) and an eleventh connector (11); the signal types include TTL low-frequency signals, which are two groups in total; Signals transmitted between layer 5 and layer 6; Signal type: multi-core RF signal; Layer 6 and layer 7 are mixed; layer 6 and layer 7 are connected through a twelfth connector (12); signal types are radio frequency signal and single-ended control signal; the connector adopts a cross-shaped structure with elastic needles and buttons on both sides, a radio frequency signal port is arranged in the center, and the four pins of the cross are arranged with single-ended signal ports; the entire twelfth connector (12) is a whole without segmentation; Signal transmission between layer 1 and layer 6; the signal type is RF signal, the interface area at layer 1 matches the component power supply pad to ensure the button crimping requirements, the connector height is the structural connection length from layer 1 to layer 6, and can be set to segment; The rear cover plate completes the aggregation and spacing transformation of the button pads of some connectors in the module through the PCB board, and completes the crimping with the array motherboard through the single-sided welded button connector.

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