Time synchronization method and device, equipment, storage medium and computer program product

Abstract

The invention relates to a time synchronization method and device, equipment, a storage medium and a computer program product. The method comprises the following steps: a master clock device in an industrial network sends a time synchronization frame to a slave clock device in the industrial network based on a master-slave clock synchronization path corresponding to a transmission mode under the current transmission mode; wherein the time synchronization frame is used for performing time synchronization on the slave clock equipment and the master clock equipment, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode. By adopting the method, accurate time synchronization between equipment in an industrial network can be realized.

Description

Technical Field

[0001] The present application relates to the field of clock synchronization technology, and in particular to a time synchronization method, apparatus, device, storage medium and computer program product. Background Art

[0002] In the field of industrial networks, data is transmitted between industrial equipment and controllers based on wired networks. Time synchronization between devices plays an important role in the real-time performance and system stability of industrial networks. Inaccurate time synchronization may cause data delays or command delays, or even incorrect execution of commands, affecting production efficiency and product quality.

[0003] Therefore, how to achieve accurate time synchronization between devices in industrial networks is of great significance. Summary of the invention

[0004] Based on this, it is necessary to provide a time synchronization method, apparatus, device, storage medium and computer program product that can achieve accurate time synchronization between devices in an industrial network in response to the above technical problems.

[0005] In a first aspect, the present application provides a time synchronization method for a master clock device in an industrial network, the method comprising:

[0006] In the current transmission mode, based on the master-slave clock synchronization path corresponding to the transmission mode, sending a time synchronization frame to a slave clock device in the industrial network;

[0007] The time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0008] In one of the embodiments, in the current transmission mode, based on the master-slave clock synchronization path corresponding to the transmission mode, sending a time synchronization frame to a slave clock device in the industrial network includes:

[0009] When the transmission mode is a loopback mode or a unidirectional mode, in the outbound direction of the controller in the industrial network, a first time synchronization frame is received, and a timestamp in the first time synchronization frame is updated to obtain a second time synchronization frame;

[0010] Based on the first master-slave clock synchronization path corresponding to the loopback mode or the second master-slave clock synchronization path corresponding to the unidirectional mode, the second time synchronization frame is sent to the slave clock device in the outbound direction.

[0011] In one of the embodiments, in the current transmission mode, based on the master-slave clock synchronization path corresponding to the transmission mode, sending a time synchronization frame to a slave clock device in the industrial network further includes:

[0012] When the transmission mode is the loopback mode, in the inbound direction of the controller, updating the timestamp in the received time synchronization frame to obtain a third time synchronization frame;

[0013] Based on the first master-slave clock synchronization path, the third time synchronization frame is sent to the slave clock device in the inbound direction.

[0014] In one of the embodiments, in the current transmission mode, based on the master-slave clock synchronization path corresponding to the transmission mode, sending a time synchronization frame to a slave clock device in the industrial network further includes:

[0015] When the transmission mode is the unidirectional mode, generating a fourth time synchronization frame in an inbound direction of the controller;

[0016] Based on the second master-slave clock synchronization path, the fourth time synchronization frame is sent to the slave clock device in the inbound direction.

[0017] In one of the embodiments, each port in the master clock device and the slave clock device is respectively used to send a link delay measurement frame so that the master-slave clock synchronization path is consistent with the shortest physical communication path;

[0018] The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

[0019] In one embodiment, the method further comprises:

[0020] Based on the redundant clock synchronization path corresponding to the transmission mode, a redundant time synchronization frame is sent to the slave clock device. In the event of a failure in the master-slave clock synchronization path, the redundant time synchronization frame is used for the slave clock device to perform time synchronization with the master clock device based on the redundant time synchronization frame.

[0021] In one of the embodiments, when the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

[0022] In one of the embodiments, the time interval between two consecutive transmissions of link delay measurement frames by the faulty device is inconsistent with the time interval between two consecutive transmissions of link delay measurement frames by the neighboring device.

[0023] In one embodiment, the method further comprises:

[0024] Determining a controller in the industrial network as the master clock device according to a clock frequency stability parameter and a position parameter of each industrial device in the industrial network;

[0025] Among them, when the industrial network is a single-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among all the industrial devices; when the industrial network is a multi-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among the first branch device in the multi-layer topology and the devices before the first branch device.

[0026] In a second aspect, the present application provides a time synchronization method for a slave clock device in an industrial network, the method comprising:

[0027] In the current transmission mode, receiving a time synchronization frame sent by a master clock device in the industrial network;

[0028] Based on the time synchronization frame, performing time synchronization with the master clock device;

[0029] The time synchronization frame is sent by the master clock device to the slave clock device based on the master-slave clock synchronization path corresponding to the transmission mode, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0030] In one of the embodiments, each port in the master clock device and the slave clock device is respectively used to send a link delay measurement frame so that the master-slave clock synchronization path is consistent with the shortest physical communication path;

[0031] The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

[0032] In one embodiment, the method further comprises:

[0033] Receive a redundant time synchronization frame sent by the master clock device based on a redundant clock synchronization path corresponding to the transmission mode, wherein the redundant time synchronization frame is used to perform time synchronization with the master clock device based on the redundant time synchronization frame when a failure occurs in the master-slave clock synchronization path.

[0034] In one of the embodiments, when the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

[0035] In one of the embodiments, the time interval between two consecutive transmissions of link delay measurement frames by the faulty device is inconsistent with the time interval between two consecutive transmissions of link delay measurement frames by the neighboring device.

[0036] In one of the embodiments, after performing time synchronization with the master clock device based on the time synchronization frame, the method further includes:

[0037] Acquire an Allan variance curve corresponding to the slave clock device according to the time after synchronization of the slave clock device;

[0038] Based on the Allan variance curve, influencing factors affecting the stability of the clock frequency of the slave clock device are determined, and the influencing factors are used to detect overall problems in the environment.

[0039] In a third aspect, the present application provides a time synchronization method for a controller in an industrial network, the method comprising:

[0040] Determine a master clock device according to clock frequency stability parameters and position parameters of each industrial device in the industrial network;

[0041] Among them, the master clock device is used to send time synchronization frames to the slave clock devices in the industrial network under a preset transmission mode based on the master-slave clock synchronization path corresponding to the transmission mode; the time synchronization frame is used for the slave clock device to synchronize time with the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0042] In one embodiment, determining the master clock device according to the clock frequency stability parameter and the location parameter of each industrial device in the industrial network includes:

[0043] In the case where the industrial network is a single-layer topology, if there is only one industrial device with the smallest clock frequency stability parameter among the industrial devices, then one of the industrial devices is determined as the master clock device;

[0044] If there are multiple industrial devices with the smallest clock frequency stability parameters among the multiple industrial devices, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the topological center position of the single-layer topology among the multiple industrial devices is determined as the master clock device.

[0045] In one embodiment, determining the master clock device according to the clock frequency stability parameter and the location parameter of each industrial device in the industrial network includes:

[0046] In the case where the industrial network is a multi-level topology, if there is one industrial device with the smallest clock frequency stability parameter among the first branch device and the devices before the first branch device in the multi-level topology, one of the industrial devices is determined as the master clock device;

[0047] If there are multiple industrial devices with the smallest clock frequency stability parameters among the first branch device and the devices before the first branch device, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the first branch device among the multiple industrial devices is determined as the master clock device.

[0048] In one embodiment, the method further comprises:

[0049] In the case that the master clock device is different from the controller and the master clock device fails, a redundant master clock is determined according to clock frequency stability parameters and position parameters of other industrial devices among the industrial devices except the master clock device.

[0050] In a fourth aspect, the present application provides a time synchronization device for a master clock device in an industrial network, the device comprising:

[0051] A sending module, configured to send a time synchronization frame to a slave clock device in the industrial network based on a master-slave clock synchronization path corresponding to the transmission mode in a current transmission mode;

[0052] The time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0053] In a fifth aspect, the present application provides a time synchronization device for a slave clock device in an industrial network, the device comprising:

[0054] A receiving module, used for receiving a time synchronization frame sent by a master clock device in the industrial network in a current transmission mode;

[0055] A synchronization module, configured to perform time synchronization with the master clock device based on the time synchronization frame;

[0056] The time synchronization frame is sent by the master clock device to the slave clock device based on the master-slave clock synchronization path corresponding to the transmission mode, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0057] In a sixth aspect, the present application provides a time synchronization device for a controller in an industrial network, the device comprising:

[0058] A determination module, used to determine a master clock device according to clock frequency stability parameters and position parameters of each industrial device in the industrial network;

[0059] Among them, the master clock device is used to send time synchronization frames to the slave clock devices in the industrial network under a preset transmission mode based on the master-slave clock synchronization path corresponding to the transmission mode; the time synchronization frame is used for the slave clock device to synchronize time with the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0060] In a seventh aspect, the present application provides a master clock device, including a memory, a transceiver, and a processor:

[0061] The memory is used to store a computer program; the transceiver is used to send and receive data under the control of the processor; the processor is used to read the computer program in the memory and perform the following operations:

[0062] In the current transmission mode, based on the master-slave clock synchronization path corresponding to the transmission mode, controlling the transceiver to send a time synchronization frame to a slave clock device in the industrial network;

[0063] The time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0064] In an eighth aspect, the present application provides a slave clock device, including a memory, a transceiver, and a processor:

[0065] The memory is used to store a computer program; the transceiver is used to send and receive data under the control of the processor; the processor is used to read the computer program in the memory and perform the following operations:

[0066] In the current transmission mode, controlling the transceiver to receive a time synchronization frame sent by a master clock device in the industrial network;

[0067] Based on the time synchronization frame, performing time synchronization with the master clock device;

[0068] The time synchronization frame is sent by the master clock device to the slave clock device based on the master-slave clock synchronization path corresponding to the transmission mode, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0069] In a ninth aspect, the present application provides a controller, including a memory, a transceiver, and a processor:

[0070] The memory is used to store a computer program; the transceiver is used to send and receive data under the control of the processor; the processor is used to read the computer program in the memory and perform the following operations:

[0071] Determine the master clock device according to the clock frequency stability parameters and location parameters of each industrial device in the industrial network;

[0072] Among them, the master clock device is used to send time synchronization frames to the slave clock devices in the industrial network under a preset transmission mode based on the master-slave clock synchronization path corresponding to the transmission mode; the time synchronization frame is used for the slave clock device to synchronize time with the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0073] In a tenth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method described in the first aspect, the second aspect or the third aspect above are implemented.

[0074] In an eleventh aspect, the present application provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the method described in the first aspect, the second aspect or the third aspect above.

[0075] The above-mentioned time synchronization method, apparatus, device, storage medium and computer program product, the master clock device in the industrial network sends a time synchronization frame to the slave clock device in the industrial network based on the master-slave clock synchronization path corresponding to the transmission mode in the current transmission mode (the transmission mode can be, for example, a loopback mode or a unidirectional mode), wherein the time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode. In this way, it can be avoided that when the time synchronization frame is transmitted in the master-slave clock synchronization path, the accuracy of the timestamp of the master clock device in the time synchronization frame is affected by the master-slave clock synchronization path being too long. In the embodiment of the present application, since the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode, the master-slave clock synchronization path is the shortest, which can improve the accuracy of the timestamp in the time synchronization frame when the time synchronization frame is transmitted in the master-slave clock synchronization path, thereby improving the synchronization accuracy of time synchronization based on the timestamp, and realizing accurate time synchronization between devices in the industrial network. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0077] Figure 1 A schematic diagram of a network topology of a wired industrial network;

[0078] Figure 2 A schematic diagram of network topology of another wired industrial network;

[0079] Figure 3 A schematic diagram of a time synchronization method according to an embodiment of the present invention;

[0080] Figure 4 is a flow chart of step 301 in another embodiment;

[0081] Figure 5 A schematic diagram of transmission of a time synchronization frame in a multi-level topology in one embodiment;

[0082] Figure 6 A schematic diagram of transmission of a time synchronization frame in a single-layer topology in another embodiment;

[0083] Figure 7 A schematic diagram of transmission of a time synchronization frame in a multi-level topology in another embodiment;

[0084] Figure 8 A schematic diagram of transmission of a time synchronization frame in a single-layer topology in another embodiment;

[0085] Fig. 9 It is a schematic diagram of a process of link delay measurement under a single-layer topology in another embodiment;

[0086] Fig.10 It is a schematic diagram of a process of link delay measurement under a multi-level topology in another embodiment;

[0087] Fig.11 A schematic diagram of a selection range of a master clock device in a single-layer topology in another embodiment;

[0088] Fig.12 A schematic diagram of a selection range of a master clock device in a multi-level topology in another embodiment;

[0089] Fig.13 is a flow chart of a time synchronization method in another embodiment;

[0090] Fig.14is a flow chart of a time synchronization method in another embodiment;

[0091] Fig.15 is a structural block diagram of a time synchronization device in an embodiment;

[0092] Fig.16 is a structural block diagram of a time synchronization device in another embodiment;

[0093] Fig.17 is a structural block diagram of a time synchronization device in another embodiment;

[0094] Fig.18 FIG. 1 is a diagram showing the internal structure of an industrial device in one embodiment. DETAILED DESCRIPTION

[0095] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0096] In the traditional industrial network field, data transmission between industrial equipment and controllers is based on wired networks.

[0097] See also Figure 1 , Figure 1 Figure 1 is a schematic diagram of the network topology of a wired industrial network. Figure 1 In the wired industrial network shown in FIG, the controller and industrial devices 1 to 3 form a simple single-layer topology through wired cables. Figure 2 , Figure 2 Figure 1 is a schematic diagram of another wired industrial network topology. Figure 2 In the wired industrial network shown, the controller and industrial devices 1 - 5 form a complex multi-level topology through wired cables.

[0098] In wired industrial networks, time synchronization between devices plays an important role in the real-time performance and system stability of industrial networks. Inaccurate time synchronization may cause data delays or command delays, or even incorrect execution of commands, affecting production efficiency and product quality. Therefore, how to achieve accurate time synchronization between devices in industrial networks is of great significance.

[0099] In view of this, embodiments of the present application provide a time synchronization method, apparatus, device, storage medium, and computer program product, which can achieve accurate time synchronization between devices in an industrial network.

[0100] The time synchronization method provided in the embodiment of the present application can be applied to any industrial network, for example, Figure 1 or Figure 2In the industrial network shown, it can be understood that Figure 1 and Figure 2 The industrial network shown does not constitute a limitation on the network topology of the industrial network to which the time synchronization method of the embodiment of the present application is applied.

[0101] Below, in conjunction with the drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application are clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0102] The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0103] In an exemplary embodiment, Figure 3 As shown, a time synchronization method is provided, which is described by taking the method applied to a master clock device in an industrial network as an example, and includes the following steps:

[0104] Step 301, in the current transmission mode, based on the master-slave clock synchronization path corresponding to the transmission mode, a time synchronization frame is sent to the slave clock device in the industrial network, the time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0105] In an embodiment of the present application, the master clock device is selected by the controller from the controllers and various industrial devices in the industrial network through a master clock selection algorithm. The manner in which the controller selects the master clock device will be described in the following embodiment.

[0106] The transmission mode can be loopback mode or one-way mode. The loopback mode means that when the loopback frame sent by the controller reaches the destination industrial device, the destination industrial device modifies the destination address in the loopback frame to the controller address, and then loops back to transmit it to the controller; the one-way mode means that the controller sends a one-way frame to the destination industrial device, and the destination industrial device performs frame elimination and no longer continues transmission.

[0107] In an embodiment of the present application, for any transmission mode, the master-slave clock synchronization path corresponding to the transmission mode is consistent with the shortest physical communication path corresponding to the transmission mode. The shortest physical communication path can also be referred to as the shortest physical path, which refers to the shortest path among the various paths formed by the physical connection of each device in the network topology. The shortest physical communication path includes: a first path between the master clock device and the last device in the outbound direction of the controller, and a second path between the master clock device and the controller in the inbound direction of the controller. Each slave clock device in the shortest physical communication path only appears once in the shortest physical communication path, that is, the shortest physical communication path will not pass through the same slave clock device multiple times to cause path redundancy, and therefore, it is called the shortest physical communication path. In an industrial network, the shortest physical communication path is the main path (other paths are redundant paths), and the number of main paths (i.e., the shortest physical communication path) in the industrial network is one.

[0108] The master-slave clock synchronization path (or the effective master-slave clock synchronization path) is consistent with the shortest physical communication path. In this way, the master-slave clock synchronization path will not pass through the same slave clock device multiple times to cause path redundancy and repeated clock synchronization. Each slave clock device in the master-slave clock synchronization path only performs time synchronization once.

[0109] It should be noted that, in loopback mode, after the time synchronization frame is transmitted to the last device in the outbound direction based on the master-slave clock synchronization path corresponding to the loopback mode, it is necessary to first transmit the time synchronization frame to the master clock device in the inbound direction through the path between the last device and the master clock device, and then transmit the time synchronization frame from the master clock device to the controller based on the master-slave clock synchronization path. However, since in the process of time synchronization, the devices that have been time synchronized in the outbound direction (i.e., the slave clock devices between the master clock device and the above-mentioned last device, including the last device) will not repeat the time synchronization in the inbound direction, then, in loopback mode, the effective master-slave clock synchronization paths are still: the first path between the master clock device and the last device in the outbound direction of the controller, and the second path between the master clock device and the controller in the inbound direction of the controller.

[0110] In an embodiment of the present application, each slave clock device in the master-slave clock synchronization path performs time synchronization only once, that is, the master-slave clock synchronization path will not pass through the same slave clock device multiple times to cause path redundancy and repeated time synchronization, but is consistent with the shortest physical communication path.

[0111] Take loopback mode as an example, combined with Figure 1The network topology of the wired industrial network shown in the figure assumes that industrial device 1 is the master clock device, then the master-slave clock synchronization path corresponding to the loopback mode includes: the first path between the master clock device (industrial device 1) and the last device (industrial device 3) in the outbound direction of the controller, and the second path between the master clock device (industrial device 1) and the controller in the inbound direction of the controller. It can be seen that the master-slave clock synchronization path is consistent with the shortest physical communication path, that is, the master-slave clock synchronization path will not pass through the same slave clock device (such as industrial device 2 or industrial device 3) multiple times, causing path redundancy and repeated time synchronization, but is consistent with the shortest physical communication path corresponding to the controller, industrial device 1 to industrial device 3, so that each slave clock device in the master-slave clock synchronization path only performs time synchronization once.

[0112] Taking the one-way mode as an example, combined with Figure 1 The network topology of the wired industrial network shown in the figure assumes that industrial device 1 is the master clock device. Then, the master-slave clock synchronization path corresponding to the unidirectional mode includes: the first path between the master clock device (industrial device 1) and the last device (industrial device 3) in the outbound direction of the controller, and the second path between the master clock device (industrial device 1) and the controller in the inbound direction of the controller. Similarly, each slave clock device in the master-slave clock synchronization path only performs time synchronization once, and the master-slave clock synchronization path is consistent with the shortest physical communication path. It should be noted that in the unidirectional mode, since industrial device 3 will perform frame elimination operations, then, in the inbound direction of the controller, the master clock device can generate a time synchronization frame and send it to the device in the inbound direction for time synchronization.

[0113] It is understandable that the above examples are based on Figure 1 The single-level topology shown is used as an example for the introduction. It can be understood that in the multi-level topology, there are also master-slave clock synchronization paths in the loopback mode and the unidirectional mode, which will be introduced in the following embodiments.

[0114] In this way, in the current transmission mode, the master clock device can send time synchronization frames to the next-level slave clock device in the master-slave clock synchronization path based on the master-slave clock synchronization path corresponding to the transmission mode. After the slave clock device receives the time synchronization frame sent by the master clock device in the current transmission mode, it uses the clock synchronization algorithm to synchronize time with the master clock device based on the time synchronization frame, and continues to send time synchronization frames to the next-level slave clock device in the master-slave clock synchronization path based on the master-slave clock synchronization path. The time synchronization of each slave clock device is achieved through the step-by-step transmission of the time synchronization frame.

[0115] In the above embodiment, the master clock device in the industrial network sends a time synchronization frame to the slave clock device in the industrial network based on the master-slave clock synchronization path corresponding to the transmission mode in the current transmission mode (the transmission mode may be, for example, a loopback mode or a unidirectional mode), wherein the time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode. In this way, the accuracy of the timestamp of the master clock device in the time synchronization frame may be affected due to the excessive length of the master-slave clock synchronization path when the time synchronization frame is transmitted in the master-slave clock synchronization path. In the embodiment of the present application, since the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode, the shortest master-slave clock synchronization path can improve the accuracy of the timestamp in the time synchronization frame when the time synchronization frame is transmitted in the master-slave clock synchronization path, thereby improving the synchronization accuracy of time synchronization based on the timestamp, and realizing accurate time synchronization between devices in the industrial network.

[0116] In one embodiment, based on Figure 3 In the embodiment shown, the transmission mechanism of the time synchronization frame in the loopback mode and the unidirectional mode is introduced below. Figure 4 In this embodiment, step 301 may include Figure 4 Step 401 and step 402 shown:

[0117] Step 401 , when the transmission mode is loopback mode or unidirectional mode, in the outbound direction of the controller in the industrial network, a first time synchronization frame is received, and a timestamp in the first time synchronization frame is updated to obtain a second time synchronization frame.

[0118] In loopback mode, the time synchronization frame is a loopback frame. The controller transmits the time synchronization frame outbound. When the time synchronization frame arrives at the master clock device (here it is referred to as the first time synchronization frame for distinction, and it should be noted that this embodiment is described using the master clock device other than the controller as an example), the master clock device updates the valid master clock timestamp in the first time synchronization frame to obtain a second time synchronization frame.

[0119] In the unidirectional mode, the time synchronization frame is a unidirectional frame. The controller transmits the time synchronization frame outbound. When the time synchronization frame reaches the master clock device, the master clock device updates the valid master clock timestamp in the first time synchronization frame to obtain a second time synchronization frame.

[0120] Step 402: Send a second time synchronization frame to a slave clock device in an outbound direction based on a first master-slave clock synchronization path corresponding to the loopback mode or a second master-slave clock synchronization path corresponding to the unidirectional mode.

[0121] The master clock device sends a second time synchronization frame to the next level slave clock device in the outbound direction according to the master-slave clock synchronization path and addressing rules corresponding to the current transmission mode, so that the slave clock device can correct the resident delay and link delay based on the second time synchronization frame, execute the synchronization algorithm, and complete the time synchronization with the master clock device. If the slave clock device is not the last slave clock device in the outbound direction, the slave clock device continues to send time synchronization frames to the next level slave clock device, and so on.

[0122] Please continue to see Figure 4 Step 301 also includes Figure 4 Step 403 and step 404 are shown:

[0123] Step 403: When the transmission mode is the loopback mode, in the inbound direction of the controller, the timestamp in the received time synchronization frame is updated to obtain a third time synchronization frame.

[0124] When the transmission mode is the loopback mode, the last industrial device in the outbound direction modifies the destination address in the time synchronization frame to the controller address, and then loops back the transmission to the controller.

[0125] When the time synchronization frame is looped back and transmitted to the master clock device, the master clock device updates the valid master clock timestamp in the received time synchronization frame to obtain a third time synchronization frame.

[0126] Step 404: Send a third time synchronization frame to the slave clock device in the inbound direction based on the first master-slave clock synchronization path.

[0127] The master clock device sends a third time synchronization frame to the next-level slave clock device in the inbound direction according to the master-slave clock synchronization path corresponding to the current transmission mode (the first master-slave clock synchronization path corresponding to the loopback mode) and the addressing rules, so that the slave clock device can correct the residence delay and link delay based on the third time synchronization frame, execute the synchronization algorithm, and complete the time synchronization with the master clock device.

[0128] In an embodiment of the present application, in the loopback mode, the master clock device updates the valid master clock timestamp in the time synchronization frame twice to ensure that the synchronization time of the device before the master clock device (i.e., the device in the direction from the master clock device to the controller) is the latest. In this way, in the loopback mode, the problem of the synchronization accuracy of the devices before the master clock device being affected by the long loopback transmission path of the time synchronization frame can be solved, ensuring that the devices before the master clock device use the latest synchronization time, thereby improving the accuracy of time synchronization.

[0129] The following, combined Figure 1 and Figure 2The topology of the industrial network shown is used as an example to illustrate the transmission mechanism of the time synchronization frame in the loopback mode of the embodiment of the present application.

[0130] 1) In loopback mode, combine Figure 2 Take the multi-level topology shown as an example:

[0131] See also Figure 5 , Figure 5 for Figure 2 The schematic diagram of a time synchronization frame transmission in a multi-level topology is shown in FIG. Figure 5 The network includes two segments (segment 1 and segment 2), and the time synchronization process in the time synchronization method in the embodiment of the present application is applicable to each segment.

[0132] Figure 5 In the example, industrial device 1 is the master clock device, and the controller transmits a time synchronization frame outbound. When the time synchronization frame arrives at the master clock device, the master clock device (industrial device 1) updates the valid master clock timestamp in the first time synchronization frame to obtain a second time synchronization frame.

[0133] For network segment 1 (same for network segment 2), the master clock device (industrial device 1) sends the second time synchronization frame to the next-level slave clock device (industrial device 2) in the outbound direction according to the current first master-slave clock synchronization path and addressing rules. Based on the second time synchronization frame, industrial device 2 corrects the resident delay and link delay, executes the synchronization algorithm, and completes the time synchronization with the master clock device (industrial device 1). Industrial device 2 continues to send time synchronization frames to the next-level slave clock device (industrial device 3) for industrial device 3 to complete the time synchronization with the master clock device (industrial device 1).

[0134] Industrial device 3 modifies the destination address in the time synchronization frame to the controller address, and then loops back to the controller. When the time synchronization frame is looped back to the master clock device (industrial device 1), the master clock device (industrial device 1) updates the valid master clock timestamp in the received time synchronization frame to obtain the third time synchronization frame, and synchronizes the slave clock devices in the inbound direction in turn, that is, the master clock device (industrial device 1) sends the third time synchronization frame to the controller, so that the controller can correct the resident delay and link delay based on the third time synchronization frame, execute the synchronization algorithm, and complete the time synchronization with the master clock device.

[0135] In the embodiment of the present application, each industrial device includes a forward synchronization processing unit and a backward processing unit. In the loopback mode, each slave clock device performs time synchronization only once.

[0136] 2) In loopback mode, combined with Figure 1 Take the single-layer topology shown as an example:

[0137] See also Figure 6 , Figure 6 for Figure 1 The figure shows a schematic diagram of transmission of a time synchronization frame in a single-layer topology.

[0138] Figure 6 In the figure, industrial device 1 is the master clock device, and the controller transmits a time synchronization frame outbound. When the time synchronization frame arrives at the master clock device (industrial device 1), the master clock device updates the valid master clock timestamp in the first time synchronization frame to obtain a second time synchronization frame.

[0139] The master clock device (industrial device 1) sends a second time synchronization frame to the next-level slave clock device (industrial device 2) in the outbound direction according to the current first master-slave clock synchronization path and addressing rules. Based on the second time synchronization frame, industrial device 2 corrects the resident delay and link delay, executes the synchronization algorithm, and completes the time synchronization with the master clock device (industrial device 1). Industrial device 2 continues to send time synchronization frames to the next-level slave clock device (industrial device 3) for industrial device 3 to complete the time synchronization with the master clock device (industrial device 1).

[0140] Industrial device 3 modifies the destination address in the time synchronization frame to the controller address, and then loops back to the controller. When the time synchronization frame is looped back to the master clock device (industrial device 1), the master clock device (industrial device 1) updates the valid master clock timestamp in the received time synchronization frame to obtain the third time synchronization frame, and synchronizes the slave clock devices in the inbound direction in turn, that is, the master clock device (industrial device 1) sends the third time synchronization frame to the controller, so that the controller can correct the resident delay and link delay based on the third time synchronization frame, execute the synchronization algorithm, and complete the time synchronization with the master clock device.

[0141] Combination Figure 6 It can be seen that in loopback mode, each slave clock device performs time synchronization only once.

[0142] In an embodiment of the present application, in the loopback mode, the master clock device updates the valid master clock timestamp in the time synchronization frame twice to ensure that the synchronization time of the device before the master clock device (i.e., the device in the direction from the master clock device to the controller) is the latest. In this way, in the loopback mode, the problem of the synchronization accuracy of the devices before the master clock device being affected by the long loopback transmission path of the time synchronization frame can be solved, ensuring that the devices before the master clock device use the latest synchronization time, thereby improving the accuracy of time synchronization.

[0143] The above embodiment introduces the transmission mechanism of the time synchronization frame in the loopback mode. The following is an exemplary introduction to the transmission mechanism of the time synchronization frame in the unidirectional mode.

[0144] Please continue to see Figure 4Step 301 also includes Figure 4 Step 405 and step 406 are shown:

[0145] Step 405: When the transmission mode is the unidirectional mode, a fourth time synchronization frame is generated in the inbound direction of the controller.

[0146] When the transmission mode is unidirectional mode, the last industrial device in the outbound direction will perform a frame elimination operation. Therefore, in an embodiment of the present application, the master clock device has the ability to send time synchronization frames in the inbound direction, and the master clock device generates the fourth time synchronization frame by itself.

[0147] Step 406: Send a fourth time synchronization frame to the slave clock device in the inbound direction based on the second master-slave clock synchronization path.

[0148] The master clock device sends a fourth time synchronization frame to the next-level slave clock device in the inbound direction according to the master-slave clock synchronization path corresponding to the current transmission mode (the second master-slave clock synchronization path corresponding to the unidirectional mode) and the addressing rules, so that the slave clock device can correct the residence delay and link delay based on the fourth time synchronization frame, execute the synchronization algorithm, and complete the time synchronization with the master clock device.

[0149] In an embodiment of the present application, in a unidirectional mode, the master clock device has the ability to send a time synchronization frame (the fourth time synchronization frame) in the inbound direction. The fourth time synchronization frame can synchronize the slave clock device in the inbound direction, thereby ensuring that the synchronization path of the device before the master clock device (i.e., the device in the direction from the master clock device to the controller) is the shortest, thereby improving the accuracy of time synchronization.

[0150] The following, combined Figure 1 and Figure 2 The topology of the industrial network shown is used as an example to illustrate the transmission mechanism of the time synchronization frame in the unidirectional mode of the embodiment of the present application.

[0151] 1) In one-way mode, combined Figure 2 Take the multi-level topology shown as an example:

[0152] See also Figure 7 , Figure 7 for Figure 2 The schematic diagram of a time synchronization frame transmission in a multi-level topology is shown in FIG. Figure 7 The network includes two segments (segment 1 and segment 2), and the time synchronization process in the time synchronization method in the embodiment of the present application is applicable to each segment.

[0153] Figure 7In the example, industrial device 1 is the master clock device, and the controller transmits a time synchronization frame outbound. When the time synchronization frame arrives at the master clock device, the master clock device (industrial device 1) updates the valid master clock timestamp in the first time synchronization frame to obtain a second time synchronization frame.

[0154] For network segment 1 (same for network segment 2), the master clock device (industrial device 1) sends the second time synchronization frame to the next-level slave clock device (industrial device 2) in the outbound direction according to the current second master-slave clock synchronization path and addressing rules. Based on the second time synchronization frame, industrial device 2 corrects the resident delay and link delay, executes the synchronization algorithm, and completes the time synchronization with the master clock device (industrial device 1). Industrial device 2 continues to send time synchronization frames to the next-level slave clock device (industrial device 3) for industrial device 3 to complete the time synchronization with the master clock device (industrial device 1), and industrial device 3 performs frame elimination operations.

[0155] The master clock device has the ability to send time synchronization frames in the inbound direction. The master clock device generates a fourth time synchronization frame and synchronizes the slave clock devices in the inbound direction in turn, that is, the master clock device (industrial equipment 1) sends the fourth time synchronization frame to the controller, so that the controller can correct the residence delay and link delay based on the fourth time synchronization frame, execute the synchronization algorithm, and complete the time synchronization with the master clock device.

[0156] In the embodiment of the present application, in the unidirectional mode, each slave clock device performs time synchronization only once.

[0157] 2) In one-way mode, combined with Figure 1 Take the single-layer topology shown as an example:

[0158] See also Figure 8 , Figure 8 for Figure 1 The figure shows a schematic diagram of transmission of a time synchronization frame in a single-layer topology.

[0159] Figure 8 In the example, industrial device 1 is the master clock device, and the controller transmits a time synchronization frame outbound. When the time synchronization frame arrives at the master clock device, the master clock device (industrial device 1) updates the valid master clock timestamp in the first time synchronization frame to obtain a second time synchronization frame.

[0160] The master clock device (industrial device 1) sends the second time synchronization frame to the next-level slave clock device (industrial device 2) in the outbound direction according to the current second master-slave clock synchronization path and addressing rules. Based on the second time synchronization frame, industrial device 2 corrects the resident delay and link delay, executes the synchronization algorithm, and completes the time synchronization with the master clock device (industrial device 1). Industrial device 2 continues to send time synchronization frames to the next-level slave clock device (industrial device 3) for industrial device 3 to complete the time synchronization with the master clock device (industrial device 1), and industrial device 3 performs frame elimination operation.

[0161] The master clock device has the ability to send time synchronization frames in the inbound direction. The master clock device generates a fourth time synchronization frame and synchronizes the slave clock devices in the inbound direction in turn, that is, the master clock device (industrial equipment 1) sends the fourth time synchronization frame to the controller, so that the controller can correct the residence delay and link delay based on the fourth time synchronization frame, execute the synchronization algorithm, and complete the time synchronization with the master clock device. Each slave clock device only performs time synchronization once.

[0162] In unidirectional mode, the master clock device has the ability to send time synchronization frames (fourth time synchronization frames) in the inbound direction. The fourth time synchronization frame can synchronize the slave clock devices in the inbound direction, ensuring that the synchronization path of the devices before the master clock device (i.e., the devices from the master clock device to the controller) is the shortest, thereby improving the accuracy of time synchronization.

[0163] In the embodiment of the present application, the time synchronization frame is supported to be transmitted in the loopback mode and the unidirectional mode. In the loopback mode, the controller transmits the time synchronization frame outbound. When the time synchronization frame reaches the master clock device twice, the master clock device updates the valid master clock timestamp in the time synchronization frame twice. The slave clock device receives the time synchronization frame carrying the valid master clock timestamp, corrects the resident delay and link delay, executes the synchronization algorithm, and completes the time synchronization with the master clock device. In the loopback mode, the problem that the device before the master clock device affects the synchronization accuracy due to the long loopback transmission path of the time synchronization frame can be solved, and the device before the master clock device is guaranteed to use the latest synchronization time, thereby improving the accuracy of time synchronization; in the unidirectional mode, the controller transmits the time synchronization frame outbound, and synchronizes the slave clock devices in the outbound direction in turn. When the time synchronization frame arrives at the destination device, after performing the elimination operation of the unidirectional frame, the master clock device has the ability to send the time synchronization frame to the inbound direction. In the unidirectional mode, the synchronization path of the device before the master clock device (i.e., the device from the master clock device to the controller) can be guaranteed to be the shortest, thereby improving the accuracy of time synchronization.

[0164] Based on any of the above embodiments, in the embodiment of the present application, each port in the master clock device and the slave clock device is used to send a link delay measurement frame to make the master-slave clock synchronization path consistent with the shortest physical communication path. The link delay measurement frame is used to measure the link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

[0165] In an embodiment of the present application, each port in the master clock device and the slave clock device can send link delay measurement frames to neighboring devices point-to-point, so that each port of the device can obtain the link delay value with the neighboring device and store it inside the device.

[0166] like Fig. 9 and Fig.10 , respectively, are the link delay measurement processes under simple single-layer topology and complex multi-layer topology. The controller and each port of each industrial device can send link delay measurement frames to neighboring devices point-to-point, where the requester sends a delay request (Delay-req) to the responder. After receiving the delay request, the responder sends a delay response (Delay-rsp service) to the requester. Thus, the requester obtains the four timestamps required for link delay calculation (sending time of delay request, receiving time of delay request, receiving time of delay response, and sending time of delay response). The requester device executes the link delay algorithm to obtain the link delay value between each port and the neighboring device.

[0167] In an embodiment of the present application, each port in the master clock device and the slave clock device stores a link delay value with the neighboring device. In a ring and multi-path network, the time synchronization frame can seamlessly change the transmission path to ensure that the master-slave clock synchronization path can be changed in multiple ways according to the corresponding shortest physical communication path.

[0168] In the related technology, EtherCAT time synchronization adopts a distributed clock (DC) mechanism. Under the DC synchronization mechanism, the reference clock reads its own time and writes it into the message, and other slave stations read the time from the message for synchronization. The controller or the first slave station device serves as the system master clock, and the link delay is measured and calculated by the controller. In this way, there are problems such as the link delay measurement frame can only be initiated by the controller, the master clock timestamp in the time synchronization frame lacks an update mechanism, the transmission path of the time synchronization frame is single and the transmission path is not optimal, which cannot meet the time synchronization requirements of complex scenarios.

[0169] In the above embodiments of the present application, each port in the master clock device and the slave clock device stores a link delay value with the neighboring device. In a ring and multi-path network, the time synchronization frame can seamlessly change the transmission path, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode. In the loopback mode, it can ensure that the device before the master clock device uses the latest synchronization time. In the unidirectional mode, it can ensure that the synchronization path of the device before the master clock device is the shortest, thereby improving the accuracy and flexibility of time synchronization.

[0170] Optionally, after the slave clock device performs time synchronization with the master clock device based on the time synchronization frame, the slave clock device can also obtain the Allen variance curve corresponding to the slave clock device according to the time after the synchronization of the slave clock device, and determine the influencing factors affecting the clock frequency stability of the slave clock device based on the Allen variance curve, which is used to detect overall problems in the environment.

[0171] The measurement of standard deviation (Allen variance) can be used to detect overall problems in the environment. The Allan variance curve inside a single slave clock device can be used to analyze the clock frequency stability in the time domain. Frequency stability is a measure of the degree to which the frequency of an oscillator or clock in a slave clock device remains constant over a specified time interval. It plays a vital role in many fields such as communications, navigation, radar, etc., and can detect frequency changes caused by oscillations, drift, random noise, etc.

[0172] In the embodiment of the present application, the slave clock device can also calculate the Allen variance according to the time after the slave clock device is synchronized to obtain the Allen variance curve, and obtain the operating state of the crystal frequency stability of the slave clock device from the Allen variance curve. According to the Allen variance curve, the influencing factors of the frequency stability can be determined, and the degree of influence of extreme thermal fluctuations and vibrations on the clock can be found. If the standard deviation is compared with the jitter element of the clock in the slave clock device, the influence of extreme thermal fluctuations and shocks on the clock can also be found, and a more fine-grained indicator analysis can be performed through the Allen variance curve.

[0173] In one embodiment, based on any of the above embodiments, in this embodiment, the current transmission mode may also correspond to a redundant clock synchronization path, and the master clock device may also send redundant time synchronization frames to the slave clock device based on the redundant clock synchronization path corresponding to the transmission mode. In this way, when there is a failure in the master-slave clock synchronization path, the redundant time synchronization frame is used for the slave clock device to synchronize time with the master clock device based on the redundant time synchronization frame.

[0174] In an embodiment of the present application, in order to save bandwidth resources in the industrial network, a redundant clock synchronization path can be configured. In the event of a failure in the master-slave clock synchronization path, the redundant clock synchronization path is used as an alternative clock synchronization path to synchronize the time between the slave clock device and the master clock device.

[0175] Optionally, multiple redundant clock synchronization paths may be configured. When a master-slave clock synchronization path fails, any redundant clock synchronization path that is not faulty may be selected from the multiple redundant clock synchronization paths to perform time synchronization between the slave clock device and the master clock device.

[0176] Optionally, when configuring multiple redundant clock synchronization paths, priorities can also be configured for the multiple redundant clock synchronization paths. When a fault occurs in the master-slave clock synchronization path, the redundant clock synchronization path with the highest priority and no faults is selected from the multiple redundant clock synchronization paths to perform time synchronization between the slave clock device and the master clock device, and so on.

[0177] A fault in the master-slave clock synchronization path may refer to the presence of a faulty device or a connection error in the master-slave clock synchronization path, that is, the presence of a faulty device or a link failure. The embodiment of the present application configures a redundant clock synchronization path to allow seamless switching of the clock synchronization path for synchronization configuration in the event of a connection or node error.

[0178] In the following, the identification of a faulty device is exemplarily introduced by taking the case where the master-slave clock synchronization path includes a faulty device as an example.

[0179] In the embodiment of the present application, the faulty device is determined during the process of measuring link delays between the faulty device and a neighboring device of the faulty device.

[0180] Exemplarily, the time interval between two consecutive link delay measurement frames sent by the faulty device is inconsistent with the time interval between two consecutive link delay measurement frames sent by the neighboring device.

[0181] Since the sending rate of the delay request and the delay response is fixed, that is, for a slave clock device, the time for sending two delay request frames is fixed. For example, the time for slave clock device 1 to send two delay requests is t1 and t1' respectively, and the time for slave clock device 2 to send two delay responses is t2 and t2' respectively. If t1-t1' is not equal to t2-t2', the faulty slave clock device can be identified.

[0182] In the embodiment of the present application, the reported errors obtained by each slave clock device performing link delay measurement can be used to identify the erroneous device.

[0183] In this way, by identifying the faulty device, when the master-slave clock synchronization path fails, the slave clock device can quickly synchronize time with the master clock device based on the redundant time synchronization frame, ensuring the smooth time synchronization of the slave clock device and improving the stability of time synchronization.

[0184] In one embodiment, the selection process of the master clock device is described below by way of example. In the embodiment of the present application, the controller selects the optimal master clock device.

[0185] Optionally, the controller may also determine the master clock device according to the clock frequency stability parameters and position parameters of each industrial device in the industrial network.

[0186] In an embodiment of the present application, the optimal master clock selection algorithm is integrated in the controller, and the controller directly selects the master clock device based on the optimal master clock selection algorithm, which can avoid the problems of slow convergence and slow selection caused by competition between slave clock devices for the master clock device, and ensure fast selection of the master clock device.

[0187] Exemplarily, the controller can obtain the clock frequency stability parameters and position parameters of each industrial device in the industrial network (each industrial device includes the controller and each industrial device connected to the controller). The clock frequency stability parameters of the industrial equipment are inherent attribute parameters of the clock of the industrial equipment. The clock frequency stability parameters are used to characterize the frequency characteristics of the crystal oscillator of the industrial equipment (or called clock accuracy). The unit is PPM (Parts Per Million). For example, 20PPM means that the clock of the industrial equipment has an error of 20 parts per million.

[0188] Then, the controller determines the selection range of the master clock device based on the location parameters of each industrial device and the topological structure of the industrial network. For example, in the case of a single-level topology, all industrial devices in the single-level topology are within the selection range. In a multi-level topology, the first branch device in the multi-level topology and the devices before the first branch device are within the selection range.

[0189] See also Fig.11 and Fig.12 , Fig.11 This is a schematic diagram of the selection range of the master clock device in a single-level topology. Fig.12 Schematic diagram of the selection range of master clock devices in a multi-level topology. Fig.11 In the single-layer topology, all industrial devices are candidates for master clock devices and participate in the selection process of the master clock device. Fig.12 In the process, the first branch device (industrial device 2) and the devices before the first branch device (controller and industrial device 1) are candidate master clock devices and participate in the selection process of the master clock device.

[0190] In this way, the controller continues to select the master clock device from the selection range of the determined master clock device. As mentioned above, in the case of a single-layer topology of the industrial network, all industrial devices in the single-layer topology are within the selection range. In a multi-layer topology, the first branch device in the multi-layer topology and the industrial devices before the first branch device are within the selection range. The controller can compare the size of the clock frequency stability parameters of each candidate master clock device within the selection range. The smaller the clock frequency stability parameter, the better the clock frequency stability of the candidate master clock device. The controller selects the industrial device with the smallest clock frequency stability parameter (i.e., the best clock frequency stability) from among the candidate master clock devices within the selection range as the master clock device.

[0191] Therefore, when the industrial network has a single-layer topology, if there is only one industrial device with the smallest clock frequency stability parameter among all industrial devices in the single-layer topology, then this industrial device is determined as the master clock device. When the industrial network has a multi-layer topology, if there is only one industrial device with the smallest clock frequency stability parameter among the first branch device and the devices before the first branch device in the multi-layer topology, then this industrial device is also determined as the master clock device.

[0192] It is understandable that the controller may also find multiple industrial devices with the smallest clock frequency stability parameters within the selection range. In this case, the controller needs to select one industrial device from the multiple industrial devices with the smallest clock frequency stability parameters as the main clock device based on a certain selection strategy.

[0193] Optionally, in the case where the industrial network has a single-layer topology, if there are multiple industrial devices with the smallest clock frequency stability parameter among the industrial devices, then according to the location parameters of the multiple industrial devices, the industrial device with the smallest distance from the topological center of the single-layer topology among the multiple industrial devices is determined as the master clock device. Fig.11 For example, industrial device 2 is the topological center of the single-layer topology. If the clock frequency stability parameters of the controller and industrial device 1 are both the smallest, since the distance between industrial device 1 and industrial device 2 is the smallest, industrial device 1 is used as the master clock device. In this way, during the time synchronization process, the master clock device is closer to each slave clock device, which is beneficial to improve the accuracy of time synchronization.

[0194] Optionally, in the case of a multi-level industrial network topology, if there are multiple industrial devices with the smallest clock frequency stability parameters among the first branch device and the devices before the first branch device, then according to the location parameters of the multiple industrial devices, the industrial device with the smallest distance from the first branch device among the multiple industrial devices is determined as the main clock device. Fig.12For example, if the clock frequency stability parameters of the controller and industrial equipment 1 are both the smallest, since the distance between industrial equipment 1 and the first branch device (industrial equipment 2) is the smallest, industrial equipment 1 will be used as the master clock device; and if the clock frequency stability parameters of the controller, industrial equipment 1 and industrial equipment 2 are all the smallest, since the distance between industrial equipment 2 and the first branch device (industrial equipment 2) is 0, that is, the distance is the smallest, industrial equipment 2 will be used as the master clock device. In this way, during the time synchronization process, the master clock device is closer to each slave clock device, which is beneficial to improving the accuracy of time synchronization.

[0195] In the embodiment of the present application, if the master clock device is a controller in an industrial network, it can be understood that when the industrial network is a single-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among all industrial devices, and when the industrial network is a multi-layer topology, the controller is the first branch device in the multi-layer topology and the devices before the first branch device. The industrial device with the smallest clock frequency stability parameter. Figure 3 In the embodiment shown, the master clock device generates a time synchronization frame and sends the time synchronization frame to the slave clock device based on the master-slave clock synchronization path corresponding to the current transmission mode.

[0196] If the master clock device is not a controller in the industrial network, then the controller outputs a transmission time synchronization frame. After the time synchronization frame reaches the master clock device (referred to as the first time synchronization frame here), the master clock device updates the timestamp in the first time synchronization frame to obtain a second time synchronization frame, and then sends the second time synchronization frame to the slave clock device.

[0197] In this way, the controller directly selects the master clock device based on the clock frequency stability parameters of each industrial device, which can avoid the problems of slow convergence and slow selection caused by the competition of the slave clock devices for the master clock device, and ensure the rapid selection of the master clock device.

[0198] Optionally, when the master clock device is different from the controller and the master clock device fails, the controller may also determine a redundant master clock based on clock frequency stability parameters and position parameters of other industrial devices except the master clock device.

[0199] When the controller detects a failure in the master clock device, it can quickly and seamlessly switch to the redundant master clock based on the clock frequency stability parameters within the optional range of the master clock device to ensure smooth clock synchronization.

[0200] In the related technology, PROFINET-PTCP time synchronization adopts the Precision Transparent Clock Protocol (PTCP) synchronization mechanism. In the PTCP synchronization mechanism, both the master station and the slave station can serve as master clock devices. The master station and the slave station initiate Announce frames to compete for the best master clock. This method has the problems of difficulty in selecting the master clock and complex master clock switching process.

[0201] In an embodiment of the present application, the controller can quickly select a master clock device. In the event of a failure in the master clock device, the controller can quickly switch to a redundant master clock, thereby solving the problems of difficult switching of the master clock device and complex switching process, improving the accuracy of time synchronization and the flexibility of synchronization information transmission, and significantly improving the performance of time synchronization.

[0202] In one embodiment, Fig.13 As shown, a time synchronization method is provided, which is described by taking the method applied to a slave clock device in an industrial network as an example, and includes the following steps:

[0203] Step 1301: In the current transmission mode, a time synchronization frame sent by a master clock device in an industrial network is received.

[0204] Step 1302: Perform time synchronization with a master clock device based on a time synchronization frame.

[0205] The time synchronization frame is sent by the master clock device to the slave clock device based on the master-slave clock synchronization path corresponding to the transmission mode, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0206] In one of the embodiments, each port in the master clock device and the slave clock device is used to send a link delay measurement frame, so that the master-slave clock synchronization path is consistent with the shortest physical communication path;

[0207] The link delay measurement frame is used to measure the link delay value, and the link delay value is used to synchronize the time between the slave clock device and the master clock device.

[0208] In one embodiment, the method further comprises:

[0209] A redundant time synchronization frame is received from a master clock device based on a redundant clock synchronization path corresponding to a transmission mode, wherein the redundant time synchronization frame is used to perform time synchronization with the master clock device based on the redundant time synchronization frame when a failure occurs in the master-slave clock synchronization path.

[0210] In one of the embodiments, when the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and neighboring devices of the faulty device.

[0211] In one of the embodiments, the time interval between two consecutive transmissions of link delay measurement frames by the faulty device is inconsistent with the time interval between two consecutive transmissions of link delay measurement frames by the neighboring device.

[0212] In one embodiment, after performing time synchronization with a master clock device based on a time synchronization frame, the method further includes:

[0213] According to the time after synchronization of the slave clock device, obtaining an Allen variance curve corresponding to the slave clock device;

[0214] Based on the Allan variance curve, the factors affecting the clock frequency stability of the slave clock device are determined, and the influencing factors are used to detect overall problems in the environment.

[0215] Regarding the implementation and beneficial effects of the time synchronization method for a slave clock device, reference may be made to the relevant description in the above embodiment of the time synchronization method for a master clock device, which will not be repeated here.

[0216] In one embodiment, Fig.14 As shown, a time synchronization method is provided, which is described by taking the method applied to a controller in an industrial network as an example, and includes the following steps:

[0217] Step 1401, determine the master clock device according to the clock frequency stability parameters and position parameters of each industrial device in the industrial network, the master clock device is used to send time synchronization frames to the slave clock devices in the industrial network under a preset transmission mode and based on the master-slave clock synchronization path corresponding to the transmission mode; the time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0218] In one embodiment, determining a master clock device according to clock frequency stability parameters and location parameters of each industrial device in an industrial network includes:

[0219] In the case where the industrial network has a single-layer topology, if there is only one industrial device with the smallest clock frequency stability parameter among the industrial devices, then one industrial device is determined as the master clock device;

[0220] If there are multiple industrial devices with the smallest clock frequency stability parameters among the multiple industrial devices, the industrial device with the smallest distance from the topological center of the single-layer topology among the multiple industrial devices is determined as the main clock device according to the location parameters of the multiple industrial devices.

[0221] In one embodiment, determining a master clock device according to clock frequency stability parameters and location parameters of each industrial device in an industrial network includes:

[0222] In the case where the industrial network has a multi-level topology, if there is only one industrial device with the smallest clock frequency stability parameter among the first branch device and the devices before the first branch device in the multi-level topology, then one industrial device is determined as the master clock device;

[0223] If there are multiple industrial devices with the smallest clock frequency stability parameters among the first branch device and the devices before the first branch device, the industrial device with the smallest distance from the first branch device among the multiple industrial devices is determined as the main clock device according to the location parameters of the multiple industrial devices.

[0224] In one embodiment, the method further comprises:

[0225] In the case that the master clock device is different from the controller and fails, a redundant master clock is determined according to clock frequency stability parameters and position parameters of other industrial devices except the master clock device in each industrial device.

[0226] Regarding the implementation and beneficial effects of the time synchronization method for a controller, reference may be made to the relevant description in the above embodiment of the time synchronization method for a master clock device, which will not be repeated here.

[0227] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0228] Based on the same technical concept, the embodiment of the present application also provides a time synchronization device, which can implement the functions of the master clock device side in the above embodiment.

[0229] In an exemplary embodiment, Fig.15 As shown, a time synchronization device is provided, which is used for a master clock device in an industrial network, including:

[0230] The sending module 1501 is used to send a time synchronization frame to a slave clock device in the industrial network based on a master-slave clock synchronization path corresponding to the transmission mode in the current transmission mode;

[0231] The time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0232] In one embodiment, the sending module 1501 includes:

[0233] A receiving unit, configured to receive a first time synchronization frame in an outbound direction of a controller in the industrial network when the transmission mode is a loopback mode or a unidirectional mode, and update a timestamp in the first time synchronization frame to obtain a second time synchronization frame;

[0234] A sending unit is used to send the second time synchronization frame to the slave clock device in the outbound direction based on the first master-slave clock synchronization path corresponding to the loopback mode or the second master-slave clock synchronization path corresponding to the unidirectional mode.

[0235] In one embodiment, the sending module 1501 further includes:

[0236] An updating module, configured to update a timestamp in a received time synchronization frame in an inbound direction of the controller to obtain a third time synchronization frame when the transmission mode is the loopback mode;

[0237] The sending unit is further configured to send the third time synchronization frame to the slave clock device in the inbound direction based on the first master-slave clock synchronization path.

[0238] In one embodiment, the sending module 1501 further includes:

[0239] A generating module, configured to generate a fourth time synchronization frame in an inbound direction of the controller when the transmission mode is the unidirectional mode;

[0240] The sending unit is further configured to send the fourth time synchronization frame to the slave clock device in the inbound direction based on the second master-slave clock synchronization path.

[0241] In one of the embodiments, each port in the master clock device and the slave clock device is respectively used to send a link delay measurement frame so that the master-slave clock synchronization path is consistent with the shortest physical communication path;

[0242] The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

[0243] In one of the embodiments, the sending module 1501 is also used to send redundant time synchronization frames to the slave clock device based on the redundant clock synchronization path corresponding to the transmission mode. In the event of a failure in the master-slave clock synchronization path, the redundant time synchronization frame is used for the slave clock device to perform time synchronization with the master clock device based on the redundant time synchronization frame.

[0244] In one of the embodiments, when the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

[0245] In one of the embodiments, the time interval between two consecutive transmissions of link delay measurement frames by the faulty device is inconsistent with the time interval between two consecutive transmissions of link delay measurement frames by the neighboring device.

[0246] In one embodiment, the device further comprises:

[0247] A determination module, configured to determine, based on the clock frequency stability parameters and position parameters of each industrial device in the industrial network, that a controller in the industrial network is the master clock device;

[0248] Among them, when the industrial network is a single-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among all the industrial devices; when the industrial network is a multi-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among the first branch device in the multi-layer topology and the devices before the first branch device.

[0249] It should be noted here that the above-mentioned time synchronization device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned time synchronization method embodiment for the master clock device, and can achieve the same technical effect. The parts and beneficial effects that are the same as the method embodiment in this embodiment will not be specifically repeated here. Each module in the above-mentioned time synchronization device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the master clock device in the form of hardware, or can be stored in the memory in the master clock device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0250] Based on the same technical concept, the embodiment of the present application also provides a time synchronization device, which can implement the functions of the slave clock device in the above embodiment.

[0251] In an exemplary embodiment, Fig.16 As shown, a time synchronization device is provided, which is used for a slave clock device in an industrial network, including:

[0252] The receiving module 1601 is used to receive a time synchronization frame sent by a master clock device in the industrial network in the current transmission mode;

[0253] A synchronization module 1602, configured to perform time synchronization with the master clock device based on the time synchronization frame;

[0254] The time synchronization frame is sent by the master clock device to the slave clock device based on the master-slave clock synchronization path corresponding to the transmission mode, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0255] In one of the embodiments, each port in the master clock device and the slave clock device is respectively used to send a link delay measurement frame so that the master-slave clock synchronization path is consistent with the shortest physical communication path;

[0256] The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

[0257] In one embodiment, the receiving module 1601 is also used to receive a redundant time synchronization frame sent by the master clock device based on a redundant clock synchronization path corresponding to the transmission mode, wherein the redundant time synchronization frame is used to perform time synchronization with the master clock device based on the redundant time synchronization frame when a failure occurs in the master-slave clock synchronization path.

[0258] In one of the embodiments, when the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

[0259] In one of the embodiments, the time interval between two consecutive transmissions of link delay measurement frames by the faulty device is inconsistent with the time interval between two consecutive transmissions of link delay measurement frames by the neighboring device.

[0260] In one embodiment, the device further comprises:

[0261] The analysis module is used to obtain the Allen variance curve corresponding to the slave clock device according to the time after the synchronization of the slave clock device after the synchronization module 1602 performs time synchronization with the master clock device based on the time synchronization frame, and determine the influencing factors affecting the stability of the clock frequency of the slave clock device based on the Allen variance curve, and the influencing factors are used to detect overall problems in the environment.

[0262] It should be noted that the above-mentioned time synchronization device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned time synchronization method embodiment for the slave clock device, and can achieve the same technical effect. The parts and beneficial effects that are the same as the method embodiment in this embodiment will not be specifically repeated here. Each module in the above-mentioned time synchronization device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the slave clock device in the form of hardware, or can be stored in the memory in the slave clock device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0263] Based on the same technical concept, the embodiment of the present application further provides a time synchronization device, which can implement the functions of the controller side in the above embodiment.

[0264] In an exemplary embodiment, Fig.17 As shown, a time synchronization device is provided for a controller in an industrial network, comprising:

[0265] A determination module 1701 is used to determine a master clock device according to a clock frequency stability parameter and a position parameter of each industrial device in the industrial network;

[0266] Among them, the master clock device is used to send time synchronization frames to the slave clock devices in the industrial network under a preset transmission mode based on the master-slave clock synchronization path corresponding to the transmission mode; the time synchronization frame is used for the slave clock device to synchronize time with the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0267] In one embodiment, the determination module 1701 is specifically used for, when the industrial network is a single-layer topology, if there is only one industrial device with the smallest clock frequency stability parameter among the industrial devices, determining one of the industrial devices as the master clock device;

[0268] If there are multiple industrial devices with the smallest clock frequency stability parameters among the multiple industrial devices, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the topological center position of the single-layer topology among the multiple industrial devices is determined as the master clock device.

[0269] In one embodiment, the determination module 1701 is specifically used for determining one of the industrial devices as the master clock device when the industrial network is a multi-level topology and if there is one industrial device with the smallest clock frequency stability parameter among the first branch device and the devices before the first branch device in the multi-level topology;

[0270] If there are multiple industrial devices with the smallest clock frequency stability parameters among the first branch device and the devices before the first branch device, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the first branch device among the multiple industrial devices is determined as the master clock device.

[0271] In one embodiment, the determination module 1701 is also used to determine a redundant master clock based on clock frequency stability parameters and position parameters of other industrial devices in each of the industrial devices except the master clock device when the master clock device is different from the controller and the master clock device fails.

[0272] It should be noted here that the above-mentioned time synchronization device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned time synchronization method embodiment for the controller, and can achieve the same technical effect. The parts and beneficial effects that are the same as those in the method embodiment in this embodiment will not be specifically repeated here. Each module in the above-mentioned time synchronization device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the controller in the form of hardware, or can be stored in the memory in the controller in the form of software, so that the processor can call and execute the operations corresponding to the above-mentioned modules.

[0273] Fig.18 The schematic diagram of the structure of an industrial device provided in an embodiment of the present application is as follows. The industrial device may include a processor 1800, a transceiver 1810 and a memory 1820. The transceiver 1810 is used to receive and send data under the control of the processor 1800.

[0274] Among them, Fig.18In the embodiment of the present invention, the bus architecture may include any number of interconnected buses and bridges, specifically linking together various circuits of one or more processors represented by processor 1800 and memory represented by memory 1820. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface.

[0275] The transceiver 1810 may be a plurality of elements, i.e., include a transmitter and a receiver, and provide a unit for communicating with various other devices on a transmission medium, such as a wireless channel, a wired channel, an optical cable, etc. The processor 1800 is responsible for managing the bus architecture and general processing, and the memory 1820 may store data used by the processor 1800 when performing operations.

[0276] The processor 1800 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or a complex programmable logic device (CPLD). The processor 1800 may also adopt a multi-core architecture.

[0277] Optionally, the industrial device may be a master clock device, and the processor 1800 is configured to execute the following steps according to the obtained executable instructions by calling a computer program stored in the memory 1820:

[0278] In the current transmission mode, based on the master-slave clock synchronization path corresponding to the transmission mode, control the transceiver 1810 to send a time synchronization frame to a slave clock device in the industrial network;

[0279] The time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0280] In one embodiment, the processor 1800 is specifically configured to perform the following operations:

[0281] When the transmission mode is a loopback mode or a unidirectional mode, in the outbound direction of the controller in the industrial network, controlling the transceiver 1810 to receive a first time synchronization frame, and updating a timestamp in the first time synchronization frame to obtain a second time synchronization frame;

[0282] Based on the first master-slave clock synchronization path corresponding to the loopback mode or the second master-slave clock synchronization path corresponding to the unidirectional mode, the transceiver 1810 is controlled to send the second time synchronization frame to the slave clock device in the outbound direction.

[0283] In one embodiment, the processor 1800 is further configured to perform the following operations:

[0284] When the transmission mode is the loopback mode, in the inbound direction of the controller, updating the timestamp in the received time synchronization frame to obtain a third time synchronization frame;

[0285] Based on the first master-slave clock synchronization path, the transceiver 1810 is controlled to send the third time synchronization frame to the slave clock device in the inbound direction.

[0286] In one embodiment, the processor 1800 is further configured to perform the following operations:

[0287] When the transmission mode is the unidirectional mode, generating a fourth time synchronization frame in an inbound direction of the controller;

[0288] Based on the second master-slave clock synchronization path, the transceiver 1810 is controlled to send the fourth time synchronization frame to the slave clock device in the inbound direction.

[0289] In one of the embodiments, each port in the master clock device and the slave clock device is respectively used to send a link delay measurement frame so that the master-slave clock synchronization path is consistent with the shortest physical communication path;

[0290] The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

[0291] In one embodiment, the processor 1800 is further configured to perform the following operations:

[0292] Based on the redundant clock synchronization path corresponding to the transmission mode, the transceiver 1810 is controlled to send a redundant time synchronization frame to the slave clock device. In the event of a failure in the master-slave clock synchronization path, the redundant time synchronization frame is used for the slave clock device to perform time synchronization with the master clock device based on the redundant time synchronization frame.

[0293] In one of the embodiments, when the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

[0294] In one of the embodiments, the time interval between two consecutive transmissions of link delay measurement frames by the faulty device is inconsistent with the time interval between two consecutive transmissions of link delay measurement frames by the neighboring device.

[0295] In one embodiment, the processor 1800 is further configured to perform the following operations:

[0296] Determining a controller in the industrial network as the master clock device according to a clock frequency stability parameter and a position parameter of each industrial device in the industrial network;

[0297] Among them, when the industrial network is a single-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among all the industrial devices; when the industrial network is a multi-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among the first branch device in the multi-layer topology and the devices before the first branch device.

[0298] Optionally, the industrial device may be a slave clock device, and the processor 1800 calls a computer program stored in the memory 1820 to execute the following steps according to the obtained executable instructions:

[0299] In the current transmission mode, controlling the transceiver 1810 to receive a time synchronization frame sent by a master clock device in the industrial network;

[0300] Based on the time synchronization frame, performing time synchronization with the master clock device;

[0301] The time synchronization frame is sent by the master clock device to the slave clock device based on the master-slave clock synchronization path corresponding to the transmission mode, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0302] In one of the embodiments, each port in the master clock device and the slave clock device is respectively used to send a link delay measurement frame so that the master-slave clock synchronization path is consistent with the shortest physical communication path;

[0303] The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

[0304] In one embodiment, the processor 1800 is further configured to perform the following operations:

[0305] Control the transceiver 1810 to receive the redundant time synchronization frame sent by the master clock device based on the redundant clock synchronization path corresponding to the transmission mode, wherein the redundant time synchronization frame is used to perform time synchronization with the master clock device based on the redundant time synchronization frame when a failure occurs in the master-slave clock synchronization path.

[0306] In one of the embodiments, when the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

[0307] In one of the embodiments, the time interval between two consecutive transmissions of link delay measurement frames by the faulty device is inconsistent with the time interval between two consecutive transmissions of link delay measurement frames by the neighboring device.

[0308] In one embodiment, the processor 1800 is further configured to perform the following operations:

[0309] Acquire an Allan variance curve corresponding to the slave clock device according to the time after synchronization of the slave clock device;

[0310] Based on the Allan variance curve, influencing factors affecting the stability of the clock frequency of the slave clock device are determined, and the influencing factors are used to detect overall problems in the environment.

[0311] Optionally, the industrial device may be a controller, and the processor 1800 calls a computer program stored in the memory 1820 to execute the following steps according to the obtained executable instructions:

[0312] Determine a master clock device according to clock frequency stability parameters and position parameters of each industrial device in the industrial network;

[0313] Among them, the master clock device is used to send time synchronization frames to the slave clock devices in the industrial network under a preset transmission mode based on the master-slave clock synchronization path corresponding to the transmission mode; the time synchronization frame is used for the slave clock device to synchronize time with the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0314] In one embodiment, the processor 1800 is specifically configured to perform the following operations:

[0315] In the case where the industrial network is a single-layer topology, if there is only one industrial device with the smallest clock frequency stability parameter among the industrial devices, then one of the industrial devices is determined as the master clock device;

[0316] If there are multiple industrial devices with the smallest clock frequency stability parameters among the multiple industrial devices, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the topological center position of the single-layer topology among the multiple industrial devices is determined as the master clock device.

[0317] In one embodiment, the processor 1800 is specifically configured to perform the following operations:

[0318] In the case where the industrial network is a multi-level topology, if there is one industrial device with the smallest clock frequency stability parameter among the first branch device and the devices before the first branch device in the multi-level topology, one of the industrial devices is determined as the master clock device;

[0319] If there are multiple industrial devices with the smallest clock frequency stability parameters among the first branch device and the devices before the first branch device, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the first branch device among the multiple industrial devices is determined as the master clock device.

[0320] In one embodiment, the processor 1800 is further configured to perform the following operations:

[0321] In the case that the master clock device is different from the controller and the master clock device fails, a redundant master clock is determined according to clock frequency stability parameters and position parameters of other industrial devices among the industrial devices except the master clock device.

[0322] In one embodiment, a computer-readable storage medium is provided, which can be any available medium or data storage device that can be accessed by a processor, including but not limited to magnetic storage (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical storage (such as CDs, DVDs, BDs, HVDs, etc.), and semiconductor storage (such as ROMs, EPROMs, EEPROMs, non-volatile memories (NAND FLASH), solid-state drives (SSDs)), etc.

[0323] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0324] In the current transmission mode, based on the master-slave clock synchronization path corresponding to the transmission mode, sending a time synchronization frame to a slave clock device in the industrial network;

[0325] The time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0326] In one embodiment, when the computer program is executed by a processor, the following steps are specifically implemented:

[0327] When the transmission mode is a loopback mode or a unidirectional mode, in the outbound direction of the controller in the industrial network, a first time synchronization frame is received, and a timestamp in the first time synchronization frame is updated to obtain a second time synchronization frame;

[0328] Based on the first master-slave clock synchronization path corresponding to the loopback mode or the second master-slave clock synchronization path corresponding to the unidirectional mode, the second time synchronization frame is sent to the slave clock device in the outbound direction.

[0329] In one embodiment, when the computer program is executed by a processor, the following steps are specifically implemented:

[0330] When the transmission mode is the loopback mode, in the inbound direction of the controller, updating the timestamp in the received time synchronization frame to obtain a third time synchronization frame;

[0331] Based on the first master-slave clock synchronization path, the third time synchronization frame is sent to the slave clock device in the inbound direction.

[0332] In one embodiment, when the computer program is executed by a processor, the following steps are specifically implemented:

[0333] When the transmission mode is the unidirectional mode, generating a fourth time synchronization frame in an inbound direction of the controller;

[0334] Based on the second master-slave clock synchronization path, the fourth time synchronization frame is sent to the slave clock device in the inbound direction.

[0335] In one of the embodiments, each port in the master clock device and the slave clock device is respectively used to send a link delay measurement frame so that the master-slave clock synchronization path is consistent with the shortest physical communication path;

[0336] The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

[0337] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0338] Based on the redundant clock synchronization path corresponding to the transmission mode, a redundant time synchronization frame is sent to the slave clock device. In the event of a failure in the master-slave clock synchronization path, the redundant time synchronization frame is used for the slave clock device to perform time synchronization with the master clock device based on the redundant time synchronization frame.

[0339] In one of the embodiments, when the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

[0340] In one of the embodiments, the time interval between two consecutive transmissions of link delay measurement frames by the faulty device is inconsistent with the time interval between two consecutive transmissions of link delay measurement frames by the neighboring device.

[0341] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0342] Determining a controller in the industrial network as the master clock device according to a clock frequency stability parameter and a position parameter of each industrial device in the industrial network;

[0343] Among them, when the industrial network is a single-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among all the industrial devices; when the industrial network is a multi-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among the first branch device in the multi-layer topology and the devices before the first branch device.

[0344] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0345] In the current transmission mode, receiving a time synchronization frame sent by a master clock device in the industrial network;

[0346] Based on the time synchronization frame, performing time synchronization with the master clock device;

[0347] The time synchronization frame is sent by the master clock device to the slave clock device based on the master-slave clock synchronization path corresponding to the transmission mode, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0348] In one of the embodiments, each port in the master clock device and the slave clock device is respectively used to send a link delay measurement frame so that the master-slave clock synchronization path is consistent with the shortest physical communication path;

[0349] The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

[0350] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0351] Receive a redundant time synchronization frame sent by the master clock device based on a redundant clock synchronization path corresponding to the transmission mode, wherein the redundant time synchronization frame is used to perform time synchronization with the master clock device based on the redundant time synchronization frame when a failure occurs in the master-slave clock synchronization path.

[0352] In one of the embodiments, when the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

[0353] In one of the embodiments, the time interval between two consecutive transmissions of link delay measurement frames by the faulty device is inconsistent with the time interval between two consecutive transmissions of link delay measurement frames by the neighboring device.

[0354] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0355] Acquire an Allan variance curve corresponding to the slave clock device according to the time after synchronization of the slave clock device;

[0356] Based on the Allan variance curve, influencing factors affecting the stability of the clock frequency of the slave clock device are determined, and the influencing factors are used to detect overall problems in the environment.

[0357] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0358] Determine a master clock device according to clock frequency stability parameters and position parameters of each industrial device in the industrial network;

[0359] Among them, the master clock device is used to send time synchronization frames to the slave clock devices in the industrial network under a preset transmission mode based on the master-slave clock synchronization path corresponding to the transmission mode; the time synchronization frame is used for the slave clock device to synchronize time with the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0360] In one embodiment, when the computer program is executed by a processor, the following steps are specifically implemented:

[0361] In the case where the industrial network is a single-layer topology, if there is only one industrial device with the smallest clock frequency stability parameter among the industrial devices, then one of the industrial devices is determined as the master clock device;

[0362] If there are multiple industrial devices with the smallest clock frequency stability parameters among the multiple industrial devices, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the topological center position of the single-layer topology among the multiple industrial devices is determined as the master clock device.

[0363] In one embodiment, when the computer program is executed by a processor, the following steps are specifically implemented:

[0364] In the case where the industrial network is a multi-level topology, if there is one industrial device with the smallest clock frequency stability parameter among the first branch device and the devices before the first branch device in the multi-level topology, one of the industrial devices is determined as the master clock device;

[0365] If there are multiple industrial devices with the smallest clock frequency stability parameters among the first branch device and the devices before the first branch device, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the first branch device among the multiple industrial devices is determined as the master clock device.

[0366] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0367] In the case that the master clock device is different from the controller and the master clock device fails, a redundant master clock is determined according to clock frequency stability parameters and position parameters of other industrial devices among the industrial devices except the master clock device.

[0368] In one embodiment, a computer program product is provided, including a computer program, which, when executed by a processor, implements the following steps:

[0369] In the current transmission mode, based on the master-slave clock synchronization path corresponding to the transmission mode, sending a time synchronization frame to a slave clock device in the industrial network;

[0370] The time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0371] In one embodiment, when the computer program is executed by a processor, the following steps are specifically implemented:

[0372] When the transmission mode is a loopback mode or a unidirectional mode, in the outbound direction of the controller in the industrial network, a first time synchronization frame is received, and a timestamp in the first time synchronization frame is updated to obtain a second time synchronization frame;

[0373] Based on the first master-slave clock synchronization path corresponding to the loopback mode or the second master-slave clock synchronization path corresponding to the unidirectional mode, the second time synchronization frame is sent to the slave clock device in the outbound direction.

[0374] In one embodiment, when the computer program is executed by a processor, the following steps are specifically implemented:

[0375] When the transmission mode is the loopback mode, in the inbound direction of the controller, updating the timestamp in the received time synchronization frame to obtain a third time synchronization frame;

[0376] Based on the first master-slave clock synchronization path, the third time synchronization frame is sent to the slave clock device in the inbound direction.

[0377] In one embodiment, when the computer program is executed by a processor, the following steps are specifically implemented:

[0378] When the transmission mode is the unidirectional mode, generating a fourth time synchronization frame in an inbound direction of the controller;

[0379] Based on the second master-slave clock synchronization path, the fourth time synchronization frame is sent to the slave clock device in the inbound direction.

[0380] In one of the embodiments, each port in the master clock device and the slave clock device is respectively used to send a link delay measurement frame so that the master-slave clock synchronization path is consistent with the shortest physical communication path;

[0381] The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

[0382] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0383] Based on the redundant clock synchronization path corresponding to the transmission mode, a redundant time synchronization frame is sent to the slave clock device. In the event of a failure in the master-slave clock synchronization path, the redundant time synchronization frame is used for the slave clock device to perform time synchronization with the master clock device based on the redundant time synchronization frame.

[0384] In one of the embodiments, when the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

[0385] In one of the embodiments, the time interval between two consecutive transmissions of link delay measurement frames by the faulty device is inconsistent with the time interval between two consecutive transmissions of link delay measurement frames by the neighboring device.

[0386] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0387] Determining a controller in the industrial network as the master clock device according to a clock frequency stability parameter and a position parameter of each industrial device in the industrial network;

[0388] Among them, when the industrial network is a single-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among all the industrial devices; when the industrial network is a multi-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among the first branch device in the multi-layer topology and the devices before the first branch device.

[0389] In one embodiment, a computer program product is provided, including a computer program, which, when executed by a processor, implements the following steps:

[0390] In the current transmission mode, receiving a time synchronization frame sent by a master clock device in the industrial network;

[0391] Based on the time synchronization frame, performing time synchronization with the master clock device;

[0392] The time synchronization frame is sent by the master clock device to the slave clock device based on the master-slave clock synchronization path corresponding to the transmission mode, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0393] In one of the embodiments, each port in the master clock device and the slave clock device is respectively used to send a link delay measurement frame so that the master-slave clock synchronization path is consistent with the shortest physical communication path;

[0394] The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

[0395] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0396] Receive a redundant time synchronization frame sent by the master clock device based on a redundant clock synchronization path corresponding to the transmission mode, wherein the redundant time synchronization frame is used to perform time synchronization with the master clock device based on the redundant time synchronization frame when a failure occurs in the master-slave clock synchronization path.

[0397] In one of the embodiments, when the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

[0398] In one of the embodiments, the time interval between two consecutive transmissions of link delay measurement frames by the faulty device is inconsistent with the time interval between two consecutive transmissions of link delay measurement frames by the neighboring device.

[0399] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0400] Acquire an Allan variance curve corresponding to the slave clock device according to the time after synchronization of the slave clock device;

[0401] Based on the Allan variance curve, influencing factors affecting the stability of the clock frequency of the slave clock device are determined, and the influencing factors are used to detect overall problems in the environment.

[0402] In one embodiment, a computer program product is provided, including a computer program, which, when executed by a processor, implements the following steps:

[0403] Determine a master clock device according to clock frequency stability parameters and position parameters of each industrial device in the industrial network;

[0404] Among them, the master clock device is used to send time synchronization frames to the slave clock devices in the industrial network under a preset transmission mode based on the master-slave clock synchronization path corresponding to the transmission mode; the time synchronization frame is used for the slave clock device to synchronize time with the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

[0405] In one embodiment, when the computer program is executed by a processor, the following steps are specifically implemented:

[0406] In the case where the industrial network is a single-layer topology, if there is only one industrial device with the smallest clock frequency stability parameter among the industrial devices, then one of the industrial devices is determined as the master clock device;

[0407] If there are multiple industrial devices with the smallest clock frequency stability parameters among the multiple industrial devices, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the topological center position of the single-layer topology among the multiple industrial devices is determined as the master clock device.

[0408] In one embodiment, when the computer program is executed by a processor, the following steps are specifically implemented:

[0409] In the case where the industrial network is a multi-level topology, if there is one industrial device with the smallest clock frequency stability parameter among the first branch device and the devices before the first branch device in the multi-level topology, one of the industrial devices is determined as the master clock device;

[0410] If there are multiple industrial devices with the smallest clock frequency stability parameters among the first branch device and the devices before the first branch device, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the first branch device among the multiple industrial devices is determined as the master clock device.

[0411] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0412] In the case that the master clock device is different from the controller and the master clock device fails, a redundant master clock is determined according to clock frequency stability parameters and position parameters of other industrial devices among the industrial devices except the master clock device.

[0413] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0414] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0415] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A time synchronization method, characterized in that: For use in a master clock device in an industrial network, the method comprises: In the current transmission mode, based on the master-slave clock synchronization path corresponding to the transmission mode, sending a time synchronization frame to a slave clock device in the industrial network; The time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

2. The method according to claim 1, characterized in that The method of sending a time synchronization frame to a slave clock device in the industrial network based on a master-slave clock synchronization path corresponding to the transmission mode in the current transmission mode includes: When the transmission mode is a loopback mode or a unidirectional mode, in the outbound direction of the controller in the industrial network, a first time synchronization frame is received, and a timestamp in the first time synchronization frame is updated to obtain a second time synchronization frame; Based on the first master-slave clock synchronization path corresponding to the loopback mode or the second master-slave clock synchronization path corresponding to the unidirectional mode, the second time synchronization frame is sent to the slave clock device in the outbound direction.

3. The method according to claim 2, characterized in that The method further comprises: sending a time synchronization frame to a slave clock device in the industrial network based on a master-slave clock synchronization path corresponding to the transmission mode in the current transmission mode, and further comprising: When the transmission mode is the loopback mode, in the inbound direction of the controller, updating the timestamp in the received time synchronization frame to obtain a third time synchronization frame; Based on the first master-slave clock synchronization path, the third time synchronization frame is sent to the slave clock device in the inbound direction.

4. The method according to claim 2, characterized in that: The method further comprises: sending a time synchronization frame to a slave clock device in the industrial network based on a master-slave clock synchronization path corresponding to the transmission mode in the current transmission mode, and further comprising: When the transmission mode is the unidirectional mode, generating a fourth time synchronization frame in an inbound direction of the controller; Based on the second master-slave clock synchronization path, the fourth time synchronization frame is sent to the slave clock device in the inbound direction.

5. The method according to any one of claims 1 to 4, characterized in that: Each port in the master clock device and the slave clock device is used to send a link delay measurement frame, so that the master-slave clock synchronization path is consistent with the shortest physical communication path; The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

6. The method according to claim 1, characterized in that The method further comprises: Based on the redundant clock synchronization path corresponding to the transmission mode, a redundant time synchronization frame is sent to the slave clock device. In the event of a failure in the master-slave clock synchronization path, the redundant time synchronization frame is used for the slave clock device to perform time synchronization with the master clock device based on the redundant time synchronization frame.

7. The method according to claim 1, characterized in that In the case that the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

8. The method according to claim 7, characterized in that The time interval between two consecutive link delay measurement frames sent by the faulty device is inconsistent with the time interval between two consecutive link delay measurement frames sent by the neighboring device.

9. The method according to claim 1, characterized in that: The method further comprises: Determining a controller in the industrial network as the master clock device according to a clock frequency stability parameter and a position parameter of each industrial device in the industrial network; Among them, when the industrial network is a single-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among all the industrial devices; when the industrial network is a multi-layer topology, the controller is the industrial device with the smallest clock frequency stability parameter among the first branch device in the multi-layer topology and the devices before the first branch device.

10. A time synchronization method, characterized in that: For a slave clock device in an industrial network, the method comprises: In the current transmission mode, receiving a time synchronization frame sent by a master clock device in the industrial network; Based on the time synchronization frame, performing time synchronization with the master clock device; The time synchronization frame is sent by the master clock device to the slave clock device based on the master-slave clock synchronization path corresponding to the transmission mode, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

11. The method according to claim 10, characterized in that Each port in the master clock device and the slave clock device is used to send a link delay measurement frame, so that the master-slave clock synchronization path is consistent with the shortest physical communication path; The link delay measurement frame is used to measure a link delay value, and the link delay value is used for time synchronization between the slave clock device and the master clock device.

12. The method according to claim 10, characterized in that The method further comprises: Receive a redundant time synchronization frame sent by the master clock device based on a redundant clock synchronization path corresponding to the transmission mode, wherein the redundant time synchronization frame is used to perform time synchronization with the master clock device based on the redundant time synchronization frame when a failure occurs in the master-slave clock synchronization path.

13. The method according to claim 10, characterized in that In the case that the master-slave clock synchronization path includes a faulty device, the faulty device is determined during a process of measuring link delays between the faulty device and a neighboring device of the faulty device.

14. The method according to claim 13, characterized in that The time interval between two consecutive link delay measurement frames sent by the faulty device is inconsistent with the time interval between two consecutive link delay measurement frames sent by the neighboring device.

15. The method according to claim 10, characterized in that After performing time synchronization with the master clock device based on the time synchronization frame, the method further includes: Acquire an Allan variance curve corresponding to the slave clock device according to the time after synchronization of the slave clock device; Based on the Allan variance curve, influencing factors affecting the stability of the clock frequency of the slave clock device are determined, and the influencing factors are used to detect overall problems in the environment.

16. A time synchronization method, characterized in that: For use in a controller in an industrial network, the method comprises: Determine a master clock device according to clock frequency stability parameters and position parameters of each industrial device in the industrial network; Among them, the master clock device is used to send time synchronization frames to the slave clock devices in the industrial network under a preset transmission mode based on the master-slave clock synchronization path corresponding to the transmission mode; the time synchronization frame is used for the slave clock device to synchronize time with the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

17. The method according to claim 16, characterized in that The determining of the master clock device according to the clock frequency stability parameter and the position parameter of each industrial device in the industrial network comprises: In the case where the industrial network is a single-layer topology, if there is only one industrial device with the smallest clock frequency stability parameter among the industrial devices, then one of the industrial devices is determined as the master clock device; If there are multiple industrial devices with the smallest clock frequency stability parameters among the multiple industrial devices, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the topological center position of the single-layer topology among the multiple industrial devices is determined as the master clock device.

18. The method according to claim 16, characterized in that The determining of the master clock device according to the clock frequency stability parameter and the position parameter of each industrial device in the industrial network comprises: In the case where the industrial network is a multi-level topology, if there is one industrial device with the smallest clock frequency stability parameter among the first branch device and the devices before the first branch device in the multi-level topology, then one of the industrial devices is determined as the master clock device; If there are multiple industrial devices with the smallest clock frequency stability parameters among the first branch device and the devices before the first branch device, then according to the position parameters of the multiple industrial devices, the industrial device with the smallest distance from the first branch device among the multiple industrial devices is determined as the main clock device.

19. The method according to claim 16, characterized in that The method further comprises: In the case that the master clock device is different from the controller and the master clock device fails, a redundant master clock is determined according to clock frequency stability parameters and position parameters of other industrial devices among the industrial devices except the master clock device.

20. A time synchronization device, characterized in that: A master clock device for an industrial network, the device comprising: A sending module, configured to send a time synchronization frame to a slave clock device in the industrial network based on a master-slave clock synchronization path corresponding to the transmission mode in a current transmission mode; The time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

21. A time synchronization device, characterized in that: A slave clock device used in an industrial network, the device comprising: A receiving module, used for receiving a time synchronization frame sent by a master clock device in the industrial network in a current transmission mode; A synchronization module, configured to perform time synchronization with the master clock device based on the time synchronization frame; The time synchronization frame is sent by the master clock device to the slave clock device based on the master-slave clock synchronization path corresponding to the transmission mode, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

22. A time synchronization device, characterized in that: A controller for an industrial network, the device comprising: A determination module, used to determine a master clock device according to clock frequency stability parameters and position parameters of each industrial device in the industrial network; Among them, the master clock device is used to send time synchronization frames to the slave clock devices in the industrial network under a preset transmission mode based on the master-slave clock synchronization path corresponding to the transmission mode; the time synchronization frame is used for the slave clock device to synchronize time with the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

23. A master clock device, characterized in that: Including memory, transceiver, processor: The memory is used to store a computer program; the transceiver is used to send and receive data under the control of the processor; the processor is used to read the computer program in the memory and perform the following operations: In the current transmission mode, based on the master-slave clock synchronization path corresponding to the transmission mode, controlling the transceiver to send a time synchronization frame to a slave clock device in the industrial network; The time synchronization frame is used for time synchronization between the slave clock device and the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

24. A slave clock device, characterized in that: Including memory, transceiver, processor: The memory is used to store a computer program; the transceiver is used to send and receive data under the control of the processor; the processor is used to read the computer program in the memory and perform the following operations: In the current transmission mode, controlling the transceiver to receive a time synchronization frame sent by a master clock device in the industrial network; Based on the time synchronization frame, performing time synchronization with the master clock device; The time synchronization frame is sent by the master clock device to the slave clock device based on the master-slave clock synchronization path corresponding to the transmission mode, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

25. A controller, characterized in that: Including memory, transceiver, processor: The memory is used to store a computer program; the transceiver is used to send and receive data under the control of the processor; the processor is used to read the computer program in the memory and perform the following operations: Determine the master clock device according to the clock frequency stability parameters and location parameters of each industrial device in the industrial network; Among them, the master clock device is used to send time synchronization frames to the slave clock devices in the industrial network under a preset transmission mode based on the master-slave clock synchronization path corresponding to the transmission mode; the time synchronization frame is used for the slave clock device to synchronize time with the master clock device, and the master-slave clock synchronization path is consistent with the shortest physical communication path corresponding to the transmission mode.

26. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 19 are implemented.

27. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 19 are implemented.

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