Ethernet entity layer transceiver and channel characteristic analysis method

Abstract

The invention provides an Ethernet physical layer transceiver. The Ethernet physical layer transceiver comprises a control circuit and a processing circuit. The control circuit is used for sequentially transmitting and receiving data through a cable by adopting a plurality of different phase combinations of a transmitter clock and a receiver clock, and respectively obtaining a plurality of groups of samples from the cable under the plurality of different phase combinations of the transmitter clock and the receiver clock. The processing circuit is configured to perform channel characteristic analysis according to the plurality of sets of samples provided by the control circuit.

Description

Technical Field

[0001] The present invention relates to an Ethernet physical-layer (PHY) transceiver design, and more particularly to a method for obtaining multiple samples for channel characteristic analysis by using different phase combinations of a transmitter clock and a receiver clock, and a related channel characteristic analysis method. Background Art

[0002] The purpose of the Time Domain Reflectometry (TDR) function is to provide the characteristics of electrical lines (e.g., network lines). As long as the integrated circuit has the ability to transmit the incident signal to the medium and observe the reflected signal of the medium, it can provide channel information such as reflection ratio or impulse response. For example, the reflection ratio can provide certain channel information after post-processing, including return loss, cable length, cable quality, termination type, etc. According to the IEEE 802.3 1G / 2.5G / 5G / 10G specifications, the hardware design of the physical layer observes the reflection conditions of the signals transmitted and received at the working sampling rate in normal mode (which is the same as the baud rate). However, for TDR operation, the working sampling rate in normal mode is not enough to capture the channel response in detail. In other words, some transient changes may not be captured in normal mode, which will seriously lead to misinterpretation and instability when performing post-processing of the reflection ratio for cable length calculation and terminal detection. Therefore, it is a key task to propose an Ethernet physical layer transceiver that can effectively perform cable length calculation and terminal detection. Summary of the invention

[0003] One of the objectives of the present invention is to provide a method for obtaining a plurality of samples for channel characteristic analysis by using different phase combinations of a transmitter clock and a receiver clock and a related channel characteristic analysis method.

[0004] In one embodiment of the present invention, an Ethernet physical layer transceiver is disclosed. The Ethernet physical layer transceiver includes a control circuit and a processing circuit. The control circuit is used to sequentially use a plurality of different phase combinations of a transmitter clock and a receiver clock to transmit and receive data via a cable, and obtain a plurality of sets of samples from the cable under the plurality of different phase combinations of the transmitter clock and the receiver clock. The processing circuit is used to perform channel characteristic analysis based on the plurality of sets of samples provided by the control circuit.

[0005] In another embodiment of the present invention, a channel characteristic analysis method is disclosed. The channel characteristic analysis method includes: sequentially using a plurality of different phase combinations of a transmitter clock and a receiver clock of an Ethernet physical layer transceiver to transmit and receive data via a cable; obtaining a plurality of sets of samples from the cable under the plurality of different phase combinations of the transmitter clock and the receiver clock; and performing channel characteristic analysis based on the plurality of sets of samples.

[0006] Conventional solutions may use higher sampling rates at the expense of higher hardware costs, therefore, the present invention proposes an innovative and cost-effective solution that can overcome the problem of insufficient sampling rate without increasing the sampling rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a schematic diagram of an Ethernet physical layer transceiver supporting the high-resolution mode proposed by the present invention according to an embodiment of the present invention.

[0008] Figure 2 FIG. 4 is a schematic diagram of a control circuit according to an embodiment of the present invention.

[0009] Figure 3 is a flow chart of a method for performing data collection in a high-resolution mode by shifting the phase in a regular sequence (eg, a progressive sequence) according to an embodiment of the present invention.

[0010] Figure 4 is a schematic diagram of samples collected from different phases in a high-resolution mode according to an embodiment of the present invention.

[0011] Figure 5 is a schematic diagram of a pseudo-random binary sequence generator according to an embodiment of the present invention.

[0012] Figure 6 is a flow chart of a method for performing data collection in a high-resolution mode by shifting the phase by an irregular sequence (eg, a random sequence) according to an embodiment of the present invention.

[0013] Figure 7FIG. 4 is a schematic diagram of data samples obtained at different phases and a high-resolution profile derived by interpolation according to an embodiment of the present invention.

[0014]

Explanation of symbols

[0015] 10: Cables

[0016] 100: Ethernet physical layer transceiver

[0017] 102: Processing circuit

[0018] 104,200: Control circuit

[0019] 202: Phase multiplexer control circuit

[0020] 204: Transmitter circuit

[0021] 206: Receiver circuit

[0022] 208: Transmitter clock rotation circuit

[0023] 210: Receiver clock rotation circuit

[0024] 500: Pseudo-random binary sequence generator

[0025] TX_CLK: Transmitter clock

[0026] RX_CLK: Receiver clock

[0027] ROT_EN, PHASE_STEP, TX_ROT_EN, RX_ROT_EN: control signals

[0028] DS_1,DS_N: Sample

[0029] DONE_Flag: Flag

[0030] S302, S304, S306, S308, S602, S604, S606, S608: Steps DETAILED DESCRIPTION

[0031] Certain words are used in the specification and claims to refer to specific components. It should be understood by those with ordinary knowledge in the art that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the criterion for distinction. The terms "including" and "comprising" mentioned throughout the specification and claims are open-ended terms and should be interpreted as "including but not limited to". In addition, the term "coupled" or "coupled" herein includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0032] To address the misinterpretation and instability issues in normal mode, traditional solutions may use higher sampling rates at the expense of higher hardware costs. Therefore, an innovative and cost-effective solution is needed that can overcome the problem of insufficient sampling rate without increasing the sampling rate.

[0033] Figure 1 1 is a schematic diagram of an Ethernet physical layer transceiver supporting the high-resolution mode proposed in the present invention according to an embodiment of the present invention. For example, the Ethernet physical layer transceiver 100 may be a 1000BASE-T transceiver, a 2.5G BASE-T transceiver, a 5G BASE-T transceiver or a 10G BASE-T transceiver, and may support a hybrid mode to transmit and receive data through the cable 10. Figure 1 As shown, the Ethernet physical layer transceiver 100 includes a processing circuit 102 and a control circuit 104. Please note that Figure 1 Only the components related to the present invention are shown. Actually, the Ethernet physical layer transceiver 100 may also include other components required for other functions.

[0034] The processing circuit 102 can be implemented by a microcontroller unit (MCU). In this embodiment, the processing circuit 102 is used to manage the operation of the high-resolution mode. For example, the processing circuit 102 generates a plurality of control signals ROT_EN and PHASE_STEP to the control circuit 104, where the control signal ROT_EN can control the enabling / disabling of the function for changing the relative sampling position of the transmitter clock TX_CLK and the receiver clock RX_CLK, and the control signal PHASE_STEP can control the setting of the relative sampling position of the transmitter clock TX_CLK and the receiver clock RX_CLK.

[0035] In response to the control signals ROT_EN and PHASE_STEP generated by the processing circuit (e.g., microprocessor unit) 102, the control circuit 104 can enable the high-resolution mode proposed by the present invention, and can sequentially adopt a plurality of different phase combinations of the transmitter clock TX_CLK and the receiver clock RX_CLK to transmit and receive data through the cable 10, and obtain multiple sets of samples DS_1 to DS_N (N≥2) from the cable 10 under different phase combinations of the transmitter clock TX_CLK and the receiver clock RX_CLK. For example, an incident signal is transmitted to the cable 10 according to the transmitter clock TX_CLK, and a reflected signal (i.e., the reflection of the incident signal) is received / sampled from the cable 10 according to the receiver clock RX_CLK. In this embodiment, when the transmitter clock TX_CLK and the receiver clock RX_CLK have the i-th phase combination corresponding to the i-th phase difference PD i a set of samples DS_i (1≤i<N) is obtained from the cable 10, and when the transmitter clock TX_CLK and the receiver clock RX_CLK have the (i + 1)-th phase combination corresponding to the (i + 1)-th phase difference PD i+1 (PD i+1 ≠PD i ) the next set of samples DS_i+1 (i+1≤N) is obtained from the cable 10. For example, if the phase of one of the transmitter clock TX_CLK and the receiver clock RX_CLK is fixed, the phase difference between the transmitter clock TX_CLK and the receiver clock RX_CLK (i.e., the relative sampling position of the transmitter clock TX_CLK and the receiver clock RX_CLK) can be easily adjusted by changing the phase of the other one of the transmitter clock TX_CLK and the receiver clock RX_CLK.

[0036] In some embodiments of the present invention, the clock rate of each of the transmitter clock TX_CLK and the receiver clock RX_CLK is equal to the normal mode operating clock rate (i.e., baud rate) of the Ethernet physical layer transceiver 100. When the Ethernet physical layer transceiver 100 is a 1000BASE-T transceiver, the baud rate is 125 MHz, and the clock rates of the transmitter clock TX_CLK and the receiver clock RX_CLK used in the high-resolution mode are each equal to 125 MHz. Therefore, the high-resolution mode proposed by the present invention can be a cost-effective solution to overcome the problem of insufficient sampling rate by increasing the number of samples (i.e., the number of samples per unit interval (UI)) without increasing the sampling rate. Specifically, the number of samples obtained in the high-resolution mode can be increased by changing the relative sampling positions of the transmitter clock TX_CLK and the receiver clock RX_CLK multiple times within one UI (i.e., symbol duration time) without increasing the sampling rate.

[0037] Different phase combinations of the transmitter clock TX_CLK and the receiver clock RX_CLK can be appropriately set to ensure that there are different phase differences between the transmitter clock TX_CLK and the receiver clock RX_CLK, wherein each phase difference defines a relative sampling position between the transmitter clock TX_CLK and the receiver clock RX_CLK. In this way, the receiver can capture multiple samples at different phase difference positions within each UI (e.g., 8ns for 1000BASE-T) for subsequent channel characteristic analysis by the processing circuit 102.

[0038] Figure 2 FIG. 4 is a schematic diagram of a control circuit according to an embodiment of the present invention. Figure 1 The control circuit 104 shown may be composed of Figure 2The control circuit 200 is implemented by a control circuit (labeled as “CTRL_TOP”) 200 shown in FIG. In the present embodiment, the control circuit 200 may include a phase multiplexer control circuit (labeled as “PHASE_MUX CTRL”) 202, a transmitter circuit (labeled as “TX”) 204, a receiver circuit (labeled as “RX”) 206, a transmitter clock rotation circuit (labeled as “TX_CLK ROT”) 208, and a receiver clock rotation circuit (labeled as “RX_CLK ROT”) 210, wherein the timing of the transmitter circuit 204 is controlled by the transmitter clock TX_CLK to transmit data (i.e., incident signal for time domain reflection test (hereinafter referred to as TDR test)) through the cable 10, and the timing of the receiver circuit 206 is controlled by the receiver clock RX_CLK to receive data (i.e., reflected signal for TDR test) through the cable 10. The control circuit 200 sequentially uses different phase combinations of the transmitter clock TX_CLK and the receiver clock RX_CLK to transmit and receive data through the cable 10, and the required phase difference (i.e., relative sampling position) can be set by shifting one or both of the phases of the transmitter clock TX_CLK and the receiver clock RX_CLK according to actual design considerations.

[0039] In the first phase rotation design, the phase of the receiver clock RX_CLK remains unchanged, while the phase of the transmitter clock TX_CLK is moved to a plurality of different values ​​one by one. In response to the control signal ROT_EN, the phase multiplexer control circuit 202 generates a control signal TX_ROT_EN (TX_ROT_EN=1) to enable the transmitter clock rotation circuit 208, and generates a control signal RX_ROT_EN (RX_ROT_EN=0) to disable the receiver clock rotation circuit 210. Therefore, different phase combinations of the transmitter clock TX_CLK and the receiver clock RX_CLK include a combination of a first phase of the transmitter clock TX_CLK and a fixed phase of the receiver clock RX_CLK, and a combination of a second phase of the transmitter clock TX_CLK and a fixed phase of the receiver clock RX_CLK, wherein the second phase of the transmitter clock TX_CLK is different from the first phase of the transmitter clock TX_CLK. Specifically, the phase difference (i.e., the relative sampling position) is adjusted only by moving the phase of the transmitter clock TX_CLK.

[0040] In the second phase rotation design, the phase of the transmitter clock TX_CLK remains unchanged, while the phase of the receiver clock RX_CLK is moved to a plurality of different values ​​one by one. In response to the control signal ROT_EN, the phase multiplexer control circuit 202 generates a control signal TX_ROT_EN (TX_ROT_EN=0) to disable the transmitter clock rotation circuit 208, and generates a control signal RX_ROT_EN (RX_ROT_EN=1) to enable the receiver clock rotation circuit 210. Therefore, different phase combinations of the transmitter clock TX_CLK and the receiver clock RX_CLK include a combination of a first phase of the receiver clock RX_CLK and a fixed phase of the transmitter clock TX_CLK, and a combination of a second phase of the receiver clock RX_CLK and a fixed phase of the transmitter clock TX_CLK, wherein the second phase of the receiver clock RX_CLK is different from the first phase of the receiver clock RX_CLK. Specifically, the phase difference (i.e., the relative sampling position) is adjusted only by moving the phase of the receiver clock RX_CLK.

[0041] In the third phase rotation design, the phase of the transmitter clock TX_CLK is moved to a plurality of different values ​​one by one, and the phase of the receiver clock RX_CLK is also moved to a plurality of different values ​​one by one. In response to the control signal ROT_EN, the phase multiplexer control circuit 202 generates a control signal TX_ROT_EN (TX_ROT_EN=1) to enable the transmitter clock rotation circuit 208, and generates a control signal RX_ROT_EN (RX_ROT_EN=1) to enable the receiver clock rotation circuit 210. Therefore, different phase combinations of the transmitter clock TX_CLK and the receiver clock RX_CLK include a combination of a first phase of the transmitter clock TX_CLK and a first phase of the receiver clock RX_CLK, and a combination of a second phase of the transmitter clock TX_CLK and a second phase of the receiver clock RX_CLK, wherein the second phase of the transmitter clock TX_CLK is different from the first phase of the transmitter clock TX_CLK, the second phase of the receiver clock RX_CLK is different from the first phase of the receiver clock RX_CLK, and the phase difference between the first phase and the second phase of the transmitter clock TX_CLK is different from the phase difference between the first phase and the second phase of the receiver clock RX_CLK. Specifically, the phase difference (i.e., the relative sampling position) is adjusted by jointly moving the phase of the transmitter clock TX_CLK and the phase of the receiver clock RX_CLK.

[0042] In some embodiments of the present invention, the phase of the transmitter clock TX_CLK (or the receiver clock RX_CLK) may be shifted in a regular manner (e.g., in a sequential manner). Thus, different phase combinations of the transmitter clock TX_CLK and the receiver clock RX_CLK sequentially adopted by the control circuit 200 will correspond to different phase differences between the transmitter clock TX_CLK and the receiver clock RX_CLK, and the different phase differences will be a monotonically-increasing sequence or a monotonically-decreasing sequence.

[0043] Figure 3 FIG. is a flowchart of a method for performing data collection in a high-resolution mode by shifting phases through a regular sequence (e.g., a sequential sequence) according to an embodiment of the present invention. Assume that a UI (i.e., a symbol duration) can be evenly (or unevenly) divided into N (e.g., N = 8) partitions according to N (e.g., N = 8) phases PH_1, PH_2,..., PH_N, where PH_j < PH_j+1 and j = {1, 2,..., N - 1}. For ease of understanding, assume that the control circuit 200 adopts the second phase rotation design described above. Those skilled in the art should readily understand that the regular sequence can also be applied to the first and third phase rotation designs described above.

[0044] In step S302, the receiver clock rotation circuit 210 sets the phase of the receiver clock RX_CLK to an initial phase (e.g., PH_1). In step S304, the receiver circuit 206 samples the signal (e.g., reflection signal) received from the cable 10 according to the receiver clock RX_CLK and generates a set of samples (e.g., DS_1) for the current phase setting of the receiver clock RX_CLK. For TDR testing, the receiver circuit 206 collects samples (including reflection ratios) according to the current phase setting PH_1 of the receiver clock RX_CLK. In step S306, the phase multiplexer control circuit 202 checks whether all phases PH_1 to PH_N have been selected in sequence. If the current phase is not the last phase (e.g., PH_N), the process proceeds to step S308. In step S308, the receiver clock rotation circuit 210 moves the phase of the receiver clock RX_CLK to the next phase (e.g., PH_2), and then the receiver circuit 206 samples the signal received from the cable 10 according to the receiver clock RX_CLK and generates a set of samples (e.g., DS_2) for the current phase setting of the receiver clock RX_CLK. For TDR testing, the receiver circuit 206 collects samples (e.g., reflection ratio) according to the current phase setting PH_2 of the receiver clock RX_CLK. Step S308 continuously moves the phase of the receiver clock RX_CLK until the phase multiplexer control circuit 202 has sequentially selected all phases PH_1 to PH_N during the data collection process (e.g., collection of reflection ratio for TDR testing).

[0045] If the current phase is the last phase (e.g., PH_N), the control circuit 200 enables the flag DONE_Flag (DONE_Flag=1) to notify the processing circuit (e.g., the processing circuit 102) of the end of the data collection process. After the data collection process is completed, the processing circuit (e.g., the processing circuit 102) performs channel characteristic analysis based on the multiple sets of samples DS_1-DS_N provided by the control circuit 200. For example, the channel characteristic analysis may include TDR testing, and the multiple sets of samples DS_1-DS_N may include reflection ratios. Therefore, post-processing of the reflection ratio can provide channel information, including return loss, cable length, cable quality, terminal type, etc.

[0046] Figure 4is a schematic diagram of samples collected from different phases in high resolution mode according to an embodiment of the present invention. In order to better understand the technical features of the present invention, it is assumed that the second phase rotation design uses 8 (N=8) phases of the receiver clock RX_CLK. When the phase of the receiver clock RX_CLK is set to PH_1, the continuous samples (e.g., reflection ratio) S 1,1 , S 1,2 , S 1,3 , S 1,4 , S 1,5 , S 1,6 , S 1,7 , S 1,8 , S 1,9 , S 1,10 , S 1,11 , S 1,12 , S 1,13 , S 1,14 The receiver circuit 206 obtains the periodic sampling timing defined by the phase PH_1 of the receiver clock RX_CLK. When the phase of the receiver clock RX_CLK is set to PH_2, the continuous samples (eg, reflection ratio) S 2,1 , S 2,2 , S 2,3 , S 2,4 , S 2,5 , S 2,6 , S 2,7 , S 2,8 , S 2,9 , S 2,10 , S 2,11 , S 2,12 , S 2,13 The receiver circuit 206 obtains the periodic sampling timing defined by the phase PH_2 of the receiver clock RX_CLK. When the phase of the receiver clock RX_CLK is set to PH_8, the continuous samples (eg, reflection ratio) S 8,1 , S 8,2 , S 8,3 , S 8,4 , S 8,5 , S 8,6 , S 8,7 , S 8,8 , S 8,9 , S 8,10 , S 8,11 , S 8,12 , S 8,13It will be obtained by the receiver circuit 206 according to the periodic sampling timing defined by the phase PH_8 of the receiver clock RX_CLK. By using 8 phases of the receiver clock RX_CLK with the same clock rate as the normal mode operating clock rate (baud rate), 8 samples can be obtained by sampling at different sampling positions within one UI.

[0047] On the other hand, the phase of the transmitter clock TX_CLK (or the receiver clock RX_CLK) can also be moved in an irregular manner (e.g., randomly). Therefore, the different phase combinations of the transmitter clock TX_CLK and the receiver clock RX_CLK sequentially adopted by the control circuit 200 correspond to different phase differences between the transmitter clock TX_CLK and the receiver clock RX_CLK, and the different phase differences are not a monotonically increasing sequence or a monotonically decreasing sequence. In some embodiments of the present invention, the different phase differences can be a random sequence under the control of the processing circuit 102. For example, Figure 1 the illustrated processing circuit 102 can be implemented by a microcontroller unit having Figure 5 the illustrated pseudo random binary sequence (hereinafter simply referred to as PRBS) generator 500. The PRBS generator 500 is used to establish a pseudo random sequence as the control signal PHASE_STEP and output the control signal PHASE_STEP (which indicates the pseudo random sequence) to the control circuit 104 (which can be implemented by Figure 2 the illustrated control circuit 200). Therefore, the control circuit 104 / 200 sets different phase differences between the transmitter clock TX_CLK and the receiver clock RX_CLK in response to the pseudo random sequence provided by the processing circuit 102.

[0048] Figure 6 is a flowchart of a method for performing data collection in a high-resolution mode by moving phases with an irregular sequence (e.g., a random sequence) according to an embodiment of the present invention. Assume that one UI (i.e., symbol duration) can be evenly (or unevenly) divided into 8 (N = 8) partitions according to 8 (N = 8) phases PH_1, PH_2,..., PH_8, where PH_i < PH_i+1 and i = {1, 2,..., N - 1}. For ease of understanding, assume that the control circuit 200 adopts the aforementioned second phase rotation design. Those skilled in the art should easily understand that the irregular sequence can also be applied to the aforementioned first phase rotation design and the third phase rotation design. Take Figure 5Taking the PRBS generator 500 shown as an example, the generated pseudo-random sequence may be [7→6→4→1→2→5→3]. In step S602, the receiver clock rotation circuit 210 sets the phase of the receiver clock RX_CLK to the initial phase (e.g., PH_7) indicated by the pseudo-random sequence generated by the PRBS generator 500. In step S604, the receiver circuit 206 samples the signal (e.g., the reflected signal) received from the cable 10 according to the receiver clock RX_CLK, and generates a set of samples (e.g., DS_7) for the current phase setting of the receiver clock RX_CLK. For TDR testing, the receiver circuit 206 collects samples (e.g., reflection ratio) according to the current phase setting PH_7 of the receiver clock RX_CLK. In step S606, the phase multiplexer control circuit 202 checks whether a cycle of the pseudo-random sequence is completed (i.e., the current phase is the last phase PH_3 of the pseudo-random sequence). If the current phase is not the last phase PH_3 of the pseudo-random sequence, the process proceeds to step S608. In step S608, the receiver clock rotation circuit 210 moves the phase of the receiver clock RX_CLK to the next phase (e.g., PH_6) indicated by the pseudo-random sequence generated by the PRBS generator 500. Then, the receiver circuit 206 samples the signal (e.g., the reflected signal) received from the cable 10 according to the receiver clock RX_CLK and generates a set of samples (e.g., DS_6) for the current phase setting of the receiver clock RX_CLK. For TDR testing, the receiver circuit 206 collects samples (e.g., reflection ratio) according to the current phase setting PH_6 of the receiver clock RX_CLK. Step S608 continuously moves the phase of the receiver clock RX_CLK until one cycle of the pseudo-random sequence has been completed (i.e., the current phase is the last phase PH_3 of the pseudo-random sequence).

[0049] If one cycle of the pseudo-random sequence has been completed (i.e., the current phase is the last phase PH_3 of the pseudo-random sequence), the control circuit 200 will enable the flag DONE_Flag (DONE_Flag=1) to notify the processing circuit (e.g., the processing circuit 102) of the end of the data collection process. After the data collection process is completed, the processing circuit (e.g., the processing circuit 102) will perform channel characteristic analysis based on the multiple sets of samples DS_1~DS_N provided by the control circuit 200. For example, the channel characteristic analysis may include TDR testing, and the multiple sets of samples DS_1~DS_N may include reflection ratios. Therefore, post-processing of the reflection ratio may provide channel information, including return loss, cable length, cable quality, terminal type, etc.

[0050] As described above, the processing circuit 102 obtains multiple sets of samples DS_1-DS_N and performs channel characteristic analysis based on the multiple sets of samples DS_1-DS_N. These samples DS_1-DS_N are obtained by sampling the signal received from the cable 10 at the same normal mode sampling rate (baud rate) but different phases. The processing circuit 102 can reconstruct the sampling results of the high-resolution mode by considering these samples DS_1-DS_N together. For example, these samples DS_1-DS_N can be combined to reconstruct the sampling results of the high-resolution mode. For example, when these samples DS_1-DS_N are used for TDR testing, a high-resolution profile can be derived by interpolation.

[0051] Figure 7 is a schematic diagram of data samples obtained at different phases and the high-resolution profile derived by interpolation according to an embodiment of the present invention. Compared with the reflectance ratio profile in the normal mode (which is one of the 8 phases in the high-resolution mode), the high-resolution profile of the reflectance ratio can indicate more channel effect phenomena and transient changes. Specifically, in the normal mode, the sampling rate is the same as the working clock rate (baud rate), and the resolution of one sample can be calculated by multiplying the rate by the sampling time (i.e., the symbol duration). In contrast, the sampling rate in the high-resolution mode proposed by the present invention is the same as that in the normal mode, but the sampling phase changes over time, that is, more samples can be obtained in one UI to improve the resolution, so more information can be observed through different sampling phases. For example, the sampling time of 1000BASE-T is 8ns, and the resolution of one sample can be calculated by multiplying the rate by the sampling time. The transmission rate in copper is 2 / 3 the speed of light (3x10 8 m / s), and the signal observed by the physical layer circuit is a reflected signal, so the transmission distance of the signal is twice the length of the cable, so the resolution of a tap is 0.8m. Since the number of samples in each UI in the high-resolution mode is higher than that in the normal mode, the tap resolution in the high-resolution mode will be less than 0.8m, so more information can be observed through more sampling phases specially created by the high-resolution mode proposed by the present invention.

[0052] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. An Ethernet physical layer transceiver, comprising: a control circuit for sequentially using a plurality of different phase combinations of a transmitter clock and a receiver clock to transmit and receive data via a cable, and obtaining a plurality of sets of samples from the cable under the plurality of different phase combinations of the transmitter clock and the receiver clock; and A processing circuit is used to perform channel characteristic analysis according to the plurality of sets of samples provided by the control circuit.

2. The Ethernet physical layer transceiver as claimed in claim 1, wherein the channel characteristic analysis comprises a time domain reflection test.

3. The Ethernet physical layer transceiver as claimed in claim 1, wherein the plurality of sets of samples include a plurality of reflection ratios.

4. The Ethernet physical layer transceiver of claim 1, wherein a clock rate of each of the transmitter clock and the receiver clock is equal to a baud rate of the Ethernet physical layer transceiver.

5. The Ethernet physical layer transceiver as claimed in claim 1, wherein the plurality of different phase combinations of the transmitter clock and the receiver clock include: a combination of a first phase of the transmitter clock and a fixed phase of the receiver clock; and A combination of a second phase of the transmitter clock and the fixed phase of the receiver clock, wherein the second phase of the transmitter clock is different from the first phase of the transmitter clock.

6. The Ethernet physical layer transceiver as claimed in claim 1, wherein the plurality of different phase combinations of the transmitter clock and the receiver clock comprise: a combination of a fixed phase of the transmitter clock and a first phase of the receiver clock; and A combination of the fixed phase of the transmitter clock and a second phase of the receiver clock, wherein the second phase of the receiver clock is different from the first phase of the receiver clock.

7. The Ethernet physical layer transceiver as claimed in claim 1, wherein the plurality of different phase combinations of the transmitter clock and the receiver clock comprise: a combination of a first phase of the transmitter clock and a first phase of the receiver clock; and a combination of a second phase of the transmitter clock and a second phase of the receiver clock, wherein the second phase of the transmitter clock is different from the first phase of the transmitter clock, the second phase of the receiver clock is different from the first phase of the receiver clock, and the phase difference between the first phase and the second phase of the transmitter clock is different from the phase difference between the first phase and the second phase of the receiver clock.

8. An Ethernet physical layer transceiver as described in claim 1, wherein the multiple different phase combinations of the transmitter clock and the receiver clock sequentially adopted by the control circuit correspond to multiple different phase differences between the transmitter clock and the receiver clock, and the multiple different phase differences are a monotonically increasing sequence or a monotonically decreasing sequence.

9. An Ethernet physical layer transceiver as described in claim 1, wherein the multiple different phase combinations of the transmitter clock and the receiver clock sequentially adopted by the control circuit correspond to multiple different phase differences between the transmitter clock and the receiver clock, and the multiple different phase differences are not a monotonically increasing sequence or a monotonically decreasing sequence.

10. The Ethernet physical layer transceiver as claimed in claim 9, wherein the processing circuit comprises: A pseudo-random binary sequence generator is used to generate a pseudo-random sequence and output the pseudo-random sequence to the control circuit, wherein the multiple different phase differences between the transmitter clock and the receiver clock are set by the control circuit according to the pseudo-random sequence.

11. A channel characteristic analysis method, comprising: Sequentially using a plurality of different phase combinations of a transmitter clock and a receiver clock of an Ethernet physical layer transceiver to transmit and receive data via a cable; Under the plurality of different phase combinations of the transmitter clock and the receiver clock, respectively obtaining a plurality of sets of samples from the cable; and Channel characteristic analysis is performed based on the plurality of sets of samples.

12. The channel characteristic analysis method as claimed in claim 11, wherein the channel characteristic analysis comprises a time domain reflection test.

13. The channel characteristic analysis method as claimed in claim 11, wherein the plurality of sets of samples include a plurality of reflection ratios.

14. The channel characteristic analysis method of claim 11, wherein a clock rate of each of the transmitter clock and the receiver clock is equal to a baud rate of the Ethernet physical layer transceiver.

15. The channel characteristic analysis method as claimed in claim 11, wherein the plurality of different phase combinations of the transmitter clock and the receiver clock comprise: a combination of a first phase of the transmitter clock and a fixed phase of the receiver clock; and A combination of a second phase of the transmitter clock and the fixed phase of the receiver clock, wherein the second phase of the transmitter clock is different from the first phase of the transmitter clock.

16. The channel characteristic analysis method as claimed in claim 11, wherein the plurality of different phase combinations of the transmitter clock and the receiver clock comprise: a combination of a fixed phase of the transmitter clock and a first phase of the receiver clock; and A combination of the fixed phase of the transmitter clock and a second phase of the receiver clock, wherein the second phase of the receiver clock is different from the first phase of the receiver clock.

17. The channel characteristic analysis method as claimed in claim 11, wherein the plurality of different phase combinations of the transmitter clock and the receiver clock comprise: a combination of a first phase of the transmitter clock and a first phase of the receiver clock; and a combination of a second phase of the transmitter clock and a second phase of the receiver clock, wherein the second phase of the transmitter clock is different from the first phase of the transmitter clock, the second phase of the receiver clock is different from the first phase of the receiver clock, and the phase difference between the first phase and the second phase of the transmitter clock is different from the phase difference between the first phase and the second phase of the receiver clock.

18. The channel characteristic analysis method as described in claim 11, wherein the multiple different phase combinations of the transmitter clock and the receiver clock used sequentially correspond to multiple different phase differences between the transmitter clock and the receiver clock, and the multiple different phase differences are a monotonically increasing sequence or a monotonically decreasing sequence.

19. The channel characteristic analysis method as described in claim 11, wherein the multiple different phase combinations of the transmitter clock and the receiver clock used sequentially correspond to multiple different phase differences between the transmitter clock and the receiver clock, and the multiple different phase differences are not a monotonically increasing sequence or a monotonically decreasing sequence.

20. The channel characteristic analysis method as claimed in claim 19, further comprising: A pseudo-random sequence is generated, wherein the plurality of different phase differences between the transmitter clock and the receiver clock are set according to the pseudo-random sequence.

Images