Data packets with memory access protocol in high speed packet network

Abstract

The invention discloses data packets with a memory access protocol in a high speed packet network. Systems and methods herein are directed to one or more processing units associated with and enabling at least one switch or router to receive a communication from a source host, where the communication includes a request associated with a memory access protocol of a memory space of a target host, and providing communications to the target host to enable subsequent communications from the source host based in part on a memory access protocol received in response to the request.

Description

Technical Field

[0001] At least one embodiment relates to communications in a high speed (HS) data network using a memory access protocol with header modification to include a target host's memory space. Background Art

[0002] A high-speed data network can network multiple processing units of different hosts together. The processing units can be graphics processing units (GPUs) in different hosts that can be networked together through a high-speed data network, which provides higher bandwidth and lower latency communication between different hosts. The processing units can communicate and share data directly using such data networks, rather than through a central processing unit (CPU) that can improve the overall performance of a system with such a host and such a data network. In addition, the communication in these data networks is carried out using a series of interconnected switches or routers responsible for routing data packets between hosts of the network. The switch or router uses an internal hash function of each routing layer to determine the egress port of the packet communication from the host. Because one or more switches or routers in one or more routing layers determine to reuse the same hash function between them or within themselves, one or more switches or routers determine or select the same egress port for different traffic flows, thereby causing traffic flow polarization. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A system is shown that undergoes header modification to include association with a memory access protocol and hashing in a high-speed data network in accordance with at least one embodiment;

[0004] Figure 2 Various aspects of a system subject to header modification to include associations with memory access protocols and hashes in accordance with at least one embodiment are shown;

[0005] Figure 3 illustrating further aspects of a system including a centralized controller for including at least a hash in a header modification associated with a memory access protocol in accordance with at least one embodiment;

[0006] Figure 4A Still further aspects of a system for header modification to include an association with a memory access protocol and a hash are shown in accordance with at least one embodiment;

[0007] Figure 4B illustrating details of association with a memory access protocol according to at least one embodiment;

[0008] Figure 5AA process flow illustrating a system for header modification to include an association with a memory access protocol and a hash according to at least one embodiment;

[0009] Figure 5B A process flow of a system for header modification to include an association with a memory access protocol and a hash is shown in accordance with at least one embodiment;

[0010] Figure 6 A process flow illustrating a system for header modification to include an association with a memory access protocol and a hash according to at least one embodiment; and

[0011] Figure 7 A process flow of a system for header modification to include an association with a memory access protocol and a hash is shown in accordance with at least one embodiment. DETAILED DESCRIPTION

[0012] In at least one embodiment, Figure 1 A system 100 is shown that undergoes header modification to include an association with a memory access protocol and a hash as detailed herein. In at least one embodiment, such an association may include at least one of a request or a response associated with the memory access protocol. The system 100 includes one or more high-speed (HS) data networks 1 102, 2 106 that may be peer-to-peer networks. The HS data networks 1 102, 2 106 are capable of performing header modification to include an association with a memory access protocol and a hash value (such as a request for a memory access protocol and a hash value) to provide efficient and correctly routed access using HS switches between supported HS hosts 1-N 120, A1-AN 124. For example, HS data network 1 102, 2 106 supports use of a request for a memory access protocol and includes: a hash value transmitted from a supporting HS host 1-N 120; A1-AN 124 to a HS switch or router to enable the HS switch or router to select or determine from its available egress port for onward transmission of at least one data packet transmitted with the hash value and to enable subsequent communication from the source HS host based in part on the memory access protocol received in response to the request.

[0013] At the target end, the target HS host can provide a response memory access protocol to enable subsequent communication. For example, the source HS host provides a 10-byte portion of its header with a request associated with the memory access protocol of the target HS host, and the target HS host provides a 2-byte portion of its header with a response associated with the memory access protocol. In addition, at least in the response, an attribute can be provided to indicate the data format of the response with data, such as used by a graphics device to enable compression of read data. Another attribute can be provided in the request and supported by an appropriate response, and the other attribute belongs to several data bytes to be operated as part of the business. This may represent the data carried in the request (including write and reduction atoms), the data carried in the response (including read), or the data carried by both (including non-reduction atoms). Further attributes can be provided in the request to trigger an appropriate response as to whether the request is for a consistent memory system. For example, this helps determine whether the target HS host should or should not generate a probe. In at least one embodiment, if the source HS host determines that the probe is unnecessary (for example, due to maintaining consistency in software) and only provides bits for attributes associated with a consistent memory system as performance hints, this attribute can also be used.

[0014] In such (IB) and In HS data networks, there may be differences in protocols related to how switches handle communications from HS hosts. In at least one embodiment herein, an HS switch or router uses its corresponding graphics processing unit (GPU) to enable communications from a source host to a target host to properly route access requests and responses to the target host's memory space between the source host and the target host. For example, the source host may want to understand the internal memory protocol of the target host. For example, the internal memory protocol may be related to memory aspects such as the size of reads and writes or understanding consistency and completion status. Therefore, communications from the source host may include requests associated with the memory access protocol of the target host's memory space.

[0015] In at least one embodiment, a source host may include a hash value based in part on a source identifier of the source host and a target identifier of the target host to support routing of the request. The hash value may be generated by a hash function optimized to generate an orthogonal set of bits. In addition, in one example, the hash value occupies a first set of bits in a header position, the first set of bits being adjacent to a second set of bits used by a memory access protocol. In this manner, the first set of bits may include an identification with a hash value to indicate the presence of a request for a memory access protocol, and the hash value may be used by a switch to allow routing communications to a target host, wherein different bits in the hash value specify different routing layers, each different routing layer starting from an available egress port up to a receiving host.

[0016] In at least one embodiment, systems and methods are provided to address a GPU of a source host communicating with a target host to support different types of HS packet networks using packets with limited space in the packet header (also referred to herein as a header) after header modification to include association with a memory access protocol. For example, and may support different information in their respective headers. At least one instance of such a header may not provide a request suitable for the memory protocol of the target host. For example, this may be due to at least cross-protocol communication, including, for example, due to not knowing the memory protocol of the target host. The systems and methods described herein partially enable headers in communications from a source host, wherein the header can include a request associated with a memory access protocol of a memory space of the target host and can include a hash value, which, as part of a set of bits, can indicate the presence of a request for a memory access protocol and can be used by a switch to allow routing of communications.

[0017] In at least one embodiment, the systems and methods described herein enable communication of associations (requests and responses) for memory access protocols and hashes in an HS switch 116 or HS router 114 of an HS data network 102, 106. Such communication may be performed using the HS hosts 120, 124 and may be provided in part in a header of the communication to be sent to at least one HS switch 116 or HS router 114 in one of the different routing layers. For example, a first routing layer may be on a communication exiting the HS hosts 1-N 120 in the HS data network 1 102 and may receive the HS switches or routers therein. In addition, communication with the header may be received in subsequent routing layers to enable each HS switch or router in each routing layer to select or determine from its available egress ports to forward the data packet from the HS hosts 1-N 120. The destination of the communication is a target HS host (also referred to herein as a target host unless otherwise specified). In at least one embodiment, the hash includes portions directed to different switches in different routing layers between the two hosts. In at least one embodiment, the final routing layer may support transmission of communications to one of the provided interconnect devices 130 (such as from the HS gateway 108 to the Ethernet gateway 110 or Ethernet switch 112) before exiting the HS data network 1 102, 2 106, and therefore also to non-HS hosts such as Ethernet hosts 1-N 122 of the Ethernet network 104.

[0018] In at least one embodiment, the HS switches 116 or HS routers 114 in each routing layer can determine or select egress ports therein for routing communications based on a hash from the sending HS hosts 1-N 120, A1-AN 124. For example, at least a portion of the hash may correspond to certain egress ports of the available egress ports of the HS switches 116 or HS routers 114 of the first routing layer, while other portions may be used to determine or select other egress ports of other egress ports on other HS switches or routers of other routing layers. This is an iterative process performed in each routing layer between the sending HS host and the receiving or destination HS host. This approach eliminates the need for the HS switches 116 or HS routers 114 to perform their own hashing, which otherwise may result in each switch or multiple switches repeatedly selecting the same egress port, which in turn may result in uneven distribution of traffic through such independent but repeated selection of the same egress port of at least one HS switch 116 or HS router 114.

[0019] Thus, the systems and methods herein provide for hashing or using hashes (or hash bits) to determine an egress port of a HS switch 116 or HS router 114 of a hash header support network such as a HS data network 1 102, 2 106, and association with a memory access protocol between a source host and a destination host to enable subsequent communication between the two. The hash header support network supports, in part of the communication, the transmission of a header of a data packet intended for a receiving or destination HS host. In one example, a HS host 120, 124 may communicate with the host (such as a spray). The first HS switch 116 or HS router 114 in such a communication path may receive the communication.

[0020] In at least one embodiment, the communication is from a source HS host to at least one receiving or target HS host via at least one available egress port of the first HS switch 116 or HS router 114. The first HS switch 116 or HS router 114 is capable of determining at least one of its available egress ports for transmission based in part on a hash in the header. In at least one embodiment, the hash is generated by a hash function in the source HS host, wherein the hash function is optimized to generate an orthogonal set of bits. In addition, different bits in the hash can specify or belong to different routing layers, and each of the different routing layers starts from an available egress port of the first HS switch 116 or HS router 114 to a different HS switch closest to the receiving or target HS host. Therefore, routing decisions in one or more different routing layers are unrelated, thereby avoiding polarization of traffic flows.

[0021] In at least one embodiment, a centralized controller that may function in the HS switch 116, HS router 114, or HS hosts 1-N 120, A1-AN 124 may define the hash usage of the HS switch 116 or HS router 114 based on network information (such as available egress ports) that it obtains through periodic scans of the HS devices 114, 116, 120, 124 in the HS data network 1 102. Figure 1 In the embodiment, multiple HS hosts 1-N 120, A1-AN 124 of different HS data networks 1 102, 2 106 can use HS switches 116 and HS routers 114 to interface with each other, but can also use interconnection devices 130 to support the interface between HS data networks 1 102, 2 106 and Ethernet network 104. For Ethernet network 104, Ethernet switches 112 and Ethernet gateways 110 can coordinate the connectivity within Ethernet network 104, and can also use Ethernet interconnects 128 to coordinate the connectivity between different Ethernet hosts 1-N 122 of Ethernet network 104 and other networks such as HS data networks 1 102, 2 106. Differently, in HS data networks 1 102, 2 106, each such network relies on a centralized controller (CC) (such as at least about Figures 2 to 4B described and discussed) and related agents (such as Figures 3 to 4A 124) to coordinate network connectivity between different HS hosts 120, 124 that communicate using HS links 126. In addition, CCs may be implemented on at least one of the HS switches 116 or HS hosts 1-N 120, A1-AN 124, wherein at least one CC is provided in each HS data network 1102, 2106.

[0022] In one example, because the HS data network 1102 includes at least Figure 2-4B The CC and agents described and / or discussed herein are used to monitor the link status of the HS ports within the HS hosts 120, 124. In addition, a centralized controller (CC) 206 (such as Figures 2 to 4A ) is used to pass through a proxy 302 (such as Figure 3 , Figure 4AThe CC can collect this information when establishing which egress ports are available for the switch to determine and select, and can configure a forwarding table indicating available egress ports for one or more HS switches 116 or HS routers 114 because all connected devices must be informed. The CC can provide configuration information to one or more HS switches 116 or HS routers 114. The configuration information enables each of the one or more HS switches 116 or HS routers 114 to use a hash in the header to determine or select at least one of its available egress ports identified by the CC in order to forward data packets from each of the one or more HS switches 116 or HS routers 114. The HS switch forwards the packet from, for example, Figure 2 In each HS subnet 1 202, 2 204 in the same HS network, one HS link is routed to another HS link. The HS router can Figure 2 Routing packets between HS subnets 1 202 and 2 204 in the HS.

[0023] Figure 2 Various aspects of a system 200 for header modification to include an association with a memory access protocol and a hash are shown in accordance with at least one embodiment. In at least one embodiment, the systems and methods described herein enable association with a memory access protocol using, in part, a hash to occupy a first set of bits in a header position adjacent to a second set of bits used by the memory access protocol. Additionally, the first set of bits may collectively constitute an identifier field of the header. The hash is a portion of an identifier field used by a switch to allow routing of communications to a target host to allow determination of an egress port for forward transmission based in part on a hash provided from a HS host rather than a hash determined within a HS switch or router.

[0024] In at least one embodiment, since the routing process can be repeated across HS switches or routers in different routing layers using the same hash, a complete network forwarding solution is provided. In addition, each different routing layer can use the same hash bits. Host and host are used interchangeably to describe HS or Ethernet hosts, unless otherwise explicitly stated using the previous text HS or Ethernet or regarding HS-related aspects and Ethernet-related aspects, where HS hosts are dedicated to HS networks and Ethernet hosts are dedicated to Ethernet networks. In addition, this specificity does not limit the HS to Ethernet interconnection described herein.

[0025] In at least one embodiment, Figure 2Also shown is a system for determining an egress port in a data network, the data network including an HS switch 116 or HS router 114 for receiving communications from HS hosts 1-N 120, A1-AN 124, such as within a subnet using HS links 208 or between subnets using HS links 126. The communications include at least an association with a memory access protocol and a hash. In addition, a CC 206 may be used for each HS subnet 1 202, 2 204 to provide configuration information to its corresponding HS switch 116 or HS router 114. The CC 206 may be a combination of hardware and software or a firmware function implemented in one HS switch N (or AN) 116 in the corresponding subnet or a host HS host N (or AN) 120, 124 in the corresponding subnet. The configuration information enables the corresponding HS switch 116 or HS router 114 to determine or select at least one available egress port using the hash in the header to transmit the data packet from the HS switch 116 or HS router 114 to at least one receiving host or another router layer.

[0026] In at least one embodiment, Figure 3 Another aspect 300 of a system including a CC 206 for including at least a hash in a header modification associated with a memory access protocol is shown. The CC 206 can retain subnet information 206A associated with its corresponding subnet, such as information about each port on each device within the subnet. This information can be obtained by periodic scanning by the CC 206 of all devices to which it is connected. In one example, a CC 206 in a HS subnet is a device that manages communications between multiple HS hosts, such as GPUs or CPUs, in a computer system by acting as a central coordination point for data transfer between the hosts. The CC 206 achieves this by configuring the HS switch 116 or HS router 114 to provide an HS link 208 of the HS fabric 118.

[0027] In at least one embodiment, the subnet information 206A may include information about all HS switches 116 or HS routers 114 in its subnet. Such information may include their respective connection status, available bandwidth, available egress ports (such as Figure 4A The information may also be related to the data transmitted in the session, including forwarding rules (such as Figure 4A The information in CC 206 may also include error detection and correction aspects for managing and optimizing HS link 208.

[0028] In at least one embodiment, Figure 3 As shown, CC 206 receives its information via configuration information 308 requests and responses that may pass through the same HS link 208, but are not part of the traffic flow 304. Configuration information 308 is between CC 206 and all HS devices within the subnet, including HS hosts 120, 312 and HS switches 116. Each HS device may have an agent 302, 310, which is a software component responsible for managing communications between such HS devices, their internal operating systems, and CC 206. Agents 302, 310 may be implemented as part of a device driver in each HS device and may interact with CC 206 to control the traffic flow 304 between HS devices. However, traffic flow 304 does not need to flow to CC 206 or at least be ignored by CC 206. Configuration information 308 may pass through the same port of the connected device as traffic flow 304, but agents 302, 310 may recognize and respond to configuration information 304 and ignore traffic flow 304.

[0029] In at least one embodiment, the agent 302, 310 in each HS device may be responsible for managing the communication between that HS device and the CC 206. However, the agents 302, 310 in each HS device may also be able to communicate with each other among themselves in the subnet. In at least one embodiment, there may be an agent 302, 310 in each HS device, but at least in the case of the HS host 120, 312, there may be an agent 310 that transmits configuration information to the CC 206, such as informing about the available ports P1-N 314A, PN1-PNN 314B of the host.

[0030] The ports P1-N 314A, PN1-PNN 314B of the respective HS hosts 120, 312 may also be associated with respective processing units 320, such as GPUs therein. This allows the respective processing units 320 to form a peer-to-peer network between the hosts in the subnet. Each HS switch 116 has at least one agent 302. The HS switch 116 may include its respective egress ports EP1-N 314C representing 64 ports. However, more or fewer ports may also be available in such a HS switch. The HS router may perform similar operations with respect to the HS switch, but may also perform communications between subnets. In at least one embodiment, the agents 302, 310 may be responsible for implementing functions such as error detection and correction in addition to being responsible for flow control and data prioritization. In at least one embodiment, the HS switch 116 may include corresponding ingress ports IP1-N 316, wherein the forwarding rules transmitted from the CC 206 to the HS switch 116 may include an indication of which hash bits are used to select the egress port EP1-N 314C based in part on the ingress port IP1-N 316 receiving the packet to be forwarded to the receiving HS host 312 through one or more layers.

[0031] In at least one embodiment, Figure 4A Still another aspect 400 of a system for header modification to include association with a memory access protocol and a hash is shown according to at least one embodiment. The header modification may be provided in a header of a data packet 418 of a communication. The HS switch 116 or HS router 114 may receive a communication such as a flow 440 from a HS host 120. The communication may be provided by one or more ports P1-N 314A of the HS host 120. One or more ports P1-N 314A may be associated with corresponding identifications ID A, B 414 and an agent 310 of its host. The communication includes at least a data packet 418 and a header 416A, B. The header includes a first bit set in a first header portion 416A, the first bit set being located at a header position adjacent to a second bit set of a second header portion 416B used by a memory access protocol (MAP). The data packet 418 is for transmission to at least one receiving or target HS host 312 as forward flow 440 via at least one available egress port EP1-N 314C. Additionally, at least one available egress port EP1-N 314C is determined based in part on the hash in the first header portion 416A.

[0032] In at least one embodiment, the hash in the first header portion 416A is determined on the HS host 120 using a hash function as part of the software service 402A and applied to at least one address associated with the communication from the HS host 120. However, in at least one embodiment, the hash in the first header portion 416A is determined on the HS host 120 using a hash function as part of the software service 402A and applied to a source identifier (such as an address or label) of the source host and a target identifier of the target host. In at least one embodiment, the address used for the hash function may be one or more of the transmit ID A, B 414 of the transmit port P1-N 314A, or the target / receive ID A1, B1 434 of the target / receive port PN1-PNN 314B of one of the other HS hosts 312. As with the HS host 120, these target / receive ports PN1-PNN 314B may be associated with the agent 310 of the HS host 120.

[0033] However, in at least one embodiment, the host always maximizes the spread of the hash, and the CC 206 defines how the switch or router will use the hash. In one example, the CC 206 defines forwarding rules 422 for the routing layers (such as between switches S1, S2, between switches S2, S3, or even between the source host and the first switch S1) from the source host to follow to reach the target or receiving host. With respect to the source host, the switch S1 of the first routing layer (or the first receiving switch) can use a portion of the hash to determine its egress port to use. This process can be repeated for each switch or router in each routing layer using a different portion of the hash in the header.

[0034] In at least one embodiment, the forwarding rules 422 of the CC 206 include an identification of each ingress port (IP1-N) of each switch, and an identification of a hash bit sequence used to forward packets incoming through these individual ingress ports by selecting an egress port for each switch. The hash bit sequence informs the switch to use certain hash bits of the hash in the header to select an egress port for the packet. For example, for switch S1, a packet incoming through ingress port IP1 includes a hash with 10 hash bits. The CC 206 informs switch S1 to use hash bits H1-H3 of H1-H10 to select an egress port for forwarding the packet. Hash bits H1-H3 may be associated with certain egress ports of egress ports EP1-N. Therefore, the hash bit sequence is configuration information transmitted from the CC 206 to the HS switch 116 to enable the HS switch 116 to select an egress port by associating the hash bit sequence with the ingress port.

[0035] Therefore, in at least one embodiment, CC 206 senses the number of egress ports EP1-EPN 420 from different connected devices (such as between switch to switch and switch to host) and uses this information to determine the distribution of the hash bit order. For example, CC 206 divides the number of hash bits of the hash between each path of the router layer identified for the packet. CC 206 informs the switch to use a number of bits in the hash, such as in order from the leftmost bit to the rightmost bit. In each routing layer, the ingress port is associated with the hash bit order so that the egress port can be selected using the hash bits in a determined order.

[0036] In at least one embodiment, for a 10-bit hash, the 10 bits may be divided into two different 5-bit sets. This may be sufficient to address 32 egress ports in different connected devices at different routing layers. A switch-to-switch connection may then use 5 of the 10 bits, and a subsequent switch-to-host connection may use the remaining 5 bits. Additionally, 2 different bits in each direction may be sufficient to select an egress port, and only 8 bits may be required for four routing layers. Thus, in at least one embodiment, by performing a scan on the connected devices, the maximum size of the egress port for each connected device is known to CC 206. Each ingress port is associated with one or more different hash bits, which may be the same for different switches and allow the same egress port to be selected for different switches.

[0037] In at least one embodiment, the CC 206 can receive and provide configuration information 446 to one or more HS hosts 120, 312, and can also receive and provide configuration information 446 to one or more HS switches 116. At least a portion of this configuration information can be retained as subnet information 206A. The information can include the available egress ports EP1-EPN 420 of all HS switches 116 in the subnet; forwarding rules 422 that identify the available egress ports in each routing layer to prioritize traffic flows 440; and all active host ports 424 of the HS hosts 120, 312. The CC 206 receives the configuration information 446, but provides the configuration information 446 to at least the HS switch 116 or HS router 114. The configuration information 446 provided to the HS switch 116 or HS router defines the use of hashing (such as through forwarding rules 422) based on the network information it receives, including the available egress ports EP1-EPN 420 of the switch. In at least one embodiment, different portions of the hash in the headers 416A, 416B may be used to specify or apply to different routing layers. Thus, a portion of the hash may be used by each HS switch 116 to select at least one of its available egress ports as indicated by the CC 206, thereby reflecting the use of the hash for the available egress ports EP1-EPN 420 in each routing layer.

[0038] In at least one embodiment, the HS switch 116 or router may include two steps for forwarding a received packet. In the first step, the HS switch 116 or router may determine at least one of the available egress ports EP1-N 314C based in part on at least one different portion of a hash for specifying different routing layers from at least one available egress port. In the second step, the HS switch 116 or router sends a communication such as a data packet 418 with or without a header 416A, 416B from the HS switch 116 or router to at least one receiving HS host 312 using the at least one available egress port EP1-N 314C determined in the first step and using one of the different routing layers. In at least one embodiment, since the hash has portions for different routing layers, the process for the HS switch 116 herein applies to all switches in the different routing layers. Therefore, the headers 416A, 416B are provided with the data packets 418 for all forward transmissions, but the last switch immediately before the receiving HS host 312 may provide the data packet 418 with the header removed separately.

[0039] In at least one embodiment, the HS hosts 120, 312, the HS switches 116, the HS routers 114, and the CC 206 are all part of a system having one or more processing units adapted with communication capabilities. In the example of the HS hosts 120, 312, the one or more processing units 320, 402 may be installed in the host. The one or more processing units may perform a hash function based in part on an address associated with a communication from the HS hosts 120, 312. The communication capabilities may include an agent 310 for communicating with the CC 206 and for loading data into a data packet 418 having an associated header 416A, 416B. The communication capabilities enable communications such as traffic 440 to be provided by one or more processing units together with a hash of a hash function included in the header 416A, 416B from the communication.

[0040] In at least one embodiment, each session between the sending HS host 120 and one of the receiving / target HS hosts 312 may use the same hash value in the header. However, based in part on the HS host 120 providing new communications with a new hash in a new session associated with the same sending HS host 120 and the same one of the receiving / target HS hosts 312, the switch or router is further configured to update the hash to provide a new hash. Then, based in part on updating at least one available egress port, some of which may be inactive or busy, and based in part on determining and updating at least one available egress port previously used in the session, a different available egress port is provided or enabled to transmit the new communications in the new session between the same sending HS host and the same one of the receiving / target HS hosts 312.

[0041] In at least one embodiment, CC 206 can provide configuration information to HS switch 116 or HS router 114. The configuration information can enable the switch or router to use the hash in the header to determine at least one available egress port for transmitting the data packet from the switch or router. In at least one embodiment, software service 402A of HS host 120 can support a hash function to generate a hash for the header of the data packet.

[0042] In at least one embodiment, Figure 4B Details 450 associated with a memory access protocol are shown. A system for a high speed (HS) data network may include at least a source HS host 120, which may be a source HS host. Figures 1 to 4AThe system may include a target HS host or other HS host 312, which may also be a HS host and may be a target of the source HS host 120. The system includes a HS switch 116, which is capable of receiving communications such as data packets 418 from the source HS host 120 to access the memory space 452 of the target HS host 312.

[0043] In at least one embodiment, the communication includes an association with a memory access protocol (MAP) as provided by the second header portion 416B. For example, the second header portion 416B includes a request 458 (labeled as MAPReq) associated with a memory access protocol of a memory space 452 of the target HS host 312. The HS switch 116 provides the communication request 454 to the target HS host 312. The target HS host 312 provides a response 456 whose communication portion also includes an association with the memory access protocol (MAP). For example, the response 456 includes a response 460 (labeled as MAPRsp) associated with the memory access protocol. The response 456 enables subsequent communication from the source HS host 120 to the target HS host 312, wherein the communication is based in part on the memory access protocol received in response to the request.

[0044] In at least one embodiment, the memory access protocol defines the read, write, and atomic capabilities associated with the memory space 452 of the target HS host 312, and may be provided as part of different attributes in the header portion of the MAPReq 458 or MAPRsp 460. For example, one or more of the header portions of the MAPReq 458 or MAPRsp 460 may include one or more of a byte enable or data attribute, a header attribute, and an address extension attribute. Additionally, the MAPRsp 460 header portion may include attributes that can be used to indicate a data format to respond with data, such as used by a graphics device to enable compression of read data.

[0045] In another example, the attributes of the MAPReq 458 header portion supported by the appropriate response in the attributes of the MAPRsp 460 header portion are related to several data bytes that are operated as part of the business. This may represent data carried in the request (including writes), data carried in the response (including reads), or data carried by both (including atomic operations). Another attribute provided by the MAPReq 458 header portion for triggering an appropriate response may be related to whether the request is for a consistent memory system. For example, this helps determine whether the target HS host should or should not generate a probe. In at least one embodiment, this field may also be used if the source HS host determines that the probe is unnecessary and only provides bits for fields associated with a consistent memory system to act as performance hints.

[0046] In at least one embodiment, the communication further includes a partition key that can be part of a header portion marked as routing header 462. The partition key can be used by at least one additional switch in addition to the first switch HS116. For example, at least one additional switch in the route between the source host and the target host can use the partition key to forward the communication based at least in part on the partition key being associated with a storage key of the at least one additional switch. In at least one embodiment, the partition key is used to determine the source host's membership in the partition and can be checked on the target host to ensure that communication between them is allowed.

[0047] In at least one embodiment, the system includes a source graphics processing unit (GPU) 120A adapted to have communication capabilities. In addition, the source GPU is installed in the source HS host 120. The source GPU 120A performs a hash function based in part on a source identifier, such as an address, of the source host and a target identifier of the target host to provide a hash for an identifier header portion 416A of the data packet 418. The hash occupies a first set of bits in the header position (such as the identifier header portion 416A) adjacent to a second set of bits used by the memory access protocol (such as the MAP header portion 416B), such as Figure 4B Additionally, the HS switch 116 will use hashing to allow routing of the communication to the destination host.

[0048] In at least one embodiment, source GPU 120A includes the memory access protocol of target GPU 464 in the communication using an identifier header portion 416A disposed in a range of bits preceding the memory access protocol, such as in header portion 416B. The identifier informs target GPU 464 of the location of the memory access protocol in the communication. HS switch 116 may be further adapted to include a mapping of target identifiers including a target host and a set of egress ports associated with the target host.

[0049] Thus, in at least one embodiment, one or more processing units, such as GPU 120A, 464, may be associated with at least one HS switch 116 or HS router 114 and may enable at least one HS switch 116 or HS router 114 to receive communications, such as data packets 418, from a source host. The communications may include a request (MAPReq) 458 associated with a memory access protocol of a memory space 452 of a target HS host 312. The communications may be provided to the target HS host 312 to enable subsequent communications from the source HS host 120, wherein the subsequent communications are based in part on the memory access protocol received in a response (MAPRsp) 460 to the request (MAPReq) 458.

[0050] In at least one embodiment, Figure 5A A process flow or method 500 of a system for header modification to include an association with a memory access protocol and a hash is shown. The method 500 for communication in a high speed (HS) data network includes receiving 502 a communication from a source host in a switch to access a memory space of a target host. The method 500 includes determining 504 that the communication includes a request associated with a memory access protocol of the memory space of the target host. The method 500 may also include determining 504 that the communication includes a hash. The hash may be determined 506 from the hash and the hash may be used in the switch to determine 508 an egress port for onward transmission of the communication. In at least one embodiment, the method 500 includes providing 510 the communication to the target host to enable subsequent communication from the source host based in part on the memory access protocol received in response to the request. In addition, the communication may be provided 510 to the target host using the egress port of step 508.

[0051] In at least one embodiment, the method 500 includes: using a memory access protocol that defines read, write, and atomic operation capabilities associated with the storage of the target host. In addition, the method 500 also includes support for the communication to further have a partition key used by at least one additional switch between the source host and the target host to forward the communication. For example, based at least in part on the partition key being associated with the storage key of the at least one additional switch, the at least one additional switch can determine the membership of the source host in the partition, and the membership of the source host in the partition can also be checked on the target host to ensure that the communication is allowed.

[0052] In at least one embodiment, method 500 includes providing communication capabilities in a source graphics processing unit (GPU) to be installed in a source host. Method 500 includes using the source GPU to perform a hash function based in part on a source identifier of the source host and a target identifier of the target host to provide a hash. The hash can then be arranged to occupy a first set of bits in a header location adjacent to a second set of bits used by a memory access protocol. In addition, a switch can use the hash to allow the communication to be routed to the target host. In at least one embodiment, method 500 includes using the source GPU to include a memory access protocol of the target GPU in the communication using an identifier in a bit range arranged before the memory access protocol. Method 500 includes enabling the target GPU to determine the location of the memory access protocol in the communication based in part on the identifier.

[0053] In at least one embodiment, the method 500 includes: further supporting communication by including one or more of byte enable or data attributes, request header attributes, and address extension attributes therein. In addition, the switch of the method 500 herein may include a mapping of a target identifier. The target identifier includes a target host and a set of egress ports of the switch associated with the target host.

[0054] In at least one embodiment, Figure 5B A process flow or method 550 of a system for header modification to include an association with a memory access protocol and a hash is shown in accordance with at least one embodiment. The method 550 may be used in conjunction with Figure 5A The method 500 is performed together for the same communication. The method 550 includes: receiving 552 a communication from a host in at least one switch or router of one of the different routing layers. The method includes: verifying or determining 554 that the communication includes an association with a memory access protocol and a hash. The method includes: a further determination 556 step such as from a hash to a hash from a header. In the method 550, another further determination 508 step is performed for at least one of the available egress ports of at least one switch or router that can be used to transmit the data packet to at least one receiving host. At least one of the available egress ports is determined at least in part based on the hash in the header. The method includes: using at least one of the available egress ports determined in step 558 to transmit 560 the data packet used to support the communication of step 510. In at least one embodiment, the method 550 includes: a step or sub-step for determining, on the host, a hash to be provided in the header based on a hash function applied to at least an address associated with the communication from the host. This is in Figure 7 The method 700 is described in detail.

[0055] In at least one embodiment, Figure 6 A process flow or method 600 of a system for header modification to include an association with a memory access protocol and a hash is shown. The method 600 includes determining 602 an ingress port of at least one switch or router of a different routing layer through which the packet is received. The method 600 includes enabling 604 selection or determination for at least one of the available egress ports used in communications between a sending host and a destination / receiving host. The selection or determination is made based in part on a different portion of the hash, such as using a hash order associated with the ingress port. The different portion of the hash is used to specify a different routing layer starting from the at least one available egress port.

[0056] The method 600 includes verifying 606 whether an available egress port is selected or determined. The method 600 includes enabling 608 one of the available egress ports for transmission for at least one switch or router. The method 600 includes transmitting 610 the data packet from the switch or router to at least one receiving host using the at least one available egress port and using one of the different routing layers, as in steps 510, 560.

[0057] In at least one embodiment, Figure 7 A process flow or method 700 of a system for header modification to include an association with a memory access protocol and a hash is shown. The method 700 may be performed in a host adapted for use in an HS network with an agent and in communication with a CC as described herein. The method includes providing 702 one or more processing units having communication capabilities and installed in the host. The providing 702 step may be supported by installing one or more GPUs in the host capable of peer-to-peer communication using an agent in CC communication. The method 700 includes verifying 704 whether there is a data packet for communication from one or more processing units. The method 700 includes performing 706 a hash function based in part on an address associated with a communication from the host using one or more processing units. The address may be an address of the host and an address of a target host or a receiving host. The address may be a port identifier of these respective hosts. The method 700 also includes preparing 706 a data packet to include an association with a memory access protocol for the target host.

[0058] The method 700 includes enabling 708, using the communication capability, a communication from one or more processing units having a hash from a hash function included in a header of the communication. In at least one embodiment, one of such methods 500-700 may include a step or sub-step for updating the hash to provide a new hash, such as a new hash sent from the host and stored in the switch. The updating may be based in part on the host providing a new communication with the new hash in a new session associated with the receiving host. The new session may be a period of time after a previous communication between the host and the receiving host ended.

[0059] In at least one embodiment, one of the methods 500-700 may include a step or sub-step for updating at least one available egress port previously used between the hosts based in part on the new hash. This is to provide a different available egress port to transmit the new communication to the receiving host. In at least one embodiment, one of the methods 500-700 may include a step or sub-step for providing configuration information to a switch or router using a centralized controller. For example, the configuration information may include forwarding rules for available ports of the target host or forwarding rules for subsequent switches and routers of the remaining routing layers.

[0060] In at least one embodiment, one of the methods 500-700 may include steps or sub-steps for using configuration information to enable a switch or router to use a hash in a header for selecting at least one available egress port for transmitting a data packet from the switch or router. For example, the switch, by using forwarding rules, can apply the appropriate portion of the hash from the header to determine the egress port to be used for transmission. In at least one embodiment, one of the methods 500-700 may include steps or sub-steps for enabling a hash function using a software service of a host to generate a hash of a header of a data packet.

[0061] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described in detail above. However, it should be understood that it is not intended to limit the present disclosure to one or more specific forms disclosed, but on the contrary, it is intended to cover all modifications, alternative constructions, and equivalents that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0062] In the context of describing the disclosed embodiments (especially in the context of the following claims), the use of the terms "one" and "a kind of" and "said" and similar indicators should be interpreted as covering both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context, and not as a definition of the term. Unless otherwise noted, the terms "comprise", "have", "include" and "contain" should be interpreted as open terms (meaning "including but not limited to"). When not modified and referring to a physical connection, "connection" should be interpreted as being partially or completely contained in, attached to or connected together, even if there is an intervening object. Unless otherwise indicated herein, the statement of the value range herein is intended only to be used as a shorthand method to refer to each individual value falling within the range individually, and each individual value is incorporated into the specification as it is individually stated herein. In at least one embodiment, unless otherwise indicated or the context is contradictory, the use of the term "set" (e.g., "item set") or "subset" will be interpreted as a non-empty set including one or more members. Furthermore, unless otherwise stated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0063] Unless otherwise expressly stated or otherwise clearly contradicted by context, conjunction language (such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C") is also understood together with context to be generally used to present that an item, term, etc. can be any non-empty subset of the set of A or B or C, or A and B and C. For example, in the exemplary example of a group with three members, the conjunction phrases "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following groups: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Therefore, such conjunction language is generally not intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C, respectively. In addition, unless otherwise stated or contradicted by context, the term "plurality" means a plurality of states (e.g., "a plurality of items" means a plurality of items). In at least one embodiment, the number of items in the plurality is at least two, but can be more when explicitly or by context so indicates. Further, the phrase "based on" means "based at least in part on" rather than "based solely on" unless stated otherwise or otherwise clear from the context.

[0064] The operations of the processes described herein may be performed in any suitable order, unless otherwise indicated herein or otherwise clearly contradictory to the context. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions, and are implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed together on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program including a plurality of instructions that can be executed by one or more processors.

[0065] In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that does not include transient signals (e.g., propagating transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuits (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a collection of one or more non-transitory computer-readable storage media having executable instructions stored thereon (or other memory for storing executable instructions), which when executed (i.e., due to being executed) by one or more processors of a computer system causes the computer system to perform the operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lack all codes, while the plurality of non-transitory computer-readable storage media collectively store all codes. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors. For example, a non-transitory computer-readable storage medium stores instructions, a main central processing unit ("CPU") executes some instructions, and a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0066] In at least one embodiment, the arithmetic logic unit is a group of combinational logic circuits that accept one or more inputs to produce a result. In at least one embodiment, the processor uses the arithmetic logic unit to implement mathematical operations such as addition, subtraction, or multiplication. In at least one embodiment, the arithmetic logic unit is used to implement logical operations such as logical AND / OR or XOR. In at least one embodiment, the arithmetic logic unit is stateless and is made of physical switching elements, such as semiconductor transistors arranged to form logic gates. In at least one embodiment, the arithmetic logic unit can be constructed as an asynchronous logic circuit with an internal state that is not maintained in an associated register group. In at least one embodiment, the processor uses the arithmetic logic unit to combine operands stored in one or more registers of the processor and generate an output that can be stored by the processor in another register or storage location.

[0067] In at least one embodiment, as a result of processing instructions retrieved by the processor, the processor presents one or more inputs or operands to the arithmetic logic unit, causing the arithmetic logic unit to produce a result based at least in part on the instruction code provided to the input of the arithmetic logic unit. In at least one embodiment, the instruction code provided by the processor to the ALU is based at least in part on the instruction executed by the processor. In at least one embodiment, the combinational logic in the ALU processes the inputs and produces outputs that are placed on a bus within the processor. In at least one embodiment, the processor selects a target register, memory location, output device, or output storage location on an output bus so that the processor is clocked to send the result produced by the ALU to a desired location.

[0068] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software capable of performing the operations. Further, a computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment, is a distributed computer system comprising multiple devices that operate differently, such that the distributed computer system performs the operations described herein, and such that a single device does not perform all operations.

[0069] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate embodiments of the present disclosure and does not limit the scope of the present disclosure unless otherwise required. Language in the specification should not be construed as indicating any non-claimed element is essential to the practice of the present disclosure.

[0070] In the specification and claims, the terms "coupled" and "connected" and their derivatives may be used. It should be understood that these terms are not intended to be synonymous with each other. On the contrary, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0071] Unless specifically stated otherwise, it will be appreciated that throughout the specification terms such as "processing," "computing," "calculating," "determining," or similar terms refer to the action and / or process of a computer or computing system or similar electronic computing device that manipulates and / or transforms data represented as physical (such as electronic) quantities within the computing system's registers and / or memories into other data similarly represented as physical quantities within the computing system's memories, registers, or other such information storage, transmission, or display devices.

[0072] In a similar manner, the term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Moreover, each process may refer to multiple processes for executing instructions sequentially or in parallel, continuously or intermittently. In at least one embodiment, the terms "system" and "method" are used interchangeably herein, as long as the system can embody one or more methods and the method can be considered a system.

[0073] In this document, reference may be made to obtaining, acquiring, receiving or inputting analog or digital data into a subsystem, a computer system or a computer-implemented machine. In at least one embodiment, the process of obtaining, acquiring, receiving or inputting analog and digital data may be accomplished in various ways, such as by receiving data as a parameter of a function call or a call to an application programming interface. In at least one embodiment, the process of obtaining, acquiring, receiving or inputting analog or digital data may be accomplished by transmitting data via a serial or parallel interface. In at least one embodiment, the process of obtaining, acquiring, receiving or inputting analog or digital data may be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. In at least one embodiment, reference may also be made to providing, outputting, transmitting, sending or presenting analog or digital data. In different examples, the process of providing, outputting, transmitting, sending or presenting analog or digital data may be accomplished by transmitting data as an input or output parameter of a function call, a parameter of an application programming interface or an inter-process communication mechanism.

[0074] Although the description herein sets forth example embodiments of the described technology, other architectures may be used to implement the described functionality and are intended to be within the scope of the present disclosure. In addition, although a specific distribution of responsibilities may be defined above for descriptive purposes, the various functions and responsibilities may be distributed and divided in different ways depending on the environment.

[0075] In addition, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Instead, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

1. A system for a high-speed HS data network, comprising: A switch, the switch being configured to receive communications from a source host to access a memory space of a target host, the communications comprising a request associated with a memory access protocol for the memory space of the target host, and to provide the communications to the target host to enable subsequent communications from the source host based in part on the memory access protocol received in response to the request.

2. The system of claim 1, wherein the memory access protocol defines read, write, and atomic operation capabilities associated with the memory space of the target host.

3. The system of claim 1 , wherein the communication further comprises a partition key to be used by at least one additional switch between the source host and the target host to forward the communication based at least in part on an association of the partition key with a storage key of the at least one additional switch.

4. The system of claim 1, further comprising: a source graphics processing unit (GPU) adapted to have communication capabilities and to be installed in the source host, the source GPU performing a hash function based in part on a source identifier of the source host and a target identifier of the target host to provide a hash, the hash occupying a first set of bits in a header location adjacent to a second set of bits used by the memory access protocol, and the hash to be used by the switch to allow routing of the communication to the target host.

5. The system of claim 1, further comprising: A source GPU is configured to include the memory access protocol of the target GPU in the communication using an identifier arranged in a bit range preceding the memory access protocol, wherein the identifier is configured to notify the target GPU of a location of the memory access protocol in the communication.

6. The system of claim 1, wherein the communication further includes one or more of a byte enable or data attribute, a request header attribute, and an address extension attribute.

7. The system of claim 1, wherein the switch further comprises a map of the target identifier, the map of the target identifier comprising the target host and a set of egress ports associated with the target host.

8. A method for communicating in a high speed (HS) data network, the method comprising: receiving, in the switch, communications from a source host to access a memory space of a destination host; determining that the communication includes a request associated with a memory access protocol of the memory space of the target host; as well as The communication is provided to the target host to enable subsequent communication from the source host based in part on the memory access protocol received in response to the request.

9. The method of claim 8, wherein the memory access protocol defines read, write, and atomic operation capabilities associated with the memory space of the target host.

10. The method of claim 8, wherein the communication further comprises a partition key to be used by at least one additional switch between the source host and the target host to forward the communication based at least in part on an association of the partition key with a storage key of the at least one additional switch.

11. The method of claim 8, further comprising: providing communication capabilities in a source graphics processing unit (GPU) to be installed on the source host; performing, using the source GPU, a hash function based in part on a source identifier of the source host and a target identifier of the target host to provide a hash; as well as The hash is arranged to occupy a first set of bits in a header location adjacent to a second set of bits used by the memory access protocol, and the hash is to be used by the switch to allow routing of the communication to the target host.

12. The method of claim 8, further comprising: Using a source GPU, including the memory access protocol of the target GPU in the communication using an identifier arranged within a one-bit range preceding the memory access protocol; as well as A target GPU is enabled to determine a location of the memory access protocol in the communication based in part on the identifier.

13. The method of claim 8, wherein the communication further includes one or more of a byte enable or data attribute, a request header attribute, and an address extension attribute.

14. The method of claim 8, wherein the switch further comprises a map of the target identifier, the map of the target identifier comprising the target host and a set of egress ports associated with the target host.

15. A system comprising: One or more processing units to be associated with at least one switch or router and to enable the at least one switch or router to receive communications from a source host, the communications including requests associated with a memory access protocol for a memory space of a target host, the communications to be provided to the target host to enable subsequent communications from the source host based in part on the memory access protocol received in response to the requests.

16. The system of claim 15, wherein the memory access protocol defines read, write, and atomic operation capabilities associated with the memory space of the target host.

17. The system of claim 15, wherein the communication further comprises a partition key to be used by at least one additional switch between the source host and the target host to forward the communication based at least in part on an association of the partition key with a storage key of the at least one additional switch.

18. The system of claim 15, wherein at least one of the one or more processing units is further adapted with communication capabilities and is to be installed in the source host to perform a hash function based in part on a source identifier of the source host and a target identifier of the target host to provide a hash, the hash occupying a first set of bits in a header location adjacent to a second set of bits used by the memory access protocol, and the hash is to be used by the switch to allow the communication to be routed to the target host.

19. The system of claim 15, wherein the one or more processing units further include the memory access protocol of the target GPU in the communication using an identifier arranged within a one-bit range before the memory access protocol, wherein the identifier is used to notify the target GPU of the location of the memory access protocol in the communication.

20. The system of claim 15, wherein the communication further includes one or more of a byte enable or data attribute, a request header attribute, and an address extension attribute.

Images