25Gbps full-switching general VPX modular high-speed backboard

Abstract

The invention discloses a 25Gbps full-switching universal VPX modular high-speed backboard, and relates to the technical field of communication, the 25Gbps full-switching universal VPX modular high-speed backboard comprises a VPX high-speed backboard, a network switching module and a power supply circuit module for supplying power to the VPX high-speed backboard, the VPX high-speed backboard comprises a VPX single board computer unit, a plurality of VPX single board computer chips, a plurality of VPX single board computer chips, a plurality of VPX single board computer chips, a plurality of VPX single board computer chips and a plurality of VPX single board computer chips, the clock distribution unit comprises a clock generator and a level translator, and the clock generator and the level translator receive the signal transmitted in one direction from the communication plate sheet through the PCle switching unit; and the PCIe exchange unit comprises a PEX8796 exchange chip and an FPGA (Field Programmable Gate Array) chip which are respectively in signal connection with the communication board and the storage board. The method has the advantages of providing high-bandwidth switching capacity and high-flexibility design, and has the beneficial effects that an efficient data switching mechanism and high expandability can be considered at the same time.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a 25Gbps full-switching universal VPX modular high-speed backplane. Background Art

[0002] For complex signal processing or measurement and control systems, the system is usually composed of multiple functional modules. The transmission of low-speed control signals (usually less than 10Mbps) and high-speed data signals (usually greater than 10Gbps) between modules is achieved through a backplane with multiple slots. The backplane provides power supply for each module and signal interconnection between slots, and is the core unit of a large system.

[0003] The VITA65 backplane standard is proposed to standardize the interconnection design between modules. It mainly defines two interconnection architectures: full-mesh structure and master-slave switching structure. Although these structures are effective in some general applications, they have obvious disadvantages in systems with high bandwidth requirements. On the one hand, the full-mesh structure and master-slave switching structure of the backplane under the VITA65 standard are limited by the number of connector interfaces. In particular, the full-mesh structure usually has only 4 pairs of high-speed interconnection lines between slots, with a maximum bandwidth of 40Gbps; while in the master-slave switching structure, data exchange between slots needs to pass through the central switching board, and the bandwidth of the switching board becomes the bottleneck of the system. Taking SRIO2.0x4 as an example, its high-speed switching bandwidth is only 20Gbps, which may not provide sufficient switching capacity for some systems that require large bandwidth transmission, resulting in signal transmission delay and insufficient bandwidth. This obviously cannot meet the requirements for some complex systems that require higher bandwidth. On the other hand, since each project needs to redesign the backplane, especially when the requirements between projects are small but still need to be customized, the customized backplane requires special design and verification work, and it is difficult to improve design efficiency through standardized methods, which will lead to repeated design work and waste of a lot of R&D resources. Summary of the invention

[0004] The present invention provides a 25Gbps fully-switched universal VPX modular high-speed backplane, which solves the problem in the existing communication backplane technology that it is difficult to achieve rapid universalization and high-speed interaction of the backplane while ensuring high-capacity broadband.

[0005] The present invention is achieved through the following technical solutions: A 25Gbps fully switched universal VPX modular high-speed backplane, comprising a VPX high-speed backplane, a network switching module and a power circuit module for supplying power to the VPX high-speed backplane, wherein the VPX high-speed backplane comprises: VPX single board computer unit: including a number of VPX single board computer chips, each VPX single board computer chip is signal connected to the PCle switching unit, two VPX single board computers are respectively set as communication boards and storage boards, and the remaining VPX single board computers are set as peripheral boards, and the communication boards and storage boards are both signal connected to the clock distribution unit; Clock distribution unit: including a clock generator and a level converter, the clock generator and the level converter receive the signal transmitted unidirectionally from the communication board through the PCle switching unit, and the clock generator and the level converter transmit the signal unidirectionally to the PEX8796 switching chip and the storage board in the PCle switching unit at the same time; PCle switching unit: includes a PEX8796 switching chip and an FPGA chip that maintain signal connection with each other. The PEX8796 switching chip maintains signal connection with the communication board and the storage board respectively, and the FPGA chip maintains signal connection with each peripheral chip respectively, and the input end of the FPGA chip is connected to the external second pulse PPS timing signal.

[0006] In the existing communication backplane technology, on the one hand, the full-mesh structure and master-slave switching structure of the backplane under the VITA65 standard are limited by the number of connector interfaces. In particular, in the full-mesh structure, the high-speed interconnection lines between the slots are usually only 4 pairs, and the bandwidth is up to 40Gbps; while in the master-slave switching structure, the data exchange between the slots needs to pass through the central switching board, and the switching board bandwidth becomes the bottleneck of the system. Taking SRIO2.0x4 as an example, its high-speed switching bandwidth is only 20Gbps, which may not provide sufficient switching capacity for some systems that require large bandwidth transmission, resulting in signal transmission delay and insufficient bandwidth. This is obviously unable to meet the requirements for some complex systems that require higher bandwidth. On the other hand, since each project needs to redesign the backplane, especially when the demand difference between the projects is small but still needs to be customized, the customized backplane requires special design and verification work, and it is difficult to improve the design efficiency through standardized methods, which will lead to repeated design work and waste of a large amount of research and development resources. Based on this, the present invention provides a 25Gbps full-switch universal VPX modular high-speed backplane to solve the problem that it is difficult to achieve fast universality and high-speed interaction of the backplane in the existing communication backplane technology while ensuring high-capacity broadband.

[0007] Furthermore, the VPX high-speed backplane also includes a crystal oscillator module and a clock module; the crystal oscillator module includes a crystal oscillator element with a frequency of 156.25 MHz, and the clock module includes a clock buffer, and the four clock output ports of the clock buffer transmit the clock signal to the communication board through the LVDS differential signal.

[0008] Furthermore, the crystal oscillator module further includes a low phase noise temperature compensated crystal oscillator element with a frequency of 100 MHz, and the clock module further includes a clock selector, which selects one of at least two clock sources to perform auxiliary clock synchronization on the LVDS signal.

[0009] Furthermore, the PCle switching unit also includes two extended control IO modules, and the two extended control IO modules maintain a two-way communication connection with the FPGA chip; each of the extended control IO modules has a JL23-16ZIB chip, and the JL23-16ZIB chip uses a 12V voltage; every two of the JL23-16ZIB chips form a group of IO chipsets, and the number of the IO chipsets is the same as the number of VPX single-board computer chips.

[0010] Furthermore, the FPGA chip is also connected to a serial communication circuit from the outside, and the serial communication circuit is used to provide a timing receiving port for the FPGA chip; the serial communication circuit includes an RS422 circuit and an RS232 circuit; the RS422 circuit is constructed based on the MAX3490 transceiver chip, and the RS232 circuit is constructed based on the MAX3232EUE transceiver chip.

[0011] Furthermore, the network switching module includes an 88E6350R switch chip, and the 88E6350R switch chip maintains a single independent Ethernet signal connection with the communication board and each peripheral board through a BaseT interface.

[0012] Furthermore, the network switching module also includes a KSZ9031 physical layer chip, which is connected to the RGMII interface of the 88E6350R switch chip via the RGMII interface, and the BaseT interface of the KSZ9031 physical layer chip is connected to a backplane RJ45 socket.

[0013] Furthermore, the clock generator uses a 9DB433AGLFT generator chip, and the level converter uses a 74AVC9112DCH converter chip.

[0014] Furthermore, the signal connection between the PEX8796 switching chip and the FPGA chip adopts a 16-bit PCle3.0 bus; the signal connection between the PEX8796 switching chip and the communication board, and between the PEX8796 switching chip and the storage board adopts a 16-bit PCle3.0 bus; the signal connection between the FPGA chip and each peripheral chip adopts an 8-bit LVDS bus.

[0015] Furthermore, the PCle switching unit also includes a VU9P_PCle chip, and the clock generator transmits the signal to the VU9P_PCle chip after receiving the signal from the communication board.

[0016] Compared with the prior art, the present invention adopts a standardized design method and a modular system architecture, and adopts a combination of a VPX single board, a PEX8796 switching chip and an FPGA chip, which can support high-speed exchange of large-bandwidth data, so that the system can be customized and expanded according to actual needs without redesigning the entire backplane. Users can adapt to different functional requirements by quickly replacing or customizing each module. It has the advantages of providing high-bandwidth switching capabilities and high-flexibility design, and the beneficial effect of being able to take into account both efficient data exchange mechanisms and high scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings: Figure 1 It is a schematic diagram of the composition structure of the present invention; Figure 2 This is a schematic diagram of the VPX high-speed backplane structure of the present invention; Figure 3 It is a parameter curve diagram of the VPX high-speed backplane of the present invention. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention. Example

[0019] like Figure 1-Figure 2 As shown, this embodiment is a 25Gbps full-switching universal VPX modular high-speed backplane, including a VPX high-speed backplane, a network switching module, and a power circuit module for supplying power to the VPX high-speed backplane. The VPX high-speed backplane includes: VPX single board computer unit: including a number of VPX single board computer chips, each VPX single board computer chip is signal connected to the PCle switching unit, two VPX single board computers are respectively set as communication boards and storage boards, and the remaining VPX single board computers are set as peripheral boards, and the communication boards and storage boards are both signal connected to the clock distribution unit; Clock distribution unit: including a clock generator and a level converter, the clock generator and the level converter receive the signal transmitted unidirectionally from the communication board through the PCle switching unit, and the clock generator and the level converter transmit the signal unidirectionally to the PEX8796 switching chip and the storage board in the PCle switching unit at the same time; PCle switching unit: includes a PEX8796 switching chip and an FPGA chip that maintain signal connection with each other. The PEX8796 switching chip maintains signal connection with the communication board and the storage board respectively, and the FPGA chip maintains signal connection with each peripheral chip respectively, and the input end of the FPGA chip is connected to the external second pulse PPS timing signal.

[0020] The system includes multiple VPX single-board computer chips, two of which are set as communication boards and storage boards, and the rest are peripheral boards. This configuration ensures that the communication and storage modules can be responsible for data transmission and storage tasks, while the peripheral boards handle other auxiliary tasks. Through this division of labor, the system can optimize the workload of different modules while ensuring data transmission efficiency; each VPX single-board computer maintains a signal connection with the PCle switching unit to achieve high-speed data transmission. The clock generator and level converter generate and distribute clock signals by receiving unidirectional signals from the communication board. This mechanism ensures the clock synchronization of all modules and ensures the correct transmission and processing of data. The PEX8796 switching chip is a high-bandwidth switching chip that can support a switching rate of up to 25Gbps and is a core component for achieving 25Gbps high-speed data exchange. Through the PEX8796 switching chip, the signals of the communication board and the storage board can be exchanged quickly and stably. The FPGA chip can exchange signals with peripheral chips as needed, and can be configured according to system requirements, providing higher flexibility. At the same time, the FPGA can also process external pulse-per-second PPS synchronization signals to ensure accurate time synchronization of the system. The power circuit module provides the necessary power for the entire system, ensuring that the system can operate stably while maintaining high bandwidth and high-speed switching. The parameter curve of the VPX high-speed backplane is shown in Figure 1. Figure 3 As shown in the figure, 25Gpbs signal is transmitted on the backplane, passing through the connector and the backplane PCB routing, and the routing distance is usually more than 10000 mil (about 25cm). During the transmission process, apart from the influence of the routing length, any other impedance discontinuity will deteriorate the receiving eye diagram of the signal transmission, causing the signal to be unable to be received or bit errors. PCB passive optimization for high-speed signals is the key to the normal transmission of high-speed signals. The method is to improve the impedance discontinuity through simulation, reduce the insertion loss and return loss of the transmission link, and ensure that the signal eye diagram at the receiving end meets the protocol standard.

[0021] As a feasible implementation, in specific applications, the PCle switching unit also includes a VU9P_PCle chip, and the clock generator transmits the signal to the VU9P_PCle chip after receiving the signal of the communication board; the clock generator uses the 9DB433AGLFT generator chip, and the level converter uses the 74AVC9112DCH converter chip. As an FPGA chip, the VU9P_PCle chip enhances the flexibility and processing power of the system, and is mainly used to process tasks that require high parallel computing and provide an interface with an external system. Incorporating the VU9P_PCle chip into the PCle switching unit can further enhance the computing power and data processing capabilities of the system; it is usually used for high-throughput, low-latency tasks, and supports PCIe Gen3 / Gen4, has very strong parallel processing capabilities, and can handle large-scale data exchanges and complex data flows. The 74AVC9112DCH is a level converter chip that supports level conversion between different voltage levels and is usually used to convert between different logic levels. It can handle bidirectional signal transmission and is usually used in systems that need to work across multiple voltage domains. The 9DB433AGLFT is a high-performance clock generator chip, which is usually used to provide a stable clock signal, and it has high-frequency output and good timing accuracy; this chip can generate clock signals of multiple frequencies and is usually used as a synchronous clock source in high-speed data transmission systems.

[0022] Furthermore, as a feasible implementation, the VPX high-speed backplane also includes a crystal oscillator module and a clock module; the crystal oscillator module includes a crystal oscillator element with a frequency of 156.25 MHz, and the clock module includes a clock buffer, and the four clock output ports of the clock buffer transmit the clock signal to the communication board through an LVDS differential signal; the crystal oscillator module also includes a low phase noise temperature compensated crystal oscillator element with a frequency of 100 MHz, and the clock module also includes a clock selector, and the clock selector selects one of at least two clock sources to perform auxiliary clock synchronization on the LVDS signal.

[0023] The 156.25 MHz crystal frequency is usually used for high-precision clock synchronization, mainly when it is necessary to match with a high-speed data communication system at the 10Gbps or 25Gbps level. For example, 156.25 MHz can be used as the reference frequency of the network clock to generate a clock signal that matches the data transmission rate. The low phase noise temperature compensated crystal oscillator has good frequency stability and is suitable for precise synchronization requirements. Its temperature compensation function means that temperature changes will not significantly affect the frequency of the crystal oscillator, thereby ensuring the stability of the system in various environments, while the 100 MHz frequency is usually used as an auxiliary clock source in the system. The crystal oscillator module provides a highly stable clock signal for the system, the 156.25 MHz crystal oscillator is the main clock source, and the 100 MHz low phase noise crystal oscillator provides higher clock stability; the precise generation of the clock signal ensures the consistency of the system timing. The clock buffer is used to enhance the driving force of the clock signal, distribute the clock signal from the crystal oscillator module to multiple transmission parts (such as communication boards, etc.), and transmit it through LVDS differential signals. LVDS (Low Voltage Differential Signal) can maintain signal integrity over a long transmission distance and has strong anti-interference ability, which enables the system to effectively avoid noise influence and signal attenuation during high-speed data transmission. The four clock output ports of the clock buffer transmit the clock signal to the communication board through the LVDS differential signal; during the transmission process, the differential characteristics of the LVDS signal ensure low signal loss and high anti-interference ability, which is particularly suitable for high-speed and long-distance clock signal transmission. The clock selector is used to select an optimal clock source from multiple clock sources for synchronization to ensure stable operation of the system under different conditions; in this embodiment, the clock selector can select at least two clock sources for selection, usually switching between a 156.25 MHz crystal oscillator and a 100 MHz low phase noise crystal oscillator. When the system requires higher stability (such as precise clock synchronization), the clock selector may select a 100 MHz low phase noise crystal oscillator; and under normal working conditions, a 156.25 MHz clock signal may be selected. Through the clock selector, it is possible to switch between multiple clock sources according to different system requirements to provide the most suitable clock signal. By introducing a low phase noise temperature compensated crystal oscillator and a clock selector, this embodiment can effectively reduce clock deviation and improve the synchronization accuracy of the system during long-term operation.

[0024] Furthermore, as a feasible implementation, the PCle switching unit also includes two extended control IO modules, and the two extended control IO modules maintain a two-way communication connection with the FPGA chip; each of the extended control IO modules has a JL23-16ZIB chip, and the JL23-16ZIB chip uses a 12V voltage; every two of the JL23-16ZIB chips form a group of IO chipsets, and the number of the IO chipsets is the same as the number of VPX single-board computer chips.

[0025] In this embodiment, if Figure 2 As shown, since the total number of VPX is set to 6, including 1 communication board, 1 storage board and 4 peripheral boards, the number of IO chipsets is 6. The extended control IO module is usually used to provide a communication interface with the outside of the system or between different modules, which can help realize data exchange, signal transmission and transmission of control instructions between modules. Each extended control IO module maintains a two-way communication connection with the FPGA chip, that is, the two modules can not only receive control signals, but also send feedback signals, thereby realizing real-time data exchange and control. The JL23-16ZIB chip is a common control IO chip, which is used to process various input and output interfaces, data conversion and signal transmission; it supports 12V voltage operation, carries higher power loads and has better electrical performance. By equipping each VPX single-board computer with an IO chipset, each module of the system can perform independent input and output operations as needed; each IO module cooperates with the FPGA chip through two-way communication, and the FPGA, as a control center, can flexibly manage the IO signals of each module. Each extended control IO module communicates bidirectionally with the FPGA chip, enabling real-time data interaction and control instruction transmission. FPGA, as the main control chip, coordinates the work between various modules and performs signal processing and routing.

[0026] Furthermore, as a feasible implementation method, the FPGA chip is also connected to a serial communication circuit from the outside, and the serial communication circuit is used to provide a timing receiving port for the FPGA chip; the serial communication circuit includes an RS422 circuit and an RS232 circuit; the RS422 circuit is constructed based on the MAX3490 transceiver chip, and the RS232 circuit is constructed based on the MAX3232EUE transceiver chip.

[0027] The serial communication circuit is used to provide a communication interface for FPGA with external devices, especially in applications that require timing signals or time synchronization; data and clock signals are transmitted through the serial interface, which can help the system achieve clock synchronization, data exchange and other functions. The RS422 circuit is a differential signal circuit with strong anti-interference ability and is suitable for long-distance transmission. The RS232 circuit is another serial communication circuit, which is usually used for shorter distance communication. When the timing signal or PPS signal is connected through the RS422 (differential transmission) or RS232 (single-ended transmission) circuit, the FPGA receives these signals and performs timing adjustment or synchronization processing according to them, wherein the timing signal is generally used to accurately synchronize the working timing of the FPGA. The FPGA chip adjusts its internal clock through the received timing signal, so that the entire system can work synchronously, thereby ensuring the accurate transmission of data and signals between multiple modules. Through the serial communication circuit, the FPGA can receive high-precision timing signals from the outside, achieve accurate clock synchronization, and ensure the coordinated work of various modules in the system.

[0028] Further, as a feasible implementation mode, the network switching module includes an 88E6350R switch chip, and the 88E6350R switch chip maintains a single independent Ethernet signal connection with the communication board and each peripheral board through a BaseT interface; the network switching module also includes a KSZ9031 physical layer chip, and the KSZ9031 physical layer chip is connected to the RGMII interface of the 88E6350R switch chip through an RGMII interface, and the BaseT interface connection of the KSZ9031 physical layer chip is provided with a backplane RJ45 socket.

[0029] The 88E6350R switch chip manages the data flow between each communication board by exchanging and forwarding data packets. Each board is connected to the switch chip through an independent Ethernet connection to ensure that data between different modules can be exchanged quickly and efficiently. The 88E6350R chip maintains independent Ethernet signal connections with the communication board and each peripheral board through the BaseT interface; each module exchanges data with the switch through an independent Ethernet connection, thereby avoiding data conflicts and improving system reliability. The RGMII is a low-pin count, low-power, high-speed data interface suitable for connecting Ethernet switch chips and PHY chips; the KSZ9031 chip processes data from the switch and converts it into physical layer signals that comply with Ethernet standards for transmission over Ethernet cables. Each VPX board (communication board and peripheral board) is connected to the 88E6350R switch chip through an independent BaseT interface. Data is sent from these boards to the switch chip, and the switch is responsible for exchanging data between the boards. Since each board maintains an independent Ethernet connection with the switch, data exchanges will not interfere with each other, ensuring efficient data transmission.

[0030] Furthermore, as a feasible implementation method, the signal connection between the PEX8796 switching chip and the FPGA chip adopts a 16-bit PCle3.0 bus; the signal connection between the PEX8796 switching chip and the communication board, and between the PEX8796 switching chip and the storage board all adopt a 16-bit PCle3.0 bus; the signal connection between the FPGA chip and each peripheral chip adopts an 8-bit LVDS bus.

[0031] Through the 16-bit PCIe 3.0 bus, high-speed data exchange is achieved between the PEX8796 switch chip and the FPGA chip. The PCIe 3.0 standard provides a high data transfer rate and low latency, which is suitable for high-performance computing and real-time data processing applications. The FPGA chip exchanges data with the switch chip through the PCIe bus, processes and executes tasks. Similarly, the PEX8796 switch chip establishes a connection with the communication board and the storage board through the 16-bit PCIe 3.0 bus, which enables high-speed data exchange between different modules. The communication board and the storage board may contain different types of processing units and storage resources. Through the high-speed PCIe connection, data can flow between these modules in a high-bandwidth and efficient manner. The PGA chip is connected to each peripheral chip through an 8-bit LVDS bus. The LVDS bus transmits data through differential signals, which can reduce electromagnetic interference and provide higher signal integrity. In the data exchange between FPGA and peripherals, the LVDS bus is usually used to transmit high-frequency, low-latency data to ensure the accuracy and stability of the signal.

[0032] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A 25Gbps fully switched universal VPX modular high-speed backplane, comprising a VPX high-speed backplane, a network switching module and a power circuit module for supplying power to the VPX high-speed backplane, characterized in that: The VPX high-speed backplane includes: VPX single board computer unit: including a number of VPX single board computer chips, each VPX single board computer chip is signal connected to the PCle switching unit, two VPX single board computers are respectively set as communication boards and storage boards, and the remaining VPX single board computers are set as peripheral boards, and the communication boards and storage boards are both signal connected to the clock distribution unit; Clock distribution unit: including a clock generator and a level converter, the clock generator and the level converter receive the signal transmitted unidirectionally from the communication board through the PCle switching unit, and the clock generator and the level converter transmit the signal unidirectionally to the PEX8796 switching chip and the storage board in the PCle switching unit at the same time; PCle switching unit: includes a PEX8796 switching chip and an FPGA chip that maintain signal connection with each other. The PEX8796 switching chip maintains signal connection with the communication board and the storage board respectively, and the FPGA chip maintains signal connection with each peripheral chip respectively, and the input end of the FPGA chip is connected to the external second pulse PPS timing signal.

2. The 25Gbps fully switched universal VPX modular high-speed backplane according to claim 1, characterized in that: The VPX high-speed backplane also includes a crystal oscillator module and a clock module; the crystal oscillator module includes a crystal oscillator element with a frequency of 156.25 MHz, and the clock module includes a clock buffer, and the four clock output ports of the clock buffer transmit the clock signal to the communication board through the LVDS differential signal.

3. The 25Gbps fully switched universal VPX modular high-speed backplane according to claim 2, characterized in that: The crystal oscillator module also includes a low phase noise temperature compensated crystal oscillator element with a frequency of 100 MHz. The clock module also includes a clock selector, which selects one from at least two clock sources to perform auxiliary clock synchronization on the LVDS signal.

4. The 25Gbps fully switched universal VPX modular high-speed backplane according to claim 1, characterized in that: The PCle switching unit also includes two extended control IO modules, and the two extended control IO modules maintain a two-way communication connection with the FPGA chip; each of the extended control IO modules has a JL23-16ZIB chip, and the JL23-16ZIB chip uses a 12V voltage; every two of the JL23-16ZIB chips form a group of IO chipsets, and the number of the IO chipsets is the same as the number of VPX single-board computer chips.

5. The 25Gbps fully switched universal VPX modular high-speed backplane according to claim 1, characterized in that: The FPGA chip is also connected to a serial communication circuit from the outside, and the serial communication circuit is used to provide a timing receiving port for the FPGA chip; the serial communication circuit includes an RS422 circuit and an RS232 circuit; the RS422 circuit is constructed based on the MAX3490 transceiver chip, and the RS232 circuit is constructed based on the MAX3232EUE transceiver chip.

6. The 25Gbps fully switched universal VPX modular high-speed backplane according to claim 1, characterized in that: The network switching module includes an 88E6350R switch chip, and the 88E6350R switch chip maintains a single independent Ethernet signal connection with the communication board and each peripheral board through a BaseT interface.

7. The 25Gbps fully switched universal VPX modular high-speed backplane according to claim 6, characterized in that: The network switching module also includes a KSZ9031 physical layer chip, which is connected to the RGMII interface of the 88E6350R switch chip via an RGMII interface, and the BaseT interface of the KSZ9031 physical layer chip is connected to a backplane RJ45 socket.

8. The 25Gbps fully switched universal VPX modular high-speed backplane according to claim 1, characterized in that: The clock generator uses the 9DB433AGLFT generator chip, and the level converter uses the 74AVC9112DCH converter chip.

9. The 25Gbps fully switched universal VPX modular high-speed backplane according to claim 1, characterized in that: The signal connection between the PEX8796 switching chip and the FPGA chip adopts a 16-bit PCle3.0 bus; the signal connection between the PEX8796 switching chip and the communication board, and between the PEX8796 switching chip and the storage board adopts a 16-bit PCle3.0 bus; the signal connection between the FPGA chip and each peripheral chip adopts an 8-bit LVDS bus.

10. A 25Gbps fully switched universal VPX modular high-speed backplane according to any one of claims 1 to 9, characterized in that: The PCle switching unit also includes a VU9P_PCle chip, and the clock generator transmits the signal to the VU9P_PCle chip after receiving the signal from the communication board.

Images