Global shutter pixel structure, semiconductor image sensor and control method
By adopting a global shutter pixel structure in the semiconductor image sensor, the problem of image distortion and deformation under the roller shutter mode is solved, and higher image quality and sensitivity are achieved.
Patent Information
- Application Number
- CN202411872857.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-02-28
Smart Images
Figure CN119545204A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of image sensors, and in particular to a global shutter pixel structure, a semiconductor image sensor and a control method. Background Art
[0002] In the related art, semiconductor image sensors are widely used as imaging devices due to their high sensitivity, short exposure time and shrinking pixel unit size. Semiconductor image sensors usually use two exposure modes: rolling shutter and global shutter.
[0003] The general practice of rolling shutter is to clear the charge (reset) of each row of pixels at different time points, and also to perform analog-to-digital conversion (readout) of the charge of each row of pixels at different time points. The time from reset to readout for all rows must be the same, so as to ensure the consistency of exposure time for all pixels. However, since the reset starting time points of each row of pixels are different, there is a sequence relationship, which will cause the objects exposed in the previous row to move quickly to the next row, or even the next row, and then be exposed again when shooting fast-moving objects, which will cause obvious image distortion and deformation.
[0004] In contrast, the global shutter can reset all rows of pixels at the same time, or divide all rows of pixels into several groups and reset the pixels in the same group of rows at the same time, so as to avoid or reduce the problem of image distortion and deformation.
[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0006] In view of the problems in the prior art, the purpose of the present invention is to provide a global shutter pixel structure, a semiconductor image sensor and a control method, which overcome the difficulties of the prior art and can improve image quality.
[0007] A first aspect of the present disclosure provides a global shutter pixel structure, which includes an optical unit, a signal reading circuit, a signal storage circuit, and a signal output circuit;
[0008] The optical unit is used to convert the optical signal into a charge signal;
[0009] The signal reading circuit comprises: a charge transfer switch, a reset switch and a first source follower, wherein the reset switch is coupled between the suspension node and a reset signal terminal, the reset signal terminal provides a reset signal, the charge transfer switch is coupled between the optical unit and the suspension node, and the first source follower is coupled between the voltage conversion signal terminal and the first node;
[0010] The signal reading circuit is used to successively write the reset signal to the suspension node through the reset switch and write the charge signal to the suspension node through the charge transfer switch, and successively read the reset signal and the mixed signal of the reset signal and the charge signal through the first source follower and write them into the first node;
[0011] The signal storage circuit is coupled between the first node and the second node, comprises a switch module and a capacitor module, and is configured to store the reset signal and the mixed signal written on the first node in the capacitor module in sequence through the switch module;
[0012] The signal output circuit is coupled between the second node and the signal output end, and is used to output the reset signal and the mixed signal stored on the capacitor module in sequence through the signal output end, and the difference between the mixed signal and the reset signal is the output signal of the global shutter pixel structure.
[0013] In some embodiments, the reset switch includes a first transistor, the charge transfer switch includes a second transistor, and the first source follower includes a third transistor;
[0014] The gate of the first transistor is connected to the first control signal, and the source and drain of the first transistor are connected to the reset signal terminal and the suspension node respectively;
[0015] The gate of the second transistor is connected to a second control signal, and the source and drain of the second transistor are connected to the suspension node and the optical unit respectively;
[0016] The gate of the third transistor is connected to the suspension node, the drain of the third transistor is connected to the voltage conversion signal terminal, and the source of the third transistor is connected to the signal storage circuit.
[0017] In some embodiments, the second transistor, the first transistor and the third transistor are all NMOS transistors or PMOS transistors.
[0018] In some embodiments, the switch module comprises:
[0019] A first switch coupled between the first node and a third node;
[0020] a second switch coupled between the third node and the second node;
[0021] The capacitor module comprises:
[0022] A first capacitor coupled between the third node and the low voltage signal terminal;
[0023] A second capacitor coupled between the signal output terminal and the low voltage signal terminal;
[0024] The signal storage circuit is configured to write the reset signal into the first capacitor and the second capacitor when the first switch and the second switch are turned on, and to write the mixed signal into the first capacitor when the first switch is turned on and the second switch is turned off.
[0025] In some embodiments, the switch module comprises:
[0026] A first switch coupled between the first node and the second node;
[0027] a second switch coupled between the first node and a fifth node;
[0028] a third switch coupled between the fifth node and the second node;
[0029] The capacitor module comprises:
[0030] A first capacitor, coupled between the second node and the low voltage signal terminal;
[0031] A second capacitor coupled between the fifth node and the low voltage signal terminal;
[0032] The signal storage circuit is configured to write the reset signal into the first capacitor when the first switch is turned on, and to write the mixed signal into the second capacitor when the second switch is turned on.
[0033] In some embodiments, the first switch includes a fourth transistor, and a gate of the fourth transistor is connected to a third control signal;
[0034] The second switch includes a fifth transistor, and a gate of the fifth transistor is connected to a fourth control signal.
[0035] In some embodiments, the fourth transistor and the fifth transistor are both NMOS transistors or PMOS transistors.
[0036] In some embodiments, the third switch includes a fifth transistor, a gate of the fifth transistor is connected to a sixth control signal, and a source and a drain of the fifth transistor are respectively connected to the third node and the second node.
[0037] In some embodiments, the signal output circuit includes:
[0038] A second source follower, whose gate is connected to the second node, and whose source and drain are connected to the reset signal terminal and the fourth node respectively;
[0039] The row selection transistor has a gate connected to the fifth control signal, and a source and a drain connected to the fourth node and the signal output terminal respectively.
[0040] The disclosed embodiments further provide a semiconductor image sensor, which includes the global shutter pixel structure of any of the above embodiments.
[0041] The present disclosure also provides a method for controlling a global shutter pixel structure, which includes:
[0042] Controlling the reset switch and the charge transfer switch to be turned on to clear and reset the charge of the suspension node;
[0043] Controlling the charge transfer switch and the reset switch to be switched off to start exposure;
[0044] Controlling the reset switch to turn on, writing the reset signal to the suspension node, and storing the reset signal in the capacitor module;
[0045] Controlling the charge transfer switch to open, and writing the charge signal converted by the optical unit into the suspension node, so that the global shutter pixel structure completes exposure;
[0046] Controlling the signal reading circuit to read a mixed signal of the charge signal and the reset signal of the suspension node, and storing the mixed signal in the capacitor module;
[0047] The reset signal and the mixed signal are sequentially outputted through a signal output circuit.
[0048] In some embodiments, the switch module includes: a first switch coupled between the first node and a third node; a second switch coupled between the third node and the second node;
[0049] The capacitor module includes: a first capacitor coupled between the third node and the low-voltage signal terminal; a second capacitor coupled between the signal output terminal and the low-voltage signal terminal;
[0050] The step of storing the reset signal in the capacitor module comprises:
[0051] Controlling the first switch and the second switch to be turned on so that the reset signal is stored in the first capacitor and the second capacitor;
[0052] Controlling the signal reading circuit to read a mixed signal of the charge signal and the reset signal of the suspension node, and storing the mixed signal in the capacitor module, comprises:
[0053] The second switch is controlled to be closed, so that a mixed signal of the charge signal and the reset signal is stored in the first capacitor.
[0054] In some embodiments, the switch module includes: a first switch coupled between the first node and the second node; a second switch coupled between the first node and a fifth node; a third switch coupled between the fifth node and the second node;
[0055] The capacitor module includes: a first capacitor coupled between the second node and the low-voltage signal terminal; a second capacitor coupled between the fifth node and the low-voltage signal terminal;
[0056] The step of storing the reset signal in the capacitor module comprises:
[0057] controlling the first switch to be turned on so that the reset signal is stored in the first capacitor;
[0058] The controlling the signal reading circuit to read a mixed signal of the charge signal and the reset signal of the suspension node and storing the mixed signal in the capacitor module includes:
[0059] The first switch is controlled to be closed and the second switch is controlled to be turned on, so that the mixed signal of the reset signal and the charge signal is stored in the second capacitor.
[0060] The global shutter pixel structure, semiconductor image sensor and control method provided by the embodiments of the present disclosure have the following beneficial effects:
[0061] Compared with the related art, the global shutter pixel structure of this embodiment omits the pre-charge tube coupled to the first node and the ground terminal, and can still achieve global exposure. Among them, by reducing the pre-charge tube near the optical unit, the photosensitive area of the optical unit is increased to a certain extent, thereby improving the sensitivity and image quality.
[0062] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0063] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.
[0064] Figure 1A circuit structure diagram of a global shutter pixel structure provided in an embodiment of the present disclosure.
[0065] Figure 2 for Figure 1 Equivalent circuit diagram of the global shutter pixel structure shown.
[0066] Figure 3 for Figure 2 The control timing diagram corresponding to the equivalent circuit diagram shown.
[0067] Figure 4 for Figure 1 Equivalent circuit diagram of the global shutter pixel structure shown.
[0068] Figure 5 for Figure 4 The control timing diagram corresponding to the equivalent circuit diagram shown.
[0069] Figure 6 for Figure 1 Flow chart of the control method of the global shutter pixel structure shown. DETAILED DESCRIPTION
[0070] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0071] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.
[0072] In addition, the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.
[0073] In the related art, the global shutter pixel structure is divided into charge domain global shutter and voltage domain global shutter. Due to its own structure, the charge domain global shutter will lead to high parasitic light sensitivity and easily cause light crosstalk, so it has high design requirements. Due to its own structure, the voltage domain global shutter is also difficult to eliminate the noise contained in the buffered read voltage signal, resulting in large read noise.
[0074] In contrast, the charge domain global shutter reads the charge in the pixel faster than the voltage domain global shutter structure. However, the charge domain global shutter structure must take into account the protection of dark current and other noise when the charge is stored, so the pixel design is more difficult and increases the design cost. The voltage domain global shutter structure is more susceptible to dark current and other noise than the charge domain global shutter structure, so it has been more widely used in recent years.
[0075] The disclosed embodiments provide a voltage domain global shutter pixel structure capable of improving image quality.
[0076] like Figure 1 As shown, the global shutter pixel structure proposed in the embodiment of the present disclosure includes an optical unit 10, a signal reading circuit 20, a signal storage circuit 30 and a signal output circuit 40;
[0077] The optical unit 10 is used to convert the optical signal into a charge signal;
[0078] The signal reading circuit 20 includes: a reset switch 21, a charge transfer switch 22 and a first source follower SF1, the reset switch 21 is coupled between a floating diffusion (FD) and a reset signal terminal VDD, the reset signal terminal VDD provides a reset signal, the charge transfer switch 22 is coupled between the optical unit 10 and the floating node FD, and the first source follower SF1 is coupled between the voltage conversion signal terminal VSF and the first node n1;
[0079] The signal reading circuit 20 is used to write a reset signal to the floating node FD through the reset switch 21 and write a charge signal to the floating node FD through the charge transfer switch 22, and read the reset signal and the mixture of the reset signal and the charge signal through the first source follower SF1 and write them into the first node n1;
[0080] The signal storage circuit 30 is coupled between the first node n1 and the second node n2, and includes a switch module 31 and a capacitor module 32, and is configured to store the signal written on the first node n1 to the capacitor module 32 through the switch module 31;
[0081] The signal output circuit 40 is coupled between the second node n2 and the signal output terminal OUT, and is used to transmit the signal stored on the capacitor module 32 from the second node n2 to the signal output terminal OUT in sequence. The difference between the signals stored in sequence on the capacitor module 32 is the output signal of the global shutter pixel structure.
[0082] Figure 1 The working principle of the global shutter pixel structure shown is:
[0083] In the global exposure stage, the reset switch 21 is turned on by the first control signal RST and the charge transfer switch 22 is turned on by the second control signal TX, so that the reset signal provided by the reset signal terminal VDD clears the optical unit 10 of charges;
[0084] Next, the charge transfer switch 22 is controlled to be closed by the second control signal TX, the optical unit 10 begins to be in an exposure state, a reset signal is written into the suspension node FD, the suspension node FD is cleared of charge and pulled up to reset, so that the first source follower SF1 writes the reset signal to the first node n1, and the control signal storage circuit 30 stores the reset signal;
[0085] Next, the reset switch 21 is closed through the RST signal, and the charge transfer switch 22 is turned on through the second control signal TX to complete the exposure process. The charge signal is written into the floating node FD, so that the first source follower SF1 writes the charge signal to the first node n1, and the control signal storage circuit 30 stores a mixed signal of the charge signal and the reset signal.
[0086] Afterwards, the control signal storage circuit 30 reads the reset signal and the above mixed signal, and the difference between the two is the output signal of the global shutter pixel structure.
[0087] Compared with the related art, the global shutter pixel structure of this embodiment omits the pre-charge tube coupled to the first node and the ground terminal, and can still achieve global exposure. Among them, by reducing the pre-charge tube near the optical unit 10, the photosensitive area of the optical unit 10 is increased to a certain extent, thereby improving the sensitivity and image quality.
[0088] Reference below Figure 2 , Figure 2 for Figure 1 Equivalent circuit diagram of the global shutter pixel structure shown.
[0089] In the embodiment of the present disclosure, the optical unit 10 is a photodiode PD, which is used to receive light and generate charges.
[0090] In the disclosed embodiment, the reset switch 21 includes a first transistor M1, the charge transfer switch 22 includes a second transistor M2, and the first source follower SF1 includes a third transistor M3;
[0091] The gate of the first transistor M1 is connected to the first control signal RST, and the source and drain of the first transistor M1 are connected to the reset signal terminal VDD and the suspension node FD respectively;
[0092] The gate of the second transistor M2 is connected to the second control signal TX, and the source and drain of the second transistor M2 are connected to the suspension node FD and the optical unit 10 respectively;
[0093] A gate of the third transistor M3 is connected to the floating node FD, a drain of the third transistor M3 is connected to the voltage conversion signal terminal VSF, and a source of the third transistor M3 is connected to the signal storage circuit 30 .
[0094] As an implementation, the first transistor M1 is an NMOS transistor. When the first control signal RST is at a high level, M1 is turned on, and when RST is at a low level, M1 is turned off. In another implementation, the first transistor M1 can also be a PMOS transistor. In this case, its control method is opposite to that of the NMOS transistor, which will not be described in detail.
[0095] As an implementation, the second transistor M2 is an NMOS transistor. When the second control signal TX is at a high level, M2 is turned on, and when TX is at a low level, M2 is turned off. In another implementation, the second transistor M2 can also be a PMOS transistor. In this case, its control method is opposite to that of the NMOS transistor, which will not be described in detail here.
[0096] As an implementation, the third transistor M3 is an NMOS transistor, and when the floating node FD is pulled up to a high level, M3 is triggered to turn on, and when the high level of the floating node FD is removed, M3 is turned off.
[0097] In the embodiment of the present disclosure, the switch module 31 includes:
[0098] A first switch 311 is coupled between the first node n1 and the third node n3;
[0099] A second switch 312, coupled between a third node n3 and the second node n2;
[0100] A first capacitor C1 is coupled between the third node n3 and the low voltage signal terminal VM;
[0101] A second capacitor C2 is coupled between the signal output terminal OUT and the low voltage signal terminal VM;
[0102] The signal storage circuit 30 is configured to write the reset signal into the first capacitor C1 and the second capacitor C2 when the first switch 311 and the second switch 312 are turned on, and to write a mixed signal of the reset signal and the charge signal into the first capacitor C1 when the first switch 311 is turned on and the second switch 312 is turned off.
[0103] In this embodiment, when the floating node FD is pulled high by the reset signal, the first source follower SF1 is turned on. After that, the first switch 311 and the second switch 312 are controlled to be turned on, and the voltage conversion signal terminal VSF is controlled to be turned off, so that the reset signal of the gate of SF1 is transmitted to the first node n1, the third node n3 and the second node n2, and the first capacitor C1 and the second capacitor C2 are charged, and both store the potential corresponding to the reset signal. Among them, the reset signal represents the reset noise.
[0104] Further, when the optical unit 10 receives the light signal and converts it into charge, M2 is controlled to be turned on and M1 is turned off, and the charge is transmitted to the suspension node FD. After that, the second switch 312 is controlled to be turned off, and the voltage conversion signal terminal VSF is controlled to be turned off, so that the first source follower SF1 converts the charge of the suspension node FD into a voltage level signal, and stores it in the first capacitor C1 through the first switch 311.
[0105] At this time, the first capacitor C1 and the second capacitor C2 store different signals respectively.
[0106] In the embodiment of the present disclosure, the first switch 311 includes a fourth transistor M4, a gate of the fourth transistor M4 is connected to the third control signal S1, and a source and a drain thereof are connected to the first node n1 and the third node n3 respectively;
[0107] The second switch 312 includes a fifth transistor M5 , a gate of which is connected to the fourth control signal S2 , and a source and a drain of which are connected to the third node n3 and the second node n2 , respectively.
[0108] In this embodiment, the first switch 311 and the second switch 312 are both implemented by corresponding transistors. Figure 2 As shown, the fourth transistor M4 and the fifth transistor M5 are both NMOS transistors. Figure 2 As shown, the gate of the fourth transistor M4 is connected to the third control signal S1, the source thereof is connected to the third node n3, and the drain thereof is connected to the first node n1. Thus, when the third control signal S1 provides a high level signal, M4 is turned on, and when S1 provides a low level signal, M4 is turned off. Similarly, the gate of the fifth transistor M5 is connected to the fourth control signal S2, the source thereof is connected to the second node n2, and the drain thereof is connected to the third node n3. When S2 provides a high level potential, M5 is turned on, and when S2 provides a low level potential, M5 is turned off.
[0109] In another implementation, M4 and M5 may be PMOS transistors, which differ from NMOS transistors in that the positions of the source and the drain are just opposite. For other details, reference may be made to the connection method of the PMOS transistor, which will not be described in detail here.
[0110] In the embodiment of the present disclosure, the signal output circuit 40 includes:
[0111] A second source follower SF2, whose gate is connected to the second node n2, and whose source and drain are respectively connected to the reset signal terminal VDD and the fourth node n4;
[0112] The row selection transistor M6 has a gate connected to the fifth control signal SEL, and a source and a drain connected to the fourth node n4 and the signal output terminal OUT respectively.
[0113] The row selection transistor M6 can select an NMOS transistor, whose gate is controlled by the fifth control signal SEL and whose source serves as the signal output terminal OUT of the global shutter pixel structure. The row selection transistor M6 can sequentially sample and output the signals stored in the first capacitor C1 and the second capacitor C2 under the control of the fifth control signal SEL.
[0114] The second source follower SF2 includes an NMOS transistor M7, whose gate is connected to the second node n2, whose drain is connected to the reset signal terminal VDD, and whose source is connected to the fourth node n4. When the row selection transistor M6 is turned on, the signal on the source of M7 (i.e. corresponding to the second node n2) is transmitted to the fourth node n4, and finally outputted through the signal output terminal OUT.
[0115] As described above, the embodiments of the present disclosure provide a global shutter pixel structure with a 7T architecture.
[0116] Combination Figure 3 The control timing diagram shown is Figure 2 The global shutter pixel structure shown in the figure, the embodiment of the present disclosure provides the following control method:
[0117] In the global exposure stage, the first control signal RST and the second control signal TX are both configured as high-level signals, M1 and M2 are turned on, and the charges in the optical unit 10 are cleared;
[0118] In the global conversion stage, M2 is closed by the second control signal TX, and the current global shutter pixel structure starts to expose according to the integration time. The reset signal provided by the reset signal terminal VDD pulls up the floating node FD, that is, the gate of the first source follower SF1 is recorded with the reset signal. After a period of time after the integration time ends, the third control signal S1 and the fourth control signal S2 are controlled to be configured as high-level signals, M4 and M5 are both turned on, and VSF inputs a low-level signal, so that the reset signal on the gate of SF1 is transmitted to the first capacitor C1 and the second capacitor C2 and stored;
[0119] Next, control M5 to be turned off and control M2 to be turned on, the charges converted by the optical unit 10 are converted into a level signal through SF1, and then the level signal is transmitted to the first capacitor C1 through M4 and stored;
[0120] Finally, the reset signal is stored in the second capacitor C2, and the reset signal and the converted level signal are stored in the first capacitor C1.
[0121] When it is necessary to output the signals stored on the first capacitor C1 and the second capacitor C2, first control the fifth control signal SEL to be high, M6 to be turned on, the second capacitor C2 to be discharged, and the reset signal stored therein is output through the second source follower SF2 and M6. Then, the fourth control signal S2 is set high, M5 to be turned on, the first capacitor C1 to be discharged, and the mixed signal stored therein is output through M5, SF2 and M6. The difference between the signals provided by the first capacitor C1 and the second capacitor C2 is the output signal of the global shutter pixel structure. When the semiconductor image sensor is working, each global shutter pixel structure can be exposed at the same time, and the corresponding signals are stored in the first capacitor C1 and the second capacitor C2 of each global shutter pixel structure, and then the signals of each row of pixels are output in sequence as needed.
[0122] In the embodiment of the present disclosure, the lower plates of the first capacitor C1 and the second capacitor C2 are connected to the low-voltage signal terminal VM, which provides level control for the capacitors, thereby reducing the influence of surrounding noise when the signal is stored, thereby improving image quality.
[0123] The present disclosure also provides another global shutter pixel unit. Figure 2 compared to, Figure 4 The difference of the alternative global shutter pixel unit shown is that:
[0124] The switch module 31 includes:
[0125] A first switch 311, coupled between the first node n1 and the second node n2;
[0126] A second switch 312, coupled between the first node n1 and a fifth node n5;
[0127] A third switch 313, coupled between the fifth node n5 and the second node n2;
[0128] The capacitor module 32 includes:
[0129] A first capacitor C1 is coupled between the second node n2 and the low voltage signal terminal VM;
[0130] A second capacitor C2, coupled between the fifth node n5 and the low voltage signal terminal VM;
[0131] The signal storage circuit 30 is configured to write the reset signal into the first capacitor C1 when the first switch 311 is turned on, and to write a mixed signal of the charge signal and the reset signal into the second capacitor C2 when the second switch 312 is turned on.
[0132] In the first switch 311, the gate of the fourth transistor M4 is connected to the third control signal S1, the drain thereof is connected to the first node n1, and the source thereof is connected to the second node n2. In the second switch 312, the gate of the fifth transistor M5 is connected to the fourth control signal S2, the drain thereof is connected to the first node n1, and the source thereof is connected to the fifth node n5. In the third switch 313, the gate of the eighth transistor M8 is connected to the sixth control signal S3, the drain thereof is connected to the fifth node n5, and the source thereof is connected to the second node n2.
[0133] refer to Figure 5 , Figure 4 The control method of the global shutter pixel structure shown is different in that:
[0134] During the global exposure phase, the integration time extends to the global conversion phase;
[0135] The third control signal S1 is controlled to be high level, M4 is turned on, and the reset signal on the gate of SF1 is transmitted to the first capacitor C1 and stored;
[0136] The third control signal S1 is controlled to be at a low level and the fourth control signal S2 is controlled to be at a high level, M4 is turned off, M5 is turned on, and a mixed signal of the reset signal and the charge signal on the gate of SF1 is transmitted to the second capacitor C2 and stored.
[0137] When it is necessary to read the signals stored on the first capacitor C1 and the second capacitor C2, first control SEL to turn on M6, discharge C1, and output a reset signal. Then control S3 to turn on, discharge C2, and output a mixed signal of the reset signal and the charge signal. The difference between the signals stored in C1 and C2 is the output signal of the current global shutter pixel structure.
[0138] In this embodiment, the eighth transistor M8 is an NMOS transistor, or alternatively, the eighth transistor M8 is a PMOS transistor.
[0139] Figure 2 The global shutter pixel structure shown includes 7 transistors, compared to Figure 4 The global shutter pixel structure shown includes 8 transistors, wherein the operations of the first switch 311 and the second switch 312 do not overlap, and no noise impact is generated on the first capacitor C1 and the second capacitor C2.
[0140] The disclosed embodiment also provides a semiconductor image sensor, which can be specifically a CMOS image sensor, which includes the global shutter pixel structure of any of the above embodiments, and these global shutter pixel structures are arranged in an array. When the semiconductor image sensor is working, each global shutter pixel structure can be exposed at the same time, and the corresponding signal is stored in the capacitor module of each global shutter pixel structure, and then the signal of each row of pixels is output in sequence as needed.
[0141] The present disclosure also provides a control method for the global shutter pixel structure based on the above embodiment. Figure 6 As shown, the control method includes but is not limited to the following steps:
[0142] Step 610: Control the reset switch and the charge transfer switch to be turned on to clear and reset the charge of the suspended node;
[0143] Step 620: Control the charge transfer switch and the reset switch to be switched off to start exposure;
[0144] Step 630: Control the reset switch to turn on, write the reset signal to the floating node, and store the reset signal in the capacitor module;
[0145] Step 640: Control the charge transfer switch to be turned on, and write the charge signal converted by the optical unit into the suspension node, so that the global shutter pixel structure completes exposure;
[0146] Step 650: Control the signal reading circuit to read a mixed signal of the charge signal and the reset signal of the floating node, and store the mixed signal in the capacitor module;
[0147] Step 660: output the reset signal and the mixed signal in sequence through a signal output circuit.
[0148] In one embodiment, in combination Figure 2 The structure shown in FIG. 1 includes: controlling the signal reading circuit to read the reset signal and storing the reset signal in the capacitor module, specifically including:
[0149] Controlling the first switch 311 and the second switch 312 to be turned on, so that the reset signal is stored in the first capacitor C1 and the second capacitor C2;
[0150] The controlling the signal reading circuit to read a mixed signal of the charge signal and the reset signal of the floating node and storing the mixed signal in the capacitor module specifically includes:
[0151] The second switch 312 is controlled to be closed, so that the mixed signal of the charge signal and the reset signal is stored in the first capacitor C1.
[0152] In one embodiment, in combination Figure 4 The structure shown in FIG. 1 includes: controlling the signal reading circuit to read the reset signal and storing the reset signal in the capacitor module, specifically including:
[0153] Controlling the first switch 311 to be turned on so that the reset signal is stored in the first capacitor C1;
[0154] Controlling the signal reading circuit to read a mixed signal of the charge signal and the reset signal of the floating node and storing the mixed signal in the capacitor module specifically includes:
[0155] The first switch 311 is controlled to be turned off and the second switch 312 is controlled to be turned on, so that a mixed signal of the reset signal and the charge signal is stored in the second capacitor C2.
[0156] In summary, the global shutter pixel structure of the embodiment of the present disclosure can realize the global exposure function.
[0157] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.
Claims
1. A global shutter pixel structure, characterized in that: It includes an optical unit, a signal reading circuit, a signal storage circuit and a signal output circuit; The optical unit is used to convert the optical signal into a charge signal; The signal reading circuit comprises: a charge transfer switch, a reset switch and a first source follower, wherein the reset switch is coupled between the suspension node and a reset signal terminal, the reset signal terminal provides a reset signal, the charge transfer switch is coupled between the optical unit and the suspension node, and the first source follower is coupled between the voltage conversion signal terminal and the first node; The signal reading circuit is used to successively write the reset signal to the suspension node through the reset switch and write the charge signal to the suspension node through the charge transfer switch, and successively read the reset signal and the mixed signal of the reset signal and the charge signal through the first source follower and write them into the first node; The signal storage circuit is coupled between the first node and the second node, comprises a switch module and a capacitor module, and is configured to store the reset signal and the mixed signal written on the first node in the capacitor module in sequence through the switch module; The signal output circuit is coupled between the second node and the signal output end, and is used to output the reset signal and the mixed signal stored on the capacitor module in sequence through the signal output end, and the difference between the mixed signal and the reset signal is the output signal of the global shutter pixel structure.
2. The global shutter pixel structure according to claim 1, characterized in that: The reset switch includes a first transistor, the charge transfer switch includes a second transistor, and the first source follower includes a third transistor; The gate of the first transistor is connected to the first control signal, and the source and drain of the first transistor are connected to the reset signal terminal and the suspension node respectively; The gate of the second transistor is connected to a second control signal, and the source and drain of the second transistor are connected to the suspension node and the optical unit respectively; The gate of the third transistor is connected to the suspension node, the drain of the third transistor is connected to the voltage conversion signal terminal, and the source of the third transistor is connected to the signal storage circuit.
3. The global shutter pixel structure according to claim 2, characterized in that: The second transistor, the first transistor and the third transistor are all NMOS transistors or PMOS transistors.
4. The global shutter pixel structure according to claim 1, characterized in that: The switch module comprises: A first switch coupled between the first node and a third node; a second switch coupled between the third node and the second node; The capacitor module comprises: A first capacitor coupled between the third node and the low voltage signal terminal; A second capacitor coupled between the signal output terminal and the low voltage signal terminal; The signal storage circuit is configured to write the reset signal into the first capacitor and the second capacitor when the first switch and the second switch are turned on, and to write the mixed signal into the first capacitor when the first switch is turned on and the second switch is turned off.
5. The global shutter pixel structure according to claim 1, characterized in that: The switch module comprises: A first switch coupled between the first node and the second node; a second switch coupled between the first node and a fifth node; a third switch coupled between the fifth node and the second node; The capacitor module comprises: A first capacitor, coupled between the second node and the low voltage signal terminal; A second capacitor coupled between the fifth node and the low voltage signal terminal; The signal storage circuit is configured to write the reset signal into the first capacitor when the first switch is turned on, and to write the mixed signal into the second capacitor when the second switch is turned on.
6. The global shutter pixel structure according to claim 4 or 5, characterized in that: The first switch comprises a fourth transistor, and a gate of the fourth transistor is connected to a third control signal; The second switch includes a fifth transistor, and a gate of the fifth transistor is connected to a fourth control signal.
7. The global shutter pixel structure according to claim 6, characterized in that: The fourth transistor and the fifth transistor are both NMOS transistors or PMOS transistors.
8. The global shutter pixel structure according to claim 5, characterized in that: The third switch includes an eighth transistor, a gate of the eighth transistor is connected to the sixth control signal, and a source and a drain of the eighth transistor are respectively connected to the fifth node and the second node.
9. The global shutter pixel structure according to claim 1, characterized in that: The signal output circuit comprises: A second source follower, whose gate is connected to the second node, and whose source and drain are connected to the reset signal terminal and the fourth node respectively; The row selection transistor has a gate connected to the fifth control signal, and a source and a drain connected to the fourth node and the signal output terminal respectively.
10. A semiconductor image sensor, characterized in that: A global shutter pixel structure comprising any one of claims 1-9.
11. A method for controlling the global shutter pixel structure according to claim 1, characterized in that: include: Controlling the reset switch and the charge transfer switch to be turned on to clear and reset the charge of the suspension node; Controlling the charge transfer switch and the reset switch to be switched off to start exposure; Controlling the reset switch to turn on, writing the reset signal to the suspension node, and storing the reset signal in the capacitor module; Controlling the charge transfer switch to open, and writing the charge signal converted by the optical unit into the suspension node, so that the global shutter pixel structure completes exposure; Controlling the signal reading circuit to read a mixed signal of the charge signal and the reset signal of the suspension node, and storing the mixed signal in the capacitor module; The reset signal and the mixed signal are sequentially outputted through a signal output circuit.
12. The method for controlling a global shutter pixel structure according to claim 11, characterized in that: The switch module includes: a first switch coupled between the first node and a third node; a second switch coupled between the third node and the second node; The capacitor module includes: a first capacitor coupled between the third node and the low-voltage signal terminal; a second capacitor coupled between the signal output terminal and the low-voltage signal terminal; The step of storing the reset signal in the capacitor module comprises: Controlling the first switch and the second switch to be turned on so that the reset signal is stored in the first capacitor and the second capacitor; The controlling the signal reading circuit to read a mixed signal of the charge signal and the reset signal of the suspension node and storing the mixed signal in the capacitor module includes: The second switch is controlled to be closed, so that a mixed signal of the charge signal and the reset signal is stored in the first capacitor.
13. The control method of the global shutter pixel structure according to claim 11, characterized in that: The switch module includes: a first switch coupled between the first node and the second node; a second switch coupled between the first node and a fifth node; and a third switch coupled between the fifth node and the second node. The capacitor module includes: a first capacitor coupled between the second node and the low-voltage signal terminal; a second capacitor coupled between the fifth node and the low-voltage signal terminal; The step of storing the reset signal in the capacitor module comprises: controlling the first switch to be turned on so that the reset signal is stored in the first capacitor; The controlling the signal reading circuit to read a mixed signal of the charge signal and the reset signal of the suspension node and storing the mixed signal in the capacitor module includes: The first switch is controlled to be closed and the second switch is controlled to be turned on, so that the mixed signal of the reset signal and the charge signal is stored in the second capacitor.