NFC demodulation circuit

Abstract

The invention relates to an NFC demodulation circuit. An amplification circuit includes an amplifier circuit (provided by an operational amplifier) that amplifies a signal to be demodulated. A feedback loop of the amplifier circuit has a resistance value that is controlled to discretely vary according to a level of an output node of the amplifier circuit. A comparison of the output level relative to one or more thresholds drives selection of the resistance value, wherein the one or more thresholds define an unsaturated operating range of the amplifier circuit.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority of French patent application No. 2309057, filed on August 29, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to demodulation circuits, and more particularly to demodulation circuits for near field communications, such as the Near Field Communication (NFC) protocol. Background Art

[0004] In wireless communication devices, in particular near field communication devices, different types of modulation utilize amplitude modulation of the radio frequency signal. Two types of demodulation chains are currently used, demodulation chains with level detectors and demodulation chains with rising or falling edge detectors, both of which include amplifiers. In near field communication devices, amplitude variations of the signal can be significant and cause saturation of these demodulation chains. This causes, for example, inaccurate determination of certain parameters of the communication protocol used.

[0005] There is a need to limit the saturation of the demodulation chain and to improve the detection of certain communication protocol parameters.

[0006] There is a need to overcome all or some of the disadvantages of known demodulation circuits. Summary of the invention

[0007] An embodiment provides an amplification circuit, comprising: an amplifier circuit, including an operational amplifier and configured to amplify a signal to be demodulated; and a feedback loop, having a resistance value that discretely changes according to a level of an output node of the amplifier circuit relative to one or more thresholds defining one or more non-saturated operating ranges of the amplifier circuit.

[0008] Embodiments provide a demodulation circuit including an amplification circuit such as described above.

[0009] According to an embodiment, the resistance value of the feedback loop of the amplifier circuit takes a first value when the level is higher than a first threshold or when the level is lower than a second threshold, wherein the second threshold is lower than the first threshold.

[0010] According to an embodiment, when the level is between the first threshold and the second threshold, the resistance value of the feedback loop of the amplifier circuit takes the second value.

[0011] According to an embodiment, when the level is higher than a third threshold or when the level is lower than a fourth threshold, the resistance value of the feedback loop of the amplifier circuit takes a third value, wherein the third threshold is higher than the first threshold and the fourth threshold is lower than the second threshold.

[0012] According to an embodiment, an operational amplifier includes an inverting input terminal coupled to an input node of an amplifier circuit and to an output node of the amplifier circuit via a feedback loop.

[0013] According to an embodiment, the feedback loop includes: a first branch coupling the inverting input of the operational amplifier to the output node and formed by a resistive element having a first resistance value; N additional branches connected in parallel with the first branch, each additional branch being formed by a resistive element in series with a switch controlled by a corresponding control signal, the corresponding control signal depending on a comparison between a level of the output node of the amplifier circuit relative to a corresponding operating range in N non-saturated operating ranges of the amplifier circuit, each operating range being defined by a threshold, N being a positive integer; and N comparison circuits configured to generate a corresponding control signal for each of the N additional branches so that the corresponding switch: does not conduct when the level of the output node of the amplifier circuit is within the corresponding operating range; and conducts when the level of the output node of the amplifier circuit is outside the corresponding operating range.

[0014] According to an embodiment, the non-saturated operation range of the rank N=1 is defined between the first threshold and the second threshold; and the branch of the rank N=1 is formed by a resistive element having a fourth resistance value.

[0015] According to an embodiment, the non-saturated operation range of the rank N=2 is defined between the third threshold and the fourth threshold; and the rank N=2 branch is formed by a resistive element having a fifth resistance value.

[0016] According to an embodiment, a first comparison circuit among N comparison circuits includes: a first comparison branch, including a comparator circuit having a non-inverting input terminal coupled to an output node and an inverting input terminal coupled to a node configured to receive a voltage representing a first threshold; a second comparison branch, including a comparator circuit having a non-inverting input terminal coupled to the output node and an inverting input terminal coupled to a node configured to receive a voltage representing a second threshold, the comparator circuit being connected in series with an inverter circuit; and a logic block configured to perform an OR function based on a signal present on an output node of the comparator circuit of the first branch of the first comparison circuit and another signal present on an output node of the inverter circuit of the second branch of the first comparison circuit; the output of the logic block is a control signal of a switch of a branch of a feedback loop ranked N=1.

[0017] According to an embodiment, a second comparison circuit among the N comparison circuits includes: a third comparison branch, including a comparator circuit having a non-inverting input terminal coupled to an output node and an inverting input terminal coupled to a node configured to receive a voltage representing a third threshold; a fourth comparison branch, including a comparator circuit having a non-inverting input terminal coupled to the output node and an inverting input terminal coupled to a node configured to receive a voltage representing a fourth threshold, the comparator circuit being connected in series with another inverter circuit; and another logic block configured to perform an OR function based on a signal present at an output node of the comparator circuit of the third branch of the second comparison circuit and another signal present at an output terminal of the inverter circuit of the fourth branch of the second comparison circuit; the output of the logic block is a signal for controlling a switch of a branch of a feedback loop ranked N=2.

[0018] According to an embodiment, the amplification circuit or the demodulation circuit also includes a trigger, which has: a set input terminal, coupled to the output node of the comparator circuit of the first branch of the first comparison circuit; a reset input terminal, coupled to the output node of the inverter circuit of the second branch of the first comparison circuit; and an output terminal, coupled to the output node of the amplification circuit via the inverter circuit.

[0019] According to an embodiment, the inverting input of the operational amplifier is coupled to the input node of the amplifier circuit via a capacitive element in series with an input resistor.

[0020] According to an embodiment, the demodulation circuit is of NFC type.

[0021] An embodiment provides a near field communication device comprising a demodulation circuit such as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above features and advantages and other features and advantages will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0023] Figure 1 is a simplified illustration of a communication system including first and second near field communication devices;

[0024] Figure 2 Schematically shows Figure 1 An example of a demodulation circuit for a device;

[0025] Figure 3 Shows Figure 2 A timing diagram of the operation of the circuit;

[0026] Figure 4 Schematically shows Figure 1 An example of a demodulation circuit for a device;

[0027] Figure 5 Picture shows Figure 4 A timing diagram of the operation of the circuit;

[0028] Figure 6 Schematically shows Figure 1 An example of a demodulation circuit for a device;

[0029] Figure 7 Shows Figure 6 A timing diagram of the operation of the circuit. DETAILED DESCRIPTION

[0030] Similar features in the various figures are represented by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals, and may deploy exactly the same structure, dimensions, and material properties.

[0031] For clarity, only the steps and elements that are useful for understanding the embodiments are shown and described in detail.

[0032] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0033] In the following description, when terms that define absolute positions (such as terms "edge", "back", "top", "bottom", "left", "right", etc.) or terms that define relative positions (such as terms "above", "below", "upper", "lower", etc.) or terms that define directions (such as terms "horizontal", "vertical", etc.) are mentioned, unless otherwise specified, they refer to the orientation of the drawing.

[0034] Unless otherwise stated, the expressions “about”, “approximately”, “substantially” and “around” mean plus or minus 10%, preferably plus or minus 5%.

[0035] Figure 1 A simplified view of a communication system comprising a first 102 (terminal) near field communication device and a second 104 (smart card) near field communication device is shown.

[0036] In the remainder of this disclosure, a near field communication device is understood to mean an electronic device integrating at least one near field communication circuit implementing a contactless system protocol compliant with ISO standard 14443 or a protocol of the NFC ("Near Field Communication") Forum. References to the near field refer to and are understood to mean an electromagnetic field having a limited range from a few centimeters to approximately 2 meters, depending on the protocol used.

[0037] For example, the first device 102 is in a card reader mode, and the second device 104 is in a card emulation mode. For example, the first device 102 is configured to activate the second device 104 by transmitting a modulated magnetic field and reading the return of another modulated radio frequency signal containing the card information.

[0038] The first and second devices 102, 104 each include, for example, demodulation circuitry 106, 108 to demodulate a signal transmitted by the other device.

[0039] The type of modulation used by these devices for radio frequency communication is, for example, amplitude modulation over 1 bit. Different encodings can also be used, such as improved Miller, Manchester or NRZ codes, and modulation rates, for example, from a few percent to 100%. The signals exchanged can also take different forms to facilitate detection of rising or falling edges. The amplitude of the radio frequency field received by the second device 104 can vary significantly, for example, according to the distance separating them or according to the output level of the first device 102.

[0040] The demodulation circuits 106, 108 are, for example, of the level detection or edge detection type.

[0041] The level detector compares the signal to a threshold. When the signal exceeds the threshold, a high level is detected, and when the signal falls below the threshold, a low level is detected.

[0042] For example, an edge detector uses a comparison of the derivative of a signal with respect to two high and low thresholds.

[0043] Figure 2 Schematically shows Figure 1 104. An example of a demodulation circuit 206 for a device 102, 104.

[0044] In the example shown, the demodulation circuit 206 includes a high-pass radio frequency filter formed by a capacitive element C1 in series with a resistor R1 at its input. This filter, for example, enables the derivative of the input signal RF_IN to be provided. The filter couples the input node (N1) of the circuit to the input node (NVIN) of the amplifier circuit 210. The input node N1 is configured to receive the radio frequency signal RF_IN to be demodulated. The amplifier circuit 210 includes an operational amplifier 212, which has an inverting input terminal (-) coupled (preferably connected) to the input node NVIN. The non-inverting input terminal (+) is configured to be coupled (preferably connected) to the power supply rail of the voltage Vcm. The input node NVIN is coupled (preferably connected) to the output node (NVAOP) of the amplifier circuit 210 via a feedback loop 214. The feedback loop 214 includes a first branch and a second branch in parallel and both couple the output node NVAOP to the input node NVIN. The first branch includes a switch 216 controlled by a first gain control signal (GainCtrl1). The second branch includes a resistor (R2). The ratio of resistors R2 to R1 enables the gain of amplifier circuit 210 to be set.

[0045] In the example shown, the demodulation circuit 206 also includes a first signal level comparison circuit 250. The first comparison circuit 250 includes a first branch that couples the node NVAOP to the node N2 and a second branch that couples the node NVAOP to another node N3. The first branch includes a voltage comparator circuit 220. The comparator circuit 220 includes an operational amplifier 222, which has an inverting input terminal (-) configured to be coupled (preferably connected) to a voltage rail VREFP1 that defines a first threshold. The operational amplifier 222 includes a non-inverting input terminal (+) configured to be coupled (preferably connected) to the node NVAOP. The output terminal of the amplifier 222 is coupled (preferably connected) to the node N2. When the level of the signal on the node NVAOP is higher than VREFP1, the amplifier 222 returns a high level signal to the node N2. In the opposite case, a low level signal is returned to the node N2.

[0046] In the example shown, the second branch of the first comparison circuit 250 includes a voltage comparator circuit 230. The comparator circuit 230 includes an operational amplifier 232 having an inverting input terminal (-) configured to be coupled (preferably connected) to a voltage rail VREFN1 defining a second threshold. The operational amplifier 232 also includes a non-inverting input terminal (+) configured to be coupled (preferably connected) to a node NVAOP. The output of the amplifier 232 is coupled to the node N3 via an inverter circuit 240. When the level of the signal on the node NVAOP is higher than VREFN1, the amplifier 232 returns a high level signal, which becomes low on the node N3 after inversion. In the opposite case, the high level signal is returned to the node N3.

[0047] The two thresholds VREFP1 and VREFN1 together define a region where the amplifier circuit 210 is not saturated. For example, above VREFP1 and below VREFN1, the amplifier circuit is saturated.

[0048] In the example shown, the demodulation circuit 206 also includes a logic circuit 280 configured to perform an "OR" function based on the signals present on the nodes N2 and N3. The resulting signal is the gain control signal GainCtrl1. When the signal on the node NVAOP is greater than VREFP1 and VREFN1, the signal GainCtrl1 is at a high level; when the signal on the node NVAOP is lower than VREFP1 but higher than VREFN1, the signal GainCtrl1 is at a low level; and when the signal on the node NVAOP is lower than VREFP1 and lower than VREFN1, the signal GainCtrl1 is at a high level. When the signal GainCtrl1 is at a high level, it means, for example, that the switch 216 is turned on; and when the signal GainCtrl1 is at a low level, it means, for example, that the switch 216 is not turned on. When the switch 216 is not turned on, it means that the gain of the amplifier circuit 210 is R2 / R1, and when the switch 216 is turned on, it means that the gain of the amplifier circuit 210 is zero, that is, the node NVIN is directly connected to the node NVAOP.

[0049] In the example shown, the demodulation circuit 206 also includes a flip-flop 260 having a set input (S) coupled to node N2, a reset input (R) coupled to node N3, and an output (Q) coupled to an output node (NVOUT) of the demodulation circuit via an inverter circuit 270.

[0050] Figure 2The circuit allows automatic control (AGC, automatic gain control) of the amplification gain of the signal by automatically and discretely changing the gain from a zero value (when the switch 216 is on (i.e., conducting)) to a value R2 / R1 (when the switch 216 is off (i.e., not conducting)), and this depends on the level of the signal at the node NVAOP relative to the references VREFP1 and VREFN1.

[0051] Figure 3 Shows Figure 2 More specifically, Figure 3 Input signal RF_IN, voltage VAOP at node NVAOP, and signals GainCtrl1 and VOUT are shown.

[0052] Between time t1 and time t2 after t1 , the received signal RF_IN increases linearly.

[0053] Between time t2 and time t3 after t2, signal RF_IN is stable at a high level. Signal VAOP is between voltage levels NVREFP1 and NVREFN1, which means that signal GainCtrl1 is at a low level, such as 0, and the gain is high (strong gain) in this case and proportional to R2 / R1. During this time period, signal VOUT remains stable because signal RF_IN does not change.

[0054] Between time t3 and time t4 after t3, signal RF_IN decreases linearly. Just after time t3, signal VAOP suddenly increases and exceeds voltage threshold VREFP1. Signal GainCtrl1 then switches to a high level, which automatically switches the gain to a zero value (gain=0), and signal VOUT switches to a low level. Amplifier 212 is then short-circuited and the output voltage tends toward the common mode between VREFP1 and VREFN1. Signal VAOP then decreases linearly until it reaches below threshold voltage VREFP1. At this point, signal GainCtrl1 switches back to a low level. As signal RF_IN continues to decrease, signal VAOP, again amplified by ratio R2 / R1, rises linearly to exceed threshold VREFP1 again. When this threshold is exceeded, signal GainCtrl1 switches back to a high level, which reduces VAOP back, and so on. Thus, signal VAOP oscillates in a sawtooth shape around threshold value VREFP1, and signal GainCtrl1 alternates between high and low levels accordingly.

[0055] Between time t4 and time t6 after t4, the signal RF_IN rises linearly. As long as the signal VAOP does not drop below the threshold VREFN1, the signal VOUT remains at a low level.

[0056] Signal VAOP increases above threshold VREFP1 for the last time between time t4 and time t5 between time t4 and time t6 and then decreases back below threshold VREFP1 between time t5 and time t6 while remaining above VREFN1.

[0057] Between time t5 and time t6, signal GainCtrl1 switches to a low level and remains at a low level until signal VAOP reaches below threshold VREFN1 at time t6. Signal VOUT then switches from a low state to a high state. The change of signal RF_IN is thus digitized.

[0058] The period between time t5 and time t6 (signal delay) corresponds to the delay in the detection of the signal change. This is due to the fact that the change of the signal VAOP is not visible when the amplifier 212 is short-circuited. Therefore, the determination of the frame delay time (FDT) is modified, wherein the frame delay time (FDT) is a basic parameter of NFC and ISO protocol 14443. Figure 2 Another disadvantage of the example is due to the fact that when the amplifier 212 is short-circuited, signal discontinuities are generated and the stability of the circuit is affected.

[0059] The described embodiments provide a demodulation circuit NFC comprising an amplifier circuit configured to amplify a signal to be demodulated with a gain different from zero, the value of the gain varying discretely depending on the level of an output node of the amplifier circuit relative to one or more thresholds defining one or more non-saturated operating ranges of the amplifier.

[0060] Figure 4 Schematically shows a Figure 1 An example of a demodulation circuit 406 of one of the devices 102, 104.

[0061] In the example shown, the demodulation circuit 406 is connected to Figure 2 The demodulation circuit 206 is similar to the demodulation circuit 206, except that an additional resistor R2b is added in the first branch of the feedback loop 214 to connect the switch 216 to the node NVAOP or to connect the switch 216 to the node NVIN. The resistor R2b enables another non-zero gain level of the amplifier circuit 210 to be defined compared to the gain level obtained with the branch including the resistor R2.

[0062] and Figure 2 In contrast to the example of FIG. 1 , when switch 216 is controlled to be on, amplifier 210 is not short-circuited. Therefore, the gain of amplifier circuit 210 is R2 / R1 when signal NVAOP is between VREFP1 and VREFN1 and (R2 / R1) when signal NVAOP is higher than VREFP1 or lower than VREFN1. ·R2) / (R1(R2+R2b)) varies discretely.

[0063] exist Figure 4 In the example of , the gain region defined between VREFP1 and VREFN1 is a region outside of saturation of the amplifier 212, corresponding to high gains, while the region above VREFP1 and below VREFN1 is a region outside of saturation of the amplifier 212, corresponding to lower but non-zero gains.

[0064] Figure 5 Shows Figure 4 A timing diagram of the operation of the circuit.

[0065] More specifically, Figure 5 Signals RF_IN, VAOP, GainCtrl1, and VOUT are shown.

[0066] Before time t′1, the signal RF_IN is at a high level, the signal VAOP is stable and located between VREFP1 and VREFN1, Gaintrl1 is at a low state (G=high), and the output VOUT is at a high state.

[0067] Starting from time t'1, the signal RF_IN decreases with a first slope until time t'2. Then the signal RF_IN decreases with a lower slope until time t'3.

[0068] Between times t'1 and t'2, signal VAOP increases above threshold VREFP1, which places GainCtrl1 high (G=low) and VOUT switches to a low level.

[0069] Between times t'2 and t'3, signal VAOP remains above threshold VREFP1, which places GainCtrl1 at a high level (G=low) and VOUT remains at a low level.

[0070] From time t'3 until time t'5, signal RF_IN changes direction and increases linearly.

[0071] Between time t′3 and time t′4 , signal VAOP decreases to reach below threshold VREFP1 , which switches signal GainCtrl1 to a low state.

[0072] Between time t′4 and time t′5 , signal VAOP continues to drop and signal GainCtrl1 remains in a low state.

[0073] At time t'5, signal VAOP falls below threshold VREFN1, which switches signals GainCtrl1 and VOUT to a high state.

[0074] After time t'5, signal RF_IN stabilizes at a high state and signal VAOP rises back up and reaches above VREFN1 again at time t'6, which switches GainCtrl1 to a low state.

[0075] Figure 4 The example enables the formation of hysteresis, wherein the output signal VOUT switches state only after both thresholds VREFP1 and VREFN1 are crossed in one direction or the other.

[0076] When the signal GainCtrl1 is at a low level, the gain is high (high gain) to increase sensitivity. When the signal GainCtrl1 is at a high level, the gain is low (low gain) to limit the output dynamics and prevent saturation of the amplifier 212, while maintaining a certain gain level to allow detection of signal changes. In other words, using a non-zero gain in the region where GainCtrl1 is at a high level enables not being in saturation while improving the accuracy of detecting signal changes.

[0077] exist Figure 5 In the example of FIG. 2 , thresholds VREFP1 and VREFN1 define a non-saturated operating range for amplifier 212 , but values ​​slightly above VREFP1 and slightly below VREFN1 also define non-saturated operation due to the effect of non-zero gain.

[0078] Figure 6 Schematically shows a method according to another embodiment Figure 1 An example of a demodulation circuit for a device.

[0079] Figure 6 The demodulation circuit 606 and Figure 4 The demodulation circuit of FIG. 2 is similar to that of FIG. 2 , except that the feedback loop 214 of the amplifier circuit 210 includes a third branch including a switch 616 controlled by a signal (GainCtrl2) and connected in series with a resistor (R2c). The third branch couples the node NVIN to the node NVAOP. The resistor R2c enables a gain level different from that obtained with the branch including the resistors R2 and R2b when they are respectively activated.

[0080] Figure 6 The demodulation circuit 606 and Figure 4The demodulation circuit of 206 is also different in that the demodulation circuit 206 also includes a second signal level comparison circuit 650. The second comparison circuit 650 includes a third branch that couples the node NVAOP to an input of a logic circuit 680 configured to perform an "OR" function. The second comparison circuit 650 includes a fourth branch that couples the node NVAOP to another input of the logic circuit 680. The third branch includes a voltage comparator circuit 620. The comparator circuit 620 includes an operational amplifier 622 having an inverting input (-) configured to be coupled (preferably connected) to a voltage rail VREFP2 that is higher than VREFP1 and defines a third threshold. The operational amplifier 622 also includes a non-inverting input (+) configured to be coupled (preferably connected) to the node NVAOP. The output of the amplifier 622 is coupled (preferably connected) to one of the inputs of the logic circuit 680. When the level of the signal on the node NVAOP is higher than VREFP2, the amplifier 622 returns a high level signal at this input of the logic circuit 680. In the opposite case, a low level signal is returned.

[0081] In the example shown, the fourth branch of the second comparison circuit 650 includes a voltage comparator circuit 630. The comparator circuit 630 includes an operational amplifier 632 having an inverting input (-) configured to be coupled (preferably connected) to a voltage rail VREFN2, which is lower than VREFN1 and defines a fourth threshold. The operational amplifier 632 also includes a non-inverting input (+) configured to be coupled (preferably connected) to a node NVAOP. The output of the amplifier 632 is coupled to another of the inputs of the logic circuit 680 via an inverter circuit 640. When the level of the signal on the node NVAOP is lower than the threshold VREFN2, the amplifier 632 returns a high-level signal, which becomes low at the input of the logic circuit 680 after inversion. In the opposite case, a low-level signal is returned. The output of the logic circuit 680 is the control signal GainCtrl2.

[0082] Figure 7 Shows Figure 6 A timing diagram of the operation of the circuit.

[0083] Figure 6 The operation of the circuit is Figure 4 The operation of the circuit is similar, except that when the signal VAOP exceeds the thresholds VREFP1 and VREFP2 or falls below the thresholds VREFN1 and VREFN2, the switch 616 is activated by the signal GainCtrl2 and the gain of the amplifier circuit 210 becomes equal to (R2b · R2 · R2c) / (R1((R2 ·R2c)+(R2b · R2c)+(R2b · As signal VAOP crosses successive thresholds, its slope is attenuated by discrete reductions in the gain of amplifier circuit 210 to remain within the non-saturated operating region.

[0084] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, although Figure 4 and Figure 6 The examples of show in particular feedback loops 214 with two and three branches, respectively, but a person skilled in the art will be able to implement more branches in parallel, each branch comprising a switch and a resistor. The switch of each of these additional branches will be controlled by a signal derived from the comparison of the signal VAOP with one or more thresholds. In this case, other additional comparator circuits, such as circuits 220, 230, 620, 630, may be implemented and associated with one or more logic circuits, such as circuits 280 or 680.

[0085] Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, with regard to the type of trigger 260, other types of triggers can be used instead of trigger 260. A person skilled in the art can also implement comparator circuits 220, 230, 620 and 630 according to his knowledge. On the other hand, a person skilled in the art can implement feedback loop 214 in a different way, provided that its resistance varies discretely according to a threshold value but is not zero.

[0086] Those skilled in the art may implement the described demodulation circuit for radio frequency communication types other than the NFC type.

Claims

1. An amplifier circuit, comprising: an amplifier circuit, including an operational amplifier, the amplifier circuit being configured to amplify a signal to be demodulated; as well as A feedback loop has a resistance value that varies discretely according to the level of the output node of the amplifier circuit relative to one or more thresholds defining one or more non-saturated operating ranges of the amplifier circuit.

2. The amplifier circuit according to claim 1, wherein a resistance value of a feedback loop of the amplifier circuit is controlled to have a first resistance value when the level is higher than a first threshold or when the level is lower than a second threshold, wherein the second threshold is lower than the first threshold. 3 . The amplifier circuit according to claim 2 , wherein when the level is between a first threshold and a second threshold, a resistance value of a feedback loop of the amplifier circuit is controlled to have a second resistance value.

4. The amplifier circuit according to claim 3, wherein when the level is higher than a third threshold or when the level is lower than a fourth threshold, the resistance value of the feedback loop of the amplifier circuit is controlled to have a third resistance value, wherein the third threshold is higher than the first threshold, and wherein the fourth threshold is lower than the second threshold. 5 . The amplification circuit of claim 1 , wherein the operational amplifier comprises an inverting input terminal coupled to an input node of the amplifier circuit and coupled to an output node of the amplifier circuit via a feedback loop.

6. The amplifier circuit according to claim 5, wherein the feedback loop comprises: a first branch coupling the inverting input terminal of the operational amplifier to the output node, the first branch comprising a resistive element having a first resistance value; N additional branches coupled in parallel with the first branch, wherein each additional branch includes a resistive element connected in series with a switch controlled by a corresponding control signal, and N is a positive integer; the respective control signal being dependent on a comparison of a level of an output node of the amplifier circuit relative to a respective operating range among N non-saturated operating ranges of the amplifier circuit, each operating range being defined by a threshold value; and N comparison circuits are configured to generate a corresponding control signal for each of the N additional branches to cause the corresponding switch to: When the level of the output node of the amplifier circuit is within the corresponding operating range, it is not conducting; as well as The amplifier circuit is turned on when the level of the output node is outside the corresponding operating range.

7. The amplifier circuit according to claim 6: wherein the resistance value of the feedback loop of the amplifier circuit is controlled to have a first resistance value when the level is higher than a first threshold value or when the level is lower than a second threshold value, wherein the second threshold value is lower than the first threshold value; and The N=1 non-saturated operating range is defined between a first threshold and a second threshold, and the N=1 branch is formed by a resistive element having a fourth resistance value.

8. The amplifier circuit according to claim 7, further comprising a trigger, the trigger having: a set input terminal coupled to an output node of the comparator circuit of the first branch of the first comparison circuit; a reset input terminal coupled to an output node of the inverter circuit of the second branch of the first comparison circuit; as well as The output terminal is coupled to the output node of the amplifier circuit via the inverter circuit.

9. The amplifier circuit according to claim 7, wherein a first comparison circuit among the N comparison circuits comprises: a first comparison branch including a comparator circuit having a non-inverting input coupled to the output node and an inverting input coupled to a node configured to receive a voltage representative of a first threshold; a second comparison branch including a comparator circuit in series with an inverter circuit, the comparator circuit having a non-inverting input coupled to the output node and an inverting input coupled to a node configured to receive a voltage representative of a second threshold; as well as a logic block configured to perform an OR function based on a signal present at an output node of the comparator circuit of the first branch of the first comparison circuit and another signal present at an output node of the inverter circuit of the second branch of the first comparison circuit; The output of the logic block is the control signal for the switches of the N=1 branch of the feedback loop.

10. The amplifier circuit according to claim 9: wherein when the level is between a first threshold and a second threshold, the resistance value of the feedback loop of the amplifier circuit is controlled to have a second resistance value; wherein the resistance value of the feedback loop of the amplifier circuit is controlled to have a third resistance value when the level is higher than a third threshold or when the level is lower than a fourth threshold, wherein the third threshold is higher than the first threshold, wherein the fourth threshold is lower than the second threshold; and The N=2 non-saturated operating range is defined between the third threshold and the fourth threshold and the N=2 branch is formed by a resistive element having a fifth resistance value.

11. The amplifier circuit according to claim 10, wherein a first comparison circuit among the N comparison circuits comprises: a first comparison branch including a comparator circuit having a non-inverting input coupled to the output node and an inverting input coupled to a node configured to receive a voltage representative of a first threshold; a second comparison branch including a comparator circuit in series with an inverter circuit, the comparator circuit having a non-inverting input coupled to the output node and an inverting input coupled to a node configured to receive a voltage representative of a second threshold; as well as a logic block configured to perform an OR function based on a signal present at an output node of the comparator circuit of the first branch of the first comparison circuit and another signal present at an output node of the inverter circuit of the second branch of the first comparison circuit; The output of the logic block is the control signal for the switches of the N=1 branch of the feedback loop.

12. The amplifier circuit according to claim 11, wherein the second comparison circuit among the N comparison circuits comprises: a third comparison branch including a comparator circuit having a non-inverting input coupled to the output node and an inverting input coupled to a node configured to receive a voltage representative of a third threshold; a fourth comparison branch including a comparator circuit in series with another inverter circuit, the comparator circuit having a non-inverting input coupled to the output node and an inverting input coupled to a node configured to receive a voltage representative of a fourth threshold; as well as another logic block configured to perform an OR function based on a signal present at an output node of the comparator circuit of the third branch of the second comparison circuit and another signal present at an output of the inverter circuit of the fourth branch of the second comparison circuit; The output of the logic block is a signal used to control the switches of the N=2 branches of the feedback loop.

13. The amplifier circuit according to claim 12, further comprising a trigger, the trigger having: a set input terminal coupled to an output node of the comparator circuit of the first branch of the first comparison circuit; a reset input terminal coupled to an output node of the inverter circuit of the second branch of the first comparison circuit; as well as The output terminal is coupled to the output node of the amplifier circuit via the inverter circuit.

14. The amplifier circuit of claim 5, wherein the inverting input terminal of the operational amplifier is coupled to the input node of the amplifier circuit via a capacitive element connected in series with the input resistor.

15. A demodulation circuit comprising the amplifier circuit according to claim 1. The demodulation circuit according to claim 15 , wherein the demodulation circuit is of NFC type. 17 . A near field communication device, comprising the demodulation circuit according to claim 15 .

18. An amplifier circuit, comprising: an amplifier circuit configured to amplify a signal to be demodulated; as well as a feedback loop coupled between an input node and an output node of the amplifier circuit; wherein the feedback loop has a resistance value that varies discretely according to the level at the output node of the amplifier circuit relative to one or more thresholds defining one or more non-saturated operating ranges of the amplifier circuit; wherein the resistance value of the feedback loop of the amplifier circuit is controlled to have a first resistance value when the level is higher than a first threshold value or when the level is lower than a second threshold value, wherein the second threshold value is lower than the first threshold value; as well as The feedback loop includes: a first branch coupling an input node of the amplifier circuit to an output node, the first branch comprising a resistive element having a first resistance value; N additional branches coupled in parallel with the first branch, wherein each additional branch includes a resistive element connected in series with a switch controlled by a corresponding control signal, N being a positive integer greater than two; the respective control signal being dependent on a comparison of a level of an output node of the amplifier circuit relative to a respective operating range among N non-saturated operating ranges of the amplifier circuit, each operating range being defined by a threshold value; and N comparison circuits are configured to generate a corresponding control signal for each of the N additional branches to cause the corresponding switch to: non-conductive when the level of the output node of the amplifier circuit is within the corresponding operating range; and The amplifier circuit is turned on when the level of the output node is outside the corresponding operation range. 19 . The amplifier circuit according to claim 18 , wherein when the level is between a first threshold and a second threshold, a resistance value of a feedback loop of the amplifier circuit is controlled to have a second resistance value.

20. The amplifier circuit according to claim 19, wherein when the level is higher than a third threshold or when the level is lower than a fourth threshold, the resistance value of the feedback loop of the amplifier circuit is controlled to have a third resistance value, wherein the third threshold is higher than the first threshold, and wherein the fourth threshold is lower than the second threshold.

21. The amplifier circuit according to claim 20: wherein the resistance value of the feedback loop of the amplifier circuit is controlled to have a first resistance value when the level is higher than a first threshold value or when the level is lower than a second threshold value, wherein the second threshold value is lower than the first threshold value; and The N=1 non-saturated operating range is defined between the first threshold and the second threshold and the N=1 branch is formed by a resistive element having a fourth resistance value.

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