Radiation-resistant nonvolatile configuration memory unit

Abstract

The invention discloses a nonvolatile high-single-particle-resistance configuration memory unit, and relates to an integrated circuit technology. The circuit comprises eight MOS tubes, a gating MOS tube and a PL plate line which form a four-level DICE structure, and is characterized in that at least two nodes in four nodes of the DICE structure serve as ferroelectric connection nodes, and the ferroelectric connection nodes are nodes connected to the PL plate line through ferroelectric capacitors. The DICE structure and the ferroelectric capacitor are adopted to form the nonvolatile FPGA, so that compared with an SRAM (Static Random Access Memory) type FPGA, an external configuration memory is omitted, the system is simplified, and the single particle resistance of the nonvolatile FPGA is greatly improved.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology. Background Art

[0002] Electronic systems are increasingly used in the aerospace field, and the impact of space radiation environment on electronic systems cannot be ignored. Radiation can degrade the performance parameters of devices and even cause them to fail, affecting the reliable operation of satellites and shortening the life of satellites. According to satellite data statistics, 70% of its abnormal records are caused by the space radiation environment. With the development of aerospace electronic technology, field programmable gate arrays (FPGAs) have received more and more attention. FPGAs combine the advantages of semi-custom gate array circuits and the user-programmable characteristics of programmable logic devices, making the designed electronic products integrated, miniaturized, highly reliable, and fast, and providing designers with the ability to reprogram within the system, making the new generation of electronic systems extremely flexible and adaptable.

[0003] The structure of FPGA is mainly divided into three parts: programmable logic block, programmable I / 0 module, and programmable internal connection. There are two main types of programmable logic block and programmable interconnection resource construction: lookup table type and multiplexer type. The programmable logic unit of the lookup table type FPGA is composed of a static memory (SRAM) functioning as a lookup table to form a function generator, which controls the logic of executing the FPGA application function. The basic structure of the multiplexer type programmable logic block is a multiplexer configuration. When each input of the multiplexer is connected to a fixed level or input signal, different logic functions can be realized. A large number of multiplexers and logic gates are connected to form a logic block that realizes a large number of functions.

[0004] The most serious radiation effect in SRAM-based FPGAs is configuration flipping. Heavy particles with a certain amount of energy collide with the memory or logic circuit PN junction. The charge formed around the heavy particle movement trajectory is collected by sensitive electrodes and parallelized into a transient current. If the current exceeds a certain value, it will trigger the logic circuit, forming a flip of the logic state, which may lead to the loss of control over the integrated circuit. When exposed to heavy ion radiation, the device will obviously lose all functions until the power is restarted. If the wrong configuration is loaded in the SRAM, the device will be destroyed.

[0005] Definitions of abbreviations and key terms used in the present invention: DICE: Dual Interlocked storage Cell FPGA: Field Programmable Gate Array SRAM: Static Random Access Memory, static random access memory SEU: Single Event Upset FRAM: Ferroelectric Random Access Memory 2T-2C: Two Transistor Two Capacitor, 2 transistors and 2 capacitors LUT: Look Up Table MOSFET: Metal Oxide Silicon Field Effect Transistor NMOS: N-type metal oxide semiconductor field effect transistor PMOS: P-type metal oxide semiconductor field effect transistor Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a non-volatile high-single-particle-resistant configuration memory unit capable of enhancing the single-particle radiation resistance capability of a non-volatile FPGA.

[0007] The technical solution adopted by the present invention to solve the technical problem is a non-volatile high-resistance single-particle configuration memory unit, including 8 MOS tubes, a selection MOS tube and a PL plate line constituting a 4-level DICE structure, characterized in that among the 4 nodes of the DICE structure, at least two nodes serve as ferroelectric connection nodes, and the ferroelectric connection nodes refer to nodes connected to the PL plate line through a ferroelectric capacitor.

[0008] Furthermore, among the four nodes of the DICE structure, the two nodes at the front and rear ends are used as ferroelectric connection nodes, or the two nodes in the middle are used as ferroelectric connection nodes.

[0009] Furthermore, each ferroelectric connection node is connected to the first PL plate line via a ferroelectric capacitor and is also connected to the second PL plate line via another ferroelectric capacitor.

[0010] Furthermore, among the four nodes of the DICE structure, the first node and the fourth node are ferroelectric connection nodes, the first node is connected to the first bit line BL through the ninth selection MOS tube M9, the second node is connected to the second bit line ~BL through the eleventh selection MOS tube M11, the third node is connected to the first bit line BL through the twelfth selection MOS tube M12, the fourth node is connected to the second bit line ~BL through the tenth selection MOS tube M10, and the gate of each selection MOS tube is connected to the word line WL.

[0011] The beneficial effects of the present invention are: (1) The DICE SRAM structure does not affect the speed of FPGA operation; (2) Ferroelectric capacitors are fabricated on top of transistors and do not increase chip area; (3) The DICE structure plus ferroelectric capacitors can form a non-volatile FPGA, which eliminates the need for external configuration memory and simplifies the system compared to SRAM-based FPGAs; (4) Although the DICE structure is resistant to single-particle radiation, as the process size continues to decrease, 2-bit or multi-bit flips will weaken the DICE's ability to resist single-particle radiation. The high radiation resistance of ferroelectric capacitors effectively compensates for the weakness of the DICE structure. Therefore, the combination of the two can greatly increase the single-particle resistance of non-volatile FPGAs. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 , 2 It is a schematic diagram of prior art one.

[0013] Figure 3 It is a schematic diagram of the second prior art.

[0014] Figure 4 It is a schematic diagram of prior art three.

[0015] Figure 5 This is a schematic diagram of the structure of Example 1 described in the present invention.

[0016] Figure 6 This is a schematic diagram of the structure of Example 2 described in the present invention.

[0017] Figure 7 This is a schematic diagram of the structure of Example 3 described in the present invention.

[0018] Figure 8 This is a schematic diagram of the structure of Example 4 described in the present invention.

[0019] Fig. 9 It is a schematic diagram of the structure of Embodiment 5 (a ferroelectric configuration memory with 12T DICE and ferroelectric capacitor) described in the present invention.

[0020] Fig.10 The figure is a schematic diagram of a programmable wiring structure of the ferroelectric configuration memory described in the present invention used in an FPGA.

[0021] Fig.11 This is a schematic diagram of the ferroelectric configuration memory used for programmable I / O structure of the present invention.

[0022] Fig.12 This is a circuit diagram of a logic storage unit CLB module used in the lookup table-based FPGA described in the present invention. Specific implementation plan

[0023] Example 1: See Figure 5 .

[0024] This embodiment includes 8 MOS tubes, a gate MOS tube and a PL plate line that constitute a 4-level DICE structure. Among the 4 nodes (P1~P4) of the DICE structure, the two nodes marked as P1 and P4 are used as ferroelectric connection nodes, and the ferroelectric connection node refers to a node connected to the PL plate line through a ferroelectric capacitor.

[0025] Specifically, the present embodiment includes a first ferroelectric capacitor FeC1, a second ferroelectric capacitor FeC2, and 10 MOSFETs (M1-M10), wherein the MOS tubes marked as M1, M3, M5, and M7 are PMOS tubes, and the MOS tubes marked as M2, M4, M5, and M8 are NMOS tubes, which together form an 8-tube DICE SRAM structure. The MOS tubes marked as M9 and M10 are read-write selection tubes controlled by the word line WL signal, VCC and VSS are the high and low power supplies of the chip, BL and ~BL are a pair of opposite bit line signals, and the PL signal cooperates with the WL, BL, and ~BL signals to control the reading and writing of the ferroelectric capacitor.

[0026] The writing process is as follows: opposite voltages representing "0" and "1" are applied to the first bit line BL and the second bit line ~BL, the word line WL controls the ninth selection MOS tube M9 and the tenth selection MOS tube M10 to turn on, the signals on the first bit line BL and the second bit line ~BL are stored in DICE, and then a pulse signal is added to PL to write the BL and ~BL signals into the first ferroelectric capacitor FeC1 and the second ferroelectric capacitor FeC2 respectively. The reading process is the opposite: the WL line controls M9 and M10 to turn on, and the data is directly output to BL and ~BL.

[0027] Example 2: See Figure 6 .

[0028] The difference between this embodiment and embodiment 1 is that the connection position of FeC1 and FeC2 is changed. In embodiment 1, the two nodes at the front and rear ends are used as ferroelectric connection nodes, while in this embodiment, the two nodes in the middle are used as ferroelectric connection nodes, that is, the two nodes marked as P2 and P3 are used as ferroelectric connection nodes.

[0029] Example 3: See Figure 7 .

[0030] The difference between this embodiment and the first embodiment is that in this embodiment, four ferroelectric capacitors FeC1 to FeC4 are respectively connected to four nodes of the DICE.

[0031] Example 4: See Figure 8 .

[0032] The difference between this embodiment and Embodiment 1 is that each ferroelectric connection node is connected to the first PL plate line through a ferroelectric capacitor and is also connected to the second PL plate line through another ferroelectric capacitor.

[0033] Compared with Example 1, this embodiment adds a third ferroelectric capacitor FeC3 and a fourth ferroelectric capacitor FeC4. One plate of the third ferroelectric capacitor FeC3 is connected to the same line as the first ferroelectric capacitor FeC1, one plate of the fourth ferroelectric capacitor FeC4 is connected to the same line as the second ferroelectric capacitor FeC2, the other plates of the third ferroelectric capacitor FeC3 and the fourth ferroelectric capacitor FeC4 are connected to a new plate line PL2, and the plate line to which the first ferroelectric capacitor FeC1 and the second ferroelectric capacitor FeC2 are connected is PL1.

[0034] Example 5: See Fig. 9 This embodiment changes the 10-tube DICE structure of embodiment 1 into a 12-tube DICE structure, that is, two MOS tubes are added for writing and reading, and two identical data read out are connected to BL together, and another two identical data are connected to ~BL together.

[0035] Specifically, among the four nodes of the DICE structure, the first node and the fourth node are ferroelectric connection nodes, the first node is connected to the first bit line BL through the ninth selection MOS tube M9, the second node is connected to the second bit line ~BL through the eleventh selection MOS tube M11, the third node is connected to the first bit line BL through the twelfth selection MOS tube M12, the fourth node is connected to the second bit line ~BL through the tenth selection MOS tube M10, and the gate of each selection MOS tube is connected to the word line WL.

[0036] Fig.10 It is a basic unit of programmable wiring, which includes a ferroelectric configuration storage unit and a switch transistor. The output of the ferroelectric configuration storage unit is connected to the gate of the switch transistor, which controls the switch tube to connect or disconnect the column line and the row line to form a programmable wiring. Multiple units can be used on the wiring channel. Figure 6 When the storage unit of China Railway Electric is configured to output a high level 1, the switch tube is turned on, and the column line and the row line are connected together; Figure 6 When the output of the storage unit configured by China Railway Electric is low level 0, the switch tube is turned off and the column line is disconnected from the row line.

[0037] Fig.11It is a schematic diagram of a programmable I / O. The structure includes a port PAD. The PAD signal is connected to the D end of a D flip-flop. Under the control of the synchronous clock CK, it is input from the Q end to the inside of the chip to form an In signal. The Out signal is connected to the D end of a D flip-flop. Under the control of the synchronous clock CK, it is output from the Q end to the buffer. The buffer is controlled by the Q end of a D flip-flop. Under the control of the synchronous clock CK, the D flip-flop is determined by the ferroelectric configuration unit whether to output the Out data to the PAD port.

[0038] Fig.12 This is a circuit diagram of a logic storage unit CLB module used in an FPGA based on a lookup table (LUT), including a 4-input LUT, a D flip-flop, a 2-input data selector MUX, a transmission gate TG, and an inverter INV. The output OUT of the LUT is connected to the input terminal D of the D flip-flop, the output Q of the D flip-flop and the output OUT of the LUT are connected to the two inputs A and B of the MUX respectively, the output of the MUX is connected to the input of the TG, and the output of the TG is the output signal Y. D0 to D17 are control input terminals. By selecting appropriate values ​​from the ferroelectric configuration storage cell array, any combination function of the four input signals A, B, C, and D can be completed. For example, Y = (A + B) C, the content in the LUT needs to be set to the truth table of this function. When A, B, and C are input 000 respectively, and D is any input signal, the Y output of the LUT should be 0, and so on. At this time, D16 is selected as low level 0, and the output C of MUX is C=A. If D17 is high level, TG is turned on, and the final output signal Y is the output signal of LUT. The CLB module completes the function Y=(A+B)C. In the figure, more timing functions can be realized by adding triggers.

[0039] From the above analysis, it can be seen that the ferroelectric configuration storage unit of the present invention can store 0 and 1 separately, and the ferroelectric configuration storage unit is used in FPGA based on wiring structure and FPGA based on lookup table. Through analysis, both ferroelectric configuration memory type FPGAs can work normally.

[0040] The specification has fully explained the principles and necessary technical contents of the present invention, and ordinary technicians can implement them according to the specification, so more detailed details will not be repeated.

Claims

1. A non-volatile high-resistance single-particle configuration memory cell, comprising 8 MOS tubes, a gate MOS tube and a PL board line constituting a 4-level DICE structure, characterized in that: Among the four nodes of the DICE structure, at least two nodes serve as ferroelectric connection nodes, which are nodes connected to the PL plate lines through ferroelectric capacitors.

2. The non-volatile high-resistance single-particle configuration memory cell according to claim 1, characterized in that: Among the four nodes of the DICE structure, the two nodes at the front and rear ends serve as ferroelectric connection nodes.

3. The non-volatile high-resistance single-particle configuration memory cell according to claim 1, characterized in that: Among the four nodes of the DICE structure, the two middle nodes serve as ferroelectric connection nodes.

4. The non-volatile high-resistance single-particle configuration memory cell according to claim 1, characterized in that: Each ferroelectric connection node is connected to a first PL plate line through a ferroelectric capacitor and is also connected to a second PL plate line through another ferroelectric capacitor.

5. The non-volatile high-resistance single-particle configuration memory cell according to claim 1, characterized in that: Among the four nodes of the DICE structure, the first node and the fourth node are ferroelectric connection nodes. The first node is connected to the first bit line [BL] through the ninth selection MOS tube [M9], the second node is connected to the second bit line [~BL] through the eleventh selection MOS tube [M11], the third node is connected to the first bit line [BL] through the twelfth selection MOS tube [M12], and the fourth node is connected to the second bit line [~BL] through the tenth selection MOS tube [M10]. The gates of the selection MOS tubes are connected to the word line [WL].

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