Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a method for manufacturing the semiconductor device. The method for manufacturing a semiconductor device includes: forming a cell mode including a dummy channel pattern and a plurality of mode layers over a lower structure; forming a horizontal conductive line intersecting the dummy channel pattern; forming a dummy channel layer by trimming the dummy channel pattern; forming a data storage element coupled to the first side of the dummy channel layer; replacing the dummy channel layer with a channel layer; and forming a vertical conductive line coupled to the second side of the channel layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2023-0112774, filed on August 28, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a three-dimensional memory cell and a method for manufacturing the semiconductor device. Background Art

[0004] Recently, in order to cope with the demand for large capacity and miniaturization of memory devices, technologies for providing 3D memory devices in which a plurality of memory cells are stacked have been proposed. However, the performance and reliability of these 3D memory devices need to be further improved. Summary of the invention

[0005] Embodiments of the present invention relate to a 3D semiconductor device (hereinafter referred to as a semiconductor device) including a highly integrated memory cell and a method for manufacturing the semiconductor device.

[0006] According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a unit mold including a dummy channel pattern and a plurality of mold layers above a lower structure; forming a horizontal conductive line intersecting the dummy channel pattern; forming a dummy channel layer by trimming the dummy channel pattern; forming a data storage element coupled to a first side of the dummy channel layer; replacing the dummy channel layer with a channel layer; and forming a vertical conductive line coupled to a second side of the channel layer.

[0007] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a unit mold, which includes a dummy channel pattern located above a lower structure and a unit dielectric layer pair arranged in the upper and lower parts of the dummy channel pattern; forming a horizontal level recess pair by recessing the unit dielectric layer pair, the horizontal level recess pair exposing the top surface and the bottom surface of the dummy channel pattern; forming a gate dielectric layer on the exposed top surface and the bottom surface of the dummy channel pattern; forming a first horizontal wire and a second horizontal wire filling the horizontal level recess pair above the gate dielectric layer; forming a dummy channel layer by trimming the dummy channel pattern; forming a channel level gap between the first horizontal wire and the second horizontal wire by removing the dummy channel layer; and forming a channel layer in the channel level gap.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a lower structure; a horizontal layer arranged above the lower structure; horizontal wires arranged in the upper and lower parts of the horizontal layer, respectively; a gate dielectric layer located between the horizontal wires and the horizontal layer; a vertical wire coupled to a first side of the horizontal layer; and a data storage element coupled to a second side of the horizontal layer, wherein the horizontal layer includes: a channel layer having an internal space; and an internal gap filling layer filling the internal space of the channel layer.

[0009] These and other features and advantages of the present invention will be better understood from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a simplified schematic perspective view showing a storage unit according to an embodiment of the present invention.

[0011] Figure 1B It is shown Figure 1A A simplified schematic cross-sectional view of a memory cell is shown.

[0012] Figure 1C is a schematic plan view of the switching element shown in FIG. 1 .

[0013] Figure 1D is a simplified schematic cross-sectional view illustrating a memory cell according to another embodiment of the present invention.

[0014] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention.

[0015] Figure 3A It is shown Figure 2 A simplified schematic perspective view of a memory cell array MCA1 is shown.

[0016] Figure 3B is along Figure 2 A simplified schematic cross-sectional view taken along line AA' is shown. Figure 3C is along Figure 2 A cross-sectional view taken along line BB' is shown. Figure 3D is along Figure 2 A cross-sectional view taken along line CC' is shown.

[0017] Figures 4 to 25 A method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0018] Figure 26 to Figure 28 A method for manufacturing a semiconductor device according to another embodiment of the present invention is shown.

[0019] FIG. 29A to FIG. 29C is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0020] Figure 30 to Figure 32 is a perspective view showing a memory cell array according to another embodiment of the present invention. DETAILED DESCRIPTION

[0021] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in multiple drawings and embodiments of the present invention.

[0022] The drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0023] The following embodiments described below relate to three-dimensional memory cells. Memory cells can be stacked vertically to increase memory cell density and reduce parasitic capacitance.

[0024] Figure 1A is a simplified schematic perspective view showing a storage unit according to an embodiment of the present invention. Figure 1B It is shown Figure 1A A simplified schematic cross-sectional view of a memory cell is shown. Figure 1C It is shown Figure 1A A schematic plan view of a switching element is shown.

[0025] Reference Figures 1A to 1C , the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0026] The first wire BL may be oriented in a first direction D1. The first direction D1 may be, for example, a direction perpendicular to a plane defined by the second direction D2 and the third direction D3. In some embodiments, the plane defined by the second direction and the third direction may be a horizontal plane and the first direction may be a vertical direction. The first wire BL may include a bit line. The first wire BL may also be referred to as a vertical wire or bit line, a vertical wire or bit line, a vertically oriented wire or bit line, a vertically extending wire or bit line, or a columnar wire or bit line. The first wire BL may include a conductive material. The first wire BL may include a silicon-based material, a metal-based material, or a combination thereof. The first wire BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first wire BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first wire BL may include polysilicon or titanium nitride (TiN) doped with N-type impurities. The first wire BL may include a stack of titanium nitride and tungsten (TiN / W).

[0027] The switching element TR may have a function of controlling the voltage (or current) supply to the data storage element CAP during the data write operation and the data read operation performed on the data storage element CAP. The switching element TR may include a horizontal layer HL (also referred to as a lateral layer HL in general), an interlayer dielectric layer GD, and a second wire DWL. The second wire DWL may include a horizontal wire or a horizontal word line (also referred to as a lateral wire or a lateral word line), and the horizontal layer HL may include an active layer. The switching element TR may include a transistor, and in this case, the second wire DWL may be used as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second wire DWL may also be referred to as a horizontal gate electrode or a horizontal word line.

[0028] The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. The second wire DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, and the second direction D2 may be a first horizontal direction (also referred to as a first lateral direction), and the third direction D3 may be a second horizontal direction (also referred to as a second lateral direction). The horizontal layer HL may extend in the first horizontal direction (i.e., the second direction D2), and the second wire DWL may extend in the second horizontal direction (i.e., the third direction D3).

[0029] The horizontal layer HL may be horizontally oriented in the second direction D2 from the first wire BL. The second wire DWL may have a double structure. For example, the second wire DWL may include an upper horizontal line G1 (also referred to as an upper lateral line) and a lower horizontal line G2 (also referred to as a lower lateral line) facing each other and with the horizontal layer HL disposed therebetween. The interlayer dielectric layer GD may be formed on the upper surface and the lower surface of the horizontal layer HL. The upper horizontal line G1 may be disposed above the horizontal layer HL. The lower horizontal line G2 may be disposed at the bottom of the horizontal layer HL. The second wire DWL may include a pair of upper horizontal lines G1 and lower horizontal lines G2. In the second wire DWL, the same driving voltage may be applied to the upper horizontal line G1 and the lower horizontal line G2. For example, the upper horizontal line G1 and the lower horizontal line G2 may form a pair and be coupled to a memory cell MC. According to another embodiment of the present invention, different driving voltages may be applied to the upper horizontal line G1 and the lower horizontal line G2. In this case, one of the upper horizontal line G1 and the lower horizontal line G2 may be used as a back gate or a shielding gate.

[0030] Return to reference Figure 1C , each of the upper horizontal line G1 and the lower horizontal line G2 may have a width in the second direction D2, for example, a width of an overlapping portion overlapping with the horizontal layer HL, which is greater than a width of a portion not overlapping with the horizontal layer HL. Due to this difference in width, the second wire DWL may have a notch-shaped sidewall. The second wire DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP may refer to a portion overlapping with the channel CH of the horizontal layer HL, and the channel non-overlapping portion NOL may refer to a portion not overlapping with the horizontal layer HL. The channel overlapping portion WLP may have a cross shape or a diamond shape.

[0031] From a top view perspective, the horizontal layer HL may have a cross shape or a diamond shape. According to another embodiment of the present invention, a side surface of the horizontal layer HL may have a curved shape or a rounded shape.

[0032] The horizontal layer HL may include a conductive metal oxide or an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO).

[0033] The upper surface and the lower surface of the horizontal layer HL may have flat surfaces. The upper surface and the lower surface of the horizontal layer HL may be parallel to each other in the second direction D2.

[0034] The horizontal layer HL may include a channel CH. The horizontal layer HL may also be referred to as a channel layer, an active layer, or a thin body. The channel overlap portion WLP of the channel CH and the second wire DWL may overlap each other. The channel CH may have a cross shape or a diamond shape. The size of the channel overlap portion WLP of the second wire DWL may be larger than the size of the channel CH. The channel overlap portion WLP of the second wire DWL may completely overlap with the channel CH. The channel CH may include a conductive metal oxide or an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). The channel CH of the horizontal layer HL may include an oxide semiconductor channel, such as an IGZO channel. As will be described later, the horizontal layer HL may be formed by replacing the single crystal silicon layer with an oxide semiconductor material.

[0035] The interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second conductive line DWL. The interlayer dielectric layer GD may also be referred to as a gate dielectric layer. The interlayer dielectric layer GD may also be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer GD may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer GD may include SiO 2 、Si 3 N 4 , HfO 2 、Al 2 O 3 、ZrO 2 , AlON, HfON, HfSiO, HfSiON, HfZrO or a combination thereof. The interlayer dielectric layer GD may be formed by a thermal oxidation process of a semiconductor material.

[0036] The second wire DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second wire DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second wire DWL may include a TiN / W stack in which titanium nitride and tungsten are stacked in sequence. The second wire DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or more. The second wire DWL may include a stack of a low work function material and a high work function material.

[0037] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be arranged horizontally from the switching element TR in the second direction D2. The data storage element CAP may include a first electrode SN extending horizontally from the horizontal layer HL in the second direction D2. The data storage element CAP may also include a second electrode PN above the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be arranged horizontally in the second direction D2. The first electrode SN may include an internal space and a plurality of external surfaces, and the internal space of the first electrode SN may include a plurality of internal surfaces. The external surface of the first electrode SN may include a vertical external surface and a plurality of horizontal external surfaces. The vertical external surface of the first electrode SN may extend vertically in the first direction D1, and the horizontal external surface of the first electrode SN may extend horizontally in the second direction D2 or the third direction D3. The internal space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover the internal and external surfaces of the first electrode SN. The second electrode PN may be disposed in the internal space of the first electrode SN above the dielectric layer DE. A portion of the external surface of the first electrode SN may be electrically connected to the horizontal layer HL. The second electrode PN of the data storage element CAP may be connected to the common plate PL.

[0038] The data storage element CAP may be a three-dimensional structure. The first electrode SN may have a three-dimensional structure. The first electrode SN may have a horizontal three-dimensional structure oriented in the second direction D2. As an example of a three-dimensional structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include a cylindrical inner surface and a cylindrical outer surface. A portion of the cylindrical surface of the first electrode SN may be electrically connected to the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the cylindrical inner surface of the first electrode SN.

[0039] According to another embodiment of the present invention, the first electrode SN may have a pillar shape or a cylindrical barrel shape. The cylindrical barrel shape may refer to a structure in which a pillar shape and a barrel shape are combined.

[0040] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium (Ir), iridium oxide (IrO 2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap filling material filling the inside of the first electrode SN, titanium nitride (TiN) may be used as the second electrode PN of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0041] The dielectric layer DE may also be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may include hafnium oxide (HfO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ) or strontium titanium oxide (SrTiO 3 According to another embodiment of the present invention, the dielectric layer DE may be formed of a composite layer including two or more layers of the aforementioned high-k material.

[0042] The dielectric layer DE may be formed of zirconium-based oxide (Zr-based oxide). The dielectric layer DE may have a zirconium oxide (ZrO 2 ) stacked structure. The dielectric layer DE may include ZA (ZrO 2 / Al 2 O 3 ) stack or ZAZ(ZrO 2 / Al 2 O 3 / ZrO 2 ) stack. The ZA stack may have a 2 O 3 ) stacked on zirconium oxide (ZrO 2 ) structure above. The ZAZ stack may have a structure in which zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ) and zirconium oxide (ZrO 2 ) are stacked in sequence. ZA stacking and ZAZ stacking can also be called zirconium oxide based (ZrO 2According to another embodiment of the present invention, the dielectric layer DE may be formed of a hafnium-based oxide (Hf-based oxide). The dielectric layer DE may have a 2 ) stacked structure. The dielectric layer DE may include HA (HfO 2 / Al 2 O 3 ) stack or HAH(HfO 2 / Al 2 O 3 / HfO 2 ) stack. The HA stack may have a 2 O 3 ) stacked on hafnium oxide (HfO 2 ) structure above. The HAH stack may have a structure in which hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ) and hafnium oxide (HfO 2 ) are stacked in sequence. HA stacking and HAH stacking can also be referred to as hafnium oxide-based (HfO 2 In ZA stacking, ZAZ stacking, HA stacking and HAH stacking, aluminum oxide (Al 2 O 3 ) can have a higher 2 ) and hafnium oxide (HfO 2 ) has a large band gap energy. 2 O 3 ) can have a higher 2 ) and hafnium oxide (HfO 2 ) has a low dielectric constant. Therefore, the dielectric layer DE may include a stack of a high-k material and a high-bandgap material having a larger bandgap energy than the high-k material. 2 O 3 ), the dielectric layer DE may include silicon oxide (SiO 2 ). By including a high bandgap material in the dielectric layer DE, leakage current can be suppressed. The high bandgap material can be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure in which high-k materials and high bandgap materials are alternately stacked. For example, the dielectric layer DE may include ZAZA (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ) stack, ZAZAZ(ZrO 2 / Al 2 O 3 / ZrO2 / Al 2 O 3 / ZrO 2 ) stacking, HAHA(HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) stack, or HAHAH(HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ) stacked. In the above stacked structure, aluminum oxide (Al 2 O 3 ) can be compared with zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 )Thin.

[0043] According to another embodiment of the present invention, the dielectric layer DE may include a high-k material and a high bandgap material, and the dielectric layer DE may have a stacked structure in which multiple high-k materials and multiple high bandgap materials are stacked, or a mixed structure in which the high-k material and the high bandgap material are mixed with each other.

[0044] According to another embodiment of the present invention, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0045] According to another embodiment of the present invention, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, or a combination of a high-k material or a ferroelectric material and an antiferroelectric material.

[0046] According to another embodiment of the present invention, an interface control layer may be further formed between the first electrode SN and the dielectric layer DE to improve leakage current. The interface control layer may include titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), niobium nitride (NbN), or a combination thereof. An interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0047] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced by other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction MTJ, or a variable resistance material.

[0048] For example, the memory cell MC may include a thyristor, the first wire BL may be a cathode wire, and the data storage element CAP may be replaced by an anode wire. Therefore, the horizontal layer HL may include four semiconductor layers stacked in the second direction D2. The thyristor may include a first diode and a second diode coupled in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high conductance state in which a large amount of current flows or a low conductance state in which a small amount of current or no current flows. The memory cell MC according to this embodiment of the present invention may have a "1" state and a "0" state by using the high conductance state and the low conductance state of the thyristor, respectively.

[0049] Return to reference Figure 1A and Figure 1B , the memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon. The first contact node BLC and the second contact node SNC may include a conductive metal nitride or a conductive metal oxide. For example, the first contact node BLC and the second contact node SNC may include TiN, indium zinc oxide (IZO), indium tin oxide (ITO), or a combination thereof. According to another embodiment of the present invention, the second contact node SNC may be omitted. When the first contact node BLC and the second contact node SNC include metal oxides such as IZO, ITO, etc., the contact resistance between the first contact node BLC and the second contact node SNC and the horizontal layer HL may be improved.

[0050] Figure 1D is a simplified schematic cross-sectional view illustrating a memory cell according to another embodiment of the present invention. Figure 1D The memory cell MC1 can be similar to Figures 1A to 1C In the following, the memory cell MC that also appears in Figures 1A to 1C Repeated detailed description of the constituent elements in.

[0051] Reference Figure 1D , the memory cell MC1 may include a first wire BL, a switching element TR, and a data storage element CAP arranged in the mentioned order along the second direction. The switching element TR may include a horizontal layer HL and a second wire DWL. The second wire DWL may include a pair of upper wires G1 and lower wires G2. The data storage element CAP may include a first electrode SN, a second electrode PN, and a dielectric layer DE disposed between the first electrode SN and the second electrode PN.

[0052] The horizontal layer HL may include a channel layer HL1 and an internal gap filling layer IG. The channel layer HL1 may have a cup shape positioned in a lateral orientation, wherein the bottom surface of the cup contacts the second contact node SNC and the open space of the cup is adjacent to the bit line contact BLC. The internal space within the cup shape is filled with the internal gap filling layer IG. Therefore, the internal gap filling layer IG is in direct contact with the bit line contact BLC but not in contact with the second contact node SNC. The channel layer HL1 may include a conductive material, and the internal gap filling layer IG may include a dielectric material. The channel layer HL1 may include a conductive metal oxide or an oxide semiconductor material. The channel layer HL1 may include IGZO. The internal gap filling layer IG may include silicon oxide, silicon nitride, an air gap, or a combination thereof.

[0053] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention. Figure 3A It is shown Figure 2 A simplified schematic perspective view of a first memory cell array MCA1 is shown. Figure 3B is along Figure 2 A simplified schematic cross-sectional view taken along line AA' is shown. Figure 3C is along Figure 2 A cross-sectional view taken along line BB' as shown, and Figure 3D is along Figure 2 A cross-sectional view taken along line CC' is shown.

[0054] Reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D , the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells MC. For each memory cell MC, reference may also be made to Figures 1A to 1C Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0055] The memory cell array MCA may include a three-dimensional array of memory cells MC. The three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of memory cells MC may include a plurality of memory cells MC stacked in a first direction D1. The row array of memory cells MC may include a plurality of memory cells MC arranged horizontally in a second direction D2 and a third direction D3. The memory cell array MCA may include sub-memory cell arrays MCA1 adjacent to each other in the second direction D2. The sub-memory cell arrays MCA1 may have a mirror-type structure in which two memory cells MC share a first conductive line BL. According to another embodiment of the present invention, the semiconductor device 100 may further include a sub-memory cell array having a mirror-type structure in which two memory cells MC share a second electrode PN of a data storage element CAP. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 in which memory cells MC are vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 arranged horizontally in a third direction D3.

[0056] The inter-cell dielectric layer IL may be disposed between the memory cells MC stacked in the first direction D1. The inter-cell dielectric layer IL may include silicon oxide. The inter-cell dielectric layer IL may also be referred to as a horizontal inter-cell dielectric layer.

[0057] The cell isolation layers ISOA and ISOB may be disposed between adjacent memory cells MC disposed in the third direction D3. The cell isolation layers ISOA and ISOB may also be referred to as vertical inter-cell dielectric layers. The cell isolation layers ISOA and ISOB may include silicon oxide, silicon oxycarbide (SiCO), silicon nitride, or a combination thereof. The cell isolation layers ISOA and ISOB may include a first cell isolation layer ISOA and a second cell isolation layer ISOB. The first cell isolation layer ISOA and the second cell isolation layer ISOB may extend vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may have a column structure extending vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may be alternately disposed in the second direction D2. The first cell isolation layer ISOA may be disposed between the data storage elements CAP in the third direction D3. The second cell isolation layer ISOB may be disposed between the first conductive lines BL in the third direction D3. The second conductive line DWL may be disposed between the first cell isolation layer ISOA and the second cell isolation layer ISOB in the second direction D2. Each of the first cell isolation layer ISOA and the second cell isolation layer ISOB may include a stack of a cell isolation liner layer ISOL and a cell isolation gap-filling layer ISOG. The cell isolation liner layer ISOL may include silicon oxide, and the cell isolation gap-filling layer ISOG may include silicon oxycarbide.

[0058] The memory cell array MCA may be disposed over the lower structure LS.

[0059] The memory cell array MCA may include a plurality of second conductive lines DWL vertically stacked in a first direction D1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of first conductive lines BL spaced apart from each other in a third direction D3.

[0060] like Figure 1C As shown, each second conductor DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may have a cross shape or a diamond shape. The channel overlap portion WLP may completely overlap with the channel CH. The second conductor DWL extending in the third direction D3 may include a plurality of channel overlap portions WLP. Since the channel overlap portion WLP and the channel non-overlap portion NOL are alternately repeated in the third direction D3, the second conductor DWL may have a notch-shaped sidewall.

[0061] A plurality of first passivation layers BF1 may be disposed between the bottommost second wire DWL among the second wires DWL and the lower structure LS. The second passivation layer BF2 may be disposed between the first wire BL and the lower structure LS. The third passivation layer BF3 may be disposed between the data storage element CAP and the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may include a dielectric material. The first to third passivation layers BF1, BF2, and BF3 may include silicon oxide. The first to third passivation layers BF1, BF2, and BF3 may electrically disconnect the first wire BL, the second wire DWL, and the data storage element CAP from the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may also be referred to as bottom dielectric layers or bottom passivation layers. The lowest level inter-cell dielectric layer LIL may be disposed between the first passivation layer BF1 and the data storage element CAP.

[0062] The first wire BL may extend vertically from the upper portion of the lower structure LS in the first direction D1. The horizontal layer HL may extend in the second direction D2 intersecting the first direction D1. The second wire DWL may extend in the third direction D3 intersecting the first direction D1 and the second direction D2.

[0063] From the perspective of the top view, the horizontal layer HL may have a cross shape or a diamond shape. According to another embodiment of the present invention, the side surface of the horizontal layer HL may have a curved shape or a circular shape. Figure 1B As shown, the horizontal layer HL may include a channel CH.

[0064] The first cover layer BC may be disposed between the second wire DWL and the first wire BL. The second cover layer CC may be disposed between the second wire DWL and the first electrode SN of the data storage element. The first cover layer BC may be disposed between the upper horizontal line G1 and the first wire BL, and the first cover layer BC may also be disposed between the lower horizontal line G2 and the first wire BL. The second cover layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second cover layer CC may also be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. One memory cell MC may include a pair of first cover layers BC and a pair of second cover layers CC.

[0065] The first cover layer BC and the second cover layer CC may include a dielectric material. The first cover layer BC and the second cover layer CC may include silicon oxide, silicon nitride, silicon oxycarbide, an air gap or a combination thereof. The first cover layer BC may include silicon oxide, and the second cover layer CC may include a stack of silicon oxide and silicon nitride.

[0066] Each memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon. The first contact node BLC and the second contact node SNC may include TiN, indium zinc oxide (IZO), indium tin oxide (ITO), or a combination thereof. According to another embodiment of the present invention, the second contact node SNC may be omitted.

[0067] The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL. The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may be coupled to different first wires BL. The switching elements TR stacked in the first direction D1 may share one first wire BL. The switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL.

[0068] The first cell isolation layer ISOA may be disposed between the first electrodes SN of the data storage element CAP in the third direction D3. The first electrodes SN may be separated from each other by the first cell isolation layer ISOA. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0069] The lower structure LS may include a semiconductor substrate, a metal interconnect structure, a dielectric structure, a conductive structure, a bonding pad structure, another memory, or a peripheral circuit portion.

[0070] For example, the lower structure LS may include a structure in which a peripheral circuit portion, a metal interconnection structure, and a bonding pad structure are stacked in the stated order. The memory cell array MCA and the peripheral circuit portion of the lower structure LS may be combined by wafer bonding.

[0071] The peripheral circuit portion of the lower structure LS may be arranged at a level lower than the memory cell array MCA. This may also be referred to as a COP (Cell on Peripheral) structure. The peripheral circuit portion may include at least one control circuit for driving the memory cell array MCA. At least one control circuit of the peripheral circuit portion may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit portion may include an address decoder circuit, a read circuit, a write circuit, and the like. At least one control circuit of the peripheral circuit portion may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), and the like.

[0072] For example, the peripheral circuit part may include a sub word line driver and a sense amplifier. The first conductive line BL may be coupled to the sense amplifier, and the second conductive line DWL may be coupled to the sub word line driver.

[0073] According to another embodiment of the present invention, the peripheral circuit part may be arranged at a level higher than the memory cell array MCA. This may also be referred to as a POC (Peripheral on Cell) structure.

[0074] According to another embodiment of the present invention, the memory cell array MCA may include a dynamic random access memory (DRAM), an embedded DRAM, a NAND, a FeRAM, a STTRAM, a PCRAM, or a ReRAM.

[0075] According to another embodiment of the present invention, each memory cell MC may be composed of Figure 1D The memory cell MC1 shown is replaced.

[0076] Figures 4 to 21 A method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0077] Reference Figure 4, the stacked structure SB may be formed above the lower structure 11. The lower structure 11 may be a material suitable for semiconductor processing. The lower structure 11 may include at least one of a conductive material, a dielectric material, and a semiconductor material. Different materials may be formed above the lower structure 11. The lower structure 11 may include a semiconductor substrate. The lower structure 11 may be formed of a silicon-containing material. The lower structure 11 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The lower structure 11 may also include other semiconductor materials, such as germanium. The lower structure 11 may include a III / V semiconductor substrate, such as a compound semiconductor substrate of, for example, GaAs. The lower structure 11 may include a silicon-on-insulator (SOI) substrate.

[0078] The stacked structure SB may include a plurality of sub-stacks stacked alternately. Each sub-stack may include a first layer 12A, a second layer 13, a third layer 12B, and a dummy channel material layer 14 stacked in the order mentioned. The first layer 12A and the third layer 12B may be formed of the same material and may include silicon germanium. The second layer 13 and the dummy channel material layer 14 may include single crystal silicon. The first layer 12A, the second layer 13, the third layer 12B, and the dummy channel material layer 14 may be formed by an epitaxial growth process. The first layer 12A at the lowest level may be used as a seed layer during the epitaxial growth process. The first layer 12A may be thinner than the second layer 13, and the dummy channel material layer 14 may be thicker than the second layer 13.

[0079] The stacked structure SB may include a plurality of dummy channel material layers 14, a first sacrificial layer stack SB1, a second sacrificial layer stack SB2, and a third sacrificial layer stack SB3. The stacked structure SB may include a first sacrificial layer stack SB1, a dummy channel material layer 14, a second sacrificial layer stack SB2, a dummy channel material layer 14, and a third sacrificial layer stack SB3 stacked in the following order. The second layer 13 may be disposed at the uppermost level of the stacked structure SB. Each of the first sacrificial layer stack SB1, the second sacrificial layer stack SB2, and the third sacrificial layer stack SB3 may be a three-layer stack of a first layer 12A / a second layer 13 / a third layer 12B. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 includes a single crystal silicon layer, the first sacrificial layer stack SB1, the second sacrificial layer stack SB2, and the third sacrificial layer stack SB3 may include a stack (SiGe / Si / SiGe) of a first silicon germanium layer / a single crystal silicon layer / a second silicon germanium layer. The third sacrificial layer stack SB3 may be four layers of the first layer 12A / the second layer 13 / the third layer 12B / the second layer 13. The third sacrificial layer stack SB3 may be used as a hard mask.

[0080] The second layer 13 may include a first single crystal silicon layer, and the dummy channel material layer 14 may include a second single crystal silicon layer. Therefore, the stacked structure SB may include a first sacrificial layer stack SB1 disposed below the second single crystal silicon layer, and a second sacrificial layer stack SB2 disposed above the second single crystal silicon layer. Each of the first sacrificial layer stack SB1 and the second sacrificial layer stack SB2 may include a stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer. The second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0081] The first layer 12A, the second layer 13 and the third layer 12B may also be referred to as “sacrificial layers”, and the dummy channel material layer 14 may also be referred to as a “recess target layer”.

[0082] The stacked structure SB may also be referred to as a vertical stack. The stacked structure SB may be formed by alternating a plurality of sacrificial layers and a recessed target layer. The sacrificial layer may include a first sacrificial layer stack SB1, a second sacrificial layer stack SB2, and a third sacrificial layer stack SB3, and each of the first sacrificial layer stack SB1, the second sacrificial layer stack SB2, and the third sacrificial layer stack SB3 may include a stack of a first layer 12A / a second layer 13 / a third layer 12B. The recessed target layer may include a dummy channel material layer 14. Each sacrificial layer may include a stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer, and each recessed target layer may include a second single crystal silicon layer, wherein the second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0083] As described in the above embodiments of the present invention, when stacking memory cells, the first sacrificial layer stack SB1 , the dummy channel material layer 14 , the second sacrificial layer stack SB2 , and the dummy channel material layer 14 and the third sacrificial layer stack SB3 may be alternately stacked multiple times.

[0084] According to another embodiment of the present invention, the dummy channel material layer 14 may include amorphous silicon or polycrystalline silicon.

[0085] Reference Figure 5 , a hard mask layer pattern 15 may be formed over the stacked structure SB. The hard mask layer pattern 15 may include silicon nitride. The hard mask layer pattern 15 may be formed by an etching process using a mask layer (not shown). The hard mask layer pattern 15 may include a plurality of hole-type openings defined therein. The hard mask layer pattern 15 may be formed using a double patterning process.

[0086] Portions of the stacked structure SB may be etched using the hard mask layer pattern 15 as an etching barrier. Thus, a plurality of sacrificial vertical openings 16' and 17' may be formed in the stacked structure SB. The sacrificial vertical openings 16' and 17' may include a first sacrificial vertical opening 16' and a second sacrificial vertical opening 17'. The first sacrificial vertical opening 16' and the second sacrificial vertical opening 17' may be hole-type openings. The first sacrificial vertical opening 16' and the second sacrificial vertical opening 17' may extend vertically in the first direction D1. From a top view perspective, the cross-sections of the first sacrificial vertical opening 16' and the second sacrificial vertical opening 17' may be square, circular, or elliptical.

[0087] Reference Figure 6 , a portion of the hard mask layer pattern 15 may be trimmed (see reference numeral 18 ).

[0088] Subsequently, the first layer 12A and the third layer 12B may be selectively removed through the first sacrificial vertical opening 16' and the second sacrificial vertical opening 17'. The first layer 12A and the third layer 12B may be selectively removed based on the difference in etching selectivity of the second layer 13 and the dummy channel material layer 14 to the first layer 12A and the third layer 12B. The first layer 12A and the third layer 12B may be removed using a wet etching process or a dry etching process. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 and the dummy channel material layer 14 include a single crystal silicon layer, an etchant or an etchant gas having selectivity relative to the single crystal silicon layer may be used to etch the silicon germanium layer.

[0089] Subsequently, a recess process may be performed to remove the second layer 13. In order to recess the second layer 13, a wet etching process or a dry etching process may be used. According to this embodiment of the present invention, the dummy channel material layer 14 may be partially etched while removing the second layer 13. Therefore, the second layer 13 may be removed, and the dummy channel material layer 14 may be thinned, as shown in the reference numeral "14A". The recess process for forming a thin dummy channel material layer 14, i.e., a dummy channel pattern 14A, may also be referred to as a thinning process or trimming process of the dummy channel material layer 14. In order to form the dummy channel pattern 14A, the top surface, bottom surface, and side surface of the dummy channel material layer 14 may be recessed. The dummy channel pattern 14A may include a single crystal silicon layer. The recess process for forming the dummy channel pattern 14A may use, for example, HSC1 (Hot SC-1). HSC1 may include ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 O) A solution mixed in a ratio of about 1:4:20. The second layer 13 and the dummy channel material layer 14 may be selectively etched using HSC1.

[0090] The dummy channel pattern 14A may be formed by a recess process performed on the dummy channel material layer 14 as described above, and a horizontal recess 18 may be formed between vertically disposed dummy channel patterns 14A. Each of top and bottom surfaces of the dummy channel pattern 14A may include a flat surface.

[0091] From a top view perspective, the dummy channel pattern 14A may have a cross shape. A side surface of the dummy channel pattern 14A may have a curved shape or a rounded shape.

[0092] After forming the dummy channel pattern 14A, the first sacrificial vertical opening and the second sacrificial vertical opening (as shown by reference numerals 16 and 17) may be expanded. The horizontally arranged dummy channel patterns 14A may be spaced apart from each other by the first sacrificial vertical opening 16 and the second sacrificial vertical opening 17. From a top view perspective, the dummy channel pattern 14A may have a shape in which a plurality of cross shapes are merged.

[0093] When forming the dummy channel pattern 14A, the surface of the lower structure 11 may be recessed to a predetermined depth (see reference numeral ' 11A'). Therefore, the depths of the first sacrificial vertical opening 16 and the second sacrificial vertical opening 17 may be increased.

[0094] Reference Figure 7 , a first dielectric layer 20 covering the dummy channel pattern 14A may be formed. The first dielectric layer 20 may include silicon nitride. The first dielectric layer 20 may completely cover the top surface, the bottom surface, and the side surface of the dummy channel pattern 14A.

[0095] When forming the first dielectric layer 20, a dummy dielectric layer 19D may be formed on the surface of the lower structure 11. A portion of the first dielectric layer 20 may completely cover the top, bottom, and side surfaces of the hard mask layer pattern 15.

[0096] Subsequently, a second dielectric layer 21 may be formed over the first dielectric layer 20. The second dielectric layer 21 may fill between vertically adjacent first dielectric layers 20. The second dielectric layer 21 may include silicon oxide. Portions of the second dielectric layer 21 may be conformally formed on the surfaces of the first sacrificial vertical opening 16 and the second sacrificial vertical opening 17. Figure 6 Reference numeral “ 18 ” shown may be filled with the first dielectric layer 20 and the second dielectric layer 21 .

[0097] Subsequently, a sacrificial column 22 may be formed over the second dielectric layer 21 disposed in the first sacrificial vertical opening 16 and the second sacrificial vertical opening 17. The sacrificial column 22 may include amorphous carbon as a sacrificial material. According to another embodiment of the present invention, a column cover layer may also be formed over the sacrificial column 22. The column cover layer may include a metal-based material. The column cover layer may include titanium nitride. Forming the sacrificial column 22 may include depositing a sacrificial material and planarizing the sacrificial material. A planarization process for forming the sacrificial column 22 may be performed until the first dielectric layer 20 of the uppermost level is exposed. Subsequently, the second dielectric layer 21 of the uppermost level may also be planarized until the first dielectric layer 20 of the uppermost level is exposed. The sacrificial column 22 may not be formed between the vertically stacked first dielectric layers 20.

[0098] The second dielectric layer 21 and the sacrificial column 22 may form a first sacrificial column structure SV1 and a second sacrificial column structure SV2 filling the first sacrificial vertical opening 16 and the second sacrificial vertical opening 17. The first sacrificial column structure SV1 may fill the first sacrificial vertical opening 16, and the second sacrificial column structure SV2 may fill the second sacrificial vertical opening 17. According to another embodiment of the present invention, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include a dielectric material, a carbonaceous material, a metal-based material, or a combination thereof. According to another embodiment of the present invention, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. From the perspective of the top view, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be hole-type sacrificial columns. According to another embodiment of the present invention, a portion of the first dielectric layer 20 may be conformally formed on the surface of the first sacrificial vertical opening 16 and the second sacrificial vertical opening 17. As a result, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may also include a portion of the first dielectric layer 20.

[0099] As described above, by forming the dummy channel pattern 14A, the first dielectric layer 20 and the second dielectric layer 21, a unit mold structure can be formed. The unit mold structure may include a plurality of unit molds CM. Each unit mold CM may include a plurality of mold layers. The mold layer may refer to the dummy channel pattern 14A, the first dielectric layer 20 and the second dielectric layer 21. Each unit mold CM may include an ONSN (oxide-nitride-silicon-nitride) stack. Here, the ONSN stack may refer to a structure in which silicon oxide, a first silicon nitride, a single crystal silicon layer and a second silicon nitride are stacked in sequence. Silicon oxide may correspond to the second dielectric layer 21, the first silicon nitride and the second silicon nitride may correspond to the first dielectric layer 20, and the single crystal silicon layer may correspond to the dummy channel pattern 14A. A unit mold structure including a plurality of unit molds CM may also be referred to as a vertical stack. From another perspective, the unit mold structure may include an ONSNNO (oxide-nitride-silicon-nitride-oxide) stack. Here, the ONSNO stack may refer to a structure in which a first silicon oxide, a first silicon nitride, a single crystal silicon layer, a second silicon nitride, and a second silicon oxide are sequentially stacked.

[0100] As mentioned above, through Figures 4 to 7 In the series of processes shown, the sub-stack of the stack structure SB can be replaced by a unit mold. The first layer 12A, the second layer 13 and the third layer 12B can be replaced by the first dielectric layer 20 and the second dielectric layer 21. The dummy channel material layer 14 can be changed into a dummy channel pattern 14A through a recess process. The first dielectric layer 20 can also be referred to as a trimming target layer.

[0101] Reference Figure 8 , the hard mask layer pattern 15 and the uppermost-level first dielectric layer 20 may be removed to form a hard mask level recess 23 ′.

[0102] Reference Fig. 9 , a top dielectric layer 23 may be formed to fill the hard mask level recess 23'. The top dielectric layer 23 may include silicon oxide.

[0103] Reference Fig.10 , the initial hole-type vertical opening 24 may be formed by removing the first sacrificial post structure SV1. To form the initial hole-type vertical opening 24, the second dielectric layer 21 and the sacrificial post 22 of the first sacrificial post structure SV1 may be selectively etched.

[0104] Subsequently, the second dielectric layer 21 may be horizontally recessed. Subsequently, the first dielectric layer 20 may be horizontally recessed. The recessed amount of the first dielectric layer 20 may be greater than the recessed amount of the second dielectric layer 21.

[0105] The first dielectric level recess 20R may be formed by a recess process of the first dielectric layer 20 , and may expose a portion of the dummy channel pattern 14A.

[0106] Reference Fig.11 , a first vertical sacrificial structure 25 may be formed to fill the first dielectric level recess 20R and the initial hole-type vertical opening 24. The first vertical sacrificial structure 25 may include a dielectric material. The first vertical sacrificial structure 25 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. Each first vertical sacrificial structure 25 may include a body portion 25A filling the initial hole-type vertical opening 24 and an extension portion 25B filling the first dielectric level recess 20R.

[0107] Reference Fig.12 In order to form the vertical level path 26 , the sacrificial pillar 22 of the second sacrificial pillar structure SV2 may be removed.

[0108] Subsequently, the dummy dielectric layer 20D below the vertical level path 26 may be removed to form a lower level gap 20D′.

[0109] Reference Fig.13 , the second dielectric layer 21 may be cut 27 to form a first hole-type vertical opening 28 .

[0110] Subsequently, a first passivation layer BF1 and a second passivation layer BF2 may be formed to fill the lower gap 20D'. The first passivation layer BF1 may include silicon oxide. Forming the first passivation layer BF1 may include depositing silicon oxide to fill the lower gap 20D' and etching the silicon oxide. The surface of the lower structure 11 may be oxidized to form a second passivation layer BF2.

[0111] Reference Fig.14 , the first dielectric layer 20 may be removed through the first hole-type vertical opening 28 to form a horizontal level recess 29 and expose a portion (first edge) of the dummy channel pattern 14A. Therefore, each dummy channel pattern 14A may be partially exposed through two adjacent horizontal level recesses 29.

[0112] Reference Fig.15 , an interlayer dielectric layer 30 may be formed over the exposed portion of the dummy channel pattern 14A. The interlayer dielectric layer 30 may be formed by oxidizing the surface of the dummy channel pattern 14A. According to another embodiment of the present invention, the interlayer dielectric layer 30 may be formed by a silicon oxide deposition process.

[0113] The interlayer dielectric layer 30 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material or a combination thereof. The interlayer dielectric layer 30 may include SiO 2 、Si 3 N 4 , HfO 2 、Al 2 O 3 、ZrO 2, AlON, HfON, HfSiO, HfSiON or a combination thereof.

[0114] The interlayer dielectric layer 30 may be formed by a thermal oxidation process. For example, the interlayer dielectric layer 30 may be formed by oxidizing the surface of the dummy channel pattern 14A. Thus, since the interlayer dielectric layer 30 is formed by a thermal oxidation process, a high-quality interlayer dielectric layer 30 may be obtained. Silicon oxide produced by a thermal oxidation process may have better quality than silicon oxide produced by a deposition process.

[0115] Subsequently, a horizontal conductive line 31 filling the horizontal level recess 29 may be formed above the interlayer dielectric layer 30. Forming the horizontal conductive line 31 may include depositing a conductive material filling the horizontal level recess 29 above the interlayer dielectric layer 30 and etching back the conductive material. The horizontal conductive line 31 may include a pair of first-layer horizontal conductive lines 31A and second-layer horizontal conductive lines 31B facing each other and having a dummy channel pattern 14A disposed therebetween. The first horizontal conductive line 31A and the second horizontal conductive line 31B may include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal conductive line 31A and the second horizontal conductive line 31B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal conductive line 31A and the second horizontal conductive line 31B may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal conductive line 31A and the second horizontal conductive line 31B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or more. Reference Figures 1A to 1C Each of the first horizontal conductive line 31A and the second horizontal conductive line 31B may have a cross shape and may include a channel overlap portion WLP. The horizontal conductive line 31 may correspond to Figures 1A to 3B The first horizontal wire 31A and the second horizontal wire 31B may correspond to the second wire DWL shown in FIG. Figures 1A to 3B An upper horizontal line G1 and a lower horizontal line G2 are shown.

[0116] As described above, after forming the dummy channel material layer 14 and the dummy channel pattern 14A, a process of forming the interlayer dielectric layer 30 and a process of forming the horizontal conductive line 31 may be performed. The process of forming the interlayer dielectric layer 30 and the process of forming the horizontal conductive line 31 may be performed at a relatively higher temperature than the process of forming the dummy channel material layer 14 and the dummy channel pattern 14A.

[0117] Reference Fig.16 , a second vertical sacrificial structure 32 may be formed on a first side of the horizontal conductive line 31 to fill the first hole-type vertical opening 28. The second vertical sacrificial structure 32 may include a dielectric material. The second vertical sacrificial structure 32 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0118] Reference Fig.17 , the second hole-type vertical opening 33 may be formed by removing the body portion 25A of the first vertical sacrificial structure 25. Subsequently, a third passivation layer BF3 may be formed on the surface of the lower structure 11. The third passivation layer BF3 may include silicon oxide.

[0119] Subsequently, the extended portion 25B of the first vertical sacrificial structure 25 and the dummy channel pattern 14A may be horizontally trimmed from the second hole-type vertical opening 33 to form a storage opening 34. The extended portion 25B of the first vertical sacrificial structure 25 remaining after forming the storage opening 34 may be referred to as a "first cover layer 35", and the remaining dummy channel pattern 14A may be referred to as a "dummy channel layer 14B". From a top view perspective, the dummy channel layer 14B may have a cross shape. The dummy channel layer 14B may be formed by a process of trimming the dummy channel pattern 14A. The first cover layer 35 may be formed by a process of trimming the extended portion 25B of the first vertical sacrificial structure 25.

[0120] According to some embodiments of the present invention, after horizontally trimming the dummy channel pattern 14A, the expansion portion 25B of the first vertical sacrificial structure 25 may be trimmed.

[0121] The storage opening 34 may also be referred to as a capacitor opening.

[0122] The storage opening 34 may be disposed between the second dielectric layers 21. The first capping layers 35 may be disposed in lower and upper portions of the dummy channel layer 14B, respectively.

[0123] Reference Fig.18 The first contact node 36 may be formed above the first edge of the dummy channel layer 14B. The first contact node 36 may include a metal-based material, doped polysilicon, or a combination thereof. The first contact node 36 may include TiN, IZO, ITO, or a combination thereof.

[0124] Subsequently, the first electrodes 37 of the data storage element may be formed over the first contact nodes 36. The first electrodes 37 may have a horizontally oriented cylindrical shape. The first electrodes 37 may be disposed in the storage openings 34, respectively.

[0125] Reference Fig.19 , the second dielectric layer 21 may be horizontally recessed (see reference numeral "38"). As a result, the outer wall of the first electrode 37 may be exposed. The recessed second dielectric layer 21 may correspond to Figure 3B The inter-cell dielectric layer IL is shown.

[0126] Then, refer to Fig. 20, a dielectric layer 39 and a second electrode 40 may be sequentially formed over the first electrode 37. The first electrode 37, the dielectric layer 39, and the second electrode 40 may become a data storage element CAP.

[0127] The first electrode 37 may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode 37 may include a plurality of inner surfaces. The outer surface of the first electrode 37 may include a vertical outer surface and a plurality of horizontal outer surfaces. The inner space of the first electrode 37 may be a three-dimensional space. The dielectric layer 39 may conformally cover the inner and outer surfaces of the first electrode 37. The second electrode 40 may be disposed in the inner space of the first electrode 37 above the dielectric layer 39. A portion of the outer surface of the first electrode 37 may be coupled to the dummy channel layer 14B.

[0128] The first electrode 37 may have a cylindrical shape. The cylindrical shape of the first electrode 37 may include a cylindrical inner surface and a cylindrical outer surface. The dielectric layer 39 and the second electrode 40 may be disposed over the cylindrical inner surface of the first electrode 37 .

[0129] The first electrode 37 and the second electrode 40 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 37 and the second electrode 40 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium (Ir), iridium oxide (IrO 2 ), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack or a combination thereof. The second electrode 40 may include a combination of a metal-based material and a silicon-based material. For example, the second electrode 40 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap filling material filling the inner space of the first electrode 37, titanium nitride (TiN) may be used as the second electrode 40 of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0130] The dielectric layer 39 may also be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 39 may include silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The dielectric layer 39 may include hafnium oxide (HfO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO2 ), Tantalum Oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ) or strontium titanate (SrTiO 3 ). The dielectric layer 39 may include ZA (ZrO 2 / Al 2 O 3 ) stack, ZAZ(ZrO 2 / Al 2 O 3 / ZrO 2 ) stack, ZAZA(ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ) stack, ZAZAZ(ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 / ZrO 2 ) stacking, HA(HfO 2 / Al 2 O 3 ) stack, HAH(HfO 2 / Al 2 O 3 / HfO 2 ) stacking, HAHA(HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) stack, or HAHAH(HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ) stack.

[0131] According to another embodiment of the present invention, an interface control layer for improving leakage current may also be formed between the first electrode 37 and the dielectric layer 39. The interface control layer may include titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5An interface control layer may be formed between the second electrode 40 and the dielectric layer 39.

[0132] As described above, after forming the dummy channel material layer 14 and the dummy channel pattern 14A, a process of forming the interlayer dielectric layer 30, a process of forming the horizontal conductive line 31, and a process of forming the data storage element CAP may be performed. The process of forming the interlayer dielectric layer 30, the process of forming the horizontal conductive line 31, and the process of forming the data storage element CAP may be performed at a relatively higher temperature than the process of forming the dummy channel material layer 14 and the dummy channel pattern 14A.

[0133] Reference Fig.21 , the second vertical sacrificial structure 32 may be etched to form a second hole-type vertical opening 41. A portion of the second vertical sacrificial structure 32 may remain on the first side of the horizontal conductive line 31. Hereinafter, the remaining portion of the second vertical sacrificial structure 32 may be referred to as a second capping layer 42. The second capping layer 42 may include silicon oxide, silicon nitride, or a combination thereof.

[0134] When or after forming the second capping layer 42 , a portion of the interlayer dielectric layer 30 may be removed to expose a second edge of each dummy channel layer 14B adjacent to the second hole-type vertical opening 41 .

[0135] Reference Fig. 22 , a channel-level gap 43 may be formed by removing the dummy channel layer 14B. Each channel-level gap 43 may be disposed between each pair of first horizontal conductive lines 31A and second horizontal conductive lines 31B, wherein the interlayer dielectric layer 30 is disposed on an upper surface (i.e., top surface) and a lower surface (i.e., bottom surface) of each channel-level gap 43. When the dummy channel layer 14B is removed, the interlayer dielectric layer 30, the first capping layer 35, and the first contact node 36 may serve as an etching barrier.

[0136] Reference Fig.23 , the channel material layer 44A may be conformally formed to cover the wall of the second hole-type vertical opening 41 and formed above the channel-level gap 43, and may fill the channel-level gap 43. The channel material layer 44A may include an oxide semiconductor material, such as IGZO. The channel material layer 44A may be a deposited channel material. The channel material layer 44A may be deposited by an atomic layer deposition (ALD) method.

[0137] Reference Fig.24 The channel layer 44 may be formed by selectively etching the channel material layer 44A to remove the channel material layer 44A from the inside of the second hole-type vertical opening 41 and to remain only inside the channel-level gap 43. Therefore, the channel layer 44 may be disposed inside the channel-level gap 43.

[0138] The channel layer 44 may also be referred to as a replacement channel. The process of forming the replacement channel may include forming the dummy channel layer 14B, forming the channel-level gap 43 by removing the dummy channel layer 14B, and forming the channel layer 44 in the channel-level gap 43.

[0139] Figure 22 to Figure 24 The series of processes shown may be simply referred to as “channel layer 44 replacement process”, which replaces the dummy channel layer 14B with the channel layer 44 .

[0140] Reference Fig.25 , vertical wires 46 commonly coupled to the channel layer 44 may be formed inside the second hole-type vertical opening 41. Each vertical wire 46 may fill a corresponding second hole-type vertical opening 41. The vertical wire 46 may include titanium nitride, tungsten, or a combination thereof. The vertical wire 46 may include a bit line. The vertical wire 46 may correspond to Figures 1A to 3B The first wire BL is shown.

[0141] Before forming the vertical conductive line 46, a second contact node 45 may be formed. The second contact node 45 may be conformally formed inside each second hole-type vertical opening 41, and thus may cover the side surface and bottom surface of the vertical conductive line 46. The second contact node 45 may include a metal-based material or a semiconductor material. The second contact node 45 may include doped polysilicon. The second contact node 45 may include TiN, IZO, ITO, or a combination thereof.

[0142] Figure 26 to Figure 28 A method for manufacturing a semiconductor device according to another embodiment of the present invention is shown.

[0143] First, you can execute Figures 4 to 22 A series of processes shown.

[0144] In the formation Fig. 22 After the channel level gap 43 is formed, a channel material layer 44A may be conformally formed, as shown in FIG. Fig.26 As shown. Therefore, the channel material layer 44A may be conformally formed inside each channel-level gap 43. The channel material layer 44A may only partially fill each channel-level gap 43. The channel material layer 44A may include an oxide semiconductor material, such as IGZO.

[0145] An inner gap filling layer 44' filling the remaining portion of the channel level gap 43 may be formed over the channel material layer 44A. The inner gap filling layer 44' may include a dielectric material. Forming the inner gap filling layer 44' may include forming an inner gap filling material over the channel material layer 44A and etching the inner gap filling material.

[0146] Reference Fig. 27, the channel material layer 44A may be etched using the inner gap filling layer 44' as a barrier. As a result, the channel layer 44 may be formed. The cross section of each channel layer 44 may have a cup shape, wherein the inner gap filling layer 44' is disposed in the inner space of the channel layer 44. From the perspective of the top view, as shown Figure 1C As shown, the channel layer 44 may have a cross shape.

[0147] Reference Fig.28 , a second contact node 45 and a vertical conductive line 46 may be formed.

[0148] According to the above-described embodiment of the present invention, the process of forming the dummy channel pattern 14A, the high temperature process, and the replacement process of the channel layer 44 can be sequentially performed to prevent thermal degradation of the channel. In addition, since the interlayer dielectric layer 30 is formed by the thermal oxidation process, the quality of the interlayer dielectric layer 30 can be improved.

[0149] according to Figures 4 to 28 , a method for manufacturing a semiconductor device may include: forming a unit mold including a dummy channel pattern 14A above a lower structure 11; forming a horizontal conductive line 31 crossing the dummy channel pattern 14A; forming a dummy channel layer 14B by trimming the dummy channel pattern 14A; forming a data storage element CAP coupled to a first side of the dummy channel layer 14B; replacing the dummy channel layer 14B with a channel layer 44; and forming a vertical conductive line 46 coupled to a second side of the channel layer 44.

[0150] Reference Figures 4 to 28 , a method for forming a switching element may include: forming a unit mold CM, the unit mold CM including a dummy channel pattern 14A above a lower structure 11 and a dielectric layer disposed in an upper portion and a lower portion of the dummy channel pattern 14A; replacing the dielectric layer with a horizontal conductive line 31; forming a dummy channel layer 14B by trimming the dummy channel pattern 14A; and replacing the dummy channel layer 14B with a channel layer 44.

[0151] FIG. 29A to FIG. 29C is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0152] Reference Fig.29A The stacked structure SB10 may be formed above the lower structure 11. The stacked structure SB10 may include an alternating stack of a first semiconductor layer and a second semiconductor layer. For example, the alternating stack may include a plurality of silicon germanium layers 12 and a plurality of single crystal silicon layers 14' alternately stacked by epitaxial growth. The silicon germanium layer 12 may be a sacrificial layer, and the single crystal silicon layer 14' may be a recessed target layer. The silicon germanium layer 12 may correspond to Figure 4 The first layer 12A or the third layer 12B, and the single crystal silicon layer 14 'may correspond to Figure 4The dummy channel material layer 14. Figure 4 Different from the stack structure SB of FIG. 1 , the stack structure SB10 may be formed by alternating stacks of silicon germanium layers 12 and single crystal silicon layers 14 ′.

[0153] Reference Fig.29B , a hard mask layer pattern 15 may be formed over the stacked structure SB10.

[0154] Subsequently, the stack structure SB10 may be etched using the hard mask layer pattern 15 as an etch barrier. As a result, a plurality of first sacrificial vertical openings 16 ′ and second sacrificial vertical openings 17 ′ may be formed in the stack structure SB10 .

[0155] Reference Fig.29C , a dummy channel pattern 14A' and a horizontal recess 19 may be formed. The dummy channel pattern 14A' and the horizontal recess 19 may be formed by Fig.29B Specifically, the silicon germanium layer 12 may be removed first, and after the silicon germanium layer 12 is removed, a recess process of the single crystal silicon layer 14' may be performed to thin the single crystal silicon layer 14' and form a thinner preliminary horizontal layer 14A'. The preliminary horizontal layer 14A' may correspond to Figure 6 The dummy channel pattern 14A.

[0156] A wet etching process or a dry etching process may be used to recess the silicon germanium layer 12. The silicon germanium layer 12 may be etched using an etchant or an etching gas having selectivity with respect to the single crystal silicon layer 14'.

[0157] The recessing process for forming the single crystal silicon layer 14' of the dummy channel pattern 14A' may use, for example, HSC1 (HotSC-1). HSC1 may include ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 O) A solution mixed in a ratio of about 1:4:20. The single crystal silicon layer 14' can be selectively etched using HSC1.

[0158] After forming the dummy channel pattern 14A', the first sacrificial vertical opening and the second sacrificial vertical opening (as shown in reference numerals "16" and "17") may be expanded. When forming the dummy channel pattern 14A', the surface of the lower structure 11 may be recessed to a certain depth (see reference numeral "11A"). As a result, the depths of the first sacrificial vertical opening 16 and the second sacrificial vertical opening 17 may be increased.

[0159] Then, you can execute Figures 7 to 25 A series of processes shown.

[0160] Figure 30 to Figure 32 1 is a perspective view showing a memory cell array according to another embodiment of the present invention. The memory cell arrays MCA100, MCA200 and MCA300 may be connected to Figure 3A The memory cell array MCA is similar to the memory cell array MCA. Figure 3A A detailed description of the constituent elements also appears in.

[0161] Reference Fig.30 , the memory cell array MCA100 may include a plurality of memory cells MC10.

[0162] The memory cell array MCA100 may include a three-dimensional array of memory cells MC10. The three-dimensional array of memory cells MC10 may include a column array of memory cells MC10 and a row array of memory cells MC10. The column array of memory cells MC10 may include a plurality of memory cells MC10 stacked in a first direction D1. The row array of memory cells MC10 may include a plurality of memory cells MC10 horizontally arranged in a second direction D2 and a third direction D3.

[0163] Each memory cell MC10 may include a first conductive line BL, a switching element TR, and a data storage element CAP. The detailed description of the first conductive line BL and the data storage element CAP may also refer to the above embodiments.

[0164] The switching element TR may include a horizontal layer HL and a second conductive line DWL. The horizontal layer HL may extend in the second direction D2. The second conductive line DWL may extend in the third direction D3.

[0165] The second conductive line DWL may have a double structure. For example, the second conductive line DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other with the horizontal layer HL interposed therebetween. Figure 3B As shown, the interlayer dielectric layer GD may be formed in the upper and lower surfaces of the horizontal layer HL.

[0166] Each of the upper horizontal line G1 and the lower horizontal line G2 may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may refer to vertical sidewalls. The flat sidewalls FS may have a line shape extending in the third direction D3.

[0167] Reference Fig.31 , the memory cell array MCA200 may include a plurality of memory cells MC20.

[0168] The memory cell array MCA200 may include a three-dimensional array of memory cells MC20. The three-dimensional array of memory cells MC20 may include a column array of memory cells MC20 and a row array of memory cells MC20. The column array of memory cells MC20 may include a plurality of memory cells MC20 stacked in a first direction D1. The row array of memory cells MC20 may include a plurality of memory cells MC20 horizontally arranged in a second direction D2 and a third direction D3.

[0169] Each memory cell MC20 may include a first conductive line BL, a switching element TR, and a data storage element CAP. The detailed description of the first conductive line BL and the data storage element CAP may also refer to the above embodiments.

[0170] The switching element TR may include a horizontal layer HL and a second conductive line SWL. The horizontal layer HL may extend in the second direction D2. The second conductive line SWL may extend in the third direction D3.

[0171] The second conductive line SWL may have a single structure. For example, the second conductive line SWL may be disposed above the horizontal layer HL. Figure 3B , an interlayer dielectric layer GD may be formed between the upper surface of the horizontal layer HL and the second conductive line SWL. According to another embodiment of the present invention, the second conductive line SWL may be disposed below the horizontal layer HL.

[0172] The second conductive line SWL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may refer to vertical sidewalls.

[0173] According to another embodiment of the present invention, the second conductive line SWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. Figure 1C shown.

[0174] Reference Fig.32 , the memory cell array MCA300 may include a plurality of memory cells MC30.

[0175] The memory cell array MCA300 may include a three-dimensional array of memory cells MC30. The three-dimensional array of memory cells MC30 may include a column array of memory cells MC30 and a row array of memory cells MC30. The column array of memory cells MC30 may include a plurality of memory cells MC30 stacked in a first direction D1. The row array of memory cells MC30 may include a plurality of memory cells MC30 horizontally arranged in a second direction D2 and a third direction D3.

[0176] Each memory cell MC30 may include a first conductive line BL, a switching element TR, and a data storage element CAP. The detailed description of the first conductive line BL and the data storage element CAP may also refer to the above embodiments.

[0177] The switching element TR may include a horizontal layer HL and a second conductive line GAA-WL. The horizontal layer HL may extend in the second direction D2. The second conductive line GAA-WL may extend in the third direction D3.

[0178] The second conductive line GAA-WL may have a fully surrounding gate structure GAA. For example, the second conductive line GAA-WL may extend in the third direction D3 while surrounding the horizontal layer HL. An interlayer dielectric layer GD may be formed between the horizontal layer HL and the second conductive line GAA-WL. The interlayer dielectric layer GD may surround each horizontal layer HL.

[0179] The second conductive line GAA-WL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may refer to vertical sidewalls.

[0180] According to an embodiment of the present invention, each memory cell may include a first wire BL extending horizontally in a third direction D3, a second wire DWL extending vertically in a first direction D1, and a horizontal layer HL extending horizontally in a second direction D2. The second wire DWL may have a double structure. In an embodiment, the second wire DWL may be replaced by a single structure or a full surround gate structure.

[0181] According to an embodiment of the present invention, since a high temperature process is performed before a channel layer replacement process, degradation of a channel layer that may be caused by a thermal process may be prevented.

[0182] According to the embodiment of the present invention, since the gate dielectric layer is formed by a thermal oxidation process, the quality of the gate dielectric layer can be improved.

[0183] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a unit mold including a dummy channel pattern and a plurality of mold layers over the lower structure; forming a horizontal conductive line intersecting the dummy channel pattern; forming a dummy channel layer by trimming the dummy channel pattern; forming a data storage element coupled to a first side of the dummy channel layer; replacing the dummy channel layer with a channel layer; as well as A vertical conductive line is formed coupled to the second side of the channel layer.

2. The method according to claim 1, wherein: Replacing the dummy channel layer with the channel layer includes: forming a channel-level gap by removing the dummy channel layer; forming a channel material layer over the channel level gap; and The channel layer is formed by selectively removing the channel material layer.

3. The method according to claim 2, wherein: The dummy channel pattern and the dummy channel layer include a silicon material, and The channel layer includes an oxide semiconductor material.

4. The method according to claim 1, further comprising: Before forming the horizontal conductive line intersecting the dummy channel pattern, A gate dielectric layer is formed on top and bottom surfaces of the dummy channel pattern, respectively.

5. The method according to claim 4, wherein: Forming the gate dielectric layer comprises: The top surface and the bottom surface of the dummy channel pattern are exposed to a thermal oxidation process.

6. The method according to claim 1, wherein: Forming the horizontal conductive line intersecting the dummy channel pattern comprises: forming a horizontal level recess intersecting the dummy channel pattern by removing the mold layer of the unit mold; forming a conductive material over the horizontal level recess; and The horizontal conductive lines are formed by selectively etching the conductive material.

7. The method according to claim 1, wherein: Forming the unit mold including the dummy channel pattern includes: forming the dummy channel pattern above the lower structure; forming a first unit dielectric layer surrounding the dummy channel pattern; and A second unit dielectric layer is formed surrounding the first unit dielectric layer.

8. The method according to claim 7, wherein: The first unit dielectric layer includes silicon nitride, and The second unit dielectric layer includes silicon oxide.

9. The method according to claim 1, wherein: Forming the unit mold including the dummy channel pattern includes: forming a stacked structure, the stacked structure comprising a dummy channel material layer above the lower structure and sacrificial layers respectively disposed on a top surface and a bottom surface of the dummy channel material layer; forming an opening by etching a portion of the stacked structure; removing the sacrificial layer through the opening; and The dummy channel pattern is formed by thinning the dummy channel material layer through the opening.

10. The method according to claim 9, wherein: The sacrificial layer includes a silicon layer, a silicon germanium layer or a combination thereof.

11. The method according to claim 1, wherein: The dummy channel pattern includes a silicon material, and The channel layer includes an oxide semiconductor material.

12. The method according to claim 1, wherein: Replacing the dummy channel layer with the channel layer includes: forming a channel-level gap by removing the dummy channel layer; conformally forming a channel material layer over the channel level gap; forming an inner gap-filling layer over the channel material layer; and The channel layer is formed by selectively removing the channel material layer.

13. The method according to claim 12, wherein: The channel material layer includes an oxide semiconductor material, and The inner gap-fill layer includes a dielectric material.

14. A method for manufacturing a semiconductor device, the method comprising: forming a unit mold including a dummy channel pattern located above a lower structure and a pair of unit dielectric layers disposed in upper and lower portions of the dummy channel pattern; forming a pair of horizontal-level recesses by recessing the pair of cell dielectric layers, the pair of horizontal-level recesses exposing top and bottom surfaces of the dummy channel pattern; forming a gate dielectric layer on the exposed top and bottom surfaces of the dummy channel pattern; forming a first horizontal conductive line and a second horizontal conductive line filling the pair of horizontal level recesses over the gate dielectric layer; forming a dummy channel layer by trimming the dummy channel pattern; forming a channel-level gap between the first horizontal conductive line and the second horizontal conductive line by removing the dummy channel layer; and A channel layer is formed in the channel-level gap.

15. The method according to claim 14, wherein: The dummy channel layer includes silicon material, and The channel layer includes an oxide semiconductor material.

16. The method according to claim 14, wherein: Forming the gate dielectric layer comprises: The exposed top and bottom surfaces of the dummy channel pattern are exposed to a thermal oxidation process.

17. The method according to claim 14, wherein: Forming the channel layer includes: forming a channel material layer filling the channel level gap; and The channel layer is formed by selectively removing the channel material layer.

18. The method according to claim 14, wherein: Forming the channel layer includes: conformally forming a channel material layer over the channel level gap; forming an inner gap-filling layer over the channel material layer; and The channel layer is formed by selectively removing the channel material layer.

19. The method according to claim 14, further comprising: After forming the dummy channel layer, a data storage element coupled to the dummy channel layer is formed.

20. The method of claim 14, further comprising: After forming the channel layer, a vertical conductive line coupled to the channel layer is formed.

21. A semiconductor device comprising: Lower structure; a horizontal layer disposed above the lower structure; horizontal conductors, which are respectively arranged in the upper part and the lower part of the horizontal layer; a gate dielectric layer located between the horizontal conductive line and the horizontal layer; a vertical conductive line coupled to the first side of the horizontal layer; as well as a data storage element coupled to the second side of the horizontal layer, Wherein, the horizontal layer includes: a channel layer having an inner space; and The inner gap-filling layer fills the inner space of the channel layer.

22. The semiconductor device according to claim 21, wherein The channel layer has a horizontally oriented cup shape.

23. The semiconductor device according to claim 21, wherein The channel layer includes an oxide semiconductor material.

24. The semiconductor device according to claim 21, wherein The gate dielectric layer includes an oxide of a silicon material.

25. The semiconductor device according to claim 21, further comprising: a first contact node located between the horizontal layer and the data storage element; as well as The second contact node is located between the horizontal layer and the vertical conductive line.

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