Method of erasing flash memory cells

Abstract

The present disclosure provides an erase method for a flash memory cell. The flash memory cell includes a storage transistor and a select transistor connected in series. The erase method according to the present disclosure includes applying erase voltages to each electrode of the flash memory cell and a gate electrode of each transistor, wherein the erase voltage applied to the gate electrode of the storage transistor to be erased is lower than a second power supply voltage, so that a channel hot electron induced hot hole injection physical effect occurs to attract hot holes in the channel into a storage medium layer to achieve erasing. The erase method for the flash memory cell according to the present disclosure has a wider hole distribution and a higher injection efficiency than the existing band-to-band hot hole (BBHH) erase method, so that the erase method according to the present disclosure has a higher erase speed, a larger erase window, less hot carrier damage, a lower leakage current, and a higher endurance reliability.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, the present disclosure relates to an erase method of a flash memory cell. BACKGROUND

[0002] Flash memory, abbreviated as flash, is a kind of non-volatile memory, i.e. the stored data will not be lost in the case of power off, which is particularly suitable for mobile communication and computer storage components and other fields. In addition, some flash memories also have high-density storage capacity, which are suitable for applications in large-capacity mobile storage media and other aspects.

[0003] The conventional flash memory adopts a floating gate type cell structure. The floating gate type non-volatile memory originates from the MIMIS (Metal-Insulator-Metal-Insulator-Semiconductor) structure proposed by D. Kahng and S. Sze in 1967. The structure increases a metal floating gate and an ultra-thin tunneling oxide layer on the basis of the conventional MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), so as to store charges by using the metal floating gate. Based on this, Masuoka et al. first proposed the concept of flash memory in 1984, i.e. to realize high-speed erasing ability by erasing by blocks and writing (programming) by bits, and to eliminate the necessary selection tube in EEPROM (Erasable Programmable Read-only memory), so as to have smaller storage cell size. After the emergence of flash memory, it has been rapidly developed due to its high write speed, high integration and superior performance. Intel Corporation proposed an ETOX structure flash memory cell (ETOX: Electron Tunneling Oxide device) in 1988, which has become the basis for the development of most floating gate type flash memory cell structures to date.

[0004] However, the floating gate type flash memory has the following disadvantages: the process is relatively complex; the existence of the floating gate structure in the flash memory cell increases the vertical height of the gate structure, which is not conducive to the scaling of the process size and the cell area; and because of the conductivity of the floating gate, the stored charge can move freely in the floating gate, which is not conducive to improving the reliability of the memory. To solve the problems of process complexity and poor reliability of the floating gate type flash memory, researchers have proposed a charge trapping type memory (CTM: Charge-Trapping-Memory) that uses a silicon nitride medium to store charge, also known as a SONOS type (Silicon-Oxide-Nitride-Oxide-Silicon: silicon-oxide-nitride-oxide-silicon) flash memory. Based on this, B. Eitan et al. proposed a two-bit memory cell structure NROM (Nitride-Read-Only-Memory: Nitride Read-Only Memory) in 2000, which uses the non-conductive characteristics of the insulating silicon nitride storage medium to realize two storage bits at the source end and the drain end of a storage transistor, respectively. However, this cell structure has the disadvantages of mutual interference between the two storage bits, and the device size cannot be reduced. On the other hand, the existing SONOS type flash memory cell generally uses channel hot electron injection (CHE) physical effect for writing operation, and uses band-to-band hot hole injection (BBHH) physical effect or FN tunneling physical effect for erasing operation. Due to the different physical mechanisms used for writing and erasing, the distribution of trap electron charges injected by writing operation and the distribution of trap hole charges injected by erasing operation are inconsistent, i.e. trap charge mismatch effect (TCME) is easy to occur, which leads to the degradation of the endurance and retention reliability of the flash memory cell.

[0005] However, the existing floating gate type ETOX flash memory and SONOS type NROM flash memory both have the problems of unable to reduce the process size, large cell area, high writing power consumption, and large array area overhead, and cannot realize high-density integration of gigabit (Gb) capacity or above.

[0006] With the rapid development of mobile intelligent terminals, wearable devices, intelligent sensor networks and other applications, higher requirements are put forward for the power consumption, storage capacity and cost of flash memory, and therefore a flash memory technology with low power consumption, small cell area, scalable process size, high array integration density, large capacity and other advantages is needed. SUMMARY

[0007] The above information disclosed in the background section of the present disclosure is only for understanding the background of the inventive concept, and therefore it can contain information that does not constitute the prior art.

[0008] To solve the above problems existing in the prior art, the present disclosure proposes an erasing method for a flash memory cell.

[0009] According to an aspect of the disclosure, there is provided an erase method of a flash memory cell including a substrate and a well region disposed in the substrate, a memory transistor disposed on the well region and configured to store data, and a pass transistor disposed on the well region at one side of the memory transistor in a horizontal direction and configured to perform a pass operation for the memory transistor, wherein the pass transistor and the memory transistor are connected in series, wherein a source region of the memory transistor is connected to a first electrode of the flash memory cell, a drain region of the pass transistor is connected to a second electrode of the flash memory cell, the erase method including performing an erase operation for the memory transistor by applying a second power voltage to the well region, applying a first erase voltage to the first electrode, applying a second erase voltage to the second electrode, applying a third erase voltage to a gate electrode of the memory transistor, and applying a fourth erase voltage to a gate electrode of the pass transistor, wherein the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power voltage, the third erase voltage is equal to or lower than the second power voltage, and the fourth erase voltage is equal to or lower than a first power voltage, wherein the first power voltage is higher than the second power voltage, wherein the preset voltage is previously set according to a carrier barrier height at an interface between the substrate and a gate dielectric stack of the memory transistor, and wherein the first erase voltage and the fourth erase voltage are higher than the second erase voltage so that both the memory transistor and the pass transistor are turned on.

[0010] According to another aspect of the present disclosure, there is provided an erase method of a flash memory cell including a substrate and a well region disposed within the substrate; a first storage transistor disposed on the well region and configured to store first data; a second storage transistor disposed on the well region and configured to store second data; and a gate-on transistor disposed between the first storage transistor and the second storage transistor in a horizontal direction on the well region, configured to isolate and perform a gate-on operation on the first storage transistor and the second storage transistor, wherein the first storage transistor, the gate-on transistor, and the second storage transistor are connected in series, wherein a source region of the first storage transistor is connected to a first electrode of the flash memory cell, a drain region of the second storage transistor is connected to a second electrode of the flash memory cell, the erase method including: performing an erase operation on the first storage transistor or the second storage transistor by applying a second power voltage to the well region, applying a first erase voltage to the first electrode or the second electrode, applying a second erase voltage to the second electrode or the first electrode, applying a third erase voltage to a gate electrode of the first storage transistor or the second storage transistor, applying a fourth erase voltage to a gate electrode of the gate-on transistor, and applying a fifth erase voltage to a gate electrode of the second storage transistor or the first storage transistor, wherein the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power voltage, the third erase voltage is equal to or lower than the second power voltage, and the fourth erase voltage is equal to or lower than a first power voltage, wherein the first power voltage is higher than the second power voltage, wherein the preset voltage is previously set according to a carrier barrier height at an interface between the substrate and a gate medium stack of the first storage transistor and the second storage transistor, and wherein the first erase voltage, the fourth erase voltage, and the fifth erase voltage are higher than the second erase voltage, such that the first storage transistor, the second storage transistor, and the gate-on transistor are all turned on.

[0011] According to the erase method of the present disclosure, the erase voltage applied to the gate electrode of the storage transistor being erased is lower than the second power voltage, thereby inducing a channel hot electron induced hot hole injection physical effect to attract hot holes in the channel into the storage medium layer to achieve erasing, such that there is a wider hole distribution and higher injection efficiency compared to the existing band-to-band tunneling hot hole (BBHH) erase method, and thus the erase method according to the present disclosure has a higher erase speed (tens of microseconds), a larger erase window, less hot carrier damage, lower leakage current, and higher endurance reliability.

[0012] However, the effects of the present disclosure are not limited to the above-mentioned effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that the foregoing General Description and the following Detailed Description are exemplary and explanatory, and are intended to provide further explanation of the claimed present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the inventive concepts.

[0014] Figure 1 A cross-sectional view of a flash memory cell according to an embodiment of the present disclosure is shown.

[0015] Figure 2 An equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure is shown.

[0016] Figure 3 A schematic diagram showing an erase operation performed on a first storage transistor by an erase method according to an embodiment of the present disclosure is shown.

[0017] Figure 4 A schematic diagram showing an erase operation performed on a second storage transistor by an erase method according to an embodiment of the present disclosure is shown.

[0018] Figure 5 A cross-sectional view of a flash memory cell according to another embodiment of the present disclosure is shown.

[0019] Figure 6 An equivalent circuit diagram of a flash memory cell according to another embodiment of the present disclosure is shown.

[0020] Figure 7 A schematic diagram showing an erase operation performed on a storage transistor by an erase method according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0021] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more exemplary embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are non-limiting terms that refer to a non-limiting example of an apparatus or method that employs one or more inventive concepts disclosed herein. It will be evident, however, that the exemplary embodiments can be practiced without these specific details, or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more exemplary embodiments. Further, various exemplary embodiments can be different from one another and not necessarily mutually exclusive. For example, a specific shape, configuration, and characteristic of an exemplary embodiment can be used or implemented in other exemplary embodiments without departing from the inventive concepts.

[0022] Unless otherwise stated, the exemplary implementations explained herein should be understood to provide example features, which can vary in detail without departing from the inventive concept. Hence, unless otherwise stated, features, components, modules, layers, films, substrates, areas and / or aspects, etc. (hereinafter individually or collectively referred to as “elements”) of the implementations can be combined, separated, interchanged, and / or rearranged without departing from the inventive concept.

[0023] The use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries, regions, and / or areas of the elements illustrated in the drawings. As such, no inference should be drawn from the presence or absence of cross-hatching and / or shading in any individual figure that a particular material, material property, dimension, ratio, commonality between elements, and / or any other characteristic, attribute, property, shape, etc. is / are necessarily related to or in any way binding to any other element, feature, or portion of an element in any particular figure. Moreover, the elements illustrated in the figures are not necessarily drawn to scale. Wherever possible, like reference numerals have been used to refer to like elements.

[0024] When an element such as a layer, region, or substrate is referred to as being “on” or “connected to” another element, it can be directly on or connected to the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly connected to” another element, there are no intervening elements present. In this specification, the term “connected” can mean physical, electrical, and / or fluidic connection, with or without intervening elements. In addition, the D1 axis, the D2 axis, and the D3 axis are not limited to three axes of a straight rectangular coordinate system, such as x, y, and z axes, and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purpose of the present disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any one of X, Y, Z, or an arbitrary combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0025] Although the terms "first," "second," etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0026] Spatially relative terms, such as "under", "below", "lower", "above", "upper", "higher", and "sideward", for example, as found in the a "sidewall", are used herein for descriptive purposes only, and can not necessarily be construed as limiting, unless otherwise stated. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device is turned over, elements described as "below" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. Moreover, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description and / or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising". It should also be noted that, as used herein, the terms "substantially", "approximately", and other similar terms are used as synonyms for "about", and are employed to account for inherent variations in, for example, measuring, calculating, and / or providing a value.

[0028] Embodiments are described herein with reference to cross-sectional and / or exploded illustrations that are schematic illustrations of idealized embodiments and / or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments disclosed herein are not to be construed as being limited to the particular shapes of regions as illustrated in the drawings but are to include deviations in shapes that result, for example, from manufacturing. In this manner, the regions illustrated in the drawings can be schematic in nature and the shapes of the regions can not reflect actual shapes of the regions of a device and, as such, are not intended to limit the scope of the disclosure.

[0029] Unless specifically defined, all other technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein, such as that found in commonly utilized dictionaries, shall be interpreted as having a meaning that is consistent with its meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0030] Figure 1 A cross-sectional view of a flash memory cell MC 100 according to an embodiment of the present disclosure is shown.

[0031] As Figure 1 shown, a flash memory cell MC 100 according to an embodiment of the present disclosure can include a substrate 101 including a deep well region DNW 103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103.

[0032] Although the first doping type is defined as P-type and the second doping type is defined as N-type in Figure 1 , the person skilled in the art will recognize that the present disclosure is not limited thereto and that the first doping type can also be N-type, in which case the second doping type can be P-type.

[0033] According to an embodiment of the present disclosure, the substrate 101 can be, for example, a silicon (Si) substrate.

[0034] Further, the flash memory cell MC 100 includes a first memory transistor MS 110, a gate transistor MG 120, and a second memory transistor MD 130 connected in series in that order. The first memory transistor MS 110 can be disposed on the well region PW 102 and store first data DATA1. The second memory transistor MD 130 can be disposed on the well region PW 102 and store second data DATA2. The gate transistor MG 120 is disposed between the first memory transistor MS 110 and the second memory transistor MD 130 along a horizontal direction DR1 on the well region PW 102 for isolating and performing a gate operation on the first memory transistor MS 110 and the second memory transistor MD 130.

[0035] According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two memory transistors MS 110 and MD 130, and thus the flash memory cell MC 100 is capable of realizing a function of two-bit storage, i.e., storing the first data DATA1 and the second data DATA2 at the same time.

[0036] Further, as Figure 1As shown, the source region of the first storage transistor MS 110 is connected to the first electrode S of the flash memory cell MC 100, which can also be referred to as the source S of the flash memory cell MC 100, while the drain region of the second storage transistor MD 130 is connected to the second electrode D of the flash memory cell MC 100, which can also be referred to as the drain D of the flash memory cell MC 100.

[0037] Those skilled in the art will appreciate that the source and drain of the flash memory cell are defined herein for ease of description, however the definition of the source and drain of the flash memory cell is relative, and the terms "source" and "drain" can be used interchangeably under different working conditions.

[0038] Furthermore, as Figure 1 As shown, the first storage transistor MS 110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask stopper 117 arranged in sequence along the vertical direction DR2. The gate dielectric stack 112 has a first oxide layer 113, a storage medium layer 114, and a second oxide layer 115 stacked in sequence along the vertical direction. Furthermore, the second storage transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask stopper 137 arranged in sequence along the vertical direction DR2. The gate dielectric stack 132 has a first oxide layer 133, a storage medium layer 134, and a second oxide layer 135 stacked in sequence along the vertical direction.

[0039] According to embodiments of the present disclosure, the flash memory cell MC 100 includes two storage transistors MS 110 and MD 130, and thus the function of two-bit storage can be achieved.

[0040] According to embodiments of the present disclosure, as Figure 1 As shown, the flash memory cell MC 100 for two-bit storage can be composed of three transistors arranged closely, i.e., a gate transistor MG 120 located in the middle of the flash memory cell MC 100, a first storage transistor MS 110 located at the first end of the flash memory cell MC 100, and a second storage transistor MD 130 located at the second end of the flash memory cell MC 100.

[0041] As Figure 1 As shown, the flash memory cell MC 100 can be formed on a well region PW 102 in a semiconductor substrate 101. Furthermore, in order to isolate the well region PW 102 from the substrate 101 so as to apply a voltage to the well region PW 102 under certain working conditions, as Figure 1 As shown, the well region PW 102 can be formed in a deep well region DNW 103.

[0042] As Figure 1As shown, a source region 140 is formed by N-type doping at a first end of the flash memory cell MC 100, and a drain region 150 is also formed by N-type doping at a second end of the flash memory cell MC 100. The source region 140 is connected by a contact hole 141 and a metal source 142, i.e., a first electrode S, located in an upper layer, and the drain region 150 is connected by a contact hole 151 and a metal drain 152, i.e., a second electrode D, located in an upper layer.

[0043] According to embodiments of the present disclosure, the first electrode S and the second electrode D can include a metal or a highly doped polysilicon. When the first electrode S and the second electrode D are formed of a metal, they can include at least one of the following materials: aluminum, titanium, titanium nitride, copper, tungsten, cobalt, and manganese.

[0044] As described above, as Figure 1 As shown, the gate structure of the first memory transistor MS 110 can have, in sequence from bottom to top, a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask stop 117 for sidewall self-alignment. According to embodiments of the present disclosure, the gate electrode 116 can include, for example, polysilicon, a metal gate, a metal silicide material, or a combination of the above-mentioned materials. According to embodiments of the present disclosure, the hard mask stop 117 can include, for example, silicon oxide, silicon nitride, a silicon glass material, or a combination of the above-mentioned materials.

[0045] In addition, as Figure 1 As shown, the gate dielectric stack 112 has, in sequence from bottom to top along the vertical direction DR2, a first oxide layer (tunnel oxide layer) 113, a storage medium layer (charge storage layer) 114, and a second oxide layer (blocking oxide layer) 115. According to embodiments of the present disclosure, the first oxide layer 113 and the second oxide layer 115 can include, for example, silicon oxide or aluminum oxide, etc. According to embodiments of the present disclosure, the thickness of the first oxide layer (tunnel oxide layer) 113 can be 1 to 6 nm.

[0046] According to embodiments of the present disclosure, the storage medium layer 114 can include one or more layers of storage medium. In addition, according to embodiments of the present disclosure, the storage medium forming the storage medium layer 114 can include: a one- or multi-element oxide, such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide; a one- or multi-element nitride, such as silicon nitride; a one- or multi-element oxynitride, such as silicon oxynitride; polysilicon or nanocrystal material; or a combination of the above-mentioned materials.

[0047] According to embodiments of the present disclosure, when the storage medium layer 114 is formed of, for example, a silicon nitride material, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 can form a gate medium stack 112 as an ONO (Oxide-Nitride-Oxide) composite storage medium. At this time, the first storage transistor MS 110 can be a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) type storage transistor.

[0048] Further, according to embodiments of the present disclosure, the first storage transistor MS 110 can be another trap charge trapping type storage transistor having a similar operation mechanism as the SONOS type storage transistor, which type of storage transistor employs a high-K material rich in charge traps such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, etc. in place of the silicon nitride material in the SONOS memory as the storage medium layer 114.

[0049] Further, according to embodiments of the present disclosure, the first storage transistor MS 110 can also be a floating gate type storage transistor, which type of storage transistor employs a polysilicon material in place of the silicon nitride material in the SONOS memory to form a floating gate for storing charges as the storage medium layer 114.

[0050] Further, according to embodiments of the present disclosure, the first storage transistor MS 110 can also be a nano-crystal memory, which type of storage transistor employs a nano-crystal material having quantum dots in place of the silicon nitride material in the SONOS memory as the storage medium layer 114.

[0051] According to embodiments of the present disclosure, the length of the gate electrode 116 of the first storage transistor MS 110 can be defined by the length of the hard mask stopper 117 provided on the gate electrode 116 by a self-alignment process. It is noted by those skilled in the art that the "length" mentioned herein means the size of the stated object in the first direction DR1.

[0052] According to embodiments of the present disclosure, the second storage transistor MD 130 has the same structure as the first storage transistor MS 110 and can be manufactured by the same process as the first storage transistor MS 110 except that it is provided on the opposite side of the gate transistor MG 120, and thus a detailed description of the structure of the second storage transistor MD 130 will be omitted here for brevity.

[0053] The gate structure of the gate transistor MG 120 may, from bottom to top, include a channel region 121, a gate dielectric layer 122, and a gate electrode 123. According to embodiments of this disclosure, the gate electrode 123 of the gate transistor MG 120 is connected to a word line, and the length of the gate electrode 123 is defined by the process dimensions of the photolithography process. According to embodiments of this disclosure, the gate dielectric layer 122 may include materials such as silicon oxide, silicon oxynitride, hafnium oxide, etc. Furthermore, according to embodiments of this disclosure, the gate electrode 123 may include materials such as polysilicon, a metal gate, a metal silicide, or a combination of the above materials.

[0054] According to embodiments of this disclosure, the channel regions 111, 131, and 121 of the first storage transistor MS110, the second storage transistor MD130, and the gating transistor MG120 may all have a first doping type, and the doping concentration of the channel regions 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 may be lower than the doping concentration of the channel region 121 of the gating transistor MG120.

[0055] Furthermore, according to embodiments of this disclosure, the channel regions 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 may have a second doping type or an undoped intrinsic channel region, and the channel region 121 of the gate transistor MG120 may have a first doping type different from the second doping type.

[0056] For example, such as Figure 1 As shown, when the first doping type is P-type and the second doping type is N-type, the doping concentration of the P-type channels 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 is lower than the doping concentration of the P-type channel 121 of the gate transistor MG120. Furthermore, according to embodiments of this disclosure, channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions.

[0057] According to embodiments of this disclosure, the flash memory cell MC 100 may further include: a first isolation portion 124, which is disposed horizontally DR1 between the first storage transistor MS110 and the gate transistor MG 120, for isolating the gate electrode 116 of the first storage transistor MS110 and the gate electrode 123 of the gate transistor MG 120; and a second isolation portion 125, which is disposed horizontally DR1 between the gate transistor MG 120 and the second storage transistor MD 130, for isolating the gate electrode 123 of the gate transistor MG 120 and the gate electrode 136 of the second storage transistor MD 130.

[0058] Specifically, such as Figure 1As shown, the gate electrode 123 of the gate transistor MG 120 is provided with a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls on both sides thereof, which are respectively used to electrically isolate the gate electrode 116 of the first storage transistor MS 110 and the gate electrode 136 of the second storage transistor MD 130 with a specific isolation gap length. According to the embodiments of the present disclosure, the first isolation portion 124 and the second isolation portion 125 can comprise the same material as the gate dielectric layer 122.

[0059] The flash memory cell according to the embodiments of the present disclosure can realize two storage transistors in one flash memory cell, thus can greatly reduce the equivalent area of each storage bit, and further obtain lower cost and higher integration density.

[0060] In addition, the storage transistors in the flash memory cell according to the embodiments of the present disclosure can adopt a SONOS type device structure with simple structure, and have the advantages of simple process, low gate electrode operating voltage, and good data retention reliability.

[0061] In addition, in the flash memory cell according to the embodiments of the present disclosure, the mutual influence of the two storage bits is isolated by the gate transistor, and the distribution width and lateral diffusion of the storage charge are suppressed, so that a higher storage charge density can be obtained in the silicon nitride storage layer, and the problems of wide charge distribution, large mutual interference, and inability to reduce the gate length of the existing NROM storage cell which also stores two bits can be avoided, and the storage window and data reliability are significantly improved.

[0062] In particular, the equivalent channel length of the flash memory cell according to the embodiments of the present disclosure is the sum of the lengths of the gate electrodes of the first storage transistor, the gate transistor, and the second storage transistor. As described above, the length of the gate electrode of the gate transistor is defined by the process feature size of the photolithography process, and is usually approximately equal to or slightly greater than the critical feature size (Critical Feature Size) of the photolithography process, which is usually represented as F (or CF). In addition, the lengths of the gate electrodes of the first storage transistor and the second storage transistor are respectively defined by the lengths of the self-aligned sidewall hard mask blocking portions, and thus the sizes thereof can be less than F. Therefore, according to the embodiments of the present disclosure, a smaller channel length of the flash memory cell can be obtained under the same process feature size, and thus the area and manufacturing cost of the flash memory cell can be reduced.

[0063] Furthermore, in the flash memory cell array composed of the flash memory cell according to the embodiments of the present disclosure, for the flash memory cell not being selected for operation, the gate electrodes of the pass transistor and the first and second storage transistors are all grounded, so that the entire series channel of the flash memory cell is completely turned off, the equivalent channel length is enlarged, and thus the source-drain punch-through of the flash memory cell at high operating voltage can be avoided at smaller process feature size, thereby overcoming the problem that the gate electrode length of the existing flash memory cell cannot be reduced with the reduction of the process feature size. Therefore, the flash memory cell according to the embodiments of the present disclosure has better process scaling capability, and thus smaller cell area and manufacturing cost can be obtained by reducing the process feature size.

[0064] Furthermore, in the flash memory cell according to the embodiments of the present disclosure, by reducing the doping concentration of the P-type channel region of the first and second storage transistors or designing it as an N-type doped channel region, the threshold voltage of the storage transistors and the gate electrode operating voltage during the erase and read operations can be reduced, and thus the reliability of the storage transistors can be improved. At the same time, by increasing the doping concentration of the P-type channel region of the pass transistor, the punch-through voltage resistance of the flash memory cell can be improved, and the leakage current between the source and drain of the unselected flash memory cell can be reduced.

[0065] Figure 2 An equivalent circuit diagram of the flash memory cell MC 100 according to the embodiments of the present disclosure is shown. Figure 3 A schematic diagram of performing an erase operation on the first storage transistor MS 110 by the erase method according to the embodiments of the present disclosure is shown. Figure 4 A schematic diagram of performing an erase operation on the second storage transistor MD 130 according to the erase method according to the embodiments of the present disclosure is shown.

[0066] Specifically, as shown in Figure 2 The flash memory cell MC 100 includes a first storage transistor MS 110, a pass transistor MG 120 and a second storage transistor MD 130 connected in series. The pass transistor MG 120 can isolate the first storage transistor MS 110 and the second storage transistor MD 130 and perform a pass operation on the first storage transistor MS 110 and the second storage transistor MD 130. As shown in Figure 2 By controlling the voltages applied to the source region (i.e. the first electrode S) of the first storage transistor MS 110, the gate electrode 116 of the first storage transistor MS 110, the gate electrode 123 of the pass transistor MG 120, the gate electrode 136 of the second storage transistor MD 130 and the drain region (i.e. the second electrode D) of the second storage transistor MD 130, the erase operation on the first storage transistor MS 110 or the second storage transistor MD 130 can be realized, respectively.

[0067] According to embodiments of the present disclosure, the well region PW 102 of the flash memory cell MC 100 can be grounded when performing an erase operation on the flash memory cell MC 100.

[0068] Specifically, according to embodiments of the present disclosure, as shown in FIG. 1, when performing an erase operation on the first memory transistor MS 110 of the flash memory cell MC 100, the erase method according to the present disclosure includes applying a second power supply voltage VSS to the well region PW 102, applying a first erase voltage VE1 to the first electrode S, applying a second erase voltage VE2 to the second electrode D, applying a third erase voltage VE3 to the gate electrode 116 of the first memory transistor MS 110, applying a fourth erase voltage VE4 to the gate electrode 123 of the gate transistor MG 120, and applying a fifth erase voltage VE5 to the gate electrode 136 of the second memory transistor MD 130. For example, the second power supply voltage VSS can be a ground voltage GND, such as 0 V. Figure 3

[0069] According to embodiments of the present disclosure, the first erase voltage VE1 can be higher than a preset voltage VP, wherein the preset voltage VP is preset according to a carrier potential barrier height at an interface between the substrate and the gate dielectric stack 112 of the first memory transistor MS 110. For example, in the flash memory cell MC 100 shown in FIG. 1, the preset voltage can enable a carrier to overcome a carrier potential barrier at an interface between the P-type channel region 111 and a lower first oxide layer (tunneling oxide) 113 in the gate dielectric stack 112. For example, in the case where the P-type channel region 111 includes silicon and the first oxide layer 113 includes silicon dioxide, the carrier is a hole, and the hole potential barrier height is 4.8 electron volts (eV). In this case, the first erase voltage VE1 is typically greater than 4 volts (V). For example, the first erase voltage VE1 can be in the range of 3 V to 6 V, such as the first erase voltage VE1 can be 4.6 V. According to embodiments of the present disclosure, the first erase voltage VE1 can be provided by an external constant voltage source. Figure 1

[0070] According to embodiments of the present disclosure, the second erase voltage VE2 can be equal to or higher than the second power supply voltage VSS, wherein the second power supply voltage VSS can be a ground voltage GND. For example, according to embodiments of the present disclosure, the second erase voltage VE2 can be 0.2 V.

[0071] According to embodiments of the present disclosure, the third erase voltage VE3 can be equal to or lower than the second power supply voltage VSS. According to embodiments of the present disclosure, the third erase voltage VE3 can be in the range of -8 V to 0 V. For example, according to embodiments of the present disclosure, the third erase voltage VE3 can be -4.8 V.

[0072] ​​According to embodiments of the present disclosure, the negative third erase voltage VE3 applied to the gate electrode 116 of the first storage transistor MS 110 can cause ionized hot holes (indicated by the open circle in Figure 3 ) in the depletion region of the first electrode S (source) to be attracted by the negative third erase voltage VE3 and injected into the storage dielectric layer 114, for example, silicon nitride, in the gate dielectric stack 112 of the first storage transistor MS 110 (as indicated by the open arrow in Figure 3 ). The hot holes will neutralize the electrons (indicated by the solid circle in Figure 3 ) stored during the write (program) operation of the flash memory cell MC 100, causing the threshold voltage of the first storage transistor MS 110 to drop, thereby achieving the erase of the first storage transistor MS 110.

[0073] According to embodiments of the present disclosure, the fourth erase voltage VE4 can be equal to or lower than the first supply voltage VDD, where the first supply voltage VDD is higher than the second supply voltage VSS, and can be in the range of 0.8V to 5V. For example, according to embodiments of the present disclosure, the fourth erase voltage VE4 can be 1V.

[0074] According to embodiments of the present disclosure, the first erase voltage VE1, the fourth erase voltage VE4, and the fifth erase voltage VE5 are higher than the second erase voltage VE2, such that the first storage transistor MS 110, the second storage transistor MD 130, and the gate transistor MG 120 are all turned on, i.e., the flash memory cell MC 100 is turned on as a whole.

[0075] According to embodiments of the present disclosure, the fifth erase voltage VE5 can be in the range of 3V to 8V. For example, according to embodiments of the present disclosure, the fifth erase voltage VE5 can be 5V.

[0076] Similarly, according to embodiments of the present disclosure, as shown in Figure 4 , when performing an erase operation on the second storage transistor MD 130 of the flash memory cell MC 100, the erase method according to the present disclosure includes applying the second supply voltage VSS to the well region PW 102, applying the first erase voltage VE1 to the second electrode D, applying the second erase voltage VE2 to the first electrode S, applying the fifth erase voltage VE5 to the gate electrode 116 of the first storage transistor MS 110, applying the fourth erase voltage VE4 to the gate electrode 123 of the gate transistor MG 120, and applying the third erase voltage VE3 to the gate electrode 136 of the second storage transistor MD 130.

[0077] As can be seen, due to the symmetric structure of the flash memory cell MC 100, the erase voltages VE1 to VW5 applied during erasing the first memory transistor MS 110 and the second memory transistor MD 130 also have a symmetric relationship. Therefore, for the sake of brevity, the repetitive description of the erase voltages applied during erasing the second memory transistor MD 130 is not repeated here.

[0078] Specifically, taking the first memory transistor MS 110 as an example, when performing the erase operation on the first memory transistor MS 110, the gate electrode 123 of the pass transistor MG 120 is applied with the fourth erase voltage VE4 slightly higher than its threshold voltage, thus being in a weakly on state, thereby suppressing the on current (usually in the order of microamperes) of the flash memory cell MC 100, which can greatly reduce the voltage difference of the series channel (121 and 131) of the pass transistor MG 120 and the second memory transistor MD 130. Therefore, the voltage difference VE1-VE2 between the first electrode S and the second electrode D of the flash memory cell MC 110 is mostly applied to the channel region 111 of the first memory transistor MS 110, thereby causing the Channel Hot Electron Induced Hot Hole Injection physical effect.

[0079] Specifically, the erase method according to the embodiments of the present disclosure is based on the Channel Hot Electron Induced Hot Hole Injection physical effect first discovered by the inventors. Specifically, taking the first memory transistor MS 110 as an example, when performing the erase operation on the first memory transistor MS 110, the pass transistor MG 120 and the second memory transistor MD 130 are turned on, and at the same time, due to the first erase voltage VE1 applied to the first electrode 142, the channel region 111 of the first memory transistor MS 110 is completely depleted to form a depletion region, the whole flash memory cell MC 100 is turned on, an electron current is generated in the channel region and hot electrons are formed under the acceleration of the lateral electric field, and then an electron-hole pair is generated in the depletion region through collision ionization, wherein the hot hole is injected into the storage medium layer 114 of the first memory transistor MS 110 under the attraction of the negative third erase voltage VE3 applied to the gate electrode 116 of the first memory transistor MS 110, thereby achieving the erasing of the first memory transistor MS 110.

[0080] According to the embodiment of the present disclosure, when performing the erase operation on the first storage transistor MS 110, both the fourth erase voltage VE4 applied to the gate electrode 123 of the gate transistor MG 120 and the erase voltage VE5 applied to the gate electrode 136 of the second storage transistor MD 130 are higher than the second power supply voltage VSS, i.e. positive voltage, so that the second storage transistor MD 130 and the gate transistor MG 120 are turned on. In addition, according to the embodiment of the present disclosure, when performing the erase operation on the first storage transistor MS 110, although the third erase voltage VE3 applied to the gate electrode 116 of the first storage transistor MS 110 is equal to or lower than the second power supply voltage VSS, the first storage transistor MS 110 is still turned on due to the first erase voltage VE1 which depletes the channel region 111 of the first storage transistor MS 110 entirely to form a depletion region, as described above. Therefore, when performing the erase method according to the embodiment of the present disclosure, the flash memory cell MC 100 as a whole is turned on.

[0081] Although in the above example the first doping type is defined as P-type and the second doping type is defined as N-type, so that the first storage transistor MS 110, the gate transistor MG 120 and the second storage transistor MD 130 are all N-type transistors. However, those skilled in the art should appreciate that the present disclosure is not limited thereto, and the first doping type can also be N-type and the second doping type can be P-type accordingly, in which case the first storage transistor MS 110, the gate transistor MG 120 and the second storage transistor MD 130 are all P-type transistors. In this case, the erase method according to the embodiment of the present disclosure is based on the Channel Hot Hole Induced Hot Electron Injection physical effect, the basic principle of which is consistent with the Channel Hot Electron Induced Hot Hole Injection physical effect described above, so no more detailed description is made.

[0082] In addition, since the gate electrode length of the first storage transistor MS 110 is much smaller than the equivalent channel length of the flash memory cell MC 100, the lateral electric field of the on channel of the first storage transistor MS 110 and the channel hot hole injection efficiency can be significantly increased.

[0083] Those skilled in the art should appreciate that although the erase method of the flash memory cell according to the present disclosure is described above in combination with the flash memory cell MC 100 shown in FIG. 1, the erase method of the flash memory cell according to the present disclosure is not limited to the flash memory cell MC 100 shown in FIG. 1. Figure 1 Those skilled in the art should appreciate that although the erase method of the flash memory cell according to the present disclosure is described above in combination with the flash memory cell MC 100 shown in FIG. 1, the erase method of the flash memory cell according to the present disclosure is not limited to the flash memory cell MC 100 shown in FIG. 1. Figure 1The flash memory cell MC 100 is shown. Those skilled in the art, based on the teachings of this disclosure, can conceive of applying the erasure method of the flash memory cell of this disclosure to other types of flash memory cells, such as flash memory cells comprising only a single storage transistor, and all such variations should be covered within the scope of this disclosure.

[0084] Figure 5 A cross-sectional view of a flash memory cell MC 200 according to another embodiment of the present disclosure is shown. Figure 6 An equivalent circuit diagram of a flash memory cell MC 200 according to another embodiment of the present disclosure is shown.

[0085] like Figure 5 and Figure 6 As shown, the flash memory cell MC 200 is similar to the one mentioned above. Figure 1 and Figure 2 The only difference between the described flash memory cell MC 100 and MC 200 is that the flash memory cell MC 200 includes only one storage transistor, which can correspond to the first storage transistor MS110 in the flash memory cell MC 100. Figure 5 and Figure 6 In the flash memory cell MC 200 shown, with Figure 1 and Figure 2 The same components as those in the flash memory cell MC 100 shown are indicated by the same reference numerals, and corresponding detailed descriptions will be omitted.

[0086] like Figure 5 As shown, a flash memory cell MC 200 according to another embodiment of the present disclosure may include a substrate 101, which includes a deep well region DNW 103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103. According to an embodiment of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

[0087] like Figure 5 and Figure 6 As shown, according to another embodiment of this disclosure, the flash memory cell MC 200 includes a storage transistor MS110 and a gating transistor MG 120 connected in series. The storage transistor MS110 may be disposed on the well region PW 102 and stores data DATA1. The gating transistor MG 120 is disposed on one side of the storage transistor MS110 on the well region PW 102 along the horizontal direction DR1, and is used to perform a gating operation on the storage transistor MS110.

[0088] like Figure 5As shown, according to another embodiment of the present disclosure, the source region of the storage transistor MS110 is connected to the first electrode S of the flash memory cell MC200, which may also be referred to as the source S of the flash memory cell MC200, and the drain region of the gate transistor MG120 is connected to the second electrode D of the flash memory cell MC200, which may also be referred to as the drain D of the flash memory cell MC200.

[0089] like Figure 5 As shown, according to another embodiment of this disclosure, the storage transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask blocking portion 117 sequentially disposed along the vertical direction DR2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 sequentially stacked along the vertical direction. According to an embodiment of this disclosure, when the storage dielectric layer 114 is formed of, for example, silicon nitride, the first oxide layer 113, the storage dielectric layer 114, and the second oxide layer 115 can form a gate dielectric stack 112 as an ONO composite storage dielectric. In this case, the storage transistor MS110 can be a SONOS-type storage transistor.

[0090] like Figure 5 As shown, according to another embodiment of the present disclosure, the gate structure of the gate transistor MG 120 may include, from bottom to top, a channel region 121, a gate dielectric layer 122, and a gate electrode 123.

[0091] like Figure 5 As shown, according to another embodiment of this disclosure, a source region 140 formed by N-type doping is provided at the first end of the flash memory cell MC 200, and a drain region 150 formed by N-type doping is also provided at the second end of the flash memory cell MC 200. The source region 140 is connected to the upper metal source 142, i.e., the first electrode S, through a contact hole 141, and the drain region 150 is connected to the upper metal drain 152, i.e., the second electrode D, through a contact hole 151.

[0092] like Figure 5 As shown, according to another embodiment of the present disclosure, the flash memory cell MC 200 may further include an isolation section 124, which is disposed in the horizontal direction DR1 between the storage transistor MS110 and the gate transistor MG 120, for isolating the gate electrode 116 of the storage transistor MS110 and the gate electrode 123 of the gate transistor MG 120.

[0093] Figure 7 A schematic diagram is shown of performing an erase operation on a storage transistor MS110 by an erase method according to another embodiment of the present disclosure.

[0094] Specifically, such as Figure 6As shown, the flash memory cell MC 200 includes a storage transistor MS110 and a gating transistor MG 120 connected in series. The gating transistor MG 120 can perform a gating operation on the storage transistor MS110. Figure 6 As shown, the erase operation of the storage transistor MS110 can be realized by controlling the voltage applied to the source region (i.e., the first electrode S) of the storage transistor MS110, the gate electrode 116 of the storage transistor MS110, the gate electrode 123 of the gate transistor MG 120, and the drain region (i.e., the second electrode D) of the gate transistor MG 120.

[0095] According to another embodiment of this disclosure, when performing an erase operation on the flash memory cell MC 200, the well region PW 102 of the flash memory cell MC 200 can be grounded.

[0096] Specifically, according to another embodiment of this disclosure, such as Figure 7 As shown, when performing an erase operation on the storage transistor MS110 of the flash memory cell MC 200, the erase method according to this disclosure includes applying a second power supply voltage VSS to the well region PW102, applying a first erase voltage VE1 to the first electrode S, applying a second erase voltage VE2 to the second electrode D, applying a third erase voltage VE3 to the gate electrode 116 of the storage transistor MS110, and applying a fourth erase voltage VE4 to the gate electrode 123 of the gate transistor MG 120. For example, the second power supply voltage VSS can be ground voltage GND, such as 0V.

[0097] According to another embodiment of this disclosure, the first erase voltage VE1 can be higher than a preset voltage VP, wherein the preset voltage VP is preset based on the carrier barrier height at the interface between the substrate and the gate dielectric stack 112 of the storage transistor MS110. For example, in Figure 5 In the flash memory cell MC 200 shown, a preset voltage allows holes to overcome the hole barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunneling oxide) 113 in the gate dielectric stack 112. For example, if the P-type channel region 111 comprises silicon and the first oxide layer 113 comprises silicon dioxide, the barrier height is 4.8 electron volts (eV). In this case, the first erase voltage VE1 is typically greater than 4 volts (V). For example, the first erase voltage VE1 can be in the range of 3V to 6V, such as 4.6V. According to embodiments of this disclosure, the first erase voltage VE1 can be provided by an external constant voltage source.

[0098] According to another embodiment of the present disclosure, the second erase voltage VE2 can be equal to or higher than a second power supply voltage VSS, where the second power supply voltage VSS can be a ground voltage GND. For example, according to an embodiment of the present disclosure, the second erase voltage VE2 can be 0.2V.

[0099] According to another embodiment of the present disclosure, the third erase voltage VE3 can be equal to or lower than the second power supply voltage VSS. According to an embodiment of the present disclosure, the third erase voltage VE3 can be in a range of -8V to 0V. For example, according to an embodiment of the present disclosure, the third erase voltage VE3 can be -4.8V.

[0100] According to another embodiment of the present disclosure, the negative third erase voltage VE3 applied to the gate electrode 116 of the storage transistor MS110 can cause the ionized hot holes (represented by the hollow circles in Figure 7 ) in the depletion region of the first electrode S (source) to be attracted by the negative third erase voltage VE3 and injected into the storage dielectric layer 114 (e.g., silicon nitride) in the gate dielectric stack 112 of the storage transistor MS110 (as indicated by the hollow arrows in Figure 3 ). The hot holes will neutralize the electrons (represented by the solid circles in Figure 7 ) stored during the write (program) operation of the flash memory cell MC200, causing the threshold voltage of the storage transistor MS110 to drop, thereby achieving the erase of the storage transistor MS110.

[0101] According to an embodiment of the present disclosure, the fourth erase voltage VE4 can be equal to or lower than the first power supply voltage VDD, where the first power supply voltage VDD is higher than the second power supply voltage VSS and can be in a range of 0.8V to 5V. For example, according to an embodiment of the present disclosure, the fourth erase voltage VE4 can be 1V.

[0102] According to an embodiment of the present disclosure, the first erase voltage VE1 and the fourth erase voltage VE4 are higher than the second erase voltage VE2, such that both the storage transistor MS110 and the gate transistor MG120 are turned on, i.e., the flash memory cell MC200 is turned on as a whole.

[0103] The erase method according to another embodiment of the present disclosure is also based on the Channel Hot Electron Induced Hot Hole Injection physical effect first discovered by the inventors, and thus will not be described in further detail for the sake of brevity.

[0104] The erase method according to the embodiments of the present disclosure is based on the channel hot electron induced hot hole injection physical effect first discovered by the inventors, has a wider hole distribution and a higher injection efficiency than the existing band-to-band tunneling hot hole (BBHH) erase method, so that the erase method according to the embodiments of the present disclosure has a higher erase speed (tens of microseconds), a larger erase window, less hot carrier damage, lower leakage current, and higher endurance reliability.

[0105] Although the present disclosure has been described with reference to the embodiments of the present disclosure, those skilled in the art will appreciate that various modifications and changes can be made to the present disclosure without departing from the spirit and scope of the present disclosure disclosed in the appended claims.

Claims

1. A method for erasing a flash memory cell, the flash memory cell comprising: Substrate and well region disposed within the substrate; A storage transistor is disposed on the well region and configured to store data; as well as A gating transistor, disposed horizontally on one side of the storage transistor in the well region, is configured to enable the storage transistor to perform a gating operation. The gating transistor and the storage transistor are connected in series. The source region of the storage transistor is connected to the first electrode of the flash memory cell, and the drain region of the gate transistor is connected to the second electrode of the flash memory cell. The erasure method includes: An erase operation is performed on the memory transistor by applying a second power supply voltage to the well region, applying a first erase voltage to the first electrode, applying a second erase voltage to the second electrode, applying a third erase voltage to the gate electrode of the memory transistor, and applying a fourth erase voltage to the gate electrode of the gate transistor. Wherein, the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power supply voltage, the third erase voltage is equal to or lower than the second power supply voltage, and the fourth erase voltage is equal to or lower than the first power supply voltage. Wherein, the first power supply voltage is higher than the second power supply voltage. The preset voltage is predetermined based on the carrier barrier height at the interface between the substrate and the gate dielectric stack of the storage transistor, and Wherein, the first erase voltage and the fourth erase voltage are higher than the second erase voltage, so that both the storage transistor and the gating transistor are turned on.

2. A method for erasing a flash memory cell, the flash memory cell comprising: Substrate and well region disposed within the substrate; A storage transistor includes: a first storage transistor disposed on the well region and configured to store first data; A second storage transistor is disposed on the well region and configured to store second data; and A gating transistor, horizontally disposed on the well region between the first and second storage transistors, is configured to isolate the first and second storage transistors and perform a gating operation on them. The first storage transistor, the gating transistor, and the second storage transistor are connected in series. In this configuration, the source region of the first storage transistor is connected to the first electrode of the flash memory cell, and the drain region of the second storage transistor is connected to the second electrode of the flash memory cell. The erasure method includes: An erase operation is performed on the first or second storage transistor by applying a second power supply voltage to the well region, applying a first erase voltage to the first or second electrode, applying a second erase voltage to the second or first electrode, applying a third erase voltage to the gate electrode of the first or second storage transistor, applying a fourth erase voltage to the gate electrode of the gate transistor, and applying a fifth erase voltage to the gate electrode of the second or first storage transistor. Wherein, the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power supply voltage, the third erase voltage is equal to or lower than the second power supply voltage, and the fourth erase voltage is equal to or lower than the first power supply voltage. Wherein, the first power supply voltage is higher than the second power supply voltage. The preset voltage is predetermined based on the carrier barrier height at the interface between the substrate and the gate dielectric stack of the first and second storage transistors. Wherein, the first erase voltage, the fourth erase voltage, and the fifth erase voltage are higher than the second erase voltage, so that the first storage transistor, the second storage transistor, and the gating transistor are all turned on.

3. The erasure method according to claim 1 or 2, wherein, The erasure method is based on the physical effect of channel hot electron-induced thermal hole injection.

4. The erasure method according to claim 1 or 2, wherein, The storage transistor is a charge-trapping storage transistor, and its gate dielectric stack includes a tunneling oxide layer, a charge storage layer, and a barrier oxide layer.

5. The erasure method according to claim 4, wherein, The thickness of the tunneling oxide layer is 1 to 6 nm.

6. The erasure method according to claim 4, wherein, The charge storage layer comprises a mono- or multi-component oxide, a mono- or multi-component nitride, a mono- or multi-component nitride, polycrystalline silicon or nanocrystalline material, or a combination of the above materials.

7. The erasure method according to claim 4, wherein, The charge storage layer comprises a high-K material rich in charge traps.

8. The erasure method according to claim 4, wherein, The tunneling oxide layer and the barrier oxide layer comprise silicon oxide or aluminum oxide.

9. The erasure method according to claim 1, wherein, The first power supply voltage is in the range of 0.8V to 5V. The second power supply voltage is ground voltage. The first erase voltage is in the range of 3 V to 6 V, and The third erase voltage is in the range of -8 V to 0 V.

10. The erasure method according to claim 2, wherein, The first power supply voltage is in the range of 0.8V to 5V. The second power supply voltage is ground voltage. The first erase voltage is in the range of 3 V to 6 V. The third erase voltage is in the range of -8 V to 0 V, and The fifth erase voltage is in the range of 3V to 8V.

Images