Semiconductor device and preparation method thereof, and storage system

Abstract

The invention provides a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises an effective storage block and a virtual storage block adjacent to the effective storage block in a first direction. The semiconductor device includes a first stacked structure, a first conductive contact, and a peripheral circuit. The first stacking structure is located in the virtual storage block and comprises an insulating layer and a conductive layer which are stacked, and a first conductive contact is connected with the conductive layer. The peripheral circuit is located on one side of the first stack structure and electrically connected with the first conductive contacts. The conductive layer in the virtual storage block is electrically connected with the peripheral circuit, and the structure of the conductive layer and the insulating layer in the storage block can be used as a part of the peripheral circuit, so that part of the structure in the peripheral circuit can be transferred into the virtual storage block, the waste of the area of the virtual storage block can be reduced, and the utilization rate of the virtual storage block is improved. And the area of a peripheral circuit can be saved.

Description

Technical Field

[0001] The present application generally relates to the field of electronic devices, and more specifically, to a semiconductor device and a manufacturing method and a storage system thereof. Background Art

[0002] NAND memory devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. Planar NAND devices have reached their practical expansion limit. In order to further increase storage capacity and reduce the storage cost per bit, 3D NAND memory is proposed. In the 3D NAND memory structure, a stacked memory structure is realized by vertically stacking multiple layers of data storage units.

[0003] 3D NAND memory includes an effective area and a virtual area, but currently the area of ​​the virtual area is too large, resulting in area waste.

[0004] Application Contents

[0005] The purpose of the present application is to provide a semiconductor device and a method for manufacturing the same, and a storage system, which are intended to fully utilize the structure of virtual storage blocks to reduce the area waste of virtual storage blocks.

[0006] In a first aspect, the present application provides a semiconductor device, the semiconductor device comprising an effective storage block and a virtual storage block adjacent to the effective storage block in a first direction, the semiconductor device comprising:

[0007] A first stacked structure, located in the virtual storage block and comprising a stacked insulating layer and a conductive layer;

[0008] a first conductive contact connected to the conductive layer;

[0009] The peripheral circuit is located at one side of the first stacking structure and is electrically connected to the first conductive contact.

[0010] In some embodiments, the virtual storage block includes a core area and a non-core area adjacent to the core area in the second direction, and the second direction intersects the first direction;

[0011] The first stacking structure is a step structure in the non-core area, and the first conductive contact is connected to the conductive layer in the step structure.

[0012] In some embodiments, the virtual storage block includes a main area and an edge area adjacent to the main area in a second direction, the main area includes a non-core area and a core area adjacent to the non-core area in the second direction, and the second direction intersects the first direction; the semiconductor device further includes:

[0013] A second stacking structure is located in the non-core area and includes the insulating layers and dielectric layers stacked alternately, wherein the dielectric layers are arranged in the same layer as the conductive layers;

[0014] Wherein, the first stacking structure is located in the core area and the non-core area, and the first stacking structure in the non-core area is located on both sides of the second stacking structure in the first direction;

[0015] The first conductive contact is located in the second stacking structure and connected to the conductive layer in the non-core area.

[0016] In some embodiments, the first conductive contact comprises:

[0017] a first conductive layer extending along a third direction in the second stacking structure and located on the dielectric layer, wherein the third direction intersects the first direction and the second direction;

[0018] The connection layer is arranged in the same layer as the dielectric layer and is located at the bottom of the first conductive layer. The connection layer is connected to the conductive layer in the non-core area.

[0019] In some embodiments, the first conductive contact further comprises:

[0020] A first isolation layer, located between the first conductive layer and the second stacking structure;

[0021] In some embodiments, the semiconductor device includes a plurality of storage blocks arranged along the first direction, the storage blocks include the effective storage blocks and the virtual storage blocks, and the virtual storage blocks are located outside the effective storage blocks along the first direction; the semiconductor device further includes:

[0022] a gate line gap structure, located between two adjacent storage blocks and extending along the second direction, wherein the gate line gap structure comprises a core area gate line gap structure and a non-core area gate line gap structure connected in the second direction, and the core area gate line gap structure extends to the edge area;

[0023] Wherein, the width of the non-core region gate line gap structure in the first direction is greater than the width of the core region gate line gap structure in the first direction.

[0024] In some embodiments, the semiconductor device further comprises:

[0025] a gate line partition structure, penetrating the first stacking structure along a third direction, the third direction intersecting the first direction and the second direction; the gate line partition structure is located in the core area and / or the edge area in the virtual storage area, and extends along the first direction;

[0026] The second conductive contact is located between two adjacent gate line isolation structures, and the second conductive contact is connected to the conductive layer and the peripheral circuit.

[0027] In some embodiments, the second conductive contact comprises:

[0028] A second conductive layer extending along the third direction and having a bottom connected to the conductive layer;

[0029] The second isolation layer is located between the second conductive layer and the first stacking structure.

[0030] In some embodiments, the semiconductor device further comprises:

[0031] A sub-gate line gap structure is located between two adjacent gate line gap structures and is located in the core area and the edge area;

[0032] Wherein, the sub-gate line gap structures are arranged at intervals along the second direction.

[0033] In some embodiments, the semiconductor device further comprises:

[0034] A lead-out structure connected to the first conductive contact;

[0035] A metal interconnection structure connects the lead-out structure and the peripheral circuit.

[0036] In some embodiments, the insulating layers and the conductive layers are stacked alternately, and two adjacent conductive layers constitute two electrodes of a capacitor structure.

[0037] In some embodiments, the peripheral circuit includes a charge pump circuit, and a plurality of the capacitor structures are connected in parallel via the charge pump circuit.

[0038] In a second aspect, the present application provides a method for preparing a semiconductor device, wherein the semiconductor device comprises an effective storage block and a virtual storage block adjacent to the effective storage block in a first direction, and the method for preparing the semiconductor device comprises:

[0039] forming a first stacking structure, the first stacking structure being located in the virtual storage block and comprising a stacked insulating layer and a conductive layer;

[0040] forming a first conductive contact, the first conductive contact connecting the conductive layer;

[0041] A peripheral circuit is formed on one side of the first stack structure, and the peripheral circuit is electrically connected to the first conductive contact.

[0042] In some embodiments, the virtual storage block includes a core area and a non-core area adjacent to the core area in the second direction, and the second direction intersects the first direction; the step of forming the first conductive contact includes:

[0043] Performing an etching process on the first stacked structure in the non-core area to form a step structure;

[0044] A first conductive contact is formed to connect the conductive layer in the stepped structure.

[0045] In some embodiments, the virtual storage block includes a main body area and an edge area adjacent to the main body area in a second direction, the main body area includes a non-core area and a core area adjacent to the non-core area in the second direction, and the second direction intersects the first direction; the step of forming the first stacking structure includes:

[0046] forming an initial stacking structure in the non-core region, the core region and the edge region, wherein the initial stacking structure comprises insulating layers and dielectric layers alternately stacked;

[0047] forming a gate line gap between two adjacent virtual storage blocks, and a sub-gate line gap between two adjacent gate line gaps and located in the core area and the edge area;

[0048] The dielectric layer is replaced by the gate line gap and the sub-gate line gap to form a first stacking structure and a second stacking structure, wherein the first stacking structure is located in the core area and the non-core area, the second stacking structure is located in the non-core area, and the first stacking structure in the non-core area is located on both sides of the second stacking structure in the first direction.

[0049] In some embodiments, the method for preparing the semiconductor device further includes:

[0050] forming a gate line isolation structure penetrating the first stacking structure along a third direction, wherein the third direction intersects the first direction and the second direction, and the gate line isolation structure is located in the core area and / or the edge area in the virtual storage area and extends along the first direction;

[0051] A second conductive contact is formed, wherein the second conductive contact is located between two adjacent gate line isolation structures and is connected to the conductive layer.

[0052] In some embodiments, the step of forming the second conductive contact and the step of forming the first conductive contact include:

[0053] Before the replacement process, a first conductive contact is formed in the non-core area, and a second conductive contact is formed between two adjacent gate line isolation structures;

[0054] The bottoms of the first conductive contacts are each connected to one of the conductive layers, and the bottoms of the second conductive contacts are each connected to one of the conductive layers.

[0055] In some embodiments, the step of forming a first conductive contact in the non-core area and forming a second conductive contact between two adjacent gate line isolation structures includes:

[0056] Forming a first contact hole in the initial stacking structure in the non-core area, and forming a second contact hole in the initial stacking structure between two adjacent gate line isolation structures, wherein the bottoms of the first contact hole and the second contact hole are both located on the dielectric layer;

[0057] forming a connection layer disposed at the same layer as the dielectric layer at the bottom of the first contact hole;

[0058] An isolation layer and a conductive layer are sequentially formed in the first contact hole and the second contact hole to form a first conductive layer connected to the connecting layer in the first contact hole and a second conductive layer connected to the dielectric layer in the second contact hole.

[0059] In some embodiments, the method for preparing the semiconductor device further includes:

[0060] forming a lead-out structure connected to the first conductive contact;

[0061] forming a metal interconnection structure connected to the lead-out structure, wherein the metal interconnection structure is connected to the peripheral circuit;

[0062] The insulating layers and the conductive layers are stacked alternately, and two adjacent conductive layers constitute two electrodes of a capacitor structure; the peripheral circuit includes a charge pump circuit, and a plurality of capacitor structures are connected in parallel through the charge pump circuit.

[0063] In a third aspect, the present application provides a storage system, including:

[0064] The semiconductor device in any of the above embodiments;

[0065] A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

[0066] The present application provides a semiconductor device and a method for preparing the same, as well as a storage system, comprising an effective storage block and a virtual storage block adjacent to the effective storage block in a first direction. The semiconductor device comprises a first stacking structure, a first conductive contact, and a peripheral circuit. The first stacking structure is located in the virtual storage block and comprises a stacked insulating layer and a conductive layer, and the first conductive contact connects the conductive layer. The peripheral circuit is located on one side of the first stacking structure and is electrically connected to the first conductive contact. The present application electrically connects the conductive layer in the virtual storage block to the peripheral circuit, and the structure of the conductive layer and the insulating layer in the storage block can be used as part of the peripheral circuit, and then part of the structure in the peripheral circuit can be transferred to the virtual storage block, which can not only reduce the waste of the virtual storage block area, but also save the area of ​​the peripheral circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0068] Figure 1a-1d is a schematic diagram of the distribution of effective storage blocks and virtual storage blocks in a semiconductor device provided by some embodiments of the present application;

[0069] Figure 2 is a schematic cross-sectional structure diagram of a semiconductor device provided in some embodiments of the present application;

[0070] Figure 3 is a working schematic diagram of a charge pump circuit provided in some embodiments of the present application;

[0071] Figure 4 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application;

[0072] Figure 5a Some embodiments of the present invention provide semiconductor devices along the Figure 4 Schematic diagram of the cross-sectional structure at A-A1;

[0073] Figure 5b Some embodiments of the present invention provide semiconductor devices along the Figure 4 Schematic diagram of the cross-sectional structure at A-A1;

[0074] Figure 6 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application;

[0075] Figure 7 Some embodiments of the present invention provide semiconductor devices along the Figure 6 Schematic diagram of the cross-sectional structure at B-B1;

[0076] Figure 8is a schematic flow chart of a method for preparing a semiconductor device provided in some embodiments of the present application;

[0077] Fig. 9 It is a schematic diagram of the structure of the storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0078] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0079] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.

[0080] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0081] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire lower or upper structure, or may have a range that is less than the range of the lower or upper structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more first conductive layers and a contact layer (wherein contacts, interconnect lines and / or vertical interconnect access (VIA) are formed) and one or more dielectric layers.

[0082] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0083] This article uses Cartesian coordinates to represent directions, where "X" represents the first direction, "Y" represents the second direction, and "Z" represents the third direction. The first direction, the second direction, and the third direction intersect with each other, that is, X, Y, and Z intersect with each other, for example, they may be perpendicular to each other, or at a certain angle.

[0084] The semiconductor device in the embodiment of the present application can be a wafer, or a three-dimensional memory or a part of a three-dimensional memory. The three-dimensional memory can be applied to communication products, consumer electronics products, automotive products, aerospace products, artificial intelligence products or big data, etc. Among them, consumer electronics products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses or game products, etc.

[0085] See also Figure 1a-1d , Figure 1a-1d This is a schematic diagram of the distribution of effective storage blocks and virtual storage blocks in semiconductor devices provided by some embodiments of the present application. The distribution of effective storage blocks and virtual storage blocks in each figure is adapted to the structural design of different products.

[0086] The semiconductor device includes a plurality of storage platforms (Plane), each storage platform includes a plurality of storage blocks arranged along the first direction (X), the storage blocks include an effective storage block G1 and a virtual storage block G2, and the virtual storage block G2 is adjacent to the effective storage block G1 in the first direction (X). Specifically, the effective storage block G1 is located in the middle of the storage platform, and the virtual storage block G2 is located at the edge of the storage platform, that is, the virtual storage block G2 is located at the periphery of the effective storage block G1. The number of effective storage blocks G1 and the number of virtual storage blocks G2 can be multiple, and the present application does not limit the number of effective storage blocks G1 and the number of virtual storage blocks G2.

[0087] The effective storage block G1 includes a storage channel structure, and the virtual storage block G2 includes a virtual channel structure. The effective storage block G1 can be used to implement an effective storage function, and the virtual storage block G2 is located at the edge to ensure the stability of the structure in the middle effective storage block G1, for example, the profile of the storage channel structure in the effective storage block G1 can be maintained.

[0088] In some embodiments, the virtual storage block G2 is located on both sides or outside of the effective storage block G1 in the first direction (X). Each storage block is isolated by a continuous gate line gap structure S1, and the storage block may also include a disconnected sub-gate line gap structure S2, and the gate line gap structure S1 and the sub-gate line gap structure S2 both extend along the second direction (Y).

[0089] like Figure 1a , Figure 1b and Figure 1cAs shown, the figure only shows a plurality of virtual storage blocks G2 located on one side of the effective storage block G1. Figure 1a It shows that there are three virtual storage blocks G2 on one side of the effective storage block G1. Figure 1b and Figure 1c It is shown that there are two virtual memory blocks G2 on one side of the effective memory block G1.

[0090] exist Figure 1a In the embodiment, Figure 1a There is no gate line gap structure S1 and sub-gate line gap structure S2 in the virtual storage block G2 at the edge. Figure 1b In the embodiment, one of the virtual storage blocks G2 further includes a third gate line gap structure S3 extending along the first direction (X), and the third gate line gap structure S3 is connected to the gate line gap structure S1 and the sub-gate line gap structure S2. Figure 1c Examples and Figure 1b The difference between the embodiment of the present invention is that a part of the gate line gap structure S1 and the sub-gate line gap structure S2 are disconnected by the third gate line gap structure S3.

[0091] like Figure 1d As shown, the virtual storage block G2 is located on both sides of the effective storage block G1 in the first direction (X), and the plurality of storage blocks are surrounded by the U-shaped gate line gap structure S. It can be understood that the U-shaped gate line gap structure S is also composed of the gate line gap structure S1 and the gate line gap structure extending in the first direction (X).

[0092] See also Figure 2 , Figure 2 is a schematic diagram of a cross-sectional structure of a semiconductor device provided by some embodiments of the present application. The virtual storage block distribution in the semiconductor device 100 can be as described above. Figure 1a to Figure 1d Any of the embodiments shown.

[0093] The semiconductor device 100 includes a first stack structure 10, a first conductive contact 11 and a peripheral circuit 12. Figure 2 Only a partial structure of the semiconductor device 100 at the position of the first conductive contact 11 is shown. The first stacked structure 10 is located in the virtual storage block and includes a stacked insulating layer 101 and a conductive layer 102, and the first conductive contact 11 is connected to the conductive layer 102. The peripheral circuit 12 is located on one side of the first stacked structure 10 and is electrically connected to the first conductive contact 11.

[0094] The insulating layer 101 and the conductive layer 102 may be alternately stacked in sequence. The material of the insulating layer 101 includes but is not limited to any one or more combinations of silicon oxide, silicon nitride and silicon oxynitride, and the conductive layer 102 may include at least one of a metal layer (e.g., tungsten) and a metal compound (e.g., titanium nitride), and may also include a high-K dielectric layer (e.g., aluminum oxide).

[0095] The material of the first conductive contact 11 may include metal, such as tungsten, and the structure of the first conductive contact 11 will be described in detail below. The plurality of first conductive contacts 11 are connected to the plurality of conductive layers 102 in a one-to-one correspondence.

[0096] The bottom of the first conductive contact 11 is connected to the conductive layer 102, and the first stacked structure 10 has a side close to the bottom of the first conductive contact 11 and a side away from the bottom of the first conductive contact 11. The peripheral circuit 12 can be connected to the side of the first stacked structure 10 close to the bottom of the first conductive contact 11 by bonding (e.g. Figure 2 The peripheral circuit 12 may be connected to the first stacked structure 10 at one side away from the bottom of the first conductive contact 11. The peripheral circuit 12 may include a complementary metal oxide semiconductor (CMOS) integrated circuit. CMOS may include a charge pump circuit, a page buffer circuit, a string drive circuit, a voltage supply circuit, an analog circuit, etc.

[0097] Since the first stacked structure 10 in the virtual storage block does not serve as a storage function, the present application connects the conductive layer 102 in the first stacked structure 10 to the peripheral circuit 12, so that part of the structure in the peripheral circuit 12 can be transferred to the virtual storage block, for example, the capacitor structure in the charge pump circuit can be transferred to the virtual storage block.

[0098] In some embodiments, the insulating layer 101 and the conductive layer 102 located on both sides of the insulating layer 101 can form a capacitor structure as part of the charge pump circuit. That is, two adjacent conductive layers 102 constitute two electrodes of a capacitor structure, and the two electrodes can respectively receive different voltage signals from the charge pump circuit through the first conductive contact 11. Therefore, the structure in the virtual storage block is fully utilized, the area waste is reduced, and the area of ​​the charge pump circuit in the peripheral circuit 12 can also be saved.

[0099] In some embodiments, according to the number of required capacitor structures, some of the first conductive contacts 11 can be selected to be connected to the peripheral circuit 12. For example, two conductive layers 102 can be spaced apart, and the first conductive contacts 11 connected to the first and fourth conductive layers 102 can be connected to the peripheral circuit 12.

[0100] In some embodiments, the virtual storage block includes a core area and a non-core area adjacent to the core area in the second direction (Y).

[0101] In some embodiments, the non-core region may be located on both sides of the core region in the second direction (Y). Figure 2 As shown, the first stacked structure 10 is a step structure in the non-core area, and the first conductive contact 11 is connected to the conductive layer 102 in the step structure. Specifically, the step structure includes a plurality of steps, each step includes a pair of insulating layers 101 and a conductive layer 102, and a plurality of first conductive contacts 11 are respectively connected to the conductive layer 102 in each step.

[0102] In some embodiments, the semiconductor device 100 may further include a lead structure and a metal interconnect structure (not shown), the lead structure is connected to the first conductive contact 11, and the metal interconnect structure is connected to the lead structure and the peripheral circuit 12. The peripheral circuit 12 may also include a metal interconnect structure, and the metal interconnect structure in the peripheral circuit 12 may be bonded to the metal interconnect structure in the semiconductor device 100.

[0103] See also Figure 3 , Figure 3 This is a working schematic diagram of the charge pump circuit provided in some embodiments of the present application.

[0104] The charge pump circuit includes switches S1, S2, S3 and S4, and capacitors C1 and C2 connected in parallel. During the operation of the semiconductor device 100, the charge pump circuit converts the low voltage V DD Pull to the operating voltage V out The capacitor C1 may be formed by connecting a plurality of capacitor structures in parallel, and the capacitor C2 may also be formed by connecting a plurality of capacitor structures in parallel. Since C1 and C2 are connected in parallel, all capacitor structures may be connected in parallel through a charge pump circuit.

[0105] Among them, the conductive layer 102 in the virtual storage block can be used as the electrode of the capacitor structure to form multiple capacitor structures, which are wired through the metal interconnect structure in the semiconductor device 100 and connected to the switch of the charge pump circuit, so that some of the capacitor structures are connected in parallel to form capacitor C1, and other capacitor structures are connected in parallel to form capacitor C2.

[0106] See also Figure 4 , Figure 4 1 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures in this embodiment as in the above embodiments.

[0107] Combined with reference Figure 1dThe virtual storage block G2 includes a main area G21 and an edge area G22 adjacent to the main area G21 in the second direction (Y), and the main area G21 includes a non-core area G221 and a core area G222 adjacent to the non-core area G221 in the second direction (Y). Figure 4 The structure of a core area G222 and a non-core area G221 in a virtual storage block G2 is shown.

[0108] The semiconductor device 200 may include a gate line gap structure S1 and a sub-gate line gap structure S2, wherein the gate line gap structure S1 is located between two adjacent storage blocks and extends along the second direction (Y). The sub-gate line gap structure S2 is located between two adjacent gate line gap structures S1 and is located in the core area G222 and the edge area G22, and the sub-gate line gap structure S2 is arranged at intervals along the second direction (Y). The gate line gap structure S1 includes a core area gate line gap structure S11 and a non-core area gate line gap structure S12 interconnected in the second direction (Y), and the core area gate line gap structure S11 extends to the edge area G22 ( Figure 4 The edge region G22 is not shown). The width of the non-core region gate line gap structure S12 in the first direction (X) is greater than the width of the core region gate line gap structure S11 in the first direction (X).

[0109] The semiconductor device 200 includes a first stacking structure 20, a second stacking structure 21 and a first conductive contact 23. The first stacking structure 20 is located in the core area G222 and the non-core area G221. The second stacking structure 21 is located in the non-core area G221. The first stacking structure 20 of the non-core area G221 is located on both sides of the second stacking structure 21 in the first direction (X). Therefore, the first stacking structure 20 surrounds the second stacking structure 21. Figure 2 The difference between the embodiments is that Figure 4 The first conductive contact 23 in the embodiment is located in the second stacking structure 21 , and the second stacking structure 21 is not a step structure. Figure 4 and Figure 2 Different ways of connecting the first conductive contact to the conductive layer 102 are shown. Figure 4 For specific connection methods, please refer to the attached Figure 5a .

[0110] See also Figure 5a , Figure 5a Some embodiments of the present invention provide semiconductor devices along the Figure 4 The cross-sectional structure diagram at A-A1 in FIG. It should be noted that: Figure 4 A-A1 corresponds to only one first conductive contact 23, and Figure 5a and the following Figure 5b2 shows a plurality of first conductive contacts 23 in the A-A1 cross-sectional direction. The drawings are for illustration only, and the present application does not limit the number of first conductive contacts.

[0111] The first stacked structure 20 includes insulating layers 101 and conductive layers 102 that are alternately stacked. Figure 4 2 is a cross-sectional view in the XY plane direction, showing the conductor layer 102. The second stacked structure 21 includes the insulating layer 101 and the dielectric layer 103 stacked alternately, the dielectric layer 103 is arranged in the same layer as the conductive layer 102, and the material of the dielectric layer 103 may include silicon nitride. The first conductive contact 23 is located in the second stacked structure 21 and is connected to the conductive layer 102 of the non-core area G221.

[0112] The first conductive contact 23 includes a first conductive layer 231, a connection layer 232 and a first filling layer 233. The first filling layer 233 extends along the third direction (Z) in the second stacked structure 21. The first conductive layer 231 surrounds the first filling layer 233 and is located on the dielectric layer 103. The connection layer 232 is arranged in the same layer as the dielectric layer 103 and is located at the bottom of the first conductive layer 231. The connection layer 232 is connected to the conductive layer 102 of the non-core area G221. Specifically, the connection layer 232 is connected to the conductive layer 102 of the non-core area G221, and then connected to the conductive layer 102 of the core area G222.

[0113] In some embodiments, the first conductive contact 23 includes only a first conductive layer 231 and a connecting layer 232, the first conductive layer 231 extends along a third direction (Z) in the second stacking structure 21, and the connecting layer 232 is arranged in the same layer as the dielectric layer 103 and is located at the bottom of the first conductive layer 231.

[0114] See also Figure 5b , Figure 5b Some embodiments of the present invention provide semiconductor devices along the Figure 4 For ease of understanding and brief description, this embodiment is similar to Figure 5a The same reference numerals are used for the same structures in the embodiments, and only the different structures are described in detail.

[0115] The first conductive contact 23a includes a first conductive layer 231, a connecting layer 232, a first filling layer 233 and a first isolation layer 234, wherein the first isolation layer 234 is located between the first conductive layer 231 and the second stacked structure 21. The materials of the first conductive layer 231 and the connecting layer 232 can be tungsten, and the first isolation layer 234 and the first filling layer 233 can include but are not limited to any one or more combinations of silicon oxide, silicon nitride and silicon oxynitride.

[0116] Figure 5b and Figure 5a The difference between the embodiments is that the first conductive contact 23a further includes a first isolation layer 234. Figure 5a In the embodiment, the first conductive contact 23 can be formed separately. Figure 5b The first conductive contact 23 a in the embodiment may be formed together with the second conductive contact 30 described later. For details, please refer to the method for preparing a semiconductor device described later.

[0117] It should be noted that the portions of the first conductive contacts 23 / 23 a extending out of the second stacked structure 21 are all formed in the insulating layer, which is not shown in the figure, and the second conductive contacts 30 described later are similar.

[0118] See also Figure 6 , Figure 6 It is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present application.

[0119] The semiconductor device 300 shows Figure 1d , that is, only a plurality of virtual storage blocks G2 located on one side of the effective storage block G1 are shown. Figure 6 Examples may include Figure 4 and Figure 5b In the embodiment of the present invention, the semiconductor device 300 also includes a non-core area G221, a core area G222 and an edge area G22, and the structure of the non-core area G221 of the virtual storage block G2 can refer to Figure 4 The semiconductor device 300 also includes a first conductive contact 23 a.

[0120] The semiconductor device 300 further includes a second conductive contact 30 and a gate line isolation structure 31, the gate line isolation structure 31 penetrates the first stacked structure 20 along the third direction (Z), the gate line isolation structure 31 is located in the core area G222 and / or the edge area G22 in the virtual storage area, and extends along the first direction (X). In some embodiments, the gate line isolation structure 31 can be located in the core area G222 or the edge area G22, or in the core area G222 and the edge area G22.

[0121] The second conductive contact 30 is located between two adjacent gate line isolation structures 31, and is connected to the conductive layer 102 of the first stacked structure 20 and the peripheral circuit. Therefore, the second conductive contact 30 can also be located in the core area G222 and / or the edge area G22 in the virtual storage area G2.

[0122] Since the first conductive contact 23a is connected to the conductive layer 102 of the core area G222, and the second conductive contact 30 is also connected to the conductive layer 102 of the core area G222, the gate line isolation structure 31 can divide the conductive layer 102 into multiple parts, so that even if the first conductive contact 23a and the second conductive contact 30 are connected to the same conductive layer 102, they are respectively connected to different parts of the conductive layer 102. In other words, the gate line isolation structure 31 can separate the conductive layer 102 connected to the first conductive contact 23a and the second conductive contact 30, and then the conductive layer 102 between adjacent gate line isolation structures 31 can be used as an electrode of the capacitor structure alone, thereby increasing the number of capacitor structures.

[0123] In some embodiments, a sub-gate line gap structure S2 divides a memory block into two memory fingers, and a plurality of second conductive contacts 30 may be arranged in a row along the second direction (Y) in one memory finger.

[0124] See also Figure 7 , Figure 7 Some embodiments of the present invention provide semiconductor devices along the Figure 6 Schematic diagram of the cross-sectional structure at B-B1.

[0125] The second conductive contact 30 includes a second conductive layer 301, a second isolation layer 302, and a second filling layer 303. The second conductive layer 301 extends along the third direction (Z) and is connected to the conductive layer 102 at its bottom. The second isolation layer 302 is located between the second conductive layer 301 and the first stacked structure 20. The second filling layer 303 is surrounded by the sidewall and bottom of the second conductive layer 301. The second conductive layer 301 can be made of the same material as the first conductive layer 231, the second isolation layer 302 can be made of the same material as the first isolation layer 234, and the second filling layer 303 can be made of the same material as the first filling layer 233.

[0126] and Figure 5b Different from the first conductive contact 23 a in the embodiment, the second conductive contact 30 is located in the first stacked structure 20 , that is, the second conductive layer 301 is directly connected to the conductive layer 102 .

[0127] The semiconductor device provided in the present application electrically connects the conductive layer 102 in the virtual storage block G2 with the peripheral circuit, and the structure of the conductive layer 102 and the insulating layer 101 in the virtual storage block G2 can be used as part of the peripheral circuit, and then part of the structure in the peripheral circuit can be transferred to the virtual storage block G2, which can not only reduce the waste of the area of ​​the virtual storage block G2, but also save the area of ​​the peripheral circuit.

[0128] See also Figure 8 , Figure 81 is a flow chart of a method for preparing a semiconductor device provided in some embodiments of the present application. This embodiment takes the preparation of the above-mentioned semiconductor device as an example to illustrate the method for preparing the semiconductor device, so please refer to Figure 1d-Figure 7 The method for preparing the semiconductor device includes the following steps S1-S3.

[0129] Step S1: forming a first stacking structure 10 / 20 , wherein the first stacking structure 10 / 20 is located in the virtual memory block G2 and includes insulating layers 101 and conductive layers 102 that are alternately stacked.

[0130] Step S2 : forming a first conductive contact 11 / 23 , wherein the first conductive contact 11 / 23 is connected to the conductive layer 102 .

[0131] Step S3: forming a peripheral circuit on one side of the first stacked structure 10 / 20 , wherein the peripheral circuit is electrically connected to the first conductive contact 11 / 23 .

[0132] In some embodiments, reference Figure 2 Step S2 may include, after forming the first stacking structure 10, performing an etching process on the first stacking structure 10 in the non-core area G221 to form a step structure, and then forming a first conductive contact 11 connected to the conductive layer 102 in the step structure.

[0133] Specifically, an insulating layer (not shown) covering the step structure is first formed, and then an etching process is performed at each step to form a contact hole whose bottom is connected to the conductive layer 102 , and finally a conductive material is filled in the contact hole to form the first conductive contact 11 .

[0134] In some embodiments, referring to 1d, Figure 4 and Figure 5a, step S1 may include: 1) forming an initial stacking structure in the non-core area G221, the core area G222 and the edge area G22, the initial stacking structure including an insulating layer 101 and a dielectric layer 103 alternately stacked; 2) forming a gate line gap between two adjacent virtual storage blocks G2, and a sub-gate line gap between two adjacent gate line gaps and located in the core area G222 and the edge area G22; 3) performing a replacement process on the dielectric layer 103 through the gate line gap and the sub-gate line gap to form a first stacking structure 20 and a second stacking structure 21, the first stacking structure 20 is located in the core area G222, the non-core area G221 and the edge area G22, the second stacking structure 21 is located in the non-core area G221, and the first stacking structure 20 of the non-core area G221 is located on both sides of the second stacking structure 21 in the first direction (X). After the replacement process, an insulating material is filled in the gate line gaps and the sub-gate line gaps to form a gate line gap structure S1 and a sub-gate line gap structure S2.

[0135] In some of these embodiments, reference Figure 5a , step S2 may specifically include, firstly, performing an etching process on the second stacked structure 21 to form a contact hole, the bottom of the contact hole is connected to each dielectric layer 103. Then, the dielectric layer 103 at the bottom is etched through the contact hole to form a connection hole, and the connection hole is connected to the conductive layer 102 of the non-core area G221. Finally, the contact hole and the connection hole are filled with conductive material and filling material in sequence, so that a connection layer 232 is formed in the connection hole, and a first conductive layer 231 and a first filling layer 233 are formed in the contact hole.

[0136] In some embodiments, reference Figure 6 , Figure 7 as well as Figure 4 and Figure 5b , the method for preparing the semiconductor device may further include the following steps.

[0137] 1) forming a gate line isolation structure 31 penetrating the first stacked structure 20 along a third direction (Z), wherein the gate line isolation structure 31 is located in the core area G222 and / or the edge area G22 in the virtual storage area G2, and extends along the first direction (X). The gate line isolation structure 31 may be formed together with the gate line gap structure S1, or may be formed separately.

[0138] 2) forming a second conductive contact 30 , wherein the second conductive contact 30 is located between two adjacent gate line isolation structures 31 and connected to the conductive layer 102 .

[0139] In some embodiments, the second conductive contact 30 may be formed together with the first conductive contact 23 a. Specifically, before the replacement process in step S1 , the first conductive contact 23 a is formed in the non-core region G221 , and the second conductive contact 30 is formed between two adjacent gate line isolation structures 31 .

[0140] Specifically, refer to Figure 5b and Figure 7 , before the replacement process, a first contact hole is formed in the initial stacking structure of the non-core area G221, and a second contact hole is formed in the initial stacking structure between two adjacent gate line isolation structures 31, and the bottoms of the first contact hole and the second contact hole are both located on the dielectric layer 103. Then, a connection layer 232 arranged in the same layer as the dielectric layer 103 is formed at the bottom of the first contact hole, including first forming a connection hole and then filling a conductive material. Finally, an isolation layer, a conductive layer and a filling layer are sequentially formed in the first contact hole and the second contact hole, so as to form a first conductive layer 231, a first isolation layer 234 and a first filling layer 233 connected to the connection layer 232 in the first contact hole, and a second conductive layer 301, a second isolation layer 302 and a second filling layer 303 connected to the dielectric layer 103 are formed in the second contact hole.

[0141] In some embodiments, the first isolation layer 234 and the second isolation layer 302 may be formed on the sidewalls of the first contact hole and the second contact hole respectively, and then the connection hole may be formed. Then, the conductive material and the filling material may be deposited in sequence to form the connection layer 232 in the connection hole, the first conductive layer 231 and the first filling layer 233 in the first contact hole, and the second conductive layer 301 and the second filling layer 303 in the second contact hole.

[0142] The above replacement process is then performed to form the initial stacking structure into a first stacking structure 20 and a second stacking structure 21. The first stacking structure 20 includes a conductive layer 102 and an insulating layer 101 (i.e., the dielectric layer 103 at the position of the first stacking structure 20 is replaced by the conductive layer 102). The second stacking structure 21 includes a dielectric layer 103 and an insulating layer 101. The first conductive contact 23a is located in the second stacking structure 21, and the second conductive contact 30 is located in the first stacking structure 20. The connecting layer 232 of the first conductive contact 23a is connected to the conductive layer 102 in the first stacking structure 20, and the bottom of the second conductive layer 301 of the second conductive contact 30 is connected to the conductive layer 102 in the first stacking structure 20.

[0143] Among them, the second conductive contact 30 is formed together with the first conductive contact 23a to simplify the process, and is formed before the replacement process, which can reduce the difficulty of etching the second conductive contact 30. Because if the first conductive contact 23a and the second conductive contact 30 are formed after the replacement process, the formation of the second conductive contact 30 requires etching the conductive layer 102 and the insulating layer 101. The conductive layer 102 includes a metal layer, and this etching difficulty is very large. Since the side wall of the second conductive contact 30 will be in contact with the conductive layer 102 after the replacement process, the second isolation layer 302 can separate the second conductive layer 301 from the conductive layer 102 in the first stacking structure 20. In order to simplify the process and make the process of the first conductive contact 23a consistent with that of the second conductive contact 30, a first isolation layer 234 is also formed between the first conductive layer 231 and the second stacking structure 21. When forming Figure 5a In the embodiment of the structure, since there is no second conductive contact, the first conductive contact 23 is formed separately, and there is no need to form a first isolation layer.

[0144] The method for preparing the semiconductor device may further include: 1) forming a lead-out structure connected to the first conductive contact 11 / 23; 2) forming a metal interconnection structure connected to the lead-out structure, wherein the metal interconnection structure is connected to the peripheral circuit. The insulating layer 101 and the conductive layer 102 are alternately stacked, and two adjacent conductive layers 102 constitute two electrodes of a capacitor structure. The peripheral circuit includes a charge pump circuit, and a plurality of the capacitor structures are connected in parallel through the charge pump circuit.

[0145] The embodiment of the present application provides a method for preparing a semiconductor device, wherein a first conductive contact 23a connected to a conductive layer 102 in a first stacking structure 20 is formed in a second stacking structure 21 of a virtual memory block G2, a second conductive contact 30 connected to the conductive layer 102 is formed in the first stacking structure 20 of the virtual memory block G2, and a gate line isolation structure 31 is formed to isolate the conductive layer 102 connected by the first conductive contact 23a and the second conductive contact 30. By connecting the first conductive contact 23a and the second conductive contact 30 to a peripheral circuit, the conductive layer 102 can be used as a part of the peripheral circuit, so that the structure in the virtual memory block G2 can be utilized to reduce area waste, and on the other hand, the occupied area of ​​the peripheral circuit can be saved.

[0146] See also Fig. 9 , Fig. 94 is a schematic diagram of the structure of the storage system provided by some embodiments of the present application. The storage system 400 includes a semiconductor device 401 and a controller 402. The semiconductor device 401 can be a semiconductor device in any of the above embodiments, and the semiconductor device 401 can be prepared by the preparation method of the semiconductor device in the above embodiments. The controller 402 is electrically connected to the semiconductor device 401 and is used to control the semiconductor device 401 to store data. The semiconductor device 401 can perform the operation of storing data based on the control of the controller 402.

[0147] In some embodiments, the storage system may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0148] The semiconductor device 401 may include an effective storage block and a virtual storage block adjacent to the effective storage block in a first direction, and the semiconductor device includes: a first stacking structure, located in the virtual storage block, and including a stacked insulating layer and a conductive layer; a first conductive contact, connecting the conductive layer; and a peripheral circuit, located on one side of the first stacking structure and electrically connected to the first conductive contact.

[0149] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises an effective storage block and a virtual storage block adjacent to the effective storage block in a first direction, and the semiconductor device comprises: A first stacked structure, located in the virtual storage block and comprising a stacked insulating layer and a conductive layer; a first conductive contact connected to the conductive layer; The peripheral circuit is located at one side of the first stacking structure and is electrically connected to the first conductive contact.

2. The semiconductor device according to claim 1, wherein: The virtual storage block includes a core area and a non-core area adjacent to the core area in the second direction, and the second direction intersects with the first direction; The first stacking structure is a step structure in the non-core area, and the first conductive contact is connected to the conductive layer in the step structure.

3. The semiconductor device according to claim 1, wherein: The virtual storage block includes a main area and an edge area adjacent to the main area in a second direction, the main area includes a non-core area and a core area adjacent to the non-core area in the second direction, and the second direction intersects with the first direction; The semiconductor device further comprises: A second stacking structure is located in the non-core area and includes the insulating layers and dielectric layers stacked alternately, wherein the dielectric layers are arranged in the same layer as the conductive layers; Wherein, the first stacking structure is located in the core area and the non-core area, and the first stacking structure in the non-core area is located on both sides of the second stacking structure in the first direction; The first conductive contact is located in the second stacking structure and connected to the conductive layer in the non-core area.

4. The semiconductor device according to claim 3, characterized in that The first conductive contact comprises: a first conductive layer extending along a third direction in the second stacking structure and located on the dielectric layer, wherein the third direction intersects the first direction and the second direction; The connection layer is arranged in the same layer as the dielectric layer and is located at the bottom of the first conductive layer. The connection layer is connected to the conductive layer in the non-core area.

5. The semiconductor device according to claim 4, characterized in that The first conductive contact further comprises: The first isolation layer is located between the first conductive layer and the second stacking structure.

6. The semiconductor device according to claim 3, characterized in that The semiconductor device comprises a plurality of storage blocks arranged along the first direction, the storage blocks comprising the effective storage blocks and the virtual storage blocks, the virtual storage blocks being located outside the effective storage blocks along the first direction; the semiconductor device further comprises: a gate line gap structure, located between two adjacent storage blocks and extending along the second direction, wherein the gate line gap structure comprises a core area gate line gap structure and a non-core area gate line gap structure connected in the second direction, and the core area gate line gap structure extends to the edge area; Wherein, the width of the non-core region gate line gap structure in the first direction is greater than the width of the core region gate line gap structure in the first direction.

7. The semiconductor device according to claim 6, characterized in that The semiconductor device further comprises: a gate line partition structure, penetrating the first stacking structure along a third direction, the third direction intersecting the first direction and the second direction; the gate line partition structure is located in the core area and / or the edge area in the virtual storage area, and extends along the first direction; The second conductive contact is located between two adjacent gate line isolation structures, and the second conductive contact is connected to the conductive layer and the peripheral circuit.

8. The semiconductor device according to claim 7, characterized in that The second conductive contact comprises: A second conductive layer extending along the third direction and having a bottom connected to the conductive layer; The second isolation layer is located between the second conductive layer and the first stacking structure.

9. The semiconductor device according to claim 7, characterized in that The semiconductor device further comprises: A sub-gate line gap structure is located between two adjacent gate line gap structures and is located in the core area and the edge area; Wherein, the sub-gate line gap structures are arranged at intervals along the second direction.

10. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A lead-out structure connected to the first conductive contact; A metal interconnection structure connects the lead-out structure and the peripheral circuit.

11. The semiconductor device according to claim 10, characterized in that The insulating layers and the conductive layers are stacked alternately, and two adjacent conductive layers form two electrodes of a capacitor structure.

12. The semiconductor device according to claim 11, characterized in that The peripheral circuit includes a charge pump circuit, and a plurality of the capacitor structures are connected in parallel via the charge pump circuit.

13. A method for preparing a semiconductor device, characterized in that: The semiconductor device comprises an effective storage block and a virtual storage block adjacent to the effective storage block in a first direction, and the manufacturing method of the semiconductor device comprises: forming a first stacking structure, the first stacking structure being located in the virtual storage block and comprising a stacked insulating layer and a conductive layer; forming a first conductive contact, the first conductive contact connecting the conductive layer; A peripheral circuit is formed on one side of the first stack structure, and the peripheral circuit is electrically connected to the first conductive contact.

14. The method for preparing a semiconductor device according to claim 13, characterized in that: The virtual storage block includes a core area and a non-core area adjacent to the core area in the second direction, and the second direction intersects with the first direction; The step of forming the first conductive contact comprises: Performing an etching process on the first stacked structure in the non-core area to form a step structure; A first conductive contact is formed to connect the conductive layer in the stepped structure.

15. The method for preparing a semiconductor device according to claim 13, characterized in that: The virtual storage block includes a main body area and an edge area adjacent to the main body area in a second direction, the main body area includes a non-core area and a core area adjacent to the non-core area in the second direction, and the second direction intersects with the first direction; The step of forming the first stacking structure includes: forming an initial stacking structure in the non-core region, the core region and the edge region, wherein the initial stacking structure comprises insulating layers and dielectric layers alternately stacked; forming a gate line gap between two adjacent virtual storage blocks, and a sub-gate line gap between two adjacent gate line gaps and located in the core area and the edge area; The dielectric layer is replaced by the gate line gap and the sub-gate line gap to form a first stacking structure and a second stacking structure, wherein the first stacking structure is located in the core area and the non-core area, the second stacking structure is located in the non-core area, and the first stacking structure in the non-core area is located on both sides of the second stacking structure in the first direction.

16. The method for preparing a semiconductor device according to claim 15, characterized in that: The method for preparing the semiconductor device further includes: forming a gate line isolation structure penetrating the first stacking structure along a third direction, wherein the third direction intersects the first direction and the second direction, and the gate line isolation structure is located in the core area and / or the edge area in the virtual storage area and extends along the first direction; A second conductive contact is formed, wherein the second conductive contact is located between two adjacent gate line isolation structures and is connected to the conductive layer.

17. The method for preparing a semiconductor device according to claim 16, characterized in that: The step of forming the second conductive contact and the step of forming the first conductive contact include: Before the replacement process, a first conductive contact is formed in the non-core area, and a second conductive contact is formed between two adjacent gate line isolation structures; The bottoms of the first conductive contacts are each connected to one of the conductive layers, and the bottoms of the second conductive contacts are each connected to one of the conductive layers.

18. The method for preparing a semiconductor device according to claim 17, characterized in that: The step of forming a first conductive contact in the non-core area and forming a second conductive contact between two adjacent gate line isolation structures comprises: Forming a first contact hole in the initial stacking structure in the non-core area, and forming a second contact hole in the initial stacking structure between two adjacent gate line isolation structures, wherein the bottoms of the first contact hole and the second contact hole are both located on the dielectric layer; forming a connection layer disposed at the same layer as the dielectric layer at the bottom of the first contact hole; An isolation layer and a conductive layer are sequentially formed in the first contact hole and the second contact hole to form a first conductive layer connected to the connecting layer in the first contact hole and a second conductive layer connected to the dielectric layer in the second contact hole.

19. The method for preparing a semiconductor device according to claim 13, characterized in that: The method for preparing the semiconductor device further includes: forming a lead-out structure connected to the first conductive contact; forming a metal interconnection structure connected to the lead-out structure, wherein the metal interconnection structure is connected to the peripheral circuit; The insulating layers and the conductive layers are stacked alternately, and two adjacent conductive layers constitute two electrodes of a capacitor structure; the peripheral circuit includes a charge pump circuit, and a plurality of capacitor structures are connected in parallel through the charge pump circuit.

20. A storage system, characterized in that: include: The semiconductor device according to any one of claims 1 to 12; A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

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