Ring-gate field-effect transistor, manufacturing method thereof, chip and electronic device

Abstract

This disclosure relates to the field of semiconductor technology, specifically to a gate-all-around field-effect transistor, its fabrication method, chip, and electronic device. The fabrication method includes: growing vertical nanowires vertically on a substrate; after the vertical nanowires grow to a predetermined height, changing the nanowire growth direction and laterally growing a source, channel, and drain; and depositing a layer of gate dielectric material surrounding the vertical nanowires, source, channel, and drain, and etching to obtain a gate dielectric layer. The gate dielectric layer surrounds the channel. This technical solution can reduce manufacturing difficulty and production costs, and is primarily used to fabricate gate-all-around field-effect transistors.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a gate-all-around field-effect transistor, a preparation method thereof, a chip, and an electronic device. Background Art

[0002] As chip integration continues to increase, the size of semiconductor devices must also be continuously reduced according to the principle of proportional scaling. Currently, the gate-all-around field-effect transistor (GAAFET) is attracting much attention. Its characteristic is that the surface of the channel region is surrounded by the gate, which has stronger gate control capabilities and a larger effective channel width. Due to its steep subthreshold swing (SS), quasi-ballistic transmission, and one-dimensional channel structure, it is more conducive to further improving device driving capabilities. Therefore, gate-all-around field-effect transistor devices are considered to be the next-generation mainstream devices for 3nm process nodes and below.

[0003] Currently, the gate-all-around structure of a gate-all-around field-effect transistor (GFET) is typically achieved by growing a layered structure of channel material and other materials, followed by etching to create a suspended channel. The dielectric material is then grown to create the GFET. For example, a nanosheet-type GFET is achieved by growing Si and SiGe in layers, then removing the SiGe using an isotropic etching method to create a suspended channel. The multiple growth and etching steps required to form the suspended channel significantly increase the complexity of the process, the difficulty of manufacturing, and the production cost of the product. Summary of the Invention

[0004] In order to solve the problems in the related art, the embodiments of the present disclosure provide a gate-all-around field-effect transistor, a method for manufacturing the same, a chip, and an electronic device.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for preparing a gate-all-around field-effect transistor, comprising:

[0006] Growing vertical nanowires vertically on a substrate;

[0007] After the vertical nanowire grows to a predetermined height, the nanowire growth direction is changed at the predetermined height to laterally grow a source electrode, a channel electrode, and a drain electrode;

[0008] A layer of gate dielectric material surrounding the vertical nanowire, source, channel and drain is deposited, and then etched to obtain a gate dielectric layer, wherein the gate dielectric layer surrounds the channel.

[0009] In one possible implementation, the vertically growing vertical nanowires on the substrate includes:

[0010] Epitaxial growth technology is used to grow vertical nanowires vertically on the substrate;

[0011] The laterally growing the source, channel and drain comprises:

[0012] The source, channel and drain are grown laterally using epitaxial technology.

[0013] In a possible implementation, the laterally growing the source, the channel, and the drain includes:

[0014] First, the source electrode is grown laterally using the source electrode material, and then the channel electrode is grown laterally using the channel electrode material, and then the drain electrode is grown laterally using the drain electrode material.

[0015] In one possible embodiment, the material of the vertical nanowire, the source material, the channel material, and the drain material all include Group III-V materials.

[0016] In a possible implementation, the source electrode material and the drain electrode material are one III-V group material, and the channel material is another different III-V group material.

[0017] In one possible embodiment, the doping elements in the source material and the drain material are of the first conductivity type, and the doping elements in the channel material are of the second conductivity type. When the first conductivity type is N-type, the second conductivity type is P-type; or, when the first conductivity type is P-type, the second conductivity type is N-type.

[0018] In a possible implementation, in the process of laterally growing the source electrode using the source electrode material, the doping concentration of the doping element in the source electrode material is adjusted;

[0019] In the process of continuing to laterally grow a channel using the channel material, adjusting the doping concentration of the doping element in the channel material;

[0020] In the process of continuing to laterally grow the drain electrode using the drain electrode material, the doping concentration of the doping element in the drain electrode material is adjusted.

[0021] In one possible implementation, the method further includes:

[0022] Forming a source sidewall and a drain sidewall on both sides of the gate dielectric layer, wherein the source sidewall is located on the source side, and the drain sidewall is located on the drain side;

[0023] depositing an insulating layer, wherein the insulating layer covers the structure on the substrate;

[0024] Etching the insulating layer in regions corresponding to the source and drain electrodes respectively by an etching process to form a source through hole and a drain through hole;

[0025] Interconnect lines are deposited at the source and drain vias.

[0026] In a second aspect, an embodiment of the present disclosure provides a gate-all-around field-effect transistor, which is prepared using the method for preparing a gate-all-around field-effect transistor according to any one of the first aspects, wherein the gate-all-around field-effect transistor comprises:

[0027] substrate;

[0028] A nanowire located on the substrate, the nanowire comprising a vertical nanowire and a lateral nanowire, the lateral nanowire comprising three sections of nanowires, namely a source, a channel and a drain;

[0029] The gate dielectric layer is located around the channel.

[0030] In a possible implementation, the gate-all-around field-effect transistor further includes:

[0031] A source sidewall and a drain sidewall located on both sides of the gate dielectric layer, wherein the source sidewall is located on the source side, and the drain sidewall is located on the drain side;

[0032] an insulating layer, the insulating layer covering the structure on the substrate and provided with a source through hole and a drain through hole in regions corresponding to the source and drain;

[0033] Interconnection lines are located at the source through hole and the drain through hole, and are connected to the source and the drain respectively.

[0034] In a third aspect, an embodiment of the present disclosure provides a chip comprising the above-mentioned ring-gate field-effect transistor.

[0035] In a fourth aspect, an embodiment of the present disclosure provides an electronic device comprising the above-mentioned ring-gate field-effect transistor.

[0036] According to the technical solution provided by the embodiment of the present disclosure, vertical nanowires can be grown vertically on a substrate; after the vertical nanowires grow to a predetermined height, the growth direction of the nanowires is changed, and a source, a channel, and a drain are grown laterally; a layer of gate dielectric material surrounding the vertical nanowires, the source, the channel, and the drain is deposited, and etching is performed to obtain a gate dielectric layer, wherein the gate dielectric layer is located around the channel, thereby forming a ring-gate structure of a ring-gate field-effect transistor. Through the self-growth of the laterally suspended nanowires, the grown laterally nanowires can be directly used as suspended channels in the ring gate, thereby eliminating the repeated steps of etching after growth to produce suspended channels, thereby simplifying the preparation process and reducing the manufacturing difficulty and production cost; and because the surface of the nanowires has atomic-level smoothness that cannot be achieved by traditional etching methods, carrier scattering caused by surface roughness can be greatly reduced.

[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0039] Figure 1 A flow chart of a method for preparing a gate-all-around field-effect transistor provided by an embodiment of the present disclosure is shown.

[0040] Figure 2 A schematic diagram of the growth process of a nanowire provided by an embodiment of the present disclosure is shown.

[0041] Figure 3 A flow chart for preparing a gate-all-around field-effect transistor provided by an embodiment of the present disclosure is shown.

[0042] Figure 4 A schematic structural diagram of a gate-all-around field-effect transistor provided by an embodiment of the present disclosure is shown.

[0043] Figure 5 A schematic structural diagram of another gate-all-around field-effect transistor provided in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0044] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0045] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof exist or are added.

[0046] It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0047] Figure 1 A flow chart of a method for preparing a gate-all-around field effect transistor according to an embodiment of the present disclosure is shown. Figure 1 As shown, the preparation method includes the following steps S101-S103:

[0048] In step S101 , vertical nanowires are grown vertically on a substrate;

[0049] In step S102, after the vertical nanowire grows to a predetermined height, the nanowire growth direction is changed to grow a source, a channel, and a drain laterally;

[0050] In step S103 , a layer of gate dielectric material surrounding the vertical nanowire, the source, the channel and the drain is deposited, and then etched to obtain a gate dielectric layer, wherein the gate dielectric layer surrounds the channel.

[0051] In one possible embodiment, the substrate of the ring-gate field-effect transistor can be a silicon substrate, which can be made of silicon (Si) or silicon-based materials. In some cases, in order to improve the performance of the device, other materials such as silicon germanium (SiGe) or germanium nitride (GaN) may be used to prepare the substrate, which is not limited here.

[0052] In one possible embodiment, nanowires (NWs) are one-dimensional structures that are confined to less than 100 nanometers in the lateral direction (no confinement in the longitudinal direction). Figure 2 A schematic diagram of a nanowire growth process provided by an embodiment of the present disclosure is shown. Figure 2 The direction of the arrow in the figure is the growth direction of the nanowires, which can be grown on the substrate as shown in the figure. Figure 2 As shown in FIG, a vertical nanowire 11 is first grown vertically. After the vertical nanowire 11 grows to a predetermined height, the nanowire growth direction is changed to grow horizontally to form a horizontal nanowire. The horizontal nanowire is divided into three sections: a source 12, a channel 13, and a drain 14. The channel 13 is located between the source 12 and the drain 14. The positions of the source and the drain can be as follows: Figure 2 As shown, they can also be interchanged, without limitation. Figure 2 The example shown is to generate the source 12 first, and then generate the channel 13 and the drain 14 in sequence; in this way, through the self-growth of the lateral nanowires, the grown lateral nanowires can directly serve as the suspended channel 13 in the ring gate structure, so that the repeated steps of etching after growth to produce the suspended channel in the prior art can be omitted, thereby simplifying the manufacturing steps and reducing the manufacturing difficulty and production cost. It should be noted that the predetermined height of the vertical nanowire 11 can be set according to actual needs. The vertical here refers to perpendicular to the substrate. The lateral nanowires are parallel to the substrate and perpendicular to the vertical nanowires.

[0053] In one possible implementation, Figure 3 A flow chart of manufacturing a gate-all-around field effect transistor according to an embodiment of the present disclosure is shown. Figure 3As shown, after the vertical nanowire 11 and the lateral source 12, channel 13 and drain 14 are prepared on the substrate 10, a layer of gate dielectric material 15 such as a high dielectric constant (High-K) material can be deposited to surround the vertical nanowire 11, source 12, channel 13 and drain 14, and the dielectric layer around the source 12 and drain 14 is etched away, leaving only the gate dielectric material around the channel 13 to form a gate dielectric layer 150, as shown in FIG. Figure 3 As shown, the gate dielectric layer 150 is directly above and below the channel 13, as well as directly in front of and behind the channel 13 ( Figure 3 (Not shown in the figure, the left and right sides of the channel 13 are the source and drain) Thus, a ring-gate structure of the ring-gate field effect transistor is formed.

[0054] This embodiment can vertically grow a vertical nanowire 11 on a substrate; after the vertical nanowire 11 grows to a predetermined height, the nanowire growth direction is changed, and a source 12, a channel 13 and a drain 14 are laterally grown; a layer of gate dielectric material surrounding the vertical nanowire 11, the source 12, the channel 13 and the drain 14 is deposited, and a gate dielectric layer 150 is obtained by etching. The gate dielectric layer 150 is located around the channel 13, thereby forming a ring-gate structure of a ring-gate field-effect transistor. Through the self-growth of the laterally suspended nanowire, the grown lateral nanowire can be directly used as the suspended channel 13 in the ring gate, thereby eliminating the repeated steps of etching after growth to produce the suspended channel, thereby simplifying the preparation process and reducing the manufacturing difficulty and production cost; and because the surface of the nanowire has atomic-level smoothness that cannot be achieved by traditional etching methods, the carrier scattering caused by surface roughness can be greatly reduced.

[0055] In one possible implementation, the vertically growing vertical nanowires on the substrate includes:

[0056] Epitaxial growth technology is used to grow vertical nanowires vertically on the substrate;

[0057] The laterally growing the source, channel and drain comprises:

[0058] The source, channel and drain are grown laterally using epitaxial technology.

[0059] In this embodiment, epitaxy is a material growth technique that precisely controls the growth length, growth direction, and doping concentration. This epitaxy allows for the precise growth of vertical nanowires 11 perpendicular to the substrate and of a predetermined height. The vertical nanowires 11 can be made of materials such as gallium arsenide and do not require impurity doping. When growing the source 12, channel 13, and drain 14, this epitaxy allows for the precise growth of lateral sources 12, channels 13, and drains 14 of predetermined lengths and doping concentrations.

[0060] In a possible implementation, the laterally growing the source, the channel, and the drain includes:

[0061] First, the source electrode is grown laterally using the source electrode material, and then the channel electrode is grown laterally using the channel electrode material, and then the drain electrode is grown laterally using the drain electrode material.

[0062] In this embodiment, the lateral nanowires are grown little by little. During the growth process of the lateral nanowires, the growth material of the nanowires can be changed. The source electrode is first grown laterally using the source electrode material, and then the channel electrode is continued to be grown laterally using the channel electrode material, and then the drain electrode is continued to be grown laterally using the drain electrode material.

[0063] In one possible embodiment, the material of the vertical nanowire, the source material, the channel material, and the drain material all include Group III-V materials.

[0064] In this embodiment, the III-V group material is a compound composed of Group III elements (such as boron, aluminum, gallium, indium, and thallium) and Group V elements (such as nitrogen, phosphorus, arsenic, antimony, and bismuth) in the periodic table, such as gallium arsenide (GaAs), indium phosphide (InP), and gallium nitride.

[0065] When vertical and lateral nanowires are made of III-V materials, the carrier mobility of the nanowires is greatly improved, which can be 4-60 times higher than that of existing Si.

[0066] In a possible implementation, the source electrode material and the drain electrode material are one III-V group material, and the channel material is another different III-V group material.

[0067] In this embodiment, the nanowire growth material can be changed during growth, allowing the advantages of different materials to be simultaneously utilized, resulting in a device with better performance and enhanced overall capabilities. When the properties of one III-V material are more suitable for the source 12 and drain 14, while the properties of another III-V material are more suitable for the channel 13, the nanowire growth material can be adjusted to directly grow both materials in appropriate locations. This maximizes the performance of both materials, allowing the device to combine the advantages of two different materials and achieve better overall performance.

[0068] For example, gallium arsenide can be used as the source and drain materials, and indium phosphide can be used as the channel material. First, gallium arsenide is used to grow the source 12, then indium phosphide is used to grow the channel 13, and finally, gallium arsenide is used to grow the drain 14. Gallium arsenide has a much higher electron mobility than traditional semiconductor materials such as silicon, allowing electrons to travel faster through the material, which helps improve device performance. Indium phosphide has a high saturated electron drift velocity, which is very important for improving the device's response speed and frequency characteristics. Using these two materials to prepare lateral nanowires can combine the advantages of both materials and improve the overall performance of the device.

[0069] In one possible embodiment, the doping elements in the source material and the drain material are of the first conductivity type, and the doping elements in the channel material are of the second conductivity type. When the first conductivity type is N-type, the second conductivity type is P-type; or, when the first conductivity type is P-type, the second conductivity type is N-type.

[0070] In this embodiment, the composition of the doping elements in the growing material can be adjusted during the growth of the source 12, channel 13, and drain 14, so that the doping steps of the source 12, channel 13, and drain 14 can be achieved during the nanowire growth. For example, a P-type element can be doped when the source 12 is grown, an N-type element can be doped when the channel 13 is grown, and the doping can be switched back to the P-type element when the drain 14 is grown, thus obtaining a PNP transistor. Of course, an N-type element can also be doped when the source 12 is grown, a P-type element can be doped when the channel 13 is grown, and the doping can be switched back to the N-type element when the drain 14 is grown, thus obtaining an NPN transistor.

[0071] This embodiment can perform impurity doping while growing the nanowires. Compared with the prior art which requires ion implantation for doping, the doping steps are simpler.

[0072] In one possible embodiment, in the process of laterally growing a source electrode using a source electrode material, the doping concentration of the doping element in the source electrode material is adjusted; in the process of continuing to laterally grow a channel using a channel electrode material, the doping concentration of the doping element in the channel electrode material is adjusted; and in the process of continuing to laterally grow a drain electrode using a drain electrode material, the doping concentration of the doping element in the drain electrode material is adjusted.

[0073] In this embodiment, during the growth of the source 12, channel 13, and drain 14, the concentration of the doping element can be adjusted as needed. For example, during the growth of the source 12, the concentration of the doping element can be first configured to a first concentration. After growing a section of the source, the concentration of the doping element can be adjusted to a second concentration that is a predetermined value higher than the first concentration. After growing another section of the source, the concentration of the doping element can be further adjusted to a third concentration that is a predetermined value higher than the second concentration to grow another section of the source. Alternatively, during the growth of the source 12, the concentration of the doping element can be first configured to a first concentration. After growing a section of the source, the concentration of the doping element can be further adjusted to a second concentration that is a predetermined value higher than the first concentration. After growing another section of the source, the concentration of the doping element can be further adjusted down to the first concentration to grow another section of the source. The doping concentration of the doping element in the source material can be adjusted according to different device requirements. Similarly, the doping concentration of the doping element in the channel material can be adjusted during the growth of the channel; and the doping concentration of the doping element in the drain material can be adjusted during the growth of the drain.

[0074] In this embodiment, impurity doping is performed while the nanowires are being grown, so that the doping concentration and position can be controlled more precisely.

[0075] In one possible implementation, the method further includes:

[0076] Forming a source sidewall and a drain sidewall on both sides of the gate dielectric layer, wherein the source sidewall is located on the source side, and the drain sidewall is located on the drain side;

[0077] depositing an insulating layer, wherein the insulating layer covers the structure on the substrate;

[0078] Etching the insulating layer in regions corresponding to the source and drain electrodes respectively by an etching process to form a source through hole and a drain through hole;

[0079] Interconnect lines are deposited at the source and drain vias.

[0080] In this embodiment, if Figure 3 As shown, a source sidewall 161 and a drain sidewall 162 can be formed on both sides of the gate dielectric layer 150, the source sidewall 161 is located on the side of the source 12, and the drain sidewall 162 is located on the side of the drain 14; the source sidewall 161 provides physical isolation between the gate and the source level, and the drain sidewall 162 provides physical isolation between the gate and the drain, which can prevent current from leaking from the gate to the source / drain region, thereby reducing leakage current. At the same time, the sidewall enhances the structural stability of the device and prevents damage to the gate structure due to mechanical stress during the manufacturing process or during use.

[0081] In this embodiment, the source through hole 181 and the drain through hole 182 are located in the region of the insulating layer 17 corresponding to the source 12 and the drain 14, and are used to respectively connect the source 12 and the drain 14 regions with the metal interconnection lines of the upper layer, thereby realizing vertical transmission of current; the interconnection lines can be metal wires, used to connect the source 12 and the drain 14 to form a circuit network.

[0082] The present disclosure also provides a gate-all-around field-effect transistor, which is prepared using the above-mentioned method for preparing the gate-all-around field-effect transistor. Figure 4 FIG. 1 shows a schematic structural diagram of a gate-all-around field effect transistor provided by an embodiment of the present disclosure, such as Figure 4 As shown, the gate-all-around field effect transistor includes:

[0083] substrate 10;

[0084] The nanowires are located on the substrate 10, and the nanowires include vertical nanowires 11 and lateral nanowires. The lateral nanowires include three sections of nanowires: a source 12, a channel (not shown) and a drain 14. The channel is located between the source 12 and the drain 14. The positions of the source and the drain can be as follows: Figure 4 As shown, they can also be interchanged and are not limited here; the vertical here refers to perpendicular to the substrate, the lateral nanowires are parallel to the substrate and perpendicular to the vertical nanowires;

[0085] The gate dielectric layer 150 is located around the channel 13 .

[0086] In this embodiment, the self-growth of lateral nanowires can directly serve as suspended channels in the ring gate, thus eliminating the repeated steps of etching after growth to produce suspended channels, thereby simplifying the preparation process and reducing manufacturing difficulty and production costs; and because the surface of the nanowires has atomic-level smoothness that cannot be achieved by traditional etching methods, the carrier scattering caused by surface roughness can be greatly reduced.

[0087] In one possible implementation, Figure 5 FIG. 1 shows a schematic structural diagram of another gate-all-around field effect transistor provided by an embodiment of the present disclosure, such as Figure 5 As shown, the gate-all-around field effect transistor further includes:

[0088] A source sidewall spacer 161 and a drain sidewall spacer 162 located on both sides of the gate dielectric layer 150 , wherein the source sidewall spacer 161 is located on one side of the source 12 , and the drain sidewall spacer 162 is located on one side of the drain 14 ;

[0089] an insulating layer 171 , the insulating layer covering the structure on the substrate and provided with a source through hole 181 and a drain through hole 182 in regions corresponding to the source electrode 12 and the drain electrode 14 ;

[0090] Interconnection lines are located at the source through hole 181 and the drain through hole 182 , and are connected to the source 12 and the drain 14 respectively.

[0091] In this embodiment, if Figure 5 As shown, source sidewalls and drain sidewalls can be set on both sides of the gate dielectric layer 150, the source sidewall is located on the side of the source 12, and the drain sidewall is located on the side of the drain 14; the source sidewall provides physical isolation between the gate and the source level, and the drain sidewall provides physical isolation between the gate and the drain 14, which can prevent current from leaking from the gate to the source / drain region, thereby reducing leakage current. At the same time, the sidewalls enhance the structural stability of the device and prevent damage to the gate structure due to mechanical stress during the manufacturing process or during use.

[0092] In this embodiment, the through-hole is used to connect the source 12 and drain 14 regions with the upper metal interconnection line, thereby realizing vertical transmission of current; the interconnection line can be a metal wire used to connect the source 12 and drain 14 to form a circuit network.

[0093] The embodiments of the present disclosure also provide a chip including the above-mentioned gate-all-around field-effect transistor, and an electronic device including the above-mentioned gate-all-around field-effect transistor.

[0094] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the inventive concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in this disclosure.

Claims

1. A method for preparing a gate-all-around field-effect transistor, characterized in that: include: Growing vertical nanowires vertically on a substrate; After the vertical nanowire grows to a predetermined height, the nanowire growth direction is changed at the predetermined height to laterally grow a source electrode, a channel electrode, and a drain electrode; the source electrode, the channel electrode, and the drain electrode are three sections of nanowires, the source electrode material and the drain electrode material of the source electrode are a group III-V material, and the channel material of the channel electrode is another different group III-V material; A layer of gate dielectric material surrounding the vertical nanowire, source, channel and drain is deposited, and the gate dielectric material around the source and drain is etched away to obtain a gate dielectric layer, wherein the gate dielectric layer surrounds the channel.

2. The preparation method according to claim 1, characterized in that The vertically growing vertical nanowires on the substrate comprises: Epitaxial growth technology is used to grow vertical nanowires vertically on the substrate; The laterally growing the source, channel and drain comprises: The source, channel and drain are grown laterally using epitaxial technology.

3. The preparation method according to claim 1, characterized in that The laterally growing the source, channel and drain comprises: First, the source electrode is grown laterally using the source electrode material, and then the channel electrode is grown laterally using the channel electrode material, and then the drain electrode is grown laterally using the drain electrode material.

4. The preparation method according to claim 3, characterized in that The doping elements in the source material and the drain material are of the first conductivity type, and the doping elements in the channel material are of the second conductivity type. When the first conductivity type is N-type, the second conductivity type is P-type; or when the first conductivity type is P-type, the second conductivity type is N-type.

5. The preparation method according to claim 4, characterized in that In the process of laterally growing the source electrode using the source electrode material, adjusting the doping concentration of the doping element in the source electrode material; In the process of continuing to laterally grow a channel using the channel material, adjusting the doping concentration of the doping element in the channel material; In the process of continuing to laterally grow the drain electrode using the drain electrode material, the doping concentration of the doping element in the drain electrode material is adjusted.

6. The preparation method according to claim 1, characterized in that The method further comprises: Forming a source sidewall and a drain sidewall on both sides of the gate dielectric layer, wherein the source sidewall is located on the source side, and the drain sidewall is located on the drain side; depositing an insulating layer, wherein the insulating layer covers the structure on the substrate; Etching the insulating layer in regions corresponding to the source and drain electrodes respectively by an etching process to form a source through hole and a drain through hole; Interconnect lines are deposited at the source and drain vias.

7. A gate-all-around field-effect transistor, characterized in that: The gate-all-around field-effect transistor is prepared by the method for preparing the gate-all-around field-effect transistor according to any one of claims 1 to 6, wherein the gate-all-around field-effect transistor comprises: substrate; A nanowire located on the substrate, the nanowire comprising a vertical nanowire and a lateral nanowire, the lateral nanowire comprising three sections of nanowires: a source, a channel, and a drain; the source material of the source and the drain material of the drain are a group III-V material, and the channel material of the channel is another different group III-V material; The gate dielectric layer is located around the channel.

8. The gate-all-around field-effect transistor according to claim 7, wherein: Also includes: A source sidewall and a drain sidewall located on both sides of the gate dielectric layer, wherein the source sidewall is located on the source side, and the drain sidewall is located on the drain side; an insulating layer, the insulating layer covering the structure on the substrate and provided with a source through hole and a drain through hole in regions corresponding to the source and drain; Interconnection lines are located at the source through hole and the drain through hole, and are connected to the source and the drain respectively.

9. A chip, characterized in that: The gate-all-around field-effect transistor according to claim 7 or 8 is included.

10. An electronic device, characterized in that: The gate-all-around field-effect transistor according to claim 7 or 8 is included.

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