P-channel gallium nitride transistor and preparation method thereof

Abstract

The invention discloses a p-channel gallium nitride transistor and a preparation method thereof, and relates to the technical field of microelectronics. The p-channel gallium nitride transistor comprises a substrate; a barrier layer; the p-type gallium nitride layer comprises a first groove, a first bulge and a second bulge, the first bulge and the second bulge are positioned on two opposite sides of the first groove, and the thickness L1 of the bottom of the first groove is more than or equal to 10nm and less than or equal to 15nm; the zinc oxide layer is located in the first groove; the electrode structure comprises a source electrode, a grid electrode and a drain electrode, the source electrode is located on the side, away from the substrate, of the first protrusion, the drain electrode is located on the side, away from the substrate, of the second protrusion, and the grid electrode is located in the first groove and located on the side, away from the p-type gallium nitride layer, of the zinc oxide layer. According to the technical scheme of the invention, the zinc oxide layer is arranged between the grid electrode and the p-type gallium nitride layer, so that a relatively high threshold voltage of the transistor can be ensured, and a relatively high on-state current can be ensured at the same time, thereby improving the stability and electrical performance of the transistor.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of semiconductor devices, and in particular to a p-channel gallium nitride transistor and a method for preparing the same. Background Art

[0002] P-channel GaN transistors are particularly important for realizing complementary logic circuits and have broad application prospects. To realize an enhanced p-channel GaN transistor, the p-layer GaN layer needs to be etched to a specific thickness to form a depletion region to deplete the two-dimensional hole gas (2DHG) and turn off the device.

[0003] Among them, etching the p-type GaN layer to a certain thickness can effectively enhance the depletion effect of the channel and achieve a higher threshold voltage under zero gate bias. However, etching too much p-type GaN layer will reduce the on-state current of the p-channel GaN transistor, which has a significant negative impact on the complementary logic circuit. Therefore, it is urgent to solve the technical problem of reducing the on-state current of the transistor caused by etching the p-type GaN layer. Summary of the invention

[0004] The present invention provides a p-channel gallium nitride transistor and a preparation method thereof, so as to achieve a higher on-state current while ensuring a larger threshold voltage of the transistor, thereby improving the stability and electrical performance of the transistor.

[0005] A first aspect of the present invention provides a p-channel gallium nitride transistor, the p-channel gallium nitride transistor comprising:

[0006] substrate;

[0007] A barrier layer, located on one side of the substrate;

[0008] A p-type gallium nitride layer is located on a side of the barrier layer away from the substrate; the p-type gallium nitride layer and the barrier layer form a hole heterojunction structure; the p-type gallium nitride layer includes a first groove, and a first protrusion and a second protrusion located on opposite sides of the first groove; a value range of a groove bottom thickness L1 of the first groove is: 10nm≤L1≤15nm;

[0009] a zinc oxide layer, located in the first groove;

[0010] The electrode structure comprises a source, a gate and a drain; the source is located on a side of the first protrusion away from the substrate, and the drain is located on a side of the second protrusion away from the substrate; the gate is located in the first groove and on a side of the zinc oxide layer away from the p-type gallium nitride layer.

[0011] Optionally, a thickness L2 of the p-type gallium nitride layer at the first protrusion and / or the second protrusion is in the range of 70 nm≤L2≤75 nm.

[0012] Optionally, the thickness L3 of the zinc oxide layer has a value range of 3nm≤L3≤10nm.

[0013] Optionally, the p-type gallium nitride layer includes a first p-type gallium nitride layer and a second p-type gallium nitride layer which are stacked, and the first p-type gallium nitride layer is located on a side of the second p-type gallium nitride layer close to the substrate;

[0014] The first groove penetrates the second P-type gallium nitride layer and a portion of the first P-type gallium nitride layer.

[0015] Optionally, a doping concentration of the second p-type gallium nitride layer is greater than a doping concentration of the first p-type gallium nitride layer.

[0016] A second aspect of the present invention provides a method for preparing a p-channel gallium nitride transistor, the method for preparing the p-channel gallium nitride transistor comprising:

[0017] providing a substrate;

[0018] forming a barrier layer on one side of the substrate;

[0019] forming a p-type gallium nitride layer on a side of the barrier layer away from the substrate; the p-type gallium nitride layer and the barrier layer form a hole heterojunction structure;

[0020] Patterning the p-type gallium nitride layer to form a first groove and a first protrusion and a second protrusion located on opposite sides of the first groove in the p-type gallium nitride layer; wherein a value range of a groove bottom thickness L1 of the first groove is: 10nm≤L1≤15nm;

[0021] forming a source electrode on a side of the first protrusion away from the substrate, and forming a drain electrode on a side of the second protrusion away from the substrate;

[0022] forming a zinc oxide layer in the first groove;

[0023] A gate is formed on a side of the zinc oxide layer away from the p-type gallium nitride layer.

[0024] Optionally, patterning the p-type gallium nitride layer to form a first groove and a first protrusion and a second protrusion located on opposite sides of the first groove in the p-type gallium nitride layer includes:

[0025] Etching the p-type gallium nitride layer using an inductively coupled plasma etching technique to form a first groove, and a first protrusion and a second protrusion located on two opposite sides of the first groove in the p-type gallium nitride layer;

[0026] Wherein, the plasma used in the inductively coupled plasma etching technology includes at least one of Cl2 and BCl3.

[0027] Optionally, forming a source electrode on a side of the first protrusion away from the substrate, and forming a drain electrode on a side of the second protrusion away from the substrate, comprises:

[0028] Using an electron beam evaporation process to form a first metal structure on a side of the first protrusion away from the substrate, and to form a second metal structure on a side of the second protrusion away from the substrate;

[0029] The first metal structure and the second metal structure are annealed by an annealing process to respectively form the source electrode located at a side of the first protrusion away from the substrate and the drain electrode located at a side of the second protrusion away from the substrate.

[0030] Optionally, forming a zinc oxide layer in the first groove includes:

[0031] Using magnetron sputtering technology to form a zinc oxide film layer covering the first protrusion, the second protrusion and the first groove on a side of the p-type gallium nitride layer away from the substrate;

[0032] The zinc oxide film layer is patterned to remove the zinc oxide film layer at the first protrusion and the second protrusion, and the zinc oxide film layer located in the first groove is retained to form a zinc oxide layer located in the first groove.

[0033] Optionally, forming a p-type gallium nitride layer on a side of the barrier layer away from the substrate comprises:

[0034] forming the first P-type gallium nitride layer on a side of the barrier layer away from the substrate;

[0035] The second p-type gallium nitride layer is formed on a side of the first p-type gallium nitride layer away from the barrier layer.

[0036] The technical solution provided by the present invention is to sequentially arrange a barrier layer and a p-type gallium nitride layer on one side of a substrate of a p-channel gallium nitride transistor, so that the p-type gallium nitride layer and the barrier layer form a hole heterojunction structure, in which two-dimensional hole gas is formed, and after patterning the p-type gallium nitride layer, a depletion region consisting of a first groove and a first protrusion and a second protrusion located on opposite sides of the first groove is formed, and the depletion region depletes the two-dimensional hole gas, thereby realizing the shutdown function of the p-channel gallium nitride transistor. At the same time, the groove bottom thickness L1 of the first groove is set between 10nm and 15nm, and a zinc oxide layer is set in the first groove, a source electrode is set on the side of the first protrusion away from the substrate, a drain electrode is set on the side of the second protrusion away from the substrate, and a gate is set in the first groove and on the side of the zinc oxide layer away from the p-type gallium nitride layer. At this time, the built-in electric field of the PN junction formed by the zinc oxide layer and the p-type gallium nitride layer can offset the electric field of hole carriers formed in part of the p-channel gallium nitride transistor, thereby enhancing the depletion capacity of hole carriers, so that when less p-type gallium nitride layers are patterned, the turn-off capacity of the depletion region formed when more p-type gallium nitride layers are patterned can still be achieved, and the problem of reduced on-state current when more p-type gallium nitride layers are patterned is avoided, thereby ensuring that the p-channel gallium nitride transistor has better turn-off capability, that is, has a higher threshold voltage, and can ensure that the p-channel gallium nitride transistor has a higher on-state current, thereby improving the stability and electrical performance of the transistor.

[0037] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0039] Figure 1 is a schematic diagram of a device structure of a p-channel gallium nitride transistor provided in an embodiment of the present invention;

[0040] Figure 2 is a schematic diagram of the device structure of another p-channel gallium nitride transistor provided by an embodiment of the present invention;

[0041] Figure 3 It is a flow chart of a method for preparing a p-channel gallium nitride transistor provided by an embodiment of the present invention;

[0042] Figure 4is a process flow chart of manufacturing a p-channel gallium nitride transistor provided by an embodiment of the present invention;

[0043] Figure 5 is a flow chart of another method for preparing a p-channel gallium nitride transistor provided by an embodiment of the present invention;

[0044] Figure 6 It is a process flow chart of another preparation process of a p-channel gallium nitride transistor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] Figure 1 is a schematic diagram of a device structure of a p-channel gallium nitride transistor provided by an embodiment of the present invention, such as Figure 1As shown, a p-channel gallium nitride transistor is characterized in that it includes: a substrate 1; a barrier layer 2, located on one side of the substrate 1; a p-type gallium nitride layer 3, located on a side of the barrier layer 2 away from the substrate 1; the p-type gallium nitride layer 3 and the barrier layer 2 form a hole heterojunction structure; the p-type gallium nitride layer 3 includes a first groove 301, and a first protrusion 302 and a second protrusion 303 located on opposite sides of the first groove 301; the value range of the groove bottom thickness L1 of the first groove 301 is: 10nm≤L1≤15nm; a zinc oxide layer 4, located in the first groove 301; an electrode structure 5, including a source 501, a gate 502 and a drain 503; the source 501 is located on a side of the first protrusion 302 away from the substrate 1, and the drain 503 is located on a side of the second protrusion 303 away from the substrate 1; the gate 502 is located in the first groove 301 and on a side of the zinc oxide layer 4 away from the p-type gallium nitride layer 3.

[0048] Among them, the substrate 1 can be specifically understood as a material that supports the device structure of the entire p-channel gallium nitride transistor. Exemplarily, the substrate 1 can be a combination of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material that can grow group III nitrides.

[0049] A barrier layer 2 is disposed on one side of the substrate 1. The barrier layer 2 may be specifically understood as a special material layer that limits carrier transmission by forming a barrier structure. Exemplarily, the material of the barrier layer 2 may be AlGaN or GaN.

[0050] A p-type gallium nitride layer 3 is disposed on the side of the barrier layer 2 away from the substrate 1. The p-type gallium nitride layer 3 forms a hole heterojunction structure with the barrier layer 2. A two-dimensional hole gas is formed in the hole heterojunction structure. The two-dimensional hole gas can be used as a conductive medium in the p-channel gallium nitride transistor. At the same time, due to the large band gap width of the barrier layer 2, a stable energy level structure is formed between the barrier layer 2 and the p-type gallium nitride layer 3 interface. The energy level structure can prevent the two-dimensional hole gas from freely diffusing and drifting in the p-channel gallium nitride transistor, thereby effectively confining the two-dimensional hole gas in the region between the barrier layer 2 and the p-type gallium nitride layer 3, and it will not easily escape or be lost, thereby helping to maintain the performance stability and reliability of the p-channel gallium nitride transistor.

[0051] After the p-type gallium nitride layer 3 is patterned, a first groove 301 and a first protrusion 302 and a second protrusion 303 located on opposite sides of the first groove 301 can be formed. It can be understood that the first groove 301 and the first protrusion 302 and the second protrusion 303 located on opposite sides of the first groove 301 will form a depletion region, which will deplete the two-dimensional hole gas and realize the shutdown function of the p-channel gallium nitride transistor. Among them, the patterning degree of the p-type gallium nitride layer 3 will affect the depletion capacity of the depletion region for the two-dimensional hole gas. Generally, the deeper the depth and the larger the area of ​​the first groove in the p-type gallium nitride layer 3, the stronger the depletion capacity for the two-dimensional hole gas. However, when the depth and the area of ​​the first groove in the p-type gallium nitride layer 3 are deeper, the channel of the carriers allowed to pass through the p-type gallium nitride layer 3 is smaller, thereby resulting in a decrease in the on-state current of the p-channel gallium nitride transistor. In this embodiment, the value range of the groove bottom thickness L1 of the first groove 301 is set to 10nm≤L1≤15nm, so that the channel of carriers allowed to pass through the patterned p-type gallium nitride layer 3 is large enough; at the same time, a zinc oxide layer 4 is provided in the first groove 301, and the material of the zinc oxide layer 4 is an N-type material. A PN junction is formed between the zinc oxide layer 4 and the p-type gallium nitride at the groove bottom of the first groove 301. The built-in electric field direction of the PN junction is opposite to the electric field direction of the hole carriers formed in the p-channel gallium nitride transistor. Therefore, the built-in electric field of the PN junction formed by the zinc oxide layer 4 and the p-type gallium nitride can offset part of the electric field forming the hole carriers, thereby reducing the density of the hole carriers, enhancing the depletion capability of the hole carriers, and ensuring that the p-channel gallium nitride transistor has a better turn-off capability, that is, a higher threshold voltage, and at the same time, ensuring that the p-channel gallium nitride transistor has a higher on-state current, thereby improving the stability and electrical performance of the transistor.

[0052] In addition, a source electrode 501 is arranged on a side of the first protrusion 302 away from the substrate 1, a drain electrode 503 is arranged on a side of the second protrusion 303 away from the substrate 1, and a gate electrode 502 is arranged in the first groove 301 and located on a side of the zinc oxide layer 4 away from the p-type gallium nitride layer 3, and the source electrode 501, the gate electrode 502 and the drain electrode 503 constitute an electrode structure 5 of a p-channel gallium nitride transistor. Among them, by applying a negative voltage to the gate electrode 502, when the threshold voltage of the p-channel gallium nitride transistor is reached, the source electrode 501 can introduce hole carriers into the transistor, and the drain electrode 503 receives electron carriers, thereby generating current, so that the p-channel gallium nitride transistor is turned on; and when the voltage applied by the gate electrode 502 does not meet the threshold voltage condition of the p-channel gallium nitride transistor, a current channel cannot be formed between the source electrode 501 and the drain electrode 503, so that the p-channel gallium nitride transistor is in a cut-off state.

[0053] In addition, a zinc oxide layer 4 is provided between the gate 502 and the p-type gallium nitride layer 3 to form a "metal-insulator-semiconductor" structure, which can achieve a better leakage suppression effect of the p-channel gallium nitride transistor.

[0054] The technical solution provided by the present invention is to sequentially arrange a barrier layer and a p-type gallium nitride layer on one side of a substrate of a p-channel gallium nitride transistor, so that the p-type gallium nitride layer and the barrier layer form a hole heterojunction structure, in which two-dimensional hole gas is formed, and after patterning the p-type gallium nitride layer, a depletion region consisting of a first groove and a first protrusion and a second protrusion located on opposite sides of the first groove is formed, and the depletion region depletes the two-dimensional hole gas, thereby realizing the shutdown function of the p-channel gallium nitride transistor. At the same time, the groove bottom thickness L1 of the first groove is set between 10nm and 15nm, and a zinc oxide layer is set in the first groove, a source electrode is set on the side of the first protrusion away from the substrate, a drain electrode is set on the side of the second protrusion away from the substrate, and a gate is set in the first groove and on the side of the zinc oxide layer away from the p-type gallium nitride layer. At this time, the built-in electric field of the PN junction formed by the zinc oxide layer and the p-type gallium nitride layer can offset the electric field of hole carriers formed in part of the p-channel gallium nitride transistor, thereby enhancing the depletion capacity of hole carriers, so that when less p-type gallium nitride layers are patterned, the turn-off capacity of the depletion region formed when more p-type gallium nitride layers are patterned can still be achieved, and the problem of reduced on-state current when more p-type gallium nitride layers are patterned is avoided, thereby ensuring that the p-channel gallium nitride transistor has better turn-off capability, that is, has a higher threshold voltage, and can ensure that the p-channel gallium nitride transistor has a higher on-state current, thereby improving the stability and electrical performance of the transistor.

[0055] Optional, Figure 2 is a schematic diagram of the device structure of another p-channel gallium nitride transistor provided by an embodiment of the present invention, such as Figure 2 As shown, the thickness L2 of the p-type gallium nitride layer 3 at the first protrusion 302 and / or the second protrusion 303 is in the range of 70 nm≤L2≤75 nm.

[0056] Specifically, the thickness L2 of the p-type gallium nitride layer 3 at the first protrusion 302 and / or the second protrusion 303 is between 70nm and 75nm. The value range of the thickness can ensure that the thickness of the p-type gallium nitride layer 3 is moderate on the one hand, and can ensure the stability of the p-channel gallium nitride transistor on the other hand. It can be understood that the groove bottom thickness L1 of the first groove 301 is between 10nm and 15nm. Therefore, when the depth of the first groove is between 65nm and 55nm, that is, when the p-type gallium nitride layer 3 with a thickness of 65nm to 55nm is patterned, it can ensure that the p-channel gallium nitride transistor has a good turn-off capability, that is, a higher threshold voltage, and can ensure that the p-channel gallium nitride transistor has a higher on-state current.

[0057] Optional, continue to refer to Figure 2 As shown, the thickness L3 of the zinc oxide layer 4 has a value range of 3 nm ≤ L3 ≤ 10 nm.

[0058] Specifically, the thickness L3 of the zinc oxide layer 4 is between 3 nm and 10 nm. This thickness range ensures that the preparation process of the zinc oxide layer 4 is simple on the one hand, and on the other hand, it ensures that the zinc oxide layer 4 can effectively enhance the depletion capacity of hole carriers. At the same time, the zinc oxide layer 4 can achieve an effective leakage suppression effect, thereby improving the stability and electrical performance of the p-channel gallium nitride transistor.

[0059] Optional, continue to refer to Figure 2 As shown, the p-type gallium nitride layer 3 includes a first p-type gallium nitride layer 31 and a second p-type gallium nitride layer 32 which are stacked, and the first p-type gallium nitride layer 31 is located on a side of the second p-type gallium nitride layer 32 close to the substrate 1; the first groove 301 penetrates the second p-type gallium nitride layer 32 and a portion of the first p-type gallium nitride layer 31.

[0060] The first p-type gallium nitride layer 31 and the second p-type gallium nitride layer 32 may have different doping concentrations. In an optional embodiment, the doping concentration of the second p-type gallium nitride layer 32 is greater than the doping concentration of the first p-type gallium nitride layer 31 .

[0061] Specifically, by arranging the first p-type gallium nitride layer 31 on the side of the second p-type gallium nitride layer 32 close to the substrate 1, the second p-type gallium nitride layer 32 can reduce the surface state of the p-channel gallium nitride transistor, reduce the surface leakage of the subsequent p-channel gallium nitride transistor, and suppress the current collapse, thereby improving the performance and reliability of the epitaxial structure and the p-channel gallium nitride transistor. At the same time, the first groove 301 runs through the entire second p-type gallium nitride layer 32 and part of the first p-type gallium nitride layer 31. In an optional embodiment, the thickness of the second p-type gallium nitride layer can be about 10nm. Therefore, when the first groove 301 runs through the entire second p-type gallium nitride layer 32 and runs through part of the first p-type gallium nitride layer 31 below the second p-type gallium nitride layer 32, the groove bottom thickness L1 of the first groove 301 can be maintained between 10nm and 15nm. At this time, the depletion region formed will deplete the two-dimensional hole gas, realizing the shutdown function of the p-channel gallium nitride transistor.

[0062] In addition, since the doping concentration of the second p-type gallium nitride layer 32 is greater than the doping concentration of the first p-type gallium nitride layer 31, the second p-type gallium nitride layer 32 can be a heavily doped p-type gallium nitride layer, and the first p-type gallium nitride layer 31 can be a lightly doped p-type gallium nitride layer, which is conducive to forming a source 501 on the side of the second p-type gallium nitride layer of the first protrusion 302 away from the substrate 1, and forming a drain 503 on the side of the second p-type gallium nitride layer of the second protrusion 303 away from the substrate 1. When an ohmic contact with a low Schottky barrier can be formed, it is helpful to reduce the contact resistance and improve the electrical performance and power consumption characteristics of the p-channel gallium nitride transistor.

[0063] For example, the second p-type gallium nitride layer 32 may be doped with magnesium ions, and the doping concentration of magnesium ions may be 1×10 20 cm -3 , to achieve heavy doping of the doping medium.

[0064] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a p-channel gallium nitride transistor. Figure 3 is a flow chart of a method for preparing a p-channel gallium nitride transistor provided by an embodiment of the present invention, Figure 4 is a process flow chart of a p-channel gallium nitride transistor provided by an embodiment of the present invention, combined with Figure 3 and Figure 4 As shown, the preparation method of the p-channel gallium nitride transistor includes:

[0065] S101. Provide a substrate.

[0066] Among them, the substrate 1 can be specifically understood as a material that supports the device structure of the entire p-channel gallium nitride transistor. Exemplarily, the substrate 1 can be a combination of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material that can grow group III nitrides.

[0067] S102 , forming a barrier layer on one side of the substrate.

[0068] Specifically, a semiconductor material is deposited on one side of the substrate 1 by epitaxial growth technology to form a barrier layer. Exemplarily, the material of the barrier layer 2 may be AlGaN or GaN.

[0069] S103 , forming a p-type gallium nitride layer on a side of the barrier layer away from the substrate.

[0070] Specifically, through the epitaxial growth technology, a p-type gallium nitride layer 3 is deposited on the side of the barrier layer away from the substrate 1, and the p-type gallium nitride layer 3 and the barrier layer 2 form a hole heterojunction structure. A two-dimensional hole gas is formed in the hole heterojunction structure, and the two-dimensional hole gas can be used as a conductive medium in the p-channel gallium nitride transistor.

[0071] In an optional embodiment, when the p-type gallium nitride layer 3 includes a first p-type gallium nitride layer 31 and a second p-type gallium nitride layer 32, forming the p-type gallium nitride layer 3 on a side of the barrier layer 2 away from the substrate 1 may include: forming the first p-type gallium nitride layer on a side of the barrier layer 2 away from the substrate 1; and forming the second p-type gallium nitride layer 32 on a side of the first p-type gallium nitride layer 31 away from the barrier layer 2.

[0072] Among them, the second p-type gallium nitride layer 32 can be a heavily doped p-type gallium nitride layer, and its doping concentration is greater than the doping concentration of the first p-type gallium nitride layer 31, which is conducive to forming an ohmic contact with a low Schottky barrier when forming the source and the drain, thereby reducing the contact resistance and improving the electrical performance and power consumption characteristics of the p-channel gallium nitride transistor.

[0073] Specifically, a gallium nitride crystal layer is grown on the side of the barrier layer 2 away from the substrate 1 by chemical vapor deposition technology, and p-type doping atoms, such as gallium, are injected into the gallium nitride crystal layer by ion implantation technology. By controlling the implantation parameters, the p-type doping atoms are accurately introduced to form a first p-type gallium nitride layer 31. After the first p-type gallium nitride layer 31 is formed, p-type doping atoms are injected again by ion implantation technology at a position about 10 nm downward from the top of the barrier layer 2 to form a second p-type gallium nitride layer 32. By controlling the implantation parameters, the doping concentration of the second p-type gallium nitride layer 32 is greater than the doping concentration of the first p-type gallium nitride layer 31. Exemplarily, the second p-type gallium nitride layer 32 may be doped with magnesium ions, and the doping concentration of the magnesium ions may be 1×10 20 cm -3 , to achieve heavy doping of the doping medium.

[0074] S104 , patterning the p-type gallium nitride layer to form a first groove, and a first protrusion and a second protrusion located on two opposite sides of the first groove in the p-type gallium nitride layer.

[0075] The value range of the groove bottom thickness L1 of the first groove is: 10nm≤L1≤15nm.

[0076] For example, the p-type gallium nitride layer 3 may be patterned by photolithography, etching or laser processing.

[0077] In an optional embodiment, patterning the p-type gallium nitride layer 3 to form a first groove 301 and a first protrusion 302 and a second protrusion 303 located on two opposite sides of the first groove 301 in the p-type gallium nitride layer 3 includes: etching the p-type gallium nitride layer 3 using an inductively coupled plasma etching technique to form the first groove 301 and the first protrusion 302 and the second protrusion 303 located on two opposite sides of the first groove 301 in the p-type gallium nitride layer 3; wherein the plasma used in the inductively coupled plasma etching technique includes at least one of Cl2 and BCl3.

[0078] Specifically, the p-type GaN layer is patterned by inductively coupled Cl2 / BCl3 plasma, and the Cl - The ion energy of the p-type gallium nitride layer is used to cut off the Ga-N bond in the p-type gallium nitride layer, and the Ga-N bond is removed by a dry gas such as nitrogen, thereby achieving precise patterning of the p-type gallium nitride layer and reducing the preparation cost, so as to form a first groove 301 and a first protrusion 302 and a second protrusion 303 located on opposite sides of the first groove 301 in the gallium nitride layer 3. The depletion region formed by the patterned p-type gallium nitride layer 3 depletes the two-dimensional hole gas, thereby realizing the shutdown function of the p-channel gallium nitride transistor.

[0079] S105 , forming a source electrode on a side of the first protrusion away from the substrate, and forming a drain electrode on a side of the second protrusion away from the substrate.

[0080] Exemplarily, the method of forming the source and the drain may include first forming a metal layer on the entire surface of the device, and then removing part of the metal layer through processes such as photolithography and etching, leaving the metal parts of the source and the drain; or forming the source and the drain through electron beam evaporation process, chemical vapor deposition, etc.

[0081] In an optional embodiment, a source 501 is formed on a side of the first protrusion 302 away from the substrate 1, and a drain 503 is formed on a side of the second protrusion 303 away from the substrate 1, including: using an electron beam evaporation process to form a first metal structure on a side of the first protrusion 302 away from the substrate 1, and forming a second metal structure on a side of the second protrusion 303 away from the substrate 1; using an annealing process to anneal the first metal structure and the second metal structure to respectively form the source 501 located on the side of the first protrusion 302 away from the substrate, and the drain 503 located on the side of the second protrusion 303 away from the substrate 1.

[0082] Specifically, the first metal structure and the second metal structure are formed on the side of the first protrusion 302 and the second protrusion 303 away from the substrate 1 by electron beam evaporation process. The metal structure formed by the electron beam evaporation process can provide good metal contact, which helps to reduce contact resistance and improve the performance and efficiency of the p-channel gallium nitride transistor. The first metal structure and the second metal structure are rapidly annealed to form a source 501 and a drain 503 on the side of the first protrusion 302 and the second protrusion 303 away from the substrate 1. The rapid annealing process can improve the bonding between the metal structure and the p-type gallium nitride layer 3, enhance the stability of the metal and the semiconductor, reduce the interface resistance, and improve the reliability of the p-channel gallium nitride transistor.

[0083] The first metal structure, the second metal structure and the third metal structure include at least one of Ni and Au.

[0084] S106, forming a zinc oxide layer in the first groove.

[0085] For example, the method of forming the zinc oxide layer may include thermal evaporation, solution deposition, magnetron sputtering, or chemical vapor deposition.

[0086] In an optional embodiment, if Figure 5 and Figure 6 As shown, a zinc oxide layer 4 is formed in the first groove 301, including: using magnetron sputtering technology to form a zinc oxide film layer covering the first protrusion, the second protrusion and the first groove on the side of the p-type gallium nitride layer away from the substrate; patterning the zinc oxide film layer to remove the zinc oxide film layer at the first protrusion and the second protrusion, and retaining the zinc oxide film layer located in the first groove, so as to form a zinc oxide layer located in the first groove.

[0087] Among them, the magnetron sputtering technology can be specifically understood as a thin film deposition technology that uses a magnetic field to control ions to bombard a zinc oxide target material, so that the material is sputtered and deposited on the target surface to form a desired thin film structure. Specifically, a zinc oxide film layer covering the first protrusion 302, the second protrusion 303 and the first groove 301 is formed on the side of the p-type gallium nitride layer 3 away from the substrate 1 by the magnetron sputtering technology, and the sputtering rate and deposition time can be precisely controlled, thereby achieving precise control of the thickness of the zinc oxide film layer, ensuring the uniformity and stability of the film, ensuring that the zinc oxide layer can effectively enhance the depletion capacity of hole carriers, and at the same time can achieve an effective leakage suppression effect, thereby improving the stability and electrical performance of the p-channel gallium nitride transistor.

[0088] Among them, hydrofluoric acid can be used to pattern the zinc oxide film layer. Specifically, the excess zinc oxide film layer is removed by hydrofluoric acid, and the zinc oxide film layer located in the first groove 301 is retained to form a zinc oxide layer located in the first groove 301. Hydrofluoric acid is a commonly used corrosive agent, which can selectively dissolve the zinc oxide film layer without affecting other materials, thereby achieving local removal of the zinc oxide film layer, thereby achieving precise patterning of the zinc oxide film layer, and ensuring the reliability and stability of the p-channel gallium nitride transistor during operation.

[0089] S107 , forming a gate on a side of the zinc oxide layer away from the p-type gallium nitride layer.

[0090] Exemplarily, the method of forming the source and drain may include first forming a metal layer on the entire device surface, and then removing part of the metal layer through processes such as photolithography and etching, leaving the metal part of the gate; or forming the gate through electron beam evaporation process, chemical vapor deposition, etc.

[0091] In an optional embodiment, a third metal structure is formed on the side of the zinc oxide layer 4 away from the p-type gallium nitride layer 3 by an electron beam evaporation process, so as to form a gate 502 on the side of the zinc oxide layer 4 away from the p-type gallium nitride layer 3. The electron beam evaporation process can achieve high-precision metal deposition, ensure accurate positioning and formation of the gate 502, and improve the stability and electrical performance of the p-channel gallium nitride transistor.

[0092] The third metal structure includes at least one of Ni and Au.

[0093] The above-mentioned method for preparing a p-channel gallium nitride transistor can prepare a p-channel gallium nitride transistor provided by any embodiment of the present invention, which has the corresponding functions and beneficial effects of a p-channel gallium nitride transistor. For technical details not described in detail in this embodiment, please refer to the p-channel gallium nitride transistor provided by any embodiment of the present invention.

[0094] Since the p-channel gallium nitride transistor preparation method described above can prepare the p-channel gallium nitride transistor in the embodiment of the present invention, based on the p-channel gallium nitride transistor described in the embodiment of the present invention, the skilled person in the art can understand the specific implementation of the p-channel gallium nitride transistor preparation method of the present embodiment and its various variations, so how the p-channel gallium nitride transistor preparation method can achieve the preparation of the p-channel gallium nitride transistor in the embodiment of the present invention is not described in detail here. As long as the skilled person in the art implements the p-channel gallium nitride transistor preparation method in the embodiment of the present invention, it belongs to the scope of protection of this application.

[0095] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A p-channel gallium nitride transistor, characterized in that: include: substrate; A barrier layer, located on one side of the substrate; A p-type gallium nitride layer is located on a side of the barrier layer away from the substrate; the p-type gallium nitride layer and the barrier layer form a hole heterojunction structure; the p-type gallium nitride layer includes a first groove, and a first protrusion and a second protrusion located on opposite sides of the first groove; a value range of a groove bottom thickness L1 of the first groove is: 10nm≤L1≤15nm; a zinc oxide layer, located in the first groove; The electrode structure comprises a source, a gate and a drain; the source is located on a side of the first protrusion away from the substrate, and the drain is located on a side of the second protrusion away from the substrate; the gate is located in the first groove and on a side of the zinc oxide layer away from the p-type gallium nitride layer.

2. The p-channel gallium nitride transistor according to claim 1, characterized in that: The thickness L2 of the p-type gallium nitride layer at the first protrusion and / or the second protrusion has a value range of: 70 nm≤L2≤75 nm.

3. The p-channel gallium nitride transistor according to claim 1, characterized in that: The thickness L3 of the zinc oxide layer has a value range of 3nm≤L3≤10nm.

4. The p-channel gallium nitride transistor according to claim 1, characterized in that: The p-type gallium nitride layer includes a first p-type gallium nitride layer and a second p-type gallium nitride layer which are stacked, and the first p-type gallium nitride layer is located on a side of the second p-type gallium nitride layer close to the substrate; The first groove penetrates the second P-type gallium nitride layer and a portion of the first P-type gallium nitride layer.

5. The p-channel gallium nitride transistor according to claim 4, characterized in that: The doping concentration of the second p-type gallium nitride layer is greater than the doping concentration of the first p-type gallium nitride layer.

6. A method for preparing a p-channel gallium nitride transistor, characterized in that: include: providing a substrate; forming a barrier layer on one side of the substrate; forming a p-type gallium nitride layer on a side of the barrier layer away from the substrate; The p-type gallium nitride layer and the barrier layer form a hole heterojunction structure; Patterning the p-type gallium nitride layer to form a first groove and a first protrusion and a second protrusion located on opposite sides of the first groove in the p-type gallium nitride layer; wherein a value range of a groove bottom thickness L1 of the first groove is: 10nm≤L1≤15nm; forming a source electrode on a side of the first protrusion away from the substrate, and forming a drain electrode on a side of the second protrusion away from the substrate; forming a zinc oxide layer in the first groove; A gate is formed on a side of the zinc oxide layer away from the p-type gallium nitride layer.

7. The method for preparing a p-channel gallium nitride transistor according to claim 6, characterized in that: The p-type gallium nitride layer is patterned to form a first groove and a first protrusion and a second protrusion located on opposite sides of the first groove in the p-type gallium nitride layer, comprising: Etching the p-type gallium nitride layer using an inductively coupled plasma etching technique to form a first groove, and a first protrusion and a second protrusion located on two opposite sides of the first groove in the p-type gallium nitride layer; Wherein, the plasma used in the inductively coupled plasma etching technology includes at least one of Cl2 and BCl3.

8. The method for preparing a p-channel gallium nitride transistor according to claim 6, characterized in that: A source is formed on a side of the first protrusion away from the substrate, and a drain is formed on a side of the second protrusion away from the substrate, comprising: Using an electron beam evaporation process to form a first metal structure on a side of the first protrusion away from the substrate, and to form a second metal structure on a side of the second protrusion away from the substrate; The first metal structure and the second metal structure are annealed by an annealing process to respectively form the source electrode located at a side of the first protrusion away from the substrate and the drain electrode located at a side of the second protrusion away from the substrate.

9. The method for preparing a p-channel gallium nitride transistor according to claim 6, characterized in that: Forming a zinc oxide layer in the first groove comprises: Using magnetron sputtering technology to form a zinc oxide film layer covering the first protrusion, the second protrusion and the first groove on a side of the p-type gallium nitride layer away from the substrate; The zinc oxide film layer is patterned to remove the zinc oxide film layer at the first protrusion and the second protrusion, and the zinc oxide film layer located in the first groove is retained to form a zinc oxide layer located in the first groove.

10. The method for preparing a p-channel gallium nitride transistor according to claim 6, characterized in that: Forming a p-type gallium nitride layer on a side of the barrier layer away from the substrate, comprising: forming the first P-type gallium nitride layer on a side of the barrier layer away from the substrate; The second p-type gallium nitride layer is formed on a side of the first p-type gallium nitride layer away from the barrier layer.

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