Low threshold high density trench MOSFET

Abstract

A trench MOSFET device implements a trench source / body contact structure and includes a first MOSFET portion and a second MOSFET portion. In some embodiments, the first MOSFET portion includes a trench source / body contact to form an electrical contact with a source region and a body contact doped region having a first doping level. In one embodiment, the second MOSFET portion includes a trench source / body contact that contacts only the source region. In another embodiment, the second MOSFET portion includes a trench source / body contact to make electrical contact with the source region and a second body contact doped region having a second doping level lower than the first doping level. In some embodiments, the first MOSFET portion has a transistor area that is much smaller than a transistor area of the second MOSFET portion.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to trench MOSFET devices, such as MOSFET devices used as load switches. Background Art

[0002] Portable electronic devices incorporate load switches to implement power management functions. In one application, the load switch is applied in a protection circuit module, such as a battery pack for use in a portable electronic device. In this application, the protection circuit module or PCM includes one or more load switches and a protection control circuit that is operable to protect the battery from being overcharged or over-discharged, which can result in deterioration of the battery life or catastrophic damage to the battery. The load switch is connected in series with the battery terminals and the terminals of the load, which can be another charger or electronic device. The load switch is controlled by the protection control circuit to turn on, thereby allowing current to flow between the battery and the load. Alternatively, the load switch is turned off to interrupt the charging or discharging of the battery.

[0003] Load switches are typically implemented using a switching device controlled by a switch control signal. The switching device is typically a MOSFET (metal oxide semiconductor field effect transistor) device that transfers current between two current terminals, referred to as a drain and a source, in response to a control signal applied to a gate terminal. Load switches can be configured for high-side switching or low-side switching. Typically, load switches are implemented as PMOS transistors for high-side switching and NMOS transistors for low-side switching.

[0004] Figure 1 This example shows a protection control module that includes a load switch. Figure 1 , a protection control module (PCM) 1 is installed in the battery pack to protect the battery BT. Therefore, PCM 1 is connected in parallel between the battery terminals P+ and P-. The battery terminals are to be connected to a load, which may be a charger or an electronic device. PCM 1 includes a protection control circuit 2 provided by the battery voltage and also monitoring the battery voltage. The protection control circuit 2 generates a control signal to disconnect the battery from the load to prevent the battery BT from being overcharged or over-discharged. In this example, PCM 1 includes two load switches SW-D and SW-C connected in series between the negative terminal of the battery and the battery terminal P-. The load switch SW-D is disconnected in response to a control signal from the protection control circuit 2 to prevent the battery from being over-discharged. The load switch SW-C is disconnected in response to a control signal from the protection control circuit 2 to prevent the battery from being overcharged. In this example, the load switches SW-D and SW-C are NMOS transistors configured for low-side switching.

[0005] In some examples, the load switches SW-D and SW-C are implemented as trench MOSFET devices. Figures 2(a) and 2(b) show two exemplary embodiments of trench MOSFET devices. First, referring to Figure 2(a), a trench MOSFET device 3 is formed in a semiconductor layer 4. In this example, the trench MOSFET device 3 is an NMOS MOSFET device, the semiconductor layer 4 is an N-type semiconductor layer, and serves as a drain of the MOSFET device. The MOSFET device 3 includes a trench gate 6 formed in a trench formed in the semiconductor layer 4. Each trench gate 6 is isolated from the semiconductor layer 4 by a gate oxide layer 5. In the mesa adjacent to the trench gate structure, a body region 7 of P-type conductivity is formed in the semiconductor layer 4, and a source region 8 is formed in the body region at the top surface of the semiconductor layer and adjacent to the trench. The source region 8 is a heavily doped N+ region and is typically more heavily doped than the semiconductor layer 4.

[0006] An electrical connection to the drain of the MOSFET device 3 can be provided on the back side of the semiconductor layer 4. An electrical connection to the gate formed in the trench can be provided at a selected position to electrically connect all trench gates. The electrical connection to the source and body of the MOSFET device 3 is made on the top side of the semiconductor layer 4, typically using a source / body contact that electrically connects the source region and the body region. In the example shown in Figure 2(a), a body contact doped region 9 is formed at the top surface of the body region and between the source regions 8 formed in the adjacent trenches. The body contact doped region 9 is a P-type doped region that is more heavily doped than the body region. A contact opening is formed in the covering isolation layer 11 to expose the source region 8 and the body contact doped region 9, and a conductive layer 10 is deposited in the contact opening to connect to both the source region and the body region. The conductive layer 10 is further patterned to form a conductive line to connect the source / body region to the source electrode or source pad.

[0007] The trench MOSFET device 3 shown in FIG2(a) uses a surface or lateral source / body contact structure, which requires a large lateral silicon wafer space to implement. In order to reduce the device size, a trench MOSFET device that implements a trench or vertical source / body contact structure has been developed, as shown in FIG2(b). Referring to FIG2(b), in a trench MOSFET device 12, a body contact doping region 9 is formed in a body region 7 below an N+ source region 8. A trench contact opening is formed in the covering isolation layer 11 and passes through the N+ source region 8 to reach the body contact doping region 9. A conductive layer 15, such as a tungsten plug, is deposited into the trench contact opening to contact the source region 8 on the sidewalls and the body contact doping region 9 at the bottom of the contact. A conductive layer 16, such as a metal layer, is formed on the isolation layer 11 to form a wire that connects the source / body region to a source electrode or a source pad.

[0008] By using a trench source / body contact structure, the lateral dimensions of a MOSFET device can be reduced, thereby enabling the size of the MOSFET device to be scaled down. However, the scaling or shrinking of a MOSFET device using a trench source / body contact structure may cause undesirable secondary effects in transistor characteristics. For example, the shrinking of the lateral dimensions of the mesas between adjacent trench gate structures causes the body contact doping region 9 to get closer and closer to the trench region formed in the body region on the sidewalls of the trench, which may have a negative impact on device performance, such as by increasing the threshold voltage of the MOSFET device. Summary of the invention

[0009] It is an object of the present invention to address the problem that scaling or shrinking of current MOSFET devices using a trench source / body contact structure may cause undesirable secondary effects in the transistor characteristics.

[0010] To achieve the above-mentioned object, the present invention proposes a trench MOSFET device having a first current terminal, a second current terminal and a gate terminal, comprising a trench gate structure formed in a trench in a semiconductor layer of a first conductivity type, the trench gate structure comprising a conductive gate layer formed in the trench and isolated from the semiconductor layer by a gate dielectric layer, the conductive gate layer forming the gate terminal; a second conductivity type body region in and at a first surface of the semiconductor layer adjacent to the trench; a first doped region of the first conductivity type, formed in the body region and at a first surface of the semiconductor layer adjacent to the trench, the first doped region forming the first current terminal, wherein the semiconductor forms the second current terminal; and a first body contact doped region of the second conductivity type, formed in a first portion of the body region and spaced apart from the first doped region and spaced apart from the trench, the first body contact doped region being more heavily doped than the body region. The trench MOSFET device comprises a first MOSFET portion formed in a first portion of the body region and a second MOSFET portion formed outside the first portion of the body region. The first MOSFET portion has a body contact impedance lower than the body contact resistance of the second MOSFET portion.

[0011] On the other hand, the present invention also provides a method for forming a trench MOSFET device, comprising: providing a semiconductor layer of a first conductivity type; forming an array of trench transistor cells in the semiconductor layer, including forming trench transistor cells defined by a trench gate structure; forming a body region of a second conductivity type in the array of trench transistor cells; forming a source region of a first conductivity type in the body region of the trench transistor cell array; forming a first body contact doped region of a second conductivity type in each body region in a first part of the trench transistor cell array, the first body contact doped region being spaced apart from a source region formed in a corresponding body region and being spaced apart from the trench gate structure, the first body contact doped region being more heavily doped than the body region; forming a body contact with the first body contact doped region in a first part of the body region, and forming a body connection with the source region only outside the first part of the body region; and forming a first conductive layer in contact with the body.

[0012] Compared to the prior art, the present invention solves the problem that scaling or shrinking of MOSFET devices using a trench source / body contact structure may cause undesirable secondary effects in transistor characteristics.

[0013] These and other advantages, aspects and novel features of the present invention, as well as details of illustrated embodiments thereof, will be more fully understood from the following description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various embodiments of the present invention are disclosed in the following detailed description and accompanying drawings. Although the accompanying drawings depict various examples of the present invention, the present invention is not limited to the depicted examples. It should be understood that in the accompanying drawings, the same reference numerals represent the same structural elements. In addition, it should be understood that the descriptions in the drawings are not necessarily to scale.

[0015] Figure 1 Represents an example of a protection control module including a load switch.

[0016] FIG. 2( a ) and FIG. 2( b ) illustrate two exemplary embodiments of trench MOSFET devices.

[0017] Figure 3 FIG. 4 is an equivalent circuit diagram of a trench MOSFET device in an embodiment of the present invention.

[0018] Figure 4(a) and 4(b) A perspective view showing a transistor cell in a trench MOSFET device in an embodiment of the present invention.

[0019] Figure 5 A top view of a trench MOSFET device of the present invention is shown, and in some embodiments, a portion of a trench transistor array.

[0020] Figures 6(a) to 6(f) A cross-sectional view showing a manufacturing process for forming a trench MOSFET device according to an embodiment of the present invention.

[0021] Figure 7(a) to Figure 7(f) express Figure 6(a) to Figure 6(f) A perspective view of a device structure during various processing steps in the fabrication process is shown.

[0022] Figure 8 FIG. 4 is an equivalent circuit diagram of a trench MOSFET device in an alternative embodiment of the present invention.

[0023] Figure 9(a) and 9(b) It is a cross-sectional view of a transistor unit in a trench MOSFET device in an embodiment of the present invention.

[0024] Fig.10 A top view of a trench MOSFET device of the present invention is shown, and in some embodiments, a portion of a trench transistor array.

[0025] Figure 11(a) to Figure 11(f) A cross-sectional view showing a fabrication process for forming a trench MOSFET device in an alternative embodiment of the present invention. DETAILED DESCRIPTION

[0026] According to various aspects of the present invention, a trench MOSFET device implements a trench source / body contact structure and includes a first MOSFET portion and a second MOSFET portion, wherein the body contact resistance of the first MOSFET portion is lower than the body contact resistance of the second MOSFET portion. In some embodiments, the first MOSFET portion of the trench MOSFET device includes a trench source / body contact formed in a table between adjacent trench gate structures to electrically contact a source region and a body contact doping region formed in a body region below the source region and having a first doping level. In one embodiment, the second MOSFET portion of the trench MOSFET device includes a trench source / body contact that contacts only the source region. In another embodiment, the trench MOSFET device includes a second body contact doping region, which is formed in a body region below the source region and has a second doping level that is lighter than the first doping level. The second MOSFET portion of the trench MOSFET device includes a trench source / body contact formed in a table between adjacent trench gate structures to electrically contact the source region and the second body contact doping region. In some embodiments, the first MOSFET portion has a transistor area that is much smaller than the transistor area of ​​the second MOSFET portion.

[0027] In some examples, trench MOSFET devices are applied as load switches in protection circuit modules, such as protection circuit modules implemented in battery packs, to prevent overcharging or over-discharging of batteries. When used as load switches in protection circuit modules, trench MOSFET devices with specific electrical characteristics are sometimes required.

[0028] First, it is generally desirable for trench MOSFET devices to have low on-resistance. The on-resistance of a trench MOSFET is the drain-to-source resistance when the MOSFET device is on, commonly referred to as Rds-on. In order to achieve low Rds-on resistance, high-density trench MOSFET devices are required. Trench MOSFET devices are typically formed using an array of transistor cells defined by a trench gate structure and a mesa therebetween. In order to achieve low Rds on-resistance, a high-density array of transistor cells is required. At the same time, in order to achieve efficient use of silicon real estate, trench MOSFET devices implement a trench source / body contact structure to reduce the die size used to achieve a high-density array of transistor cells.

[0029] Second, when used as a load switch for protection circuit module applications, the load switch is only activated periodically. That is, there is no AC operation or the switching frequency is very low. Therefore, there is no special capacitance requirement for the trench MOSFET device.

[0030] Third, when used as a load switch for a protection circuit module application, the load switch is typically used to switch non-inductive loads. Therefore, the requirement for trench MOSFET devices to have protection capabilities to prevent inductive loads from turning off (called undamped inductive switching (UIS) events) is also minimal. UIS capabilities are important for MOS transistor devices used to switch inductive loads. When a MOS transistor turns off an inductive load in normal operation, the MOS transistor must absorb the energy stored in the inductive load. The overvoltage transient that occurs during the disconnection of an inductive load is called a UIS event. During a UIS event, the MOS transistor device is turned off, but the drain and source junctions are in avalanche mode and conduct a large amount of current. In the absence of any circuit protection, the parasitic bipolar transistor of the MOS transistor may turn on and may cause irreversible damage to the transistor device. In this case, it is generally desirable that the MOS transistor have a low body contact resistance so that the parasitic bipolar transistor does not turn on during a UIS event. In the case of a load switch in a protection circuit module application, the load switch drives a non-inductive load, so the requirement for low body contact resistance can be relaxed.

[0031] Fourth, the load switch is usually configured for low-side switching, so the trench MOSFET device can be implemented using an N-trench or NMOS transistor device. In addition, the NMOS transistor is suitable because the NMOS transistor has a lower drain-to-source resistance than the PMOS transistor.

[0032] Finally, when the load switch is applied to the protection circuit module of the battery pack, the battery voltage is low, such as between 3.0 and 3.8 V, so it is usually desirable for the trench MOSFET device to have a low threshold voltage, such as less than 1.0 V. For example, for a trench MOSFET device used as a load switch for a battery pack, a threshold voltage of 0.6 V or 0.7 V is usually required.

[0033] In an embodiment of the present invention, a trench MOSFET device is configured to be used as a load switch in a protection circuit module. The trench MOSFET device is constructed using a trench transistor cell array having a trench gate structure and a trench source / body contact structure to achieve a high-density transistor cell array with a low on-resistance Rds-on. In addition, the trench MOSFET device includes a portion of a trench gate transistor cell forming a first MOSFET portion and a second MOSFET portion forming a second MOSFET portion. The first MOSFET portion is formed with a first type of trench source / body contact structure, while the second MOSFET portion is formed as a second type of trench drain / body contact structure. The first MOSFET portion and the second MOSFET portion are configured in a manner to optimize the body contact resistance and threshold voltage of the trench MOSFET device. In particular, the first MOSFET portion is configured with a first type of trench source / body contact structure to achieve a lower body contact resistance than the second MOSFET portion configured with a second type of trench drain / body contact structure.

[0034] In some embodiments, the first type of trench source / body contact structure includes a heavily doped body contact doping region to achieve a low body contact resistance, wherein the heavily doped body contact doping region may have a negative impact on the threshold voltage of the trench MOSFET device. At the same time, the second type of trench source / body contact structure may not have a body contact doping region or only have a lightly doped body contact doping region, which may result in a higher body contact resistance, but has no or minimal negative impact on the threshold voltage of the trench MOSFET device. In one example, for an N-type MOSFET device, a heavily doped body contact doping region as a P+ region may result in an increase in the threshold voltage of the N-type MOSFET device due to being physically close to the trench region of the NMOS transistor. By optimizing the transistor area in the first MOSFET portion relative to the transistor area of ​​the second MOSFET portion, the trench MOSFET device can achieve a desired low on-resistance Rds-on and a desired threshold voltage value with an acceptable body contact resistance to prevent transient overvoltage events. In some embodiments, the first MOSFET portion has a transistor area that is much smaller than the transistor area of ​​the second MOSFET portion.

[0035] In an embodiment of the present invention, a trench MOSFET device is used as a load switch in a protection circuit module, such as connected to the back of a battery. In some examples, the trench MOSFET device may be referred to as a switch circuit or a load switch circuit. It should be understood that the trench MOSFET device of the present invention may have many applications, and using a trench MOSFET device as a load switch for a protection circuit module is an example application. Typically, a trench MOSFET device has a first current terminal coupled to a first circuit node, a second current terminal coupled to a second circuit node, and a control or gate terminal coupled to receive a control signal for turning on or off the MOSFET device.

[0036] Figure 3 FIG. 4 is an equivalent circuit diagram of a trench MOSFET device in an embodiment of the present invention. Figure 4(a) and 4(b) is a cross-sectional view of a transistor unit in a trench MOSFET device in an embodiment of the present invention. In an embodiment of the present invention, the trench MOSFET device is constructed as an N-type MOSFET device or an N-trench or NMOS transistor device. It is understood that by reversing the conductivity type of the device layer and the doped region, a P-type MOSFET device or a PMOS transistor device can be formed in the same manner. First, refer to Figure 3In an embodiment of the present invention, the N-type trench MOSFET device 20 includes a first MOSFET portion denoted as NMOS transistor M1 and a second MOSFET portion denoted as NMMOS transistor M2. In construction, the first MOSFET portion and the second MOSFET portion are formed as an integrated monolithic MOSFET device. Figure 3 An equivalent circuit diagram for illustrating a trench MOSFET device 20 including two transistor portions. NMOS transistors M1 and M2, which are part of the same trench MOSFET device 20, are connected in parallel. That is, the source terminals of the NMOS transistors M1 and M2 are connected, the drain terminals of the NMOS-transistors M1 and M2 are connected, and the gate terminals of the NMOS-M1 and M2 are connected.

[0037] In order to provide protection against transient overvoltage events, a low resistance contact is provided to the body region of the trench MOSFET device. Figure 3 , the body contact of the trench MOSFET device 20 is represented by node 22. In the present embodiment, a low resistance body contact is formed in the NMOS transistor M1, wherein the body region is electrically connected to the source terminal. At the same time, the NMOS transistor M2 does not have any body contact. So constructed, the NMOS transistor M1 (first MOSFET section) has a lower body contact resistance than the NMOS transistor M2 (second MOSFET section). So constructed, the transistor area ratio of the NMOS transistor M1 to the NMOS transistor M2 is selected so that the trench MOSFET device has a desired on-resistance Rds-on and a desired threshold voltage, which has an acceptable body contact resistance for transient overvoltage protection, i.e., an acceptable UIS protection capability. In some embodiments, the transistor area of ​​the NMOS transistor M1 is much smaller than the transistor area of ​​the NMOS transistor M2.

[0038] In this specification, for ease of reference to the accompanying drawings, a Cartesian coordinate reference system is used, in which the Z direction is perpendicular to the plane of the semiconductor layer, and the X direction and the Y direction are orthogonal to the Z direction and to each other, as shown in the accompanying drawings. Typically, a trench in a semiconductor layer refers to a long and narrow trench formed in the semiconductor layer. In the present embodiment, the trench used to form a trench gate structure has a length L extending in a first direction (Y direction) of the semiconductor layer and a width W extending in a second direction (X direction) of the semiconductor layer orthogonal to the first direction and on the same plane as the first direction. The length L of the trench is much greater than the width W of the trench. In other words, the length of the trench refers to the long dimension of the trench, and the width of the trench refers to the narrow dimension of the trench. Finally, the trench has a depth in a third direction (Z direction).

[0039] Figure 4(a) and4(b) In some embodiments, the Figure 3 A transistor unit of a first MOSFET part and a second MOSFET part is implemented in a trench MOSFET device 20 of the present invention. Referring to FIG. 4( a) and FIG. 4( b), the trench MOSFET device 20 is formed in a semiconductor layer 32 and includes a first MOSFET part 30 (FIG. 4( a)) and a second MOSFET part 40 (FIG. 4( b)) formed in the semiconductor layer 32. In the present example, the trench MOSFET device 20 is an NMOS MOSFET device, and the semiconductor layer 32 is an N-type semiconductor layer and serves as a drain of the MOSFET device. The trench MOSFET device 20 includes a trench gate structure having a trench gate 34 formed in a trench formed in the semiconductor layer 32. Each trench gate 34 is isolated from the semiconductor layer 32 by a gate dielectric layer 33. In some embodiments, the trench gate 34 is a polysilicon layer and the gate dielectric layer 33 is a silicon dioxide layer. In a mesa adjacent to the trench gate structure, a body region 35 of P-type conductivity is formed in the semiconductor layer 32, and a source region 36 is formed in the body region at the top surface of the semiconductor layer and adjacent to the trench. The source region 36 is a heavily doped N+ region and is generally more heavily doped than the semiconductor layer 32. The body region 35 is generally more heavily doped than the semiconductor layer 32, but more lightly doped than the source region 36. In operation, the trench of the NMOS transistor is formed in a portion of the body region 35 adjacent to the trench gate structure and between the source region 36 and the semiconductor layer 32. An isolation layer 31 such as a dielectric layer is formed on the semiconductor layer 32 to insulate the structure formed therein. In some embodiments, the dielectric layer 31 may be a low temperature silicon oxide layer (LTO) and / or a BPSG layer.

[0040] In an embodiment of the present invention, an electrical connection to the drain of the MOSFET device 20 can be provided on the back side of the semiconductor layer 32. An electrical connection to the trench gate 34 formed in the trench can be provided at a selected position to electrically connect all the trench gates. An electrical connection to the source and body of the trench MOSFET device 20 is provided on the top side of the semiconductor layer 32 using a source / body contact. In an embodiment of the present invention, the trench MOSFET device 20 uses a trench source / body contact structure to electrically connect the source region and the body region or only electrically connect the source region. More specifically, in the first MOSFET portion 30, a body contact doped region 37 is formed in the body region for achieving a low resistance connection with the body region. The body contact doped region 37 has the same conductivity type as the body region 35 and is heavily doped than the body region 35. In the second MOSFET portion 40, no body contact doped region is formed.

[0041] To form a trench source / body contact, a trench contact opening is formed in the isolation layer 31. In the first MOSFET portion 30, the trench contact opening further passes through the N+ source region 36 to reach the body contact doping region 37. In the second MOSFET portion 40, the trench contact opening is formed only to the source region 36. A conductive layer 38, such as a tungsten plug, is deposited into the trench contact opening. In the first MOSFET portion 30, the conductive layer 38 contacts the source region 36 on the sidewalls and contacts the body contact doping region 37 at the bottom of the contact. In the second MOSFET portion 40, the conductive layer 38 contacts only the top surface of the source region 36. A conductive layer 39, such as a metal layer, is formed on the isolation layer 31 to form a conductive line connecting the source region and the body region to the source electrode or source pad.

[0042] In this way, the first MOSFET portion 30 achieves a low body contact resistance in the trench MOSFET device 20, even though there is a risk of affecting the device characteristics of the trench MOSFET device 20, for example by causing an increase in the threshold voltage of the trench MOSFET in this region. At the same time, the second MOSFET portion 40 does not include a body contact doping region and therefore operates with the desired device characteristics of the trench MOSFET device 20, for example, at a desired threshold voltage value. By selecting an appropriate transistor area ratio between the first MOSFET portion 30 and the second MOSFET portion 40, a trench MOSFET device 20 having a desired on-resistance Rds-on and a desired threshold voltage with an acceptable body contact resistance can be formed.

[0043] Figure 5 is a top view of a trench MOSFET device of the present invention, showing a portion of a trench transistor array in some embodiments. For example, in some examples, Figure 5 It showed Figure 3 , the trench MOSFET device 20 of FIG. 4( a) and FIG. 4( b). Figure 5 , a portion 50 of the trench MOSFET device 20 includes a trench gate layer 34 and a gate dielectric layer 33 formed in parallel trenches in the cell array region of the semiconductor layer 32. The trench gate layers 34 in the parallel trenches are connected together, for example, by additional trench gate portions, contact layers, and metal layers. In the mesa between adjacent trench gate structures, the source region 36 (e.g. Figure 5 A trench source / body contact 38 is formed over the source region to contact the source region or the source region and the body region.

[0044] The trench MOSFET device 20 includes a first MOSFET portion 30 disposed at a given position along the Y direction of the transistor cell array and a second MOSFET portion 40 formed in the remaining cell array area. In particular, in the first MOSFET portion 30, a body contact doping region 37 is formed in the body region 35, and a source / body contact 38 extends into the source region 36 to contact the body contact doping region 37, as shown by a cross frame 54. In the second MOSFET portion 40, the source / body contact 38 contacts only the top surface of the source region 36. Figure 5 As shown, the transistor area of ​​the first MOSFET portion 30 is smaller than the transistor area of ​​the second MOSFET portion 40. In some embodiments, the transistor area of ​​the first MOSFET portion 30 is a fraction of the transistor area of ​​the second MOSFET portion 40. In one embodiment, the transistor area of ​​the first MOSFET portion 30 is between 5% and 25% of the transistor area of ​​the second MOSFET portion 40.

[0045] Figures 6(a) to 6(f) 1 is a cross-sectional view illustrating a manufacturing process for forming a trench MOSFET device in an embodiment of the present invention. Figure 7(a) to Figure 7(f) It showed Figure 6(a) to Figure 6(f) A perspective view of a device structure during various processing steps in the fabrication process is shown. Figure 3 , 4(a) , 4(b), 6(a) to 6(f), and 7(a) to 7(f) are given similar reference numerals to simplify the discussion. In addition, in the following description, Figures 6(a) to 6(f) The cross-section shown is taken along Figure 5 The cross-sectional view taken along the AA' line in FIG. 4 crosses the first and second MOSFET parts 30, 40 spaced apart in the Y direction. The cross-sectional view taken along the AA' line allows the NMOS transistors formed in the first MOSFET part and the second MOSFET part to be observed in the same cross-sectional view.

[0046] Referring to FIG. 6( a), the manufacturing process starts with forming a trench in the cell array region of the semiconductor layer 32. In this example, the trench MOSFET device 80 is an NMOS MOSFET device, and the semiconductor layer 32 is an N-type semiconductor layer. The gate dielectric layer 33 is formed on the surface of the semiconductor layer 32 and in the trench, for example, by a chemical vapor deposition (CVD) process or by thermal growth. In one embodiment, the gate dielectric layer 33 is a silicon dioxide layer (SiO2), and the gate dielectric layer 33 is also referred to as a gate oxide layer. A conductive gate layer 34 is then formed in the trench. In some embodiments, the conductive gate layer 34 is a doped polysilicon layer. The doped polysilicon layer can be conformally deposited on the semiconductor layer 32, and the deposited doped polysilicon layer is etched back so that only the polysilicon layer in the trench is retained, thereby forming a conductive gate layer 34. In some examples, the polysilicon layer can be deposited using a CVD process, and the polysilicon layer can be etched back using a wet etch or dry etch process. At this stage, the manufacturing process has completed the formation of a trench gate structure for a trench MOSFET device. The manufacturing process continues with applying a body implant to form body regions 35 in the mesas of the semiconductor layer 32 between the trench gate structures. For example, the body implant can be a lightly doped P-type implant. In one example, the body implant uses boron as the P-type dopant and has a 2x10 13 / cm 2 A body annealing process of the body implant is performed to anneal and diffuse the implanted dopants to form the body region 35. The annealing process may be performed in a non-reactive environment, such as at a high temperature.

[0047] After the bulk annealing process, the manufacturing process continues with applying a source implant to form source regions 36 in the mesas of the semiconductor layer 32 between the trench gate structures. For example, the source implant can be a heavily doped N-type implant. In one example, the source implant uses arsenic as the N-type dopant and has a 1x10 15 / cm 2 Up to 5x10 15 / cm 2 The implantation dose is . A source annealing process of the source implant is performed to anneal and diffuse the implanted dopants, thereby forming a source region 36 in the trench MOSFET device. The annealing process can be performed in a non-reactive environment, such as high temperature. After the source annealing process, the trench MOSFET device is encapsulated by a dielectric layer 62. In the present embodiment, the dielectric layer 62 can be a low temperature oxide layer (LTO) or a combination of LTO and borophosphosilicate glass (BPSG) layer. The dielectric layer 62 can be deposited using, for example, a CVD process. After the BPSG deposition, the semiconductor structure can be planarized, as shown in FIG6( a).

[0048] Referring to FIG. 6( b ), a first contact mask (not shown) is applied to define the opening to be formed in the dielectric layer 62. A contact etching process, such as an anisotropic dry etching process, is then performed using the contact mask to etch the dielectric layer 62, thereby forming a contact opening 64 to the source region 36. The resulting structure is also shown in FIG. 7( a ). The contact opening 64 is formed to expose the source region 36, and the contact opening 64 extends in the Y direction along the length of the trench gate structure.

[0049] Referring now to FIG. 6( c ), a second contact mask 66 is applied to the semiconductor layer 32 above the dielectric layer 62. The second contact mask 66 defines the location where the first MOSFET portion is to be formed. In particular, as shown in FIG. 7( b ), the second contact mask 66 defines an opening 68 extending in the X direction, which is orthogonal to the direction of the contact opening 64 formed in the dielectric layer 62 (the Y direction). In this manner, the opening 68 (the X direction) is formed in self-alignment with the contact opening 64 (the Y direction) of the dielectric layer 62. In particular, the opening 68 exposes a portion of the contact opening 64, which in turn exposes the source region 36.

[0050] Using opening 68 defined by second contact mask 66, which exposes a portion of opening 64 in dielectric layer 62 exposing source region 36, the manufacturing process etches semiconductor layer 32 through source region 36 and into body region 35 to form a body contact opening, such as Figure 6(d) and 7(c) 6(d) and 7(d). For example, the body contact implant 70 may be a high dose P-type implant. In one example, the body contact implant 70 uses boron or BF2 as the P-type dopant and has a P-type dopant of 8x10 14 / cm 2 Up to 1x10 15 / cm 2 The second contact mask 66 is then removed. As shown in FIG6( e) and FIG7( e), an annealing process for the body contact implant is performed to anneal and diffuse the implanted dopant, thereby forming a body contact doping region 37 in the trench MOSFET device. The annealing process can be performed in a non-reactive environment such as high temperature. In one example, with a 2x10 17 / cm 3 Compared to the doping level of the body region 35, as annealed, the body contact doping region 37 has a doping level of 5x10 19 / cm 3 Up to 2x10 20 / cm3 of the doping level.

[0051] Subsequently, referring to FIG. 6( f) and FIG. 7( f), a tungsten plug 38 is formed in the contact opening 64. For example, the tungsten plug 38 may include a conductive adhesion layer, such as a titanium (Ti) or titanium nitride (TiN) layer, and then a tungsten filling layer, both of which are deposited by a CVD or PVD process. A conductive layer 39 is then deposited on the semiconductor structure. In one embodiment, the conductive layer 39 is an aluminum layer and may be deposited using a PVD process or evaporation. A metal mask may be applied, and the conductive layer 39 may be etched using the metal mask to form a metal interconnect. At this stage, the manufacturing process for forming a trench MOSFET device is completed.

[0052] As configured, the tungsten plug 38 contacts the source region 36 and the body contact doping region 37 in the first MOSFET portion 30, and the tungsten plug 38 contacts only the source region 36 in the second MOSFET portion 40. In this way, the NMOS transistor formed in the second MOSFET portion 40 has a higher body contact resistance than the NMOS-transistor formed in the first MOSFET portion 30 including the body contact doping region 37. However, the device characteristics of the NMOS transistor in the second MOSFET portion 40 may be better than those in the first MOSFET portion 30, for example, having a lower threshold voltage.

[0053] Figure 8 is an equivalent circuit diagram of a trench MOSFET device in an alternative embodiment of the present invention. Figure 9(a) and 9(b) is a cross-sectional view of a transistor unit in a trench MOSFET device in an embodiment of the present invention. In an embodiment of the present invention, the trench MOSFET device is constructed as an N-type MOSFET device or an N-trench or NMOS transistor device. Figure 8 , N-type trench MOSFET device 80 with Figure 3 The trench MOSFET device 20 is constructed in a substantially similar manner, except that a body contact with a high contact resistance is provided in the second MOSFET portion (represented by the NMOS transistor M2). More specifically, in the trench MOSFET device 80, the first MOSFET portion (NMOS transistor M1) has a body contact (node ​​82) to connect the body region to the source terminal. At the same time, the second MOSFET portion (NMOS transistor M2) has a body contact (node ​​84) to connect the body region to the source terminal. The resistance of the body contact of the second MOSFET portion (M2) is higher than the resistance of the body contact (M1) of the first MOSFET portion. Resistor Rx is used to represent the additional body resistance at the body contact of the second MOSFET portion (M2).

[0054] Figure 9(a) and 9(b) In some embodiments, the Figure 8 A transistor unit of a first MOSFET part and a second MOSFET part is implemented in a trench MOSFET device 80 of the present invention. Referring to Figures 9(a) and 9(b), the trench MOSFET device 80 is formed in a semiconductor layer 92 and includes a first MOSFET part 90 (Figure 9(a)) and a second MOSFET part 100 (Figure 9(b)) formed in the semiconductor film 92. In this example, the trench MOSFET device 80 is an NMOS MOSFET device, and the semiconductor layer 92 is an N-type semiconductor layer and serves as a drain of the MOSFET device. The trench MOSFET device 80 includes a trench gate structure having a trench gate 94 formed in a trench formed in the semiconductor layer 92. Each trench gate 94 is isolated from the semiconductor layer 92 by a gate dielectric layer 93. In some embodiments, the trench gate 94 is a polysilicon layer and the gate dielectric layer 93 is a silicon dioxide layer. In a table adjacent to the trench gate structure, a body region 95 of P-type conductivity is formed in the semiconductor layer 92, and a source region 96 is formed in the body region at the top surface of the semiconductor layer and adjacent to the trench. The source region 96 is a heavily doped N+ region and is typically more heavily doped than the semiconductor layer 92. The body region 95 is typically more heavily doped than the semiconductor layer 92, but more lightly doped than the source region 96. In operation, the trench of the NMOS transistor is formed in a portion of the body region 95 adjacent to the trench gate structure and between the source region 96 and the semiconductor layer 92. An isolation layer 91, such as a dielectric layer, is formed on the semiconductor layer 92 to insulate the structure formed therein. In some embodiments, the dielectric layer 91 may be a low temperature silicon oxide layer (LTO) or a combination of LTO and BPSG layers.

[0055] In an embodiment of the present invention, an electrical connection to the drain of the MOSFET device 80 may be provided on the back side of the semiconductor layer 92. An electrical connection to a trench gate 94 formed in the trench may be provided at a selected location to electrically connect all trench gates. Electrical connections to the source and body of the trench MOSFET device 80 are provided on the top side of the semiconductor layer 92 using a source / body contact. In an embodiment of the present invention, the trench MOSFET device 80 uses a trench source / body contact structure to electrically connect the source region and the body region.

[0056] More specifically, in the first MOSFET portion 90, a body contact doped region 97 is formed in the body region 95 for achieving a low resistance connection to the body region. The body contact doped region 97 has the same conductivity type as the body region 95 and has a first doping level that is more heavily doped than the body region 95. In the second MOSFET portion 100, a body contact doped region 102 is formed in the body region 95 for providing a connection to the body region. The body contact doped region 102 has the same conductivity type as the body region 95 and has a second doping level that is more heavily doped than the body region 95 but less heavily doped than the body contact doped region 97. Therefore, by providing a body contact doped region 97 that is more heavily doped than the body contact doped region 102, the first MOSFET portion 90 has a body contact impedance that is lower than the body contact resistance of the second MOSFET portion 100.

[0057] To form a trench source / body contact, a trench contact opening is formed in the isolation layer 91 and passes through the N+ source region 96 to reach the corresponding body contact doping region 97 or 102. A conductive layer 98, such as a tungsten plug, is deposited into the trench contact opening. In the first MOSFET portion 90, the conductive layer 98 contacts the source region 96 on the sidewalls and contacts the body contact doping region 97 at the bottom of the contact. In the second MOSFET portion 100, the conductive layer 98 contacts the source region 96 on the sidewalls and contacts the body contact doping region 102 at the bottom of the contact. A conductive layer 99, such as a metal layer, is formed on the isolation layer 91 to form a conductive line connecting the source and body regions to the source electrode or source pad.

[0058] In this way, the trench MOSFET device 80 is provided with an acceptable body contact resistance for preventing transient events. In particular, the first MOSFET portion 90 is provided with a low body contact resistance in the trench MOSFET device 80, while the second MOSFET portion 100 is provided with a higher body contact impedance than the first MOSFET portion 90. By using a lighter doped body contact doping region 102, the negative impact on the device characteristics of the trench MOSFET is mitigated. By selecting an appropriate transistor area ratio between the first MOSFET portion 90 and the second MOSFET portion 100, a trench MOSFET device 80 having a desired on-resistance Rds-on and a desired threshold voltage with an acceptable body contact resistance can be formed.

[0059] Fig.10 is a top view of a trench MOSFET device of the present invention, showing a portion of a trench transistor array in some embodiments. For example, in some examples, Fig.10 It showed Figure 8 , the trench MOSFET device 80 of FIG. 9( a) and FIG. 9( b). Fig.10, a portion 120 of the trench MOSFET device 80 includes a trench gate layer 94 and a gate dielectric layer 93 formed in parallel trenches in the cell array region of the semiconductor layer 92. The trench gate layers 94 in the parallel trenches are connected together, for example, by additional trench gate portions, contact layers, and metal layers. In the mesa between adjacent trench gate structures, the source region 96 (e.g. Fig.10 A trench source / body contact 98 is formed on the source region to contact the source region and the body region.

[0060] The trench MOSFET device 80 includes a first MOSFET portion 90 disposed at a given position along the Y direction of the transistor cell array and a second MOSFET portion 100 formed in the remaining cell array area. In particular, in the first MOSFET portion 90, a body contact doping region 97 is formed in the body region 95, and in the second MOSFET portion 100, a body contact doping region 102 is formed in the body region 95. A source / body contact 98 extends through the source region 96 to contact the corresponding body contact doping region 97 or 102, as shown by a cross frame 124. Fig.10 As shown, the transistor area of ​​the first MOSFET portion 90 is smaller than the transistor area of ​​the second MOSFET portion 100. In some embodiments, the transistor area of ​​the first MOSFET portion 90 is a fraction of the transistor area of ​​the second MOSFET portion 100. In one embodiment, the transistor area of ​​the first MOSFET portion 90 is between 5% and 25% of the transistor area of ​​the second MOSFET portion 100.

[0061] Figure 11(a) to Figure 11(f) 1 is a cross-sectional view illustrating a manufacturing process for forming a trench MOSFET device in an alternative embodiment of the present invention. To simplify the discussion, Figure 8 , 9(a) , 9(b) and 11(a) to 11(f) are given similar reference numerals. In addition, in the following description, Figures 11(a) to 11(f) The cross-section shown is taken along Fig.10 The cross-sectional view taken along the AA' line in FIG. 1 crosses the first and second MOSFET parts 90, 100 spaced apart in the Y direction. The cross-sectional view taken along the AA' line allows NMOS transistors formed in the first MOSFET part and the second MOSFET part to be observed in the same cross-sectional view.

[0062] Referring to FIG. 11( a), the manufacturing process starts with forming a trench in the cell array region of the semiconductor layer 92. In this example, the trench MOSFET device 80 is an NMOS MOSFET device, and the semiconductor layer 92 is an N-type semiconductor layer. The gate dielectric layer 93 is formed on the surface of the semiconductor layer 92 and in the trench, for example, by a chemical vapor deposition (CVD) process or by thermal growth. In one embodiment, the gate dielectric layer 93 is a silicon dioxide layer (SiO2), and the gate dielectric layer 93 is also referred to as a gate oxide layer. A conductive gate layer 94 is then formed in the trench. In some embodiments, the conductive gate layer 94 is a doped polysilicon layer. The doped polysilicon layer can be conformally deposited on the semiconductor layer 92, and the deposited doped polysilicon layer is etched back so that only the polysilicon layer in the trench is retained, thereby forming a conductive gate layer 94. In some examples, the polysilicon layer can be deposited using a CVD process, and the polysilicon layer can be etched back using a wet etch or dry etch process. At this stage, the manufacturing process has completed the formation of a trench gate structure for a trench MOSFET device. The manufacturing process continues with applying a body implant to form a body region 95 in the mesa of the semiconductor layer 92 between the trench gate structures. For example, the body implant can be a lightly doped P-type implant. A body annealing process of the body implant is performed to anneal and diffuse the implanted dopants to form the body region 95. The annealing process can be performed in a non-reactive environment, such as a high temperature.

[0063] After the body annealing process, the manufacturing process continues by applying a source implant to form a source region 96 in the mesa of the semiconductor layer 92 between the trench gate structures. For example, the source implant can be a heavily doped N-type implant. A source annealing process for the source implant is performed to anneal and diffuse the implanted dopants, thereby forming a source region 96 in the trench MOSFET device. The annealing process can be performed in a non-reactive environment, such as a high temperature. After the source annealing process, the trench MOSFET device is encapsulated by a dielectric layer 132. In the present embodiment, the dielectric layer 132 can be a low temperature oxide layer (LTO) or a combination of LTO and a borophosphosilicate glass (BPSG) layer. The dielectric layer 132 can be deposited using, for example, a CVD process. After the BPSG is deposited, the semiconductor structure can be planarized, as shown in FIG. 11( a).

[0064] Referring to FIG. 11( b ), a first contact mask (not shown) is applied to define openings to be formed in the dielectric layer 132 and the semiconductor layer 92. A contact etching process, such as an anisotropic dry etching process, is then performed using the first contact mask to etch the dielectric layer 132 and the semiconductor layer 92 through the source region 96 and into the body region 95, thereby forming a body contact opening 134, as shown in FIG. 11( b ). A trench source / body contact will be formed in the body contact opening 134. The contact opening 134 extends in the Y direction along the length of the trench gate structure.

[0065] 11( c ), a first body contact implant 138 is applied to dope the bottom of the body contact opening 134 . For example, the body contact implant 138 may be a low dose P-type implant. In one example, the body contact implant 138 uses boron as a P-type dopant and has a 5×10 3 / cm 2 11( d ), a second contact mask 140 is applied to the semiconductor layer 92 above the dielectric layer 132. The second contact mask 140 defines the location where the first MOSFET portion is to be formed. In particular, the second contact mask 140 defines an opening 142 extending in the X direction, which is orthogonal to the contact opening 134 extending in the Y direction. In this way, the opening 142 (X direction) is formed in self-alignment with the opening 134 (Y direction) formed in the dielectric layer 132. In particular, the opening 142 exposes a portion of the body contact opening 134.

[0066] As shown in FIG. 11( d ), a portion of the body contact opening 134 is exposed using an opening 142 defined by the second contact mask 140, and a second body contact implant is applied to introduce additional body contact dopants into the bottom of the exposed body contact opening 136. As a result, the body contact opening 136 exposed by the opening 142 receives a total implant dose 144, which is the sum of the first body contact implant and the second body contact implant. For example, the second body contact implant may be a P-type dopant using boron and having a dopant of 8×10 4 / cm 2 to 1x10 5 / cm 2 The first and second body contact implants are subjected to an annealing process to anneal and diffuse the implanted dopants to form body contact doped regions 102 and 97 in the trench MOSFET device, as shown in FIG. 11( e). The annealing process can be performed in a non-reactive environment at a high temperature, for example, after removing the second contact mask 140. In one example, with a 1x10 17 / cm 3 Up to 1x10 18 / cm 3 Compared to the doping level of the body contact region 102, as annealed, the body contact doping region 97 has a doping level of 5x10 19 / cm 3 Up to 2x10 20 / cm 3 The body region 95 may have a doping level of 5x10 16 / cm 3 Up to 2x10 17 / cm 3 of doping level.

[0067] Subsequently, referring to FIG. 11( f), a tungsten plug 98 is formed in the contact opening 134. For example, the tungsten plug 98 may include a conductive adhesion layer, such as a titanium (Ti) and / or titanium nitride (TiN) layer, and then a tungsten filling layer, both of which are deposited by a CVD or PVD process. A conductive layer 99 is then deposited on the semiconductor structure. In one embodiment, the conductive layer 99 is an aluminum layer and may be deposited using a PVD process or evaporation. A metal mask may be applied, and the conductive layer 99 may be etched using the metal mask to form a metal interconnect. At this stage, the manufacturing process for forming a trench MOSFET device is completed.

[0068] By this construction, the tungsten plug 98 contacts the source region 96 and the body contact doping region 97 in the first MOSFET portion 90, and the tungsten plug 1998 contacts the source region 96 and the body contact doping region 102 in the second MOSFET portion 100. In this way, the NMOS transistor formed in the second MOSFET portion 100 has a higher body contact resistance than the NMOS-transistor formed in the first MOSFET portion 90, which has a more heavily doped body contact doping region 97 and therefore has a lower body contact resistivity. However, the device characteristics of the NMOS transistor in the second MOSFET portion 100 can be better than those in the first MOSFET portion 90, such as having a lower threshold voltage.

[0069] The drawings provided herein are idealized representations for illustrating embodiments of the present disclosure and are not meant to be actual views of any particular component, structure, or device. The drawings are not drawn to scale, and the dimensions and relative sizes and sizes of layers and regions may be exaggerated for clarity. It is expected that the shapes of the illustrations will vary. For example, an area illustrated as a box shape may generally have rough and / or nonlinear features. Sharp angles shown may be rounded. The same numbers refer to the same components throughout the text.

[0070] In this specification, for ease of description, spatial relative terms may be used herein, for example, "below", "below", "bottom", "above", "top", etc., as shown in the figure to describe the relationship of one element or feature to another element or feature. It should be understood that spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the figure. For example, if the device in the figure is turned over, the elements described as "below" or "below" other elements or features will be oriented as "above" other elements or features. Therefore, the exemplary term "below" can include directions above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly.

[0071] It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0072] In this detailed description, a process step described for one embodiment may be used for a different embodiment even if the process step is not explicitly described in the different embodiments. When a method comprising two or more defined steps is referred to herein, the defined steps may be performed in any order or simultaneously unless the context indicates or specific instructions are otherwise provided herein. In addition, unless the context indicates or otherwise provides clear instructions, the method may also include one or more other steps performed before any defined step, between two defined steps, or after all defined steps.

[0073] In this detailed description, various embodiments or examples of the present invention can be implemented in many ways, including as a process; an instrument; a system; and a composition of matter. A detailed description of one or more embodiments of the present invention and drawings illustrating the principles of the present invention are provided above. The present invention is described in conjunction with these embodiments, but the present invention is not limited to any embodiment. Many modifications and variations within the scope of the present invention are possible. The scope of the present invention is limited only by the claims, and the present invention includes many alternatives, modifications and equivalents. In order to provide a comprehensive understanding of the present invention, many specific details are set forth in the specification. These details are provided for illustrative purposes, and the present invention can be practiced according to the claims without some or all of these specific details. For the sake of clarity, technical materials known in the technical field related to the present invention are not described in detail so that the present invention will not be unnecessarily obscured. The present invention is defined by the appended claims.

Claims

1. A trench MOSFET device having a first current terminal, a second current terminal and a gate terminal, characterized in that: The trench MOSFET device comprises: a trench gate structure formed in a trench in a semiconductor layer of a first conductivity type, the trench gate structure comprising a conductive gate layer formed in the trench and isolated from the semiconductor layer by a gate dielectric layer, the conductive gate layer forming the gate terminal; a body region of the second conductivity type in and at the first surface of the semiconductor layer adjacent to the trench; a first doped region of a first conductivity type formed in the body region and at a first surface of the semiconductor layer adjacent to the trench, the first doped region forming the first current terminal, wherein the semiconductor forms the second current terminal; and a first body contact doped region of a second conductivity type formed in a first portion of the body region and spaced apart from the first doped region and spaced apart from the trench, the first body contact doped region being more heavily doped than the body region, The trench MOSFET device includes a first MOSFET portion formed in the first portion of the body region, and a second MOSFET portion formed outside the first portion of the body region, wherein a body contact resistance of the first MOSFET portion is lower than a body contact resistance of the second MOSFET portion.

2. The trench MOSFET device according to claim 1, characterized in that Also includes: a conductive body contact formed in an isolation layer formed on the semiconductor layer, the body contact contacting a first doped region at a first surface of the semiconductor layer in an area outside the first portion of the body region; and the body contact extending through the first doped region to contact the first doped region and the first body contact doped region formed in the first portion of the body region; as well as A conductive layer is formed over the isolation layer and in contact with the body contact, wherein the first MOSFET portion includes the body contact contacting the first doped region and the first body contact doped region, and the second MOSFET portion includes a body contact contacting only the first doped region.

3. The trench MOSFET device according to claim 1, characterized in that: The length of the trench extends along a first direction in the semiconductor layer, the width of the trench extends in a second direction, the second direction is orthogonal to the first direction and is in the same plane as the first surface of the semiconductor layer, the length of the trench is greater than the width, and wherein a body region formed in the semiconductor layer adjacent to the trench extends along the first direction, and the first portion of the body region includes a portion of the body region located in the first direction.

4. The trench MOSFET device according to claim 1, characterized in that: The first MOSFET portion and the second MOSFET portion form a MOS transistor connected in parallel, wherein the first doped region forms a first current terminal of the first and second MOSFET portions, the semiconductor layer forms a second current terminal of the first and second MOSFET portions, and the conductive gate layer forms a gate terminal of the first and second MOSFET portions.

5. The trench MOSFET device according to claim 1, characterized in that: The first MOSFET portion has a first transistor area, and the second MOSFET portion has a second transistor area, the first transistor area being smaller than the second transistor area.

6. The trench MOSFET device according to claim 5, characterized in that: The first transistor area is between 5% and 25% of the second transistor area.

7. The trench MOSFET device according to claim 1, characterized in that: The first MOSFET portion has a first threshold voltage, the second MOSFET portion has a second threshold voltage, and the first threshold voltage is greater than the second threshold voltage.

8. The trench MOSFET device according to claim 1, wherein: The trench MOSFET device includes an array of trench transistor cells, which are defined by trench gate structures and associated body regions and a first doped region formed in a semiconductor layer between an adjacent pair of trench gate structures, the first MOSFET portion includes trench transistor cells formed in a first portion of a body region including the first body contact doped region, and the second MOSFET portion includes trench transistor cells formed outside the first portion of the body region.

9. The trench MOSFET device according to claim 1, characterized in that: Also includes: A second body contact doping region of a second conductivity type is formed in the body region outside the first portion, the second body contact doping region is spaced apart from the first doping region and from the trench, and the second body contact doping region is more heavily doped than the body region and more lightly doped than the first body contact doping region.

10. The trench MOSFET device according to claim 9, characterized in that: Also includes: a conductive body contact formed in an isolation layer formed over the semiconductor layer, the body contact extending through the first doped region to contact the first doped region and the first body contact doped region formed in a first portion of the body region, and the body contact extending through the first doped region to contact the first doped region and the second body contact doped region in the body region formed outside the first portion; as well as a conductive layer formed on the isolation layer and in contact with the body contact, The first MOSFET portion includes a body contact contacting the first doped region and the first body contact doped region, and the second MOSFET portion includes a body contact contacting the first doped region and the second body contact doped region.

11. A method for preparing a trench MOSFET device, characterized in that: include: providing a semiconductor layer of a first conductivity type; forming an array of trench transistor cells in the semiconductor layer, including forming trench transistor cells defined by trench gate structures; forming a body region of a second conductivity type in the array of trench transistor cells; forming a source region of a first conductivity type in a body region of the trench transistor cell array; forming a first body contact doping region of a second conductivity type in each body region in a first portion of the trench transistor cell array, the first body contact doping region being spaced apart from a source region formed in a corresponding body region and being spaced apart from the trench gate structure, the first body contact doping region being more heavily doped than the body region; forming a body contact connected to the first body contact doping region in the first portion of the body region, and forming a body contact connected only to the source region outside the first portion of the body region; and A first conductive layer is formed connecting the body contacts.

12. The method according to claim 11, characterized in that The first MOSFET portion is formed in a first portion of the trench transistor cell array, and the second MOSFET portion is formed outside the first portion, and a body contact resistance of the first MOSFET portion is lower than a body contact resistance of the second MOSFET portion.

13. The method according to claim 11, characterized in that Also includes: forming a second body contact doping region of the second conductivity type in each body region outside the first portion, the second body contact doping region being spaced apart from the source region formed in the corresponding body region and being spaced apart from the trench gate structure, the second body contact doping region being more heavily doped than the body region and more lightly doped than the first body contact doping region; and A body contact connected to the first body contact doping region is formed in the first portion of the trench transistor cell, and a body contact connected to the second body contact doping region is formed outside the first portion.

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