A radiation-resistant super-junction power MOS device and a method for preparing the same

Abstract

The present invention discloses a radiation-resistant superjunction power MOS device and a preparation method thereof, wherein the device comprises a substrate layer, a buffer layer and an epitaxial layer stacked in sequence from bottom to top, wherein a plurality of superjunction columns arranged at intervals are arranged in the epitaxial layer, and a body region is arranged above each superjunction column; a hole-doped region and a source-doped region in contact with each other are arranged in the body region; a gate oxide layer is arranged on the upper surface of the epitaxial layer, and the lower surface of the gate oxide layer is in contact with the epitaxial layer, the body region and part of the upper surface of the source-doped region; the upper surface of the gate oxide layer is covered with a polysilicon layer, and the gate oxide layer and the polysilicon layer form a gate electrode; an interval doping injection region is also arranged on the epitaxial layer not covered by the gate oxide layer between adjacent body regions. The present invention can reduce the number of holes gathered below the gate oxide region after particle incidence through the interval doping injection region, thereby improving the SEGR capability; reduce the current passing through the base resistance of the parasitic transistor, and improve the threshold of SEB.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor radiation resistance, and in particular relates to a radiation-resistant super junction power MOS device and a preparation method thereof. Background Art

[0002] There are a large number of X-rays, gamma rays, neutrons, heavy particles, etc. in the universe. Spacecraft will be irradiated by such rays and particles when operating in space, causing disturbances in the spacecraft's electronic system, and even causing the electronic system to fail, seriously affecting the safe operation of the spacecraft on orbit. X-ray and gamma ray radiation power MOS (Metal-Oxide-Semiconductor) devices mainly cause the total dose effect of ionizing radiation, causing the drift of device parameters; neutron radiation power MOS devices mainly cause the increase of the device's own power consumption, which can be solved by redundant design; and heavy particle radiation power MOS devices will cause single event gate rupture (SEGR) and single event burnout (SEB) effects, causing device failure and making the electronic system lose its function, especially for power MOS devices with micron / submicron manufacturing processes and planar structures. The single particle radiation hardening of power MOS devices has become one of the bottlenecks and shortcomings that restrict the development of satellite power technology, information security control, and independent protection of core components.

[0003] Compared with traditional power VDMOS (Vertical Double-Diffused-Metal-Oxide-Semiconductor) devices, the on-resistance per unit area of ​​super-junction power MOS devices is reduced by more than 5 times. Under the same area, the system efficiency is significantly improved. Under the same resistance specifications, the area is greatly reduced, and a smaller package can be used to save costs. At the same time, the gate charge Qg is reduced, and the conduction loss is reduced. The lateral electric field of the super-junction structure allows more holes to flow to the source through the P column, making it more difficult for the parasitic transistor to turn on, thereby improving the ability to resist SEB. On the other hand, it reduces the vertical electric field of the gate oxide layer and improves the ability to resist SEGR. These advantages make it one of the core components of secondary DC / DC (Direct Current-Direct Current) power supplies for satellites. It plays the role of power conversion or power transformation in the power supply system and provides the necessary energy for the normal operation of satellite electronic systems.

[0004] At present, the measures for strengthening the single particle effect of super junction power MOS devices are mainly to reasonably set the buffer layer doping concentration, body region doping concentration, source doping region doping concentration, etc. Although super junction power MOS devices have certain advantages in radiation resistance compared to traditional VDMOS devices, and the use of existing technologies can also improve the radiation resistance of super junction power MOS devices to a certain extent, for high-voltage and ultra-high voltage super junction power MOS devices, such as super junction power MOS devices above 600V, due to the limit capacity of the gate oxide layer, the existing reinforcement measures still cannot meet the device's resistance to single particle gate penetration, and the existing reinforcement measures will affect the performance indicators of the super junction power MOS device itself to a certain extent, such as on-resistance, conduction loss, etc. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a radiation-resistant super junction power MOS device and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] The present invention provides a radiation-resistant super-junction power MOS device, comprising a substrate layer, a buffer layer and an epitaxial layer stacked in sequence from bottom to top, wherein:

[0007] The epitaxial layer is provided with a plurality of super junction columns arranged at intervals, and a body region is provided above each super junction column;

[0008] A hole doping region and a source doping region in contact with each other are provided in the body region, and the upper surfaces of the body region, the hole doping region and the source doping region are all flush, and the depths of the hole doping region and the source doping region are less than the depth of the body region;

[0009] A gate oxide layer is also provided on the upper surface of the epitaxial layer, and the lower surface of the gate oxide layer contacts the upper surfaces of the epitaxial layer, the body region and part of the source doping region; the upper surface of the gate oxide layer is covered with a polysilicon layer, and the gate oxide layer and the polysilicon layer form a gate electrode;

[0010] An interval doping injection region is also provided on the epitaxial layer not covered by the gate oxide layer between adjacent body regions, the hole doping region is located on a side of the source doping region away from the interval doping injection region, the source doping region and the interval doping injection region have different doping types, and the super junction column, the body region, the hole doping region and the interval doping injection region have the same doping type.

[0011] Another aspect of the present invention provides a method for preparing a radiation-resistant super-junction power MOS device, the method comprising:

[0012] S1: selecting a substrate layer and growing a buffer layer on the upper surface of the substrate layer;

[0013] S2: forming an epitaxial layer on the buffer layer, wherein the epitaxial layer includes a plurality of super junction pillars arranged vertically at intervals;

[0014] S3: preparing a body region above each of the super junction pillars;

[0015] S4: forming a hole doping region in each body region, and forming an interval doping implantation region in the epitaxial layer between adjacent body regions;

[0016] S5: growing a gate oxide layer on the epitaxial layer, and depositing a polysilicon layer on the gate oxide layer, wherein a lower surface of the gate oxide layer contacts the body region and a portion of an upper surface of the epitaxial layer, and the spaced doping implantation region is distributed in a region of the epitaxial layer not covered by the gate oxide layer;

[0017] S6: forming a source doping region in each body region, wherein the source doping region is located on a side of the hole doping region close to the gate oxide layer.

[0018] Furthermore, the method further comprises:

[0019] S7: depositing an interlayer dielectric on the upper surface of the sample obtained in S6, and etching the deposited interlayer dielectric to form a contact hole to expose the hole doping region, the spacer doping injection region and a portion of the source doping region to form an interlayer dielectric layer;

[0020] S8: forming a source metal layer on the upper surface of the sample obtained in S7, and the lower surface of the source metal layer is in contact with the hole doping region, the spacer doping injection region and a part of the source doping region;

[0021] S9: forming a drain metal layer on the lower surface of the substrate layer.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The present invention provides a radiation-resistant super-junction power MOS device. The design of an interval doping injection region can reduce the number of carriers gathered below the gate oxide region during particle incidence, reduce the gate oxide electric field, and improve the device's ability to resist single-particle gate breakdown (SEGR); on the other hand, by reasonably designing the doping distribution of the interval doping injection region, the device can be preferentially broken down in the interval doping injection region under a strong electric field to form a current shunt, reduce the current passing through the base resistance of the parasitic transistor, and improve the threshold of single-particle burnout (SEB); at the same time, combined with the design of an arched source doping region, the area of ​​the source doping region is reduced, the injection efficiency of the parasitic transistor emitter is reduced, and the parasitic transistor is prevented from being turned on, thereby further reducing the probability of the device having single-particle burnout (SEB) after single-particle incidence. In addition, the present invention distributes the spaced doping injection regions at intervals in the area where the gate oxide layer is located and does not contact the gate oxide layer, which will not significantly reduce the flow path area of ​​the current during forward conduction, thereby further improving the device's resistance to single-particle radiation without changing the performance indicators of the device itself. This design reduces the area of ​​the gate, reduces the Miller capacitance, further improves the switching speed of the device, reduces switching losses, and improves the power conversion efficiency of the overall power supply system.

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a partial structural schematic diagram of a unit cell of a radiation-resistant super junction power MOS device provided by an embodiment of the present invention;

[0026] Figure 2 A vertical projection diagram of a gate oxide layer and an interval doping implantation region when the gate oxide layer includes a connecting portion provided by an embodiment of the present invention;

[0027] Figure 3 A vertical projection diagram of a gate oxide layer and an interval doping implantation region when the gate oxide layer includes two connecting parts provided by an embodiment of the present invention;

[0028] Figure 4 is a front view of a radiation-resistant super-junction power MOS device provided by an embodiment of the present invention;

[0029] Figures 5a to 5j It is a schematic diagram of a preparation process of a radiation-resistant super-junction power MOS device provided by an embodiment of the present invention;

[0030] Figure 6 is a comparison diagram of the gate oxide electric field of the radiation-resistant super junction power MOS device provided by an embodiment of the present invention and the conventional super junction power MOS device at the same time after incident at 1.5 μm under the same bias condition;

[0031] Figure 7 It is a comparison diagram of the secondary breakdown voltage of the radiation-resistant super junction power MOS device provided by an embodiment of the present invention and the traditional super junction power MOS device. DETAILED DESCRIPTION

[0032] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, a radiation-resistant super-junction power MOS device and a preparation method thereof proposed in accordance with the present invention are described in detail below in combination with the accompanying drawings and specific implementation methods.

[0033] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0034] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the statement "including one..." do not exclude the existence of other identical elements in the article or device including the elements.

[0035] Embodiment 1

[0036] See also Figure 1 , Figure 1 It is a partial structural schematic diagram of a unit cell of a radiation-resistant super junction power MOS device provided in an embodiment of the present invention. The radiation-resistant super junction power MOS device includes a substrate layer 1, a buffer layer 2 and an epitaxial layer 3 stacked in sequence from bottom to top. Exemplarily, the substrate layer 1 is a Si substrate with a thickness of 715~735μm and a resistivity of 0.002~0.006Ω.cm. The buffer layer 2 includes several layers of buffer layers with different doping concentrations and different thicknesses. Preferably, the resistivity of the buffer layer 2 is 0.01~5Ω.cm, the thickness is 5~50μm, and the number of layers is 2~5. The resistivity of the epitaxial layer 3 is 1~50Ω.cm, and the thickness is 5~20μm.

[0037] The epitaxial layer 3 is provided with a plurality of super junction pillars 4 arranged at intervals, and a body region 5 is provided above each super junction pillar 4. It should be noted that: Figure 1The schematic diagram only shows a partial structure of a unit cell of the radiation-resistant super junction power MOS device. The overall structure of the radiation-resistant super junction power MOS device is a plurality of unit cells connected along the Figure 1 That is, each radiation-resistant super-junction power MOS device includes a plurality of super-junction pillars 4 arranged in parallel, and each super-junction pillar 4 includes a body region 5. The width of the body region 5 along the lateral direction is greater than that of the super-junction pillar 4, and adjacent body regions 5 are spaced apart from each other. It should be noted that Figure 1 The superjunction column 4 and body region 5 on the left side of the middle and the superjunction column 4 and body region 5 on the right side are both half, and adjacent unit cells are spliced ​​into a complete superjunction column 4 and body region 5.

[0038] A hole-doped region 6 and a source-doped region 7 in contact with each other are provided in each body region 5, and the upper surfaces of the body region 5, the hole-doped region 6 and the source-doped region 7 are all flush with the upper surface of the epitaxial layer 3, and the depths of the hole-doped region 6 and the source-doped region 7 are both less than the depth of the body region 5, so that the hole-doped region 6 and the source-doped region 7 are not in contact with the super junction column 4 below.

[0039] Furthermore, the hole doping region 6 and the source doping region 7 in the same body region 5 are both formed from the first edge ( Figure 1 ) to the second edge ( Figure 1 ), the contact surfaces of the hole-doped region 6 and the source-doped region 7 are both in a bow shape, and respectively include protrusions and recesses arranged alternately, wherein the protrusions of the hole-doped region 6 and the recesses of the source-doped region 7 are nested with each other, and the recesses of the hole-doped region 6 and the protrusions of the source-doped region 7 are nested with each other.

[0040] Specifically, on the contact surface between the hole-doping region 6 and the source-doping region 7, the hole-doping region 6 has a plurality of protrusions and recesses are formed between adjacent protrusions, and correspondingly, the source-doping region 7 also has a plurality of protrusions and recesses are formed between adjacent protrusions, and the protrusions of the source-doping region 7 are embedded in the recesses of the hole-doping region 6, and correspondingly, the protrusions of the hole-doping region 6 are embedded in the recesses of the source-doping region 7.

[0041] The contact surface between the hole-doped region 6 and the source-doped region 7 in each body region 5 is alternately nested by protrusions and recesses, which can reduce the area of ​​the upper surface of the source-doped region 7, thereby reducing the contact area with the source metal, reducing the injection efficiency of the emitter of the parasitic transistor, and thus reducing the probability of the parasitic transistor being turned on. Combined with the design of the interval-doped injection region 10 described below, the probability of single-particle burnout (SEB) of the super-junction power MOS device after single-particle incidence can be further reduced.

[0042] In this embodiment, the upper surface of the epitaxial layer 3 is also provided with a gate oxide layer 8, and the lower surface of the gate oxide layer 8 is in contact with the upper surface of the epitaxial layer 3, the body region 5, and part of the source doping region 7; the upper surface of the gate oxide layer 8 is covered with a polysilicon layer 9, and the gate oxide layer 8 and the polysilicon layer 9 form a gate electrode; the epitaxial layer 3 between adjacent body regions 5 that is not covered by the gate oxide layer 8 is also provided with an interval doping injection region 10, and the hole doping region 6 is located on the side of the source doping region 7 away from the interval doping injection region 10, and the source doping region 7 and the interval doping injection region 10 have different doping types, and the super junction pillar 4, the body region 5, the hole doping region 6 and the interval doping injection region 10 have the same doping type. Exemplarily, the thickness of the gate oxide layer 8 is 40-120nm, and the thickness of the polysilicon layer 9 is 500-1000nm.

[0043] Specifically, the gate oxide layer 8 includes a first part, a second part and at least one connecting part, wherein the first part and the second part are parallel to each other and both extend from a first edge to a second edge of the upper surface of the epitaxial layer 3, the connecting part is connected between the first part and the second part, and the interval doping injection region 10 is arranged on the upper surface of the epitaxial layer 3 not covered by the connecting part between the first part and the second part, that is, the interval doping injection region 10 is not arranged in the epitaxial layer 3 covered by the connecting part.

[0044] When the gate oxide layer 8 includes a plurality of connection parts, different connection parts are used to connect different regions of the first part and the second part. In this case, the interval doping implantation region 10 is also arranged between two adjacent connection parts, and does not contact the lower surface of each connection part. For example, it can be arranged between some adjacent connection parts, or between every two adjacent connection parts. For example, Figure 2 As shown, when the gate oxide layer 8 includes a first portion 81, a second portion 82 and a connecting portion 83, the vertical projection of the region where the gate oxide layer 8 is located is in an "H" shape, and two spaced doping implantation regions (see Figure 2 10a, 10b) are spaced apart between the connecting parts 83. Figure 3 As shown, when the gate oxide layer 8 includes a first portion 81, a second portion 82 and two connecting portions (see Figure 3 83a and 83b), three spaced doping implantation regions (see Figure 3 10a, 10b and 10c) are spaced apart between the connecting portions (83a and 83b).

[0045] The present invention sets an interval doping injection region 10 on the epitaxial layer 3 not covered by the gate oxide layer 8 between adjacent body regions 5. On the one hand, when the super junction power MOS device encounters heavy ion radiation, under the same bias conditions, the accumulation of carriers below the gate oxide layer 8 after particle incidence is reduced, thereby reducing the electric field strength of the gate oxide layer 8 during particle incidence and improving the SEGR resistance of the super junction power MOS device; on the other hand, the interval doping injection region of the super junction power MOS device preferentially breaks down under a strong electric field to form a current shunt, thereby reducing the current passing through the base resistance of the parasitic transistor and reducing the probability of single particle burnout (SEB); at the same time, the hole doping region 6 and the source doping region 7 in each body region 5 are alternately nested and distributed through protrusions and recesses, which can reduce the area of ​​the source doping region 7, reduce the injection efficiency of the parasitic transistor emitter, and thus reduce the probability of the parasitic transistor being turned on, and finally further reduce the probability of single particle burnout (SEB) of the super junction power MOS device after single particle incidence. In addition, the present invention does not significantly reduce the flow path area of ​​the current during forward conduction by distributing the spaced doping injection regions 10 at intervals in the area where the gate oxide layer 8 is located and not contacting the gate oxide layer 8. This can further improve the device's ability to resist single-particle radiation without changing the performance indicators of the super-junction power MOS device itself. Moreover, this design reduces the gate area of ​​the super-junction power MOS device, reduces the gate-drain capacitance, further improves the switching speed of the super-junction power MOS device, reduces switching losses, and improves the power conversion efficiency of the entire power supply system where the super-junction power MOS device is located.

[0046] Also, see Figure 4 , Figure 4 It is a cross-sectional schematic diagram of a radiation-resistant super junction power MOS device provided by an embodiment of the present invention. The radiation-resistant super junction power MOS device of this embodiment also includes an interlayer dielectric layer 11 and a source metal layer 12, wherein the interlayer dielectric layer 11 covers the upper surface of the polysilicon layer 9, the source metal layer 12 is arranged on the interlayer dielectric layer 11, and the interlayer dielectric layer 11 is used to isolate the polysilicon layer 9 and the source metal layer 12, and a plurality of contact holes are opened on the interlayer dielectric layer 11, so that the source metal layer 12 can contact the hole doping region 6, the source doping region 7 and the interval doping injection region 10. The radiation-resistant super junction power MOS device also includes a drain metal layer 13 located on the lower surface of the substrate layer 1.

[0047] Exemplarily, the material of the interlayer dielectric layer 11 is silicon dioxide, with a thickness of 600-1000 nm. The material of the source metal layer 12 is Al, with a thickness of 4-6 μm. The material of the drain metal layer 13 is Ti / Ni / Ag, with a thickness of 5-10 μm. It should be noted that Figure 1In order to clearly show the structure of the super junction power MOS device, the dotted area represents the interlayer dielectric layer 11, and the source metal layer 12, the drain metal layer 13 and the conventional passivation layer are not shown.

[0048] Exemplarily, the depths of the hole doping region 6, the source doping region 7 and the spacer doping injection region 10 are all less than the depth of the body region 5; the lower surface of the super junction pillar 4 is not in contact with the upper surface of the buffer layer 2. The doping concentration of the epitaxial layer 3 and the doping concentration of the super junction pillar 4 are both less than the doping concentration of the substrate layer 1.

[0049] The radiation-resistant super-junction power MOS device of the present invention can be an N-channel device or a P-channel device. When the radiation-resistant super-junction power MOS device provided by the present invention is an N-channel device, the substrate layer 1 is an N-type substrate, the doping type of the buffer layer 2 and the epitaxial layer 3 is N, the doping type of the super-junction column 4, the body region 5, the hole doping region 6 and the interval doping injection region 10 are all P, and the doping type of the source doping region 7 is N, that is, the N-channel super-junction power MOS device provided by the present invention includes: an N-type substrate, an N-type buffer layer, an N-type epitaxial layer, a P super-junction column, a P-body region, a hole P+ region, an interval P+ region and a source N+ region.

[0050] When the radiation-resistant super-junction power MOS device set provided by the present invention is a P-channel device, the substrate layer 1 is a P-type substrate, the doping types of the buffer layer 2 and the epitaxial layer 3 are P, the doping types of the super-junction column 4, the body region 5, the hole-doped region 6 and the interval-doped injection region 10 are all N, and the doping type of the source doping region 7 is P, that is, the P-channel super-junction power MOS device provided by the present invention includes: a P-type substrate, a P-type buffer layer, a P-type epitaxial layer, an N super-junction column, an N-body region, a hole N+ region, an interval N+ region and a source P+ region.

[0051] Embodiment 2

[0052] Based on the first embodiment, this embodiment provides a method for preparing a radiation-resistant super junction power MOS device, such as Figures 5a to 5j As shown, the preparation method comprises:

[0053] S1: Select a substrate layer 1 and sequentially grow a buffer layer 2 and an epitaxial layer 3 on the upper surface of the substrate layer 1, such as Figure 5a shown.

[0054] The substrate layer 1 of this embodiment is a Si substrate, and has a thickness of 715-735 μm and a resistivity of 0.002-0.006 Ω.cm. Specifically, when preparing an N-channel device, a heavily doped N-type Si substrate is selected as the substrate layer 1, and when preparing a P-channel device, a heavily doped P-type Si substrate is selected as the substrate layer 1.

[0055] Several buffer layers 2 with different doping concentrations and thicknesses can be grown on the upper surface of the substrate layer 1. For example, the resistivity of the buffer layer 2 is 0.01-0.5Ω.cm, the thickness of the buffer layer 2 is 20-50μm, and the number of the buffer layer layers is 2-5.

[0056] S2: forming an epitaxial layer 3 on the buffer layer 2, wherein the epitaxial layer 3 includes a plurality of super junction pillars 4 arranged vertically at intervals.

[0057] In this step, after multiple epitaxial depositions and ion implantations, an epitaxial layer 3 including a plurality of super junction pillars 4 arranged vertically at intervals is formed on the upper surface of the buffer layer 2 .

[0058] Specifically, when preparing an N-channel device, an intrinsic epitaxial layer with a thickness of 1 to 10 μm can be deposited on the surface of the sample obtained in step S1, and N-type ions are implanted on the front side of the intrinsic epitaxial layer with an implantation energy of 100 to 300 KeV and an implantation dose of 1×10 12 ~9×10 13 , forming an N-type epitaxial layer; then, spin-coating photoresist, using a mask for exposure and development, to obtain a superjunction column pattern window, and performing P-type ion implantation in the superjunction column pattern window, with an energy of 100 ~300 KeV and an implantation dose of 1×10 12 ~9×10 13 The epitaxial layer deposition and ion implantation process is repeated for 5 to 15 times or more, thereby forming an epitaxial layer 3 including a plurality of superjunction pillars 4 arranged vertically at intervals on the upper surface of the buffer layer 2, such as Figure 5b shown.

[0059] When preparing a P-channel device, an intrinsic epitaxial layer with a thickness of 1 to 10 μm can be deposited on the surface of the sample obtained in step S1, and P-type ions are implanted on the front side of the intrinsic epitaxial layer with an implantation energy of 100 to 300 KeV and an implantation dose of 1×10 12 ~9×10 13 , forming a P-type epitaxial layer; then, spin-coating photoresist, using a mask plate for exposure and development, to obtain a super-junction column pattern window, and performing N-type ion implantation in the super-junction column pattern window, with an energy of 100~300 KeV and an implantation dose of 1×10 12 ~9×10 13 The epitaxial layer deposition and ion implantation process is repeated 5 to 15 times or more, thereby forming an epitaxial layer 3 including a plurality of super junction pillars 4 arranged vertically at intervals on the upper surface of the buffer layer 2.

[0060] S3: preparing a body region 5 above each super junction pillar 4 .

[0061] Specifically, when preparing an N-channel device, a photoresist is spin-coated on the sample surface, and then a mask is used for exposure and development to obtain a body pattern window. Boron ions are injected into the body pattern window with an energy of 100 to 300 KeV and an injection dose of 1×10 12 ~9×10 13 ,like Figure 5c When preparing a P-channel device, photoresist can be spin-coated on the sample surface, and then a mask is used for exposure and development to obtain a body pattern window. Phosphorus ions are injected into the body pattern window with an energy of 100 to 300 KeV and an injection dose of 1×10 12 ~9×10 13 .

[0062] S4 : forming a hole doping region 6 in each body region 5 , and forming an interval doping implantation region 10 in the epitaxial layer 3 between adjacent body regions 5 .

[0063] In some embodiments, step S4 may be implemented by the following steps:

[0064] Through photolithography and implantation processes, a hole doping region 6 is formed in each body region 5 at one time, and an interval doping implantation region 10 is formed in the epitaxial layer 3 between the body regions 5, wherein the hole doping region 6 has the same doping concentration as the interval doping implantation region 10. Specifically, a photoresist is spin-coated on the surface of the sample obtained in step S2, and then, a mask is used for exposure and development to obtain a hole doping pattern window on each body region 5 and an interval doping implantation window on the upper surface of the epitaxial layer 3 between the body regions 5, and then, boron ions are simultaneously implanted into the hole doping pattern window and the interval doping implantation window. Exemplarily, the implantation energy is 100-300 KeV, and the implantation dose is 1×10 14 ~5×10 15 .

[0065] In some other embodiments, step S4 may also be implemented as follows:

[0066] First, a hole doping region 6 is formed in each body region 5 by photolithography and implantation process. Specifically, photoresist can be spin-coated on the surface of the sample obtained in step S2, and then, a mask is used for exposure and development to obtain a hole doping pattern window on each body region 5, and then boron ions are implanted in the hole doping pattern window, such as Figure 5d As shown. For example, the implantation energy is 100-300 KeV and the implantation dose is 1×10 14 ~5×10 15 .

[0067] Subsequently, through photolithography and implantation processes, an interval doping implantation region 10 is formed in the epitaxial layer 3 between the body regions 5, wherein the doping concentrations of the hole doping region 6 and the interval doping implantation region 10 may be different or the same. Specifically, a photoresist may be spin-coated on the surface of the sample after the body regions 5 are prepared, and then, exposure and development are performed using a mask plate, and an interval doping implantation window is obtained on the upper surface of the epitaxial layer 3 between the body regions 5, and boron ions are implanted in the interval doping implantation window to form the interval doping implantation region 10, such as Figure 5e As shown. For example, the implantation energy is 100-300 KeV and the implantation dose is 1×10 14 ~5×10 15 .

[0068] In addition, in some embodiments, before preparing the body region 5 on each super junction column 4, it may also include: forming a JFET (Junction Field-Effect Transistor) region (not shown in the drawings) in the central area of ​​the epitaxial layer 3.

[0069] Specifically, when preparing an N-channel device, a photoresist is spin-coated on the sample surface after preparing the superjunction pillar 4, and then a mask is used for exposure and development to obtain a JFET injection pattern window, and then phosphorus ions are injected into the JFET injection pattern window. When preparing a P-channel device, a photoresist is spin-coated on the sample surface after preparing the superjunction pillar 4, and then a mask is used for exposure and development to obtain a JFET injection pattern window, and then boron ions are injected into the JFET injection pattern window. For example, the injection energy is 200-400 KeV, and the injection dose is 2×10 12 ~2×10 13 .

[0070] S5: growing a gate oxide layer 8 on the epitaxial layer 3, and depositing a polysilicon layer 9 on the gate oxide layer 8, wherein the lower surface of the gate oxide layer 8 is in contact with the body region 5 and a portion of the upper surface of the epitaxial layer 3, and the spaced doping implantation regions 10 are distributed in the regions of the epitaxial layer 3 not covered by the gate oxide layer 8.

[0071] Specifically, the sample surface obtained in step S3 is thermally oxidized to grow a gate oxide layer 8, and a polysilicon layer 9 is deposited on the gate oxide layer 8. After that, a photoresist is spin-coated on the obtained wafer surface, and a mask is used for exposure and development to obtain a pattern window, and etching is performed according to the pattern window. For example, the position and shape of the gate oxide layer 8 and the polysilicon layer 9 after etching are shown in FIG. Figure 1 and Figure 5f .

[0072] Exemplarily, the thickness of the gate oxide layer 8 is 50-120 nm, and the thickness of the polysilicon layer 9 is 500-1000 nm.

[0073] S6: forming a source doping region 7 in each body region 5, wherein the source doping region 7 is located on a side of the hole doping region 6 close to the gate oxide layer 8, a portion of the upper surface of the source doping region 7 is in contact with the lower surface of the gate oxide layer 8, the source doping region 7 and the interval doping injection region 10 have a different doping type, and the body region 5, the hole doping region 6 and the interval doping injection region 10 have the same doping type.

[0074] Specifically, photoresist is spin-coated on the sample surface obtained in step S5, and a mask is used for exposure and development to obtain a source doping region pattern window located on each body region 5. Then, arsenic ions are injected into each source doping region pattern window to form a source doping region 7, such as Figure 5g As shown. For example, the implantation energy is 100-200 KeV and the implantation dose is 9×10 14 ~5×10 15 .

[0075] In addition, the preparation method of this embodiment also includes:

[0076] S7: depositing an interlayer dielectric on the upper surface of the sample obtained in S6, and etching the deposited interlayer dielectric to form contact holes to expose the hole doping region 6, the interval doping injection region 10 and part of the source doping region 7, so as to form an interlayer dielectric layer 11.

[0077] Specifically, a layer of silicon dioxide is deposited on the upper surface of the sample obtained in step S6, and the thickness can be 600-1000 nm, and then a photoresist is spin-coated on the obtained sample surface, and then a mask is used for exposure and development to obtain a contact hole pattern window, and etching is performed according to the contact hole pattern window to obtain a contact hole, and the hole doping region 6, the interval doping injection region 10 and part of the source doping region 7 are exposed. For example, the position and shape of the interlayer dielectric layer 11 are shown in FIG. Figure 1 and Figure 5h .

[0078] S8: A source metal layer 12 is formed on the upper surface of the sample obtained in step S7, and the lower surface of the source metal layer 12 is in contact with the hole doping region 6, the interval doping injection region 10 and a part of the source doping region 7 through contact holes.

[0079] Specifically, a source metal is deposited on the surface of the sample obtained in step S7. For example, the metal is Al with a thickness of 4 to 6 μm. After the source metal deposition is completed, a photoresist is spin-coated on the surface of the obtained sample, and then a mask is used for exposure and development to obtain a metal interconnection line pattern window. The source metal layer 12 and the gate electrode are separated according to the metal interconnection line pattern window, as shown in FIG. Figure 5i shown.

[0080] S9: forming a drain metal layer 13 on the lower surface of the substrate layer 1 .

[0081] Specifically, a drain metal is deposited on the lower surface of the substrate layer 1 to form a drain metal layer 13. Figure 5j As shown, illustratively, the deposited metals are Ti / Ni / Ag in sequence, with a thickness of 5-10 μm.

[0082] The performance of the radiation-resistant super junction power MOS device provided by the present invention is further described below.

[0083] See also Figure 6 and Figure 7 , Figure 6 It is a comparison diagram of the gate oxide electric field (lateral direction) of the radiation-resistant super junction power MOS device provided by an embodiment of the present invention and the conventional super junction power MOS device at the same time after incident at 1.5 μm under the same bias condition; Figure 7 : is a comparison diagram of the secondary breakdown voltage of the radiation-resistant super junction power MOS device provided by the embodiment of the present invention and the traditional super junction power MOS device, wherein the abscissa represents the drain-source breakdown voltage, and the ordinate represents the drain-source leakage current. The secondary breakdown voltage capability can characterize the device's SEB resistance capability. Figure 6 and Figure 7 As shown, compared with the super junction power MOS device, the radiation-resistant super junction power MOS device provided by the present invention can reduce the accumulation of carriers under the gate oxide layer 8 under the same bias conditions when the device encounters heavy ion radiation by designing the interval doping injection region 10, and reduce the electric field strength of the gate oxide layer 8 during the particle incidence process, thereby improving the device's resistance to SEGR; and, after breakdown under a strong electric field, a portion of the current can be extracted to reduce the current passing through the base region of the parasitic transistor, thereby reducing the probability of SEB occurrence, and the design of the bow-shaped source doping region reduces the parasitic transistor emitter injection efficiency, thereby reducing the probability of the parasitic transistor being turned on, further improving the device's resistance to SEB, and compared with traditional super junction power MOS devices, the radiation-resistant super junction power MOS device provided by the present invention has a secondary breakdown voltage capability (which can characterize the device's resistance to single particle burnout) that is increased by 146V.

[0084] In the several embodiments provided by the present invention, it should be understood that the apparatus and method disclosed by the present invention can be implemented in other ways. For example, the apparatus embodiments described above are only illustrative, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0085] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0086] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A radiation-resistant super-junction power MOS device, characterized in that: It comprises a substrate layer (1), a buffer layer (2) and an epitaxial layer (3) which are stacked in sequence from bottom to top, wherein: A plurality of super junction columns (4) arranged at intervals are provided in the epitaxial layer (3), and a body region (5) is provided above each super junction column (4); A hole doping region (6) and a source doping region (7) in contact with each other are arranged in the body region (5), and the upper surfaces of the body region (5), the hole doping region (6) and the source doping region (7) are all flush, and the depths of the hole doping region (6) and the source doping region (7) are less than the depth of the body region (5); A gate oxide layer (8) is also provided on the upper surface of the epitaxial layer (3), and the lower surface of the gate oxide layer (8) is in contact with the epitaxial layer (3), the body region (5) and a portion of the upper surface of the source doping region (7); the upper surface of the gate oxide layer (8) is covered with a polysilicon layer (9), and the gate oxide layer (8) and the polysilicon layer (9) form a gate electrode; An interval doping injection region (10) is also provided on the epitaxial layer (3) between adjacent body regions (5) and not covered by the gate oxide layer (8); the hole doping region (6) is located on a side of the source doping region (7) away from the interval doping injection region (10); the source doping region (7) and the interval doping injection region (10) have different doping types; and the super junction column (4), the body region (5), the hole doping region (6) and the interval doping injection region (10) have the same doping type; The hole doping region (6) and the source doping region (7) in the same body region (5) both extend from a first edge to a second edge of the upper surface of the epitaxial layer (3); the contact surfaces of the hole doping region (6) and the source doping region (7) are both in a bow shape, and respectively include protrusions and recesses arranged alternately, wherein the protrusions of the hole doping region (6) and the recesses of the source doping region (7) are mutually nested, and the recesses of the hole doping region (6) and the protrusions of the source doping region (7) are mutually nested; the depths of the hole doping region (6) and the source doping region (7) are both less than the depth of the body region (5), so that the hole doping region (6) and the source doping region (7) are not in contact with the super junction column (4) below; The gate oxide layer (8) comprises a first portion, a second portion and at least one connecting portion, wherein: The first part and the second part are parallel to each other and both extend from a first edge to a second edge of the upper surface of the epitaxial layer (3); the connecting part is connected between the first part and the second part; and the spacer doping implantation region (10) is arranged on the upper surface of the epitaxial layer (3) not covered by the connecting part between the first part and the second part; When the gate oxide layer (8) includes a plurality of connection parts, the plurality of connection parts are arranged at intervals between the first part and the second part, and each connection part connects the first part and the second part; when the gate oxide layer (8) includes a plurality of connection parts, the interval doping injection region (10) is also arranged between two adjacent connection parts, and does not contact the lower surface of each connection part.

2. The radiation-resistant super junction power MOS device according to claim 1, characterized in that: It also includes an interlayer dielectric layer (11) and a source metal layer (12), wherein: The interlayer dielectric layer (11) covers the upper surface of the polysilicon layer (9), the source metal layer (12) is arranged on the interlayer dielectric layer (11), and the interlayer dielectric layer (11) is used to isolate the polysilicon layer (9) and the source metal layer (12), and a plurality of contact holes are opened on the interlayer dielectric layer (11), so that the source metal layer (12) can contact the hole doping region (6), the source doping region (7) and the interval doping injection region (10).

3. The radiation-resistant super junction power MOS device according to claim 1, characterized in that: It also includes a drain metal layer (13) located on the lower surface of the substrate layer (1).

4. The radiation-resistant super junction power MOS device according to claim 1, characterized in that: The depth of the interval doping injection region (10) is less than the depth of the body region (5); and the lower surface of the super junction column (4) is not in contact with the buffer layer (2).

5. The radiation-resistant super junction power MOS device according to claim 1, characterized in that: The doping concentrations of the epitaxial layer (3) and the super junction column (4) are both lower than the doping concentration of the substrate layer (1).

6. The radiation-resistant super junction power MOS device according to claim 1, characterized in that: When the radiation-resistant super junction power MOS device is an N-channel device, the substrate layer (1) is an N-type substrate, the super junction column (4), the body region (5), the hole doping region (6) and the spacer doping injection region (10) are all P-type doped, and the source doping region (7) is N-type doped; When the radiation-resistant super junction power MOS device is a P-channel device, the super junction column (4), the body region (5), the hole doping region (6) and the interval doping injection region (10) are all N-type doped, and the source doping region (7) is P-type doped.

7. A method for preparing a radiation-resistant super-junction power MOS device, characterized in that: Used to prepare the radiation-resistant super junction power MOS device according to any one of claims 1 to 6, the preparation method comprising: S1: selecting a substrate layer (1) and growing a buffer layer (2) on the upper surface of the substrate layer (1); S2: forming an epitaxial layer (3) on the buffer layer (2), wherein the epitaxial layer (3) comprises a plurality of super junction pillars (4) arranged vertically at intervals; S3: preparing a body region (5) above each of the super junction pillars (4); S4: forming a hole doping region (6) in each body region (5), and forming an interval doping implantation region (10) in the epitaxial layer (3) between adjacent body regions (5); S5: growing a gate oxide layer (8) on the epitaxial layer (3), and depositing a polysilicon layer (9) on the gate oxide layer (8), wherein the lower surface of the gate oxide layer (8) is in contact with the body region (5) and a portion of the upper surface of the epitaxial layer (3), and the spaced doping implantation region (10) is distributed in a region of the epitaxial layer (3) that is not covered by the gate oxide layer (8); S6: forming a source doping region (7) in each body region (5), wherein the source doping region (7) is located on a side of the hole doping region (6) close to the gate oxide layer (8).

8. The method for preparing a radiation-resistant super junction power MOS device according to claim 7, characterized in that: The method further comprises: S7: depositing an interlayer dielectric on the upper surface of the sample obtained in S6, and etching the deposited interlayer dielectric to form a contact hole to expose the hole doping region (6), the interval doping injection region (10) and a portion of the source doping region (7), thereby forming an interlayer dielectric layer (11); S8: forming a source metal layer (12) on the upper surface of the sample obtained in S7, and the lower surface of the source metal layer (12) is in contact with the hole doping region (6), the interval doping injection region (10) and a portion of the source doping region (7); S9: forming a drain metal layer (13) on the lower surface of the substrate layer (1).

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