Failure analysis method for SiC MOS (Metal Oxide Semiconductor) device with gate-source short circuit and related equipment

Abstract

The invention provides a gate-source short-circuit SiC MOS device failure analysis method and related equipment, and the method comprises the steps: responding to the determination that the functional characteristics of a source and a drain have no abnormal conditions, carrying out the analysis of the cause of a short-circuit fault of a gate and the source based on the characteristics of a silicon carbide material and an MOS device failure mechanism, and carrying out the analysis of the short-circuit fault of the gate and the source. Comprising the following steps: judging whether gate source chemical lap joint caused by internal water vapor exists or not through a dry chip; unsealing the chip to expose the interior of the chip, testing the chip, and judging whether a metallization layer migration short circuit caused by high temperature occurs or not; analyzing whether breakdown caused by high electric field stress exists in the gate oxide layer; according to the failure analysis method provided by the invention, the reason of the failure of the SiC MOS device can be accurately analyzed, and the problem that the microdefect of the SiC MOS device cannot be positioned by a traditional means is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of device failure analysis methods, in particular to a SiC MOS device failure analysis method for gate-source short circuit and related equipment. BACKGROUND

[0002] Compared with traditional Si-based MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) devices, SiC MOS devices have many new and unique failure modes. For example, one unique failure mode in SiC MOS devices that does not exist in traditional Si MOS devices is the gate-source short circuit anomaly. There is no obvious anomaly in the drain-source. If the failure analysis method is improper, the gate-source short circuit anomaly phenomenon will disappear after the device is opened, and there is no obvious breakdown burn mark on the surface of the chip, which makes it impossible to accurately locate the failure cause. Therefore, it is difficult to accurately find the cause of the device short circuit anomaly for this unique failure mode of SiC MOS. SUMMARY

[0003] Therefore, the purpose of the present application is to provide a SiC MOS device failure analysis method for gate-source short circuit and related equipment to accurately find the cause of the device short circuit anomaly.

[0004] To achieve the above purpose, the present application provides a SiC MOS device failure analysis method for gate-source short circuit, which includes the following steps:

[0005] In response to determining that the appearance inspection and internal scanning inspection of the chip in the device have no abnormalities, I-V curve testing is performed on the functional pins of the gate, source, and drain to determine whether there is a short circuit fault between the gate and the source, and whether there is an abnormal situation between the source and the drain.

[0006] In response to determining that there is a short circuit fault between the gate and the source, and that there is no abnormal situation between the source and the drain, static parameter testing is performed on the source and the drain to check whether the functional characteristics of the source and the drain have abnormal situations.

[0007] In response to determining that the functional characteristics of the source and the drain have no abnormal situations, the causes of the short circuit fault between the gate and the source are analyzed based on the characteristics of silicon carbide material and the failure mechanism of MOS devices, including the following steps: determining whether there is a gate-source chemical bonding caused by internal water vapor by drying the chip; exposing the inside of the chip by opening the chip and testing the chip to determine whether there is a metallization layer migration short circuit caused by high temperature; and analyzing whether there is a breakdown caused by high electric field stress in the gate oxide layer.

[0008] Optionally, the determining whether the gate and the source are short-circuited due to the chemical bridging of the gate and the source caused by the internal moisture through the drying of the chip comprises:

[0009] The I-V curve test and the static parameter test are performed on the dried chip, and in response to determining that the test data show that the short-circuit fault of the chip disappears, it is determined that the short-circuit fault of the gate and the source is caused by the chemical bridging of the gate and the source caused by the internal moisture.

[0010] Optionally, the exposing the inside of the chip by unsealing the chip comprises:

[0011] The inside of the chip is exposed by using a laser to thin the plastic package material and then using a chemical method to remove the remaining plastic package material.

[0012] Optionally, the exposing the inside of the chip by unsealing the chip and testing the chip to determine whether the metallization layer migration short-circuit caused by high temperature occurs comprises:

[0013] The inside of the chip is observed to determine whether there is a molten metal Al bridging condition in the chip, and the inside of the chip is scanned for energy spectrum analysis to determine whether there is an Al element in the scanned energy spectrum analysis;

[0014] In response to determining that there is a metal Al bridging condition or that there is an Al element at the isolation ring of the gate and the source, it is determined that the short-circuit fault of the gate and the source is caused by the metallization layer migration short-circuit caused by high temperature.

[0015] Optionally, the analysis method further comprises:

[0016] In response to determining that there is a metal Al bridging condition in the chip, the chip is subjected to thermal infrared imaging detection, and a voltage is applied to the gate pin and the source pin to determine whether there is an abnormal hot spot near the isolation ring region of the gate and the source;

[0017] In response to determining that the abnormal hot spot position is the same as the metal Al bridging position, it is further determined that the short-circuit fault of the gate and the source is caused by the metallization layer migration short-circuit caused by high temperature.

[0018] Optionally, the analysis method further comprises:

[0019] In response to determining that there is no metal Al bridging in the chip and that there is no Al element at the isolation ring of the gate and the source, the chip is subjected to I-V curve test and static parameter test, and the test data are used to determine whether the short-circuit fault of the gate and the source disappears;

[0020] In response to determining that the short-circuit fault of the gate and the source disappears, it is determined that the short-circuit fault of the gate and the source is caused by the metallization layer migration short-circuit.

[0021] Optionally, in response to determining that the gate-source short circuit fault has not disappeared, the method further comprises: determining whether a breakdown caused by high electric field stress exists in the gate oxide layer,

[0022] Optionally, the method further comprises: performing thermal infrared imaging detection on the chip; applying voltage to the gate pin and the source pin; analyzing whether an abnormal hot spot exists; performing focused ion beam cutting on the failed cell according to the position of the abnormal hot spot; and determining whether the gate-source short circuit fault is caused by the breakdown caused by high electric field stress based on a cell section obtained by the cutting.

[0023] Optionally, the method further comprises: determining whether the gate-source chemical lap caused by internal water vapor exists in the dry device, including: baking the device at 125 DEG C for 48 hours.

[0024] Optionally, the method further comprises: determining whether the plastic package material is opened by fuming nitric acid, and determining whether the plastic package material is further opened by sulfuric acid reagent according to the opening condition.

[0025] Optionally, the static parameter test comprises: measuring the drain-source breakdown voltage, the drain-source leakage current, and the body diode voltage drop.

[0026] Optionally, the appearance inspection of the chip comprises: checking whether abnormality exists in the connection of each functional pin and whether solder lap exists between the functional pins.

[0027] The internal scanning inspection of the chip comprises: checking whether abnormality exists in the chip burning, bonding, and bonding wire and bonding point.

[0028] Based on the same inventive concept, a third aspect of the present disclosure provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the failure analysis method as described above when executing the computer program.

[0029] Based on the same inventive concept, a fourth aspect of the present disclosure provides a non-transitory computer readable storage medium, which stores computer instructions for causing a computer to execute the failure analysis method as described above.

[0030] It can be seen from the above that the SiC MOS device failure analysis method provided by the application is provided. For the short circuit fault of the SiC MOS device, the packaging defects and delamination are quickly checked out through the appearance inspection and internal scanning. If no abnormality is found, the I-V curve test is used to accurately locate the gate-source short circuit fault, and whether the source-drain circuit is normal is judged. The invalid detection is effectively avoided, the fault range is gradually reduced to the gate-source loop, and the analysis efficiency is greatly improved. The foundation is laid for subsequent in-depth exploration of the root cause of the fault. Then, based on the characteristics of silicon carbide material and the failure mechanism of MOS device, the analysis of the cause of the gate-source short circuit fault is analyzed: considering that the SiC MOS device is more susceptible to water vapor, the internal water vapor of the chip is detected by drying the chip; considering that the SiC MOS device has the characteristics of high working temperature and metal migration at high temperature, the metal layer migration phenomenon is observed by opening the chip; considering that the gate oxide layer of the SiC MOS device bears large electric field stress, the cause of the gate-source short circuit fault is analyzed as the breakdown of the gate oxide layer. The embodiment comprehensively covers the failure mode of the SiC MOS device through the multi-dimensional detection means, so as to accurately find the essential cause of the fault. In addition, the failure analysis method in the application avoids using the traditional analysis method for Si-based MOS failure, so as to avoid the situation that the failure mode fault disappears and cannot be reproduced again, thereby realizing accurate failure positioning of the SiC MOS device. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the application or related art, the following will briefly introduce the drawings needed to be used in the embodiments or related art description. Obviously, the drawings in the following description are only embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0032] Figure 1 The flowchart of the failure analysis method is shown in the embodiment of the application.

[0033] Figure 2 The appearance morphology of the chip is shown in the embodiment 1 of the application.

[0034] Figure 3 The X-ray inspection morphology of the chip is shown in the embodiment 1 of the application.

[0035] Figure 4 The delamination phenomenon of the chip is shown in the embodiment 1 of the application.

[0036] Figure 5 The overall morphology of the chip inside is shown in the embodiment 1 of the application.

[0037] Figure 6Figure 1 shows the partial topography of the inside of a chip according to an embodiment of the present application;

[0038] Figure 7 Figure 2 shows the topography of the passivation layer of a chip according to an embodiment of the present application;

[0039] Figure 8 Figure 3 shows the topography of a sampling position of a chip according to an embodiment of the present application;

[0040] Figure 9 Figure 4 shows an infrared thermal image of an abnormal bright spot of a chip according to an embodiment of the present application;

[0041] Figure 10 Figure 5 shows the overall topography of the inside of a chip according to an embodiment of the present application;

[0042] Figure 11 Figure 6 shows an infrared thermal image of an abnormal bright spot of a chip according to an embodiment of the present application;

[0043] Figure 12 Figure 7 shows a cross-sectional view of a cell of a chip according to an embodiment of the present application;

[0044] Figure 13 Figure 8 shows a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the embodiments and the accompanying drawings.

[0046] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as their common meanings to those of ordinary skill in the art to which the present application pertains. The terms "first", "second", and similar terms used in the embodiments of the present application do not denote any order, quantity, or importance, but are merely used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms "connect" or "connected" and similar terms do not mean only physical or mechanical connections, but can also include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are merely used to indicate relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships can also change accordingly.

[0047] Based on the background, in the field of power semiconductor devices, traditional Si-based MOS devices have long dominated due to mature processes and stable performance. However, with the increasing demand for power devices in new energy vehicles, photovoltaic power generation, rail transit and other fields towards high voltage, high frequency, high temperature environment applications, SiC materials stand out with their wide bandgap, high critical breakdown electric field, high electron saturation drift speed and other characteristics, and SiC MOS devices based on SiC materials have emerged. Compared with traditional Si-based MOS devices, SiC MOS devices can work stably at higher voltage, frequency and temperature, significantly improving system efficiency and reducing device size, but at the same time, their unique material properties and working environment have given rise to many new and unique failure modes.

[0048] Among them, the gate-source short circuit anomaly is a unique failure mode of SiC MOS devices. In traditional Si-based MOS devices, this failure phenomenon is extremely rare or even non-existent, while SiC MOS devices are prone to gate-source short circuit anomalies, while the drain-source has no obvious anomalies. The particularity of this failure mode not only lies in the uniqueness of the failure phenomenon, but also in the great challenge faced by failure analysis. The packaging structure and material properties of SiC MOS devices make it difficult to observe obvious breakdown burn marks on the chip surface during failure analysis if the traditional failure analysis method is used and the device is blindly opened. This is because the physical stress, environmental changes and interaction between materials during the opening process can damage the microstructure of the failure point, making the original short circuit anomaly unable to reproduce. In addition, SiC material and Si material have significant differences in atomic structure and chemical bond energy, making the growth mechanism of SiC MOS device gate oxide layer and the defect formation mechanism completely different from Si-based MOS devices, further increasing the difficulty of failure cause positioning. In practical applications, due to the difficulty in accurately finding the cause of the device short circuit anomaly, engineers cannot improve the device design and manufacturing process, which makes it difficult to improve product reliability and restricts the application and promotion of SiC MOS devices in a wider field.

[0049] The following will be described in conjunction with the accompanying drawings Figures 1-13 Detailed description of the embodiments of the present application.

[0050] In some embodiments, as shown in Figure 1 A SiC MOS device failure analysis method for gate-source short circuit, comprising the following steps:

[0051] S100: In response to determining that the appearance inspection and internal scanning inspection of the chip in the device are normal, performing I-V curve test on the function pins of the gate, source and drain to determine whether there is a short circuit fault between the gate and the source, and whether there is an abnormal situation between the source and the drain.

[0052] In this step, the appearance inspection of the device also includes delamination at the interface between the chip, the functional pins and the surrounding packaging material (such as epoxy resin plastic packaging material), which may cause damage to the structural integrity of the device and thus can be used as a reference index for subsequent analysis.

[0053] In addition, the I-V curve test is a current-voltage characteristic curve test, which can qualitatively determine whether the electrical connection between the gate and the source or the source and the drain conforms to the normal working mechanism of the MOS device, so as to lock the gate-source (gate and source) short circuit fault and check the source-drain (source and drain) anomaly. If the I-V curve between the gate and the source is normal, but the source and the drain are abnormal, it is determined that the fault is concentrated in the chip body (such as the drift region, the body diode, etc.); if there is a short circuit between the gate and the source, the overall chip failure (such as damage to the multi-layer structure due to overheating) needs to be checked.

[0054] In the embodiment, the test instrument (such as a semiconductor parameter analyzer) is connected to the functional pins of the chip, and the current or voltage is applied to each electrode of the chip, and the corresponding current-voltage characteristic curve is measured, so as to lock the gate-source short circuit fault and check the source-drain anomaly according to the current-voltage characteristic curve test.

[0055] S200: In response to determining that there is a short circuit fault between the gate and the source, and that there is no abnormality in the circuit between the source and the drain, performing a static parameter test on the source and the drain to check whether the functional characteristics of the source and the drain are abnormal;

[0056] In this step, on the premise of confirming the gate-source short circuit, it is verified whether the core functions (such as voltage resistance and on-resistance) of the source and the drain are affected, and the possibility of multiple failure modes coexisting is excluded, so as to narrow the range for subsequent fault positioning. If the source and the drain parameters are normal, it indicates that the fault is concentrated in the gate region; if the source and the drain parameters are abnormal, the overall damage of the chip needs to be checked synchronously.

[0057] In the embodiment, since the failure mode targeted by the embodiment is the short circuit between the gate and the source, when performing the static test, parameters related to the gate should be avoided, such as threshold voltage, gate-source-drain current and on-resistance, and parameters related to the drain and the source can be measured, such as drain-source breakdown voltage, drain-source current and body diode voltage drop; at the same time, attention should be paid to reducing the stress condition parameters set during the test to prevent secondary damage to the device due to improper test condition setting. It is recommended to start testing according to 20% of the recommended test conditions in the device manual, and to increase the test conditions by 10% recommended value step by step until the parameter out-of-tolerance phenomenon can be observed, and 80% recommended value is used as the upper limit of the test.

[0058] S300: In response to determining that the functional characteristics of the source and the drain are normal, based on the silicon carbide material characteristics and the MOS device failure mechanism, the causes of the short circuit fault between the gate and the source are analyzed, including the following steps: judging whether there is internal water vapor leading to chemical bonding between the gate and the source through dry chips; exposing the inside of the chip by unsealing the chip and testing the chip to determine whether there is metal migration short circuit caused by high temperature; analyzing whether the gate oxide layer is broken due to high electric field stress.

[0059] In this step, it is determined that the functional characteristics of the source and the drain are normal, and the fault is determined as a short circuit fault between the gate and the source. Compared with conventional Si MOS devices, SiC MOS devices are more likely to be invaded by water vapor due to packaging process defects, and the water vapor adsorption capacity of SiC is stronger, which makes SiC MOS devices more likely to be affected by water vapor to affect normal operation. Therefore, when SiC MOS devices appear gate-source short circuit fault, it is necessary to determine whether they are affected by water vapor; SiC MOS devices can withstand higher temperatures (usually higher than 600°C), so when the temperature of the chip is significantly increased, the metallization layer on the surface of the chip is more likely to migrate and short circuit, causing abnormal bonding between the gate and the source. High temperature may also cause significant cracks in the passivation layer on the surface of the active area of the chip. The thickness of the gate oxide layer of the SiC MOS device is usually 100-200 nm (thinner than the Si-based device) to reduce the gate capacitance, and the potential barrier height between the SiC material and the gate oxide layer formed by the growth is clear and there are more defects inside the gate oxide layer. Therefore, it is more likely to appear a breakdown phenomenon caused by high electric field stress. Therefore, based on the characteristics of the silicon carbide material and the failure mechanism of the MOS device, the above three fault causes can be selected for investigation.

[0060] In specific implementation, first, it is judged whether there is internal water vapor leading to chemical bonding between the gate and the source through dry chips. This step belongs to non-destructive testing of the chip, and avoids destroying the water vapor related evidence chain in subsequent destructive operations (such as unsealing), so this step is selected first. After confirming that it is not caused by water vapor, the inside of the chip is exposed by unsealing to investigate the physical short circuit source (such as metal melting and migration). When no abnormalities are found in the above two steps, the microcosmic electric stress damage of the gate oxide layer is focused. Such defects cannot be observed by the naked eye or conventional SEM, and high-precision testing and micro-area characterization are needed, so as to ensure the comprehensiveness of the failure mechanism analysis.

[0061] In the embodiment, for the short circuit fault of the SiC MOS device, the embodiment first checks the packaging defects and delamination through appearance inspection and internal scanning, and if no abnormality is found, the I-V curve test is used to accurately locate the gate-source short circuit fault and determine whether the source-drain circuit is normal, effectively avoiding invalid detection and gradually narrowing down the fault range to the gate-source circuit, greatly improving the analysis efficiency and laying a foundation for further exploring the root cause of the fault. Then, based on the characteristics of silicon carbide material and the failure mechanism of MOS device, the embodiment analyzes the cause of the gate-source short circuit fault: considering that SiC MOS devices are more susceptible to water vapor, the chip is dried to detect whether there is water vapor inside the chip; considering the characteristics of high working temperature of SiC MOS devices and easy migration of metal at high temperature, the chip is opened to observe whether there is metal layer migration; considering that the gate oxide layer of SiC MOS device bears large electric field stress, the cause of the gate-source short circuit fault is analyzed as gate oxide layer breakdown. The embodiment uses multi-dimensional detection means to cover the failure modes of SiC MOS devices, so as to accurately find the essential cause of the fault.

[0062] In addition, the failure analysis method in the embodiment avoids using the traditional analysis method for Si-based MOS failure, so as to avoid the situation that the failure mode fault disappears and cannot be reproduced again, thereby realizing accurate failure positioning of the SiC MOS device.

[0063] In some embodiments, in the S100 step, the appearance inspection of the chip includes: checking whether there is any abnormality in the connection of each functional pin and whether there is any solder bridging between the functional pins.

[0064] The internal scanning inspection of the chip includes: checking whether there is any abnormality in the chip burning, bonding and bonding wire and bonding point.

[0065] In a specific implementation, the appearance inspection can be performed by using a body microscope, focusing on checking whether there is any abnormality in the connection of the functional pins of the device and whether there is any abnormality such as solder bridging between the pins. For the solder bridging inspection between the functional pins, it is necessary to not only observe whether there is any obvious solder bridging between the functional pins, but also pay attention to whether there is any virtual soldering at the root of the functional pins. The internal scanning inspection department performs the inspection by using an X-ray detector, focusing on checking whether there is any abnormality such as burnout, chip adhesion, bonding wire, and bonding point in the chip. For the burnout inspection of the chip, it is determined whether the chip is burned out by observing whether there is any abnormal black or dark area in the image. For the chip adhesion, it is checked whether the adhesion interface between the chip and the packaging substrate is uniform, complete, and whether there is any gap or bubble. For the inspection of the bonding wire and the bonding point, it is observed whether there is any breakage, deformation, virtual soldering, and the like of the bonding wire, and whether the bonding point is firm and whether there is any falling phenomenon. For the abnormal area found in the detection process, multi-angle scanning and magnification observation are performed to obtain more detailed information.

[0066] In the embodiment, through the appearance inspection and the internal scanning, various conventional obvious defects of the chip can be quickly checked first, the overall efficiency of the gate-source short circuit fault analysis is improved, and a basis is provided for subsequent analysis.

[0067] In some embodiments, the static parameter test of the source and the drain in the step S200 includes a drain-source breakdown voltage test, a drain-source leakage current test, and a body diode voltage drop test.

[0068] In a specific implementation, a high-precision semiconductor parameter analyzer can be used as a test device. During the test, the chip is placed in a constant temperature and humidity environment box. For example, the environmental temperature is set to 25°C, and the relative humidity is set to 45%-55% to eliminate the interference of environmental factors on the test results.

[0069] In the embodiment, through the comprehensive and accurate test of the drain-source breakdown voltage, the drain-source leakage current, and the body diode voltage drop on the source and the drain of the chip, it can be found whether there is any problem in the static parameters of the chip, thereby providing accurate data basis for the chip fault.

[0070] In some embodiments, the determination of whether there is any internal water vapor caused gate-source chemical bridging in the step S300 includes:

[0071] The I-V curve test and the static parameter test are performed on the dried chip. In response to determining that the test data shows that the chip short circuit fault disappears, it is determined that the reason for the short circuit fault between the gate and the source is the internal water vapor caused gate-source chemical bridging.

[0072] In addition, the determination of whether the gate-source chemical short caused by internal moisture exists by the drying device includes: baking the device at 125°C for 48h.

[0073] In specific implementation, a high-precision vacuum drying box can be used for drying the chip, the air pressure in the drying box is reduced by vacuum pumping to accelerate the evaporation of moisture. The drying box needs to have a precise temperature control function, the temperature is controlled at 125°C, and the fluctuation is controlled within ±1°C, so as to avoid damage to the chip due to too high temperature or residual moisture due to insufficient temperature, and also to shorten the drying time of the chip. Inert gases such as nitrogen can be filled in the drying box to further replace the humid air in the box, create a low-humidity environment, and improve the drying efficiency. After the I-V curve test is completed, the drain-source breakdown voltage test, the drain-source leakage current test, and the body diode voltage drop test are performed again, and the test procedures and standards remain consistent with the S200 step. The changes of the static parameters of the chip before and after drying are compared, if the abnormal parameters related to the gate-source short circuit before drying (such as excessive drain-source leakage current and abnormal body diode voltage drop) return to the normal range after drying, it further supports the conclusion that the gate-source short circuit fault is caused by internal moisture. If the test data shows that the chip short circuit fault has not disappeared, the next step of analysis is performed.

[0074] In the embodiment, by drying the chip and combining the I-V curve test and the static parameter test, it can be quickly and accurately determined whether the gate-source short circuit fault is caused by the gate-source chemical short caused by internal moisture, without complex disassembly of the chip or long-time repeated test, which greatly improves the fault diagnosis efficiency.

[0075] In some embodiments, in the step S300, the internal part of the chip is exposed by unsealing the chip, including:

[0076] The remaining plastic sealing material is removed by chemical method after the plastic sealing material is thinned by laser to expose the internal part of the chip.

[0077] In specific implementation, for non-plastic-sealed devices, only laser unsealing is needed, and for plastic-sealed devices, laser unsealing is performed first and then chemical unsealing is performed. The laser unsealing thins the thick plastic sealing material, avoids the removal of the plastic sealing material by chemical method, and removes the factors that may cause gate-source short circuit on the surface of the chip at the same time, so that the failure phenomenon disappears and the failure position cannot be effectively located. The device is unsealed by chemical method, and the type of chemical reagent used in this step needs to be controlled. After the plastic sealing material is removed by fuming nitric acid, it is recommended not to use sulfuric acid to further remove the plastic sealing material. After the plastic sealing material is removed by fuming nitric acid, observation is performed first, and if the unsealing effect is not ideal, a small amount of sulfuric acid reagent is used for further unsealing.

[0078] In the embodiment, the plastic encapsulated device is first laser opened and thinned plastic encapsulation, and then chemically opened, avoiding the cumbersome process of directly using a large amount of chemical reagent to remove thick plastic encapsulation, and shortening the opening time. Avoiding the use of a large amount of chemical reagent in the chemical method to remove the plastic encapsulation, the key factor of accidentally removing the chip surface may cause the gate-source short circuit, preventing the failure phenomenon from disappearing due to improper handling, so that the detection personnel can analyze based on the true failure state, accurately find the position causing the gate-source short circuit fault, avoid false judgment of the fault root cause, provide a reliable basis for subsequent fault repair and process improvement, and significantly improve the accuracy and effectiveness of fault positioning.

[0079] In some embodiments, in step S300, the chip inside is exposed by opening the chip, and the chip is tested to determine whether the metallization layer migration short circuit caused by high temperature occurs, comprising:

[0080] S301: observing the inside of the chip to determine whether there is a molten metal Al lap joint in the chip, and performing scanning energy spectrum analysis on the inside of the chip to determine whether there is an Al element in the scanning energy spectrum analysis;

[0081] In this step, the inside of the chip is first visually observed or observed under a microscope. The inside structure of the chip should have been exposed through the foregoing opening method. The focus is on observing whether there is a molten metal lap joint on the chip surface as a whole or locally (at the gate and source isolation ring position). After determining that there is no metal lap joint on the chip surface, scanning energy spectrum analysis is performed on the chip to analyze whether there is an Al element on the chip surface.

[0082] S302: in response to determining that there is a metal Al lap joint or that there is an Al element at the isolation ring of the gate and source, it is determined that the cause of the short circuit fault between the gate and the source of the device is the metallization layer migration short circuit caused by high temperature.

[0083] In this step, if there is a metal Al lap joint on the chip surface or there is an Al element at the isolation ring of the gate and source, it is preliminarily judged that the cause of the short circuit fault between the chip gate and the source is the metallization layer migration short circuit caused by high temperature. Specifically, under high temperature environment, the metal Al layer inside the chip will change physically and chemically, and migration phenomenon will occur. After the metal Al migrates, it will form a lap joint between the gate and the source that should not be connected originally, or will be enriched at the isolation ring of the gate and the source, thereby destroying the normal electrical structure of the chip, and further causing a short circuit fault between the gate and the source.

[0084] S303: in response to determining that there is a metal Al lap joint inside the chip, performing thermal infrared imaging detection on the chip, and applying voltage to the gate pin and the source pin to determine whether there is an abnormal hot spot locally near the gate and source isolation ring region;

[0085] S304: In response to determining that the abnormal hot spot position is the same as the metal Al lap position, further determining that the cause of the short circuit failure between the gate and the source is the migration short circuit of the metallization layer caused by high temperature.

[0086] In steps S303 and S304, the chip is subjected to thermal infrared imaging detection, and a voltage of about 2V is applied to the gate pin and the source pin of the chip. Then, an abnormal hot spot appears near the isolation ring area of the gate and the source. If the abnormal hot spot position is the same as the metal Al lap position, it is verified from the perspective of thermal infrared imaging that the metal Al indeed forms a circuit between the gate and the source, thereby determining that the cause of the short circuit failure between the gate and the source is the migration short circuit of the metallization layer caused by high temperature.

[0087] S305: In response to determining that there is no metal Al lap inside the chip and no Al element at the isolation ring of the gate and the source, the chip is subjected to I-V curve testing and static parameter testing, and whether the short circuit failure between the gate and the source disappears is determined according to the test data.

[0088] S306: In response to determining that the short circuit failure between the gate and the source disappears, it is determined that the cause of the short circuit failure between the gate and the source is the migration short circuit of the metallization layer.

[0089] In steps S305 and S306, if it is determined that the short circuit failure between the gate and the source disappears, it means that the chemical reagent in the opening process dissolves and destroys the part of the original molten metal lap. At this time, the failure part (the chip with short circuit failure) and the qualified part (the normal chip sample of the same type) need to be polished and polished until the metallization layer morphology (such as metal wiring and isolation ring structure) can be clearly observed. At this time, by comparing the metallization layer morphology of the failure part and the qualified part and performing energy spectrum detection on the failure part, if the morphology difference between the failure part and the qualified part can be observed or Al element is detected in the gate isolation ring area, it means that the cause of the chip gate-source short circuit failure is the migration short circuit of the metallization layer. Specifically, in the chemical opening process, the chip surface or the loose molten metal is corroded, and the metal remaining in the gap of the metallization layer and the chip substrate area can be detected by the above method, thereby determining that the cause of the chip gate-source short circuit failure is the migration short circuit of the metallization layer.

[0090] In the embodiment, by using multi-dimensional detection means and constructing a complete chip fault diagnosis system, whether the metallization layer migration causes the chip failure can be comprehensively analyzed from the aspects of microstructure, element distribution and thermal characteristics, thereby providing a reliable basis for chip failure analysis and avoiding ineffective repair and resource waste caused by misjudgment.

[0091] In some embodiments, in step S300, in response to determining that the short circuit failure between the gate and the source does not disappear, whether the gate oxide layer has a high electric field stress caused breakdown is analyzed.

[0092] comprises: performing thermal infrared imaging detection on the chip, applying voltage to the gate pin and the source pin, analyzing whether there is an abnormal hot spot, focusing ion beam cutting on the failed cell according to the position of the abnormal hot spot, and judging whether the cause of the gate and source short circuit failure is breakdown caused by high electric field stress based on the cell section obtained by cutting.

[0093] In specific implementation, the chip marked with an abnormal hot spot is fixed on a special sample stage, a scanning electron microscope (SEM) is used to observe the target area at high magnification, and a cutting path is determined. During cutting, a gallium ion source FIB (focused ion beam) device can be used. For example, in the initial stage, most of the material is quickly removed to form a rough cutting groove with a higher beam current (5 nA); when the target section is approached, the beam current is reduced to 0.1 nA for fine finishing, so that the flatness error of the section is less than 5 nm. The cutting direction is perpendicular to the gate oxide layer, and the section size is controlled to be 5 μm x 5 μm, so that the structural relationship of the gate, the oxide layer and the source can be observed completely. After cutting, a transmission electron microscope (TEM) or a scanning transmission electron microscope (STEM) is used to observe the cell section at high resolution. The thickness uniformity of the gate oxide layer, whether there is a pinhole or a crack, the interface state of the oxide layer and the silicon substrate, etc. are analyzed. Energy dispersive spectroscopy (EDS) is used to detect whether there is metal impurity diffusion in the oxide layer to judge the possibility of breakdown caused by high electric field stress.

[0094] In the present embodiment, the abnormal heating area is locked by thermal infrared imaging, and the gate oxide layer is analyzed at high precision, thereby improving the positioning accuracy of the high electric field stress breakdown failure.

[0095] The above embodiments will be described in detail below in combination with specific embodiments and examples.

[0096] Embodiment 1

[0097] The sample used in the present embodiment is a domestic SiC MOS device, the number of failed samples is 1 (numbered F), and the number of qualified samples of the same type is 1 (numbered C). The failed sample shows abnormal short circuit of the gate and the source.

[0098] Through appearance inspection, X-ray inspection, I-V curve test, electrical performance test, acoustic scanning inspection (SAM), internal visual inspection, energy spectrum analysis, infrared thermal imaging detection on the chips of the failed sample (F) and the qualified sample (C), the following results are obtained:

[0099] (1) Appearance inspection

[0100] For example, Figure 2As shown, the surfaces of the chips of the failed parts and qualified parts are coated with three-proof coatings (moisture-proof, salt spray-proof, and mildew-proof). There is solder on the pins of the failed parts, and the back is coated with heat-dissipating silicone grease. There are no obvious abnormalities such as cracking and burning. Therefore, the appearance of the failed parts does not show any defects that directly lead to short circuits; the qualified parts have no obvious abnormalities.

[0101] (2) Internal inspection

[0102] The chip is inspected by X-ray inspection, such as Figure 3 As shown, the X-ray morphology shows that the internal chips of the failed parts and the qualified parts are well bonded, and there is no sign of bond wire breakage or burning.

[0103] (3) IV curve test

[0104] Perform IV curve tests on the source, gate, and drain of the failed and qualified components to determine that the gate and source (GS) of the failed component are short-circuited, while the qualified component is in a normal open-circuit state.

[0105] (4) Scanning Acoustic Measurement (SAM)

[0106] like Figure 4 As shown in the figure, the SAM morphology of the failed parts shows chip delamination, while the qualified parts do not show delamination.

[0107] (5) Chip drying

[0108] The failed component was baked at 125℃ for 48h. After the test, the short circuit between the gate and source of the device still existed and had not been restored. It was determined that the gate-source failure was not caused by water vapor.

[0109] (6) Functional testing

[0110] Because the failed component exhibited an abnormal short circuit between the gate and source (GS), only three parameters were tested: drain-source breakdown voltage (VDS), drain-source leakage current (IDSS), and forward voltage drop (VSD) of the source-drain body diode. All parameters tested on the failed component were found to be qualified, while all electrical performance parameters of the qualified component were found to be qualified (tested twice).

[0111] (7) Internal visual inspection

[0112] The failed parts (F) and qualified parts (C) were opened by laser and chemical methods to expose their internal structures and observed under a microscope. Figures 5-7 As shown, there is no burn mark on the surface of the failed chip ( Figure 5 (a)), there are many cracks in the passivation layer on the surface of the chip functional area ( Figure 7 ), and suspected metal melting and gate-source overlap were observed on the isolation ring between the gate and source ( Figure 6 ), no abnormalities such as cracks were found on the surface of the qualified chip.

[0113] (8) Field emission scanning electron microscope (SEM) and energy spectrum analysis

[0114] To further confirm the composition of the molten material on the surface of the failed chip, a field emission scanning electron microscope (SEM) was used to observe the failed chip, and samples were taken at points 1 and 2 on the failed chip, and energy spectrum analysis was performed. The results are shown in Table 1, and the metal molten material on the gate isolation ring is aluminum. Figure 8

[0115] Table 1 Molten material composition table

[0116] Spectrum C N O Al Si Cu 1 13.02 4.62 10.66 50.41 20.46 0.83 2 12.44 / 2.96 80.74 3.86 /

[0117] (9) Infrared thermal imaging detection

[0118] The infrared thermal imaging equipment was used to detect the thermal distribution on the surface of the failed chip. The gate pin of the failed chip was applied with a voltage of 2V to the source pin. After detection, there was an abnormal hot spot near the gate-source isolation ring area of the failed chip. The position of the hot spot was the same as the observed molten aluminum lap joint position between the gate and the source (as shown in Figure 9

[0119] (10) Conclusion

[0120] According to the test results, the failed chip showed a gate-source short circuit anomaly before opening. The electrical performance tests of drain-source breakdown voltage VDS, drain-source leakage current IDSS, and source-drain body diode forward voltage drop VSD were all qualified. After opening, internal visual inspection, energy spectrum analysis, and infrared thermal imaging test showed that there was molten aluminum at the gate-source isolation ring position on the surface of the failed chip, and a gate-source lap joint short circuit anomaly was formed. At the same time, the high temperature caused multiple cracks in the passivation layer on the surface of the chip functional area. According to the test results and failure phenomenon analysis, it is believed that the device failure is due to the excessive temperature rise of the chip, which causes the molten aluminum on the surface of the chip, resulting in a gate-source lap joint short circuit anomaly.

[0121] Example 2

[0122] The sample used in this example is a domestic SiC MOS device. The number of failed samples is 1 (numbered F), and the number of qualified samples is 1 (numbered C). The failed sample shows a gate-source short circuit anomaly.

[0123] The chip of the failed sample (F) and the qualified sample (C) was subjected to appearance inspection, X-ray inspection, I-V curve test, electrical performance test, acoustic scanning inspection (SAM), internal visual inspection, energy spectrum analysis, and infrared thermal imaging detection. Steps (1)-(6) are consistent with Example 1 and are not repeated here

[0124] (7) Internal visual inspection and field emission scanning electron microscope (SEM) and energy spectrum analysis

[0125] ​​The failure part (F) and the qualified part (C) are opened by laser method and chemical method to expose the internal structure, and are placed under microscope observation. No burn marks are observed on the surface of the chip of the failure part, and no suspected metal melting is observed on the isolation ring between the gate and the source on the surface of the functional area of the chip, and no Al element is detected in the energy spectrum analysis. No abnormalities are observed in the qualified part (such as Figure 10 as shown).

[0126] (8) Infrared thermal imaging detection and FIB cutting

[0127] The infrared thermal imaging equipment is used to detect the thermal distribution on the surface of the chip of the failure part. The gate pin of the failure part applies a voltage of 2V to the source pin. As shown in Figures 11-12 , an abnormal bright spot exists above the source area of the failure part. Subsequently, the FIB (focused ion beam) cutting is performed on the position of the bright spot. It can be observed that the gate dielectric layer between the polysilicon gate and the source aluminum metal of the rightmost cell corresponding to the abnormal bright spot has a significant crack. This phenomenon indicates that the gate dielectric layer is damaged due to internal stress.

[0128] (9) Conclusion

[0129] According to the test results, the gate-source short circuit abnormality occurs in the failure part before opening. The electrical performance test of the leakage source breakdown voltage VDS, the source-drain leakage current IDSS, and the source-drain body diode forward voltage drop VSD are qualified. After opening, the internal visual inspection, energy spectrum analysis, infrared thermal imaging and FIB test can be seen that the quality of the gate oxide layer of the failure part is degraded under the electrical-thermal coupling stress, the gate leakage current continuously increases, and finally causes the gate oxide layer to break down, thereby causing the gate-source short circuit failure.

[0130] Based on the same inventive concept, the disclosure also provides an electronic device corresponding to the method of any of the above embodiments, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to realize the life determination method of the radar assembly of any one of the above embodiments.

[0131] Figure 13 A more specific electronic device hardware structure schematic diagram is shown, which can include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 for communication within the device.

[0132] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits, etc., for executing relevant programs to implement the technical solutions provided by the embodiments of the present specification.

[0133] The memory 1020 can be implemented by a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, etc. The memory 1020 can store an operating system and other application programs, and when the technical solutions provided by the embodiments of the present specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and called and executed by the processor 1010.

[0134] The input / output interface 1030 is configured to connect input / output modules to implement information input and output. The input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. The input devices can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output devices can include a display, a speaker, a vibrator, an indicator light, etc.

[0135] The communication interface 1040 is configured to connect a communication module (not shown in the figure) to implement the communication interaction between the device and other devices. The communication module can realize communication through a wired manner (such as USB, network cable, etc.) or through a wireless manner (such as mobile network, WIFI, Bluetooth, etc.).

[0136] The bus 1050 includes a channel for transmitting information between various components (such as the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040) of the device.

[0137] It should be noted that although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040, and the bus 1050, in the specific implementation process, the device can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above device can also only include the components necessary to implement the solutions of the embodiments of the present specification, and does not have to include all the components shown in the figure.

[0138] The electronic device of the above embodiment is used to implement the life determination method of the corresponding radar assembly in any of the preceding embodiments, and has the beneficial effects of the corresponding method embodiments, which are not described here again.

[0139] Based on the same inventive concept, corresponding to the method of any of the above embodiments, the disclosure also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the life determination method of the radar assembly as described in any of the above embodiments.

[0140] The computer-readable medium of the present embodiment includes permanent and non-permanent, removable and non-removable media, which can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device.

[0141] The storage medium of the above embodiment stores computer instructions for causing the computer to perform the life determination method of the radar assembly as described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which are not described here again.

[0142] Those skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present application is limited to these examples; under the idea of the present application, the above embodiments or technical features in different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of the embodiments of the present application as described above. In order to be brief, they are not provided in details.

[0143] Additionally, to simplify the description and discussion, and so as not to obscure the embodiments of the application being presented, the well-known functions or constructions of integrated circuit (IC) chips and other components can or can not be shown in the figures and will not be discussed in detail. Also, devices can be shown in block diagram form in order to avoid obscuring the embodiments of the application, and this also acknowledges the fact that the details in regard to how the block diagram devices are implemented, e.g., in circuitry, are highly dependent on the platform within which the embodiments of the application are to be implemented (i.e., these details should be well within the purview of one of ordinary skill in the art). Where specific details are set forth in order to describe an illustrative embodiment of the application, it will be apparent to one of ordinary skill in the art that the embodiment of the application can be practiced without, or with variation of, these specific details. Thus, the description is to be considered as illustrative and not restrictive, and the scope of the application should be determined not with reference to the above description, but should be given to the appended claims.

[0144] While the application has been described in connection with specific embodiments thereof, many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) can use the embodiments discussed.

[0145] Embodiments of the application are intended to cover all such alternatives, modifications and variations as falling within the scope of the broadest possible interpretation of the appended claims. Accordingly, any and all such modifications, variations or equivalents that fall within the spirit and scope of the embodiments of the application should be intended to be embraced by the claims.

Claims

1. A method for analyzing failure of a SiC MOS device with a gate-source short circuit, characterized in that: The following steps are involved: In response to determining that the appearance inspection and internal scanning inspection of the chip in the device are normal, an IV curve test is performed on the functional pins of the gate, source, and drain to determine whether there is a short circuit fault between the gate and the source, and whether there is an abnormality in the circuit between the source and the drain; In response to determining that a short circuit fault exists between the gate and the source and that there is no abnormality in the circuit between the source and the drain, performing a static parameter test on the source and the drain to check whether functional characteristics of the source and the drain have any abnormality; In response to determining that there are no abnormalities in the functional characteristics of the source and drain, based on the characteristics of silicon carbide materials and the failure mechanism of MOS devices, the cause of the short circuit failure between the gate and the source is analyzed. The method comprises the following steps: determining whether there is gate-source chemical bonding caused by internal water vapor by drying the chip; Unpack the chip to reveal the inside of the chip and test the chip to determine if there is a short circuit caused by metallization migration due to high temperature; Analyze whether the gate oxide layer has breakdown caused by high electric field stress.

2. The method for analyzing failure of a gate-source shorted SiC MOS device according to claim 1, wherein: The method of determining whether there is gate-source chemical bonding caused by internal moisture by drying the chip includes: The dried chip is subjected to IV curve testing and static parameter testing. In response to determining that the test data shows that the chip short circuit fault has disappeared, it is determined that the cause of the gate-source short circuit fault is gate-source chemical bonding caused by internal water vapor.

3. The method for analyzing failure of a gate-source shorted SiC MOS device according to claim 1, wherein: The step of unsealing the chip to reveal the interior of the chip includes: The plastic encapsulation material is thinned using a laser and then chemically removed to reveal the inside of the chip.

4. The method for analyzing failure of a gate-source shorted SiC MOS device according to claim 3, wherein: The process of opening the chip to expose the inside of the chip and testing the chip to determine whether a metallization layer migration short circuit caused by high temperature occurs includes: Observe the inside of the chip to determine whether there is any molten metal Al overlap in the chip, and perform scanning energy spectrum analysis on the inside of the chip to determine whether there is Al element in the scanning energy spectrum analysis; In response to determining that there is metal Al overlap, or Al elements exist at the isolation rings of the gate and source, it is determined that the cause of the gate-source short circuit failure of the device is the metallization layer migration short circuit caused by high temperature.

5. The method for analyzing failure of a gate-source shorted SiC MOS device according to claim 4, wherein: Also includes: In response to determining that there is a metal Al overlap inside the chip, the chip is subjected to thermal infrared imaging detection, and voltage is applied to the gate pin and the source pin to determine whether there are abnormal hot spots near the gate and source isolation ring areas; In response to determining that the abnormal hot spot position is the same as the metal Al overlap position, it is further determined that the cause of the short circuit failure between the gate and the source is the metallization layer migration short circuit caused by high temperature.

6. The method for analyzing failure of a gate-source shorted SiC MOS device according to claim 4, wherein: Also includes: In response to determining that there is no metal Al overlap inside the chip and no Al element is present at the isolation rings of the gate and source, an IV curve test and a static parameter test are performed on the chip to determine whether the short circuit fault between the gate and source has disappeared based on the test data; In response to determining that the gate-source short circuit fault disappears, it is determined that a cause of the gate-source short circuit fault is a metallization layer migration short circuit.

7. The method for analyzing failure of a gate-source shorted SiC MOS device according to claim 6, wherein: In response to determining that the gate and source short circuit fault has not disappeared, the gate oxide layer is analyzed to see whether there is breakdown caused by high electric field stress, It includes: performing thermal infrared imaging on the chip, applying voltage to the gate pin and source pin, analyzing whether there are abnormal hot spots, performing focused ion beam cutting on the failed cells according to the location of the abnormal hot spots, and judging whether the cause of the gate and source short circuit failure is breakdown caused by high electric field stress based on the cell cross-section obtained by cutting.

8. The method for analyzing failure of a gate-source shorted SiC MOS device according to claim 2, wherein: The method of determining whether there is gate-source chemical bonding caused by internal water vapor by drying the device includes: baking the device at 125° C. for 48 hours.

9. The method for analyzing failure of a gate-source shorted SiC MOS device according to claim 3, wherein: The chemical method of opening the chip uses fuming nitric acid to open the plastic packaging material, and determines whether to use sulfuric acid reagent for further opening according to the opening situation.

10. The method for analyzing failure of a SiC MOS device with a gate-source short circuit according to claim 1, wherein: The static parameter test includes measuring the drain-source breakdown voltage test, the drain-source leakage current test, and the body diode voltage drop test.

11. The method for analyzing failure of a SiC MOS device with a gate-source short according to claim 7, wherein the appearance inspection of the chip comprises: Check whether there is any abnormality in the connection of each functional pin and whether there is any solder overlap between the functional pins; The chip internal scanning inspection includes: checking whether the chip is burned, bonded, and whether there are abnormalities in the bonding wires and bonding points.

12. An electronic device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method according to any one of claims 1 to 11 is implemented.

13. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to cause a computer to execute the method according to any one of claims 1 to 11.

Images