Semiconductor device with improved termination region using multiple laterally spaced first regions, and corresponding

Abstract

A semiconductor device includes a semiconductor body including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, the epitaxial layer having a first conductivity type, and wherein an active region and a termination region adjacent to the active region are arranged in the epitaxial layer, a plurality of first regions having a second conductivity type opposite to the first conductivity type, each of the plurality of first regions surrounding the active region as viewed from a top view of the semiconductor device; and one or more second regions, where the second regions are respectively included between the plurality of spaced apart first regions, where the one or more second regions extend deeper into the epitaxial layer than the plurality of spaced apart first regions, and wherein the one or more second regions comprise an insulating material for insulating the plurality of spaced apart first regions from each other.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor devices, and more particularly to edge termination of active areas of semiconductor devices. Background Art

[0002] Edge termination is an important part of power devices. Most planar and trench power devices are based on one or several PN type junctions. When the active part of the junction terminates at the side of the device, very high electric fields may occur under reverse voltage bias due to the junction bend or trench corner.

[0003] Peripheral protection known as edge termination may be required. Reliable and robust high voltage devices may require effective edge termination structures to protect the device periphery so that blocking values ​​close to the ideal 1D avalanche voltage value can be achieved.

[0004] Several physical limitations make the design of SiC edge terminations quite complex. The main limitation is the low diffusion coefficient of dopant atoms inside the semiconductor. Deep junctions, for example >1μm, may be difficult to achieve and lateral dopant diffusion may be very limited. In addition, the higher interface trap levels observed in the SiC / passivation interface compared to silicon may also affect the efficiency of standard Si termination architectures in SiC power devices.

[0005] Charge can accumulate at the interface, producing breakdown voltage instabilities and early failures, especially with temperature. Finally, termination design may also be concerned with achieving high avalanche robustness to meet applications prone to unclamped inductive switching UIS.

[0006] Among all the possible termination structures integrated on SiC power devices, P+ floating guard rings (Kao rings) implemented in n-doped substrates have been proposed in the past. The width and distance of the P rings increase as the distance to the active area (i.e., towards the end of the diode or saw lane) increases.

[0007] In standard implementations, a P+ floating ring is integrated by implanting P-type impurities (e.g., Al) onto an N-doped epitaxial layer. However, the limited junction depth achievable on SiC and the high crystal damage caused by the use of high-dose implants (necessary for poor activation of the P dopants) motivate the search for suitable alternatives to the floating ring design that are compatible with the definition of the P-doped regions by epitaxy rather than just by implantation.

[0008] In fact, on one hand, the above-mentioned process limitations impose some restrictions on the appropriate terminal design, and on the other hand, when the device is operated under high stress conditions (e.g., high humidity, high temperature or high voltage), the high surface damage caused by the implantation process combined with the passivation charge may produce breakdown voltage instability and early failures.

[0009] Additionally, a highly doped channel stop region around the saw street area can be used to avoid depletion and / or inversion of the semiconductor due to passivation charges. If not designed properly, some leakage paths may appear at the interface between the passivation layer and the termination, ultimately resulting in reduced blocking voltage and sometimes early failure. The termination design will undoubtedly benefit from the integration of additional features to prevent inversion of the middle layers in the termination area. Summary of the invention

[0010] An object of the present disclosure is to provide a semiconductor device with an improved termination area.

[0011] It would further be advantageous to realize corresponding methods and power devices.

[0012] In a first aspect of the present disclosure, there is provided a semiconductor device, comprising:

[0013] a semiconductor body comprising a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, the epitaxial layer having a first conductivity type, and wherein an active region and a termination region adjacent to the active region are arranged in the epitaxial layer;

[0014] The terminal area includes:

[0015] a plurality of laterally spaced first regions, the first regions having a second conductivity type opposite to the first conductivity type, each of the plurality of first regions surrounding the active area when viewed from a top view of the semiconductor device;

[0016] One or more second regions, wherein the second regions are respectively included between the plurality of spaced-apart first regions, wherein the one or more second regions extend deeper into the epitaxial layer than the plurality of spaced-apart first regions, and wherein the one or more second regions include insulating material for insulating the plurality of spaced-apart first regions from each other.

[0017] In other words, the present disclosure relates to a termination concept that integrates a P-type floating ring defined by, for example, a SiC etching process, thereby being compatible with the definition of a P-doped region by epitaxy or implantation. The examples discussed below include a recessed N+ implanted region at the bottom of the trench between adjacent P-type floating rings. In some other examples, additional P+ doped regions are defined on top of the P-type floating ring between N-doped implanted regions.

[0018] The first region surrounds the active area when viewed from above the semiconductor device. This may mean that the first region may surround the active area, for example in a rounded rectangle, an ellipse or any similar shape.

[0019] The active area of ​​a semiconductor device includes functional components such as transistors, diodes or other functional elements, in which the desired electrical or electronic functions are realized. On the other hand, the termination area is the part of the device that is located outside the active area and is used for specific purposes related to device performance and protection.

[0020] The main function of the termination region is to provide a controlled transition from the active region to the surrounding environment. It helps manage the electric field distribution and prevents undesirable effects (such as electrical breakdown or leakage) that may occur at the edge or periphery of the active region.

[0021] The termination region is particularly important in high-voltage semiconductor devices such as SiC-based power devices. It is designed to distribute the electric field more evenly and reduce the concentration of electric field lines at the edges. This helps prevent voltage crowding or field-induced breakdown, improving breakdown voltage and overall device performance.

[0022] The present disclosure defines a plurality of laterally spaced first regions, for example three, four or five different laterally spaced regions. These regions can be obtained by etching a uniformly P-doped terminal region. This will be explained in more detail with reference to the accompanying drawings.

[0023] The second region is arranged between the first regions. The second region extends deeper in the semiconductor body than the first region. The second region comprises an insulating material for insulating different first regions from each other.

[0024] The second region may extend deeper into the epitaxial layer than the plurality of spaced-apart first regions, for example by at least 150%.

[0025] In one advantageous example, there are at least three laterally spaced first regions.

[0026] The doping concentration of the first region may be between 1E17 cm-3 and 5E17 cm-3. The doping concentration may be 10 to 50 times higher than the doping concentration of the epitaxial layer. The thickness of the first region may be between 0.2 μm and 0.5 μm.

[0027] In one example, the plurality of laterally spaced apart first regions are floating.

[0028] Floating means that the first region is not connected to any particular potential or reference point. In other words, it is not electrically connected to any voltage source or ground.

[0029] For example, a P-type floating ring can act as a voltage isolation structure. By making it float, it can help electrically isolate or separate different regions or components within a semiconductor device, preventing undesired electrical coupling or interference. This isolation can be very important to ensure proper device function and avoid unwanted electrical interactions.

[0030] The floating ring can be designed to shape or control the electric field distribution within the terminal area. Its floating nature allows it to modify the electric field gradient or pattern, thereby affecting the electrical behavior of the device. This can help optimize performance, increase breakdown voltage, reduce electric field crowding, or mitigate other electric field related effects.

[0031] In further examples, each first region of the plurality of spaced-apart first regions is uniformly doped.

[0032] In another example, the semiconductor device further comprises:

[0033] At least one inversion protection layer is disposed on the bottom side of the one or more second regions, wherein the inversion protection layer has the first conductivity type, wherein the doping concentration of the inversion protection layer is higher than the doping concentration of the epitaxial layer.

[0034] The inventors have found that it may be beneficial to provide an inversion protection layer on the bottom side of one or more second regions. Such an inversion protection layer may prevent inversion of the epitaxial layer. The doping concentration of the inversion protection layer is then also higher than the doping concentration of the epitaxial layer.

[0035] In another example, the semiconductor device includes at least two inversion protection layers, and wherein the doping concentrations of the at least two inversion protection layers increase as they are away from the active region.

[0036] In another example, the doping of the at least two inversion protection layers is between 1E17 cm-3 and 5E17 cm-3.

[0037] It is further noted that it may be advantageous if the doping concentration of the at least two inversion protection layers is increased by increasing the lateral distance to the active area.

[0038] In further examples, at least one first region of the plurality of laterally spaced-apart first regions has a higher doping concentration at a top side than at a bottom side.

[0039] These regions prevent surface depletion due to surface charge caused by the passivation deposition and ultimately prevent inversion of the P floating ring (ie, the first region).

[0040] The combination of an inversion protection layer between the first region on the epitaxial layer and the P+ enriched layer on top of the P-doped ring, i.e., the top side of the first region is more highly doped than the bottom side, ensures a more stable terminal behavior to surface charges in the terminal, especially in high voltage devices and under harsh environmental conditions (e.g., high temperature and high humidity).

[0041] In another example, the insulating material is any one of:

[0042] - thermal oxide;

[0043] -Tetraethyl orthosilicate TEOS;

[0044] - Silane oxides;

[0045] -Silicon Oxynitride SiON

[0046] -Silicon nitride SiN.

[0047] In another example, the semiconductor body includes silicon carbide SiC.

[0048] SiC has unique properties that make it well suited for power electronics applications. It exhibits a wide bandgap, which allows it to handle higher voltages and operate at higher temperatures than traditional semiconductor materials such as silicon Si. This wide bandgap property enables SiC power devices to have lower switching losses, higher breakdown voltages, and higher thermal conductivity.

[0049] SiC power devices offer advantages such as higher efficiency, improved power density and enhanced performance in high temperature environments. They are used in a variety of power electronics systems, including power supplies, motor drives, electric vehicles, renewable energy systems and high voltage applications.

[0050] SiC-based power devices include diodes, metal oxide semiconductor field effect transistors MOSFETs, junction field effect transistors JFETs, and insulated gate bipolar transistors IGBTs. These devices take advantage of SiC material properties to achieve higher power conversion efficiency, higher operating frequencies, and reduced energy losses.

[0051] In yet another example, a spacing between the plurality of laterally spaced-apart first regions increases in a lateral direction away from the active area.

[0052] In another example, the semiconductor device includes any one of the following:

[0053] -SiC power devices;

[0054] -SiC combined with PIN Schottky diode;

[0055] -SiC metal oxide semiconductor MOS field effect transistor FET, MOSFET;

[0056] -SiC PN diode;

[0057] -SiC barrier Schottky diode.

[0058] In yet another example, the first conductivity type corresponds to an N type, and the second conductivity type corresponds to a P type.

[0059] In a second aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the method comprises the following steps:

[0060] - providing the plurality of laterally spaced apart first regions, the first regions having a second conductivity type opposite to the first conductivity type, each of the plurality of first regions surrounding the active area when viewed from a top view of the semiconductor device;

[0061] -Providing the one or more second regions, wherein the second regions are respectively contained between the multiple spaced-apart first regions, wherein the one or more second regions extend deeper into the epitaxial layer than the multiple spaced-apart first regions, and wherein the one or more second regions include insulating material for insulating the multiple spaced-apart first regions from each other.

[0062] It should be noted that the advantages as explained with reference to the first aspect of the disclosure (being a semiconductor device) also apply to the second aspect of the disclosure (being a method of manufacturing such a semiconductor device).

[0063] In one example, each first region of the plurality of spaced-apart first regions is uniformly doped.

[0064] In another example, the method further comprises the following steps:

[0065] - providing at least one inversion protection layer at the bottom side of the one or more second regions, respectively, wherein the inversion protection layer has the first conductivity type, wherein the doping concentration of the inversion protection layer is higher than the doping concentration of the epitaxial layer.

[0066] In a third aspect of the present disclosure, a power device is provided, comprising a semiconductor device according to any example provided above.

[0067] The present disclosure is described in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0068] In the accompanying drawings, similar components and / or features may have the same reference number. In addition, various components of the same type may be distinguished by following the reference number with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any one of the similar components having the same first reference label, regardless of the second reference label.

[0069] These and other aspects of the disclosure will be apparent from and elucidated with reference to the examples described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1a A cross section of an example of a semiconductor device according to the present disclosure is disclosed;

[0071] Figure 1b A top view of an example of a semiconductor device according to the present disclosure is disclosed;

[0072] Figure 2a A cross section of another example of a semiconductor device according to the present disclosure is disclosed;

[0073] Figure 2b A top view of another example of a semiconductor device according to the present disclosure is disclosed;

[0074] Figure 3a A cross section of yet another example of a semiconductor device according to the present disclosure is disclosed;

[0075] Figure 3b A top view of yet another example of a semiconductor device according to the present disclosure is disclosed;

[0076] Figures 4a-4j Method steps for manufacturing a semiconductor device according to the present disclosure are disclosed. DETAILED DESCRIPTION

[0077] It should be noted that in the description of the drawings, the same reference numerals indicate the same or similar components performing the same or substantially similar functions.

[0078] A more detailed description will be given with reference to specific examples, some of which are illustrated in the accompanying drawings in a manner that enables the features of the present disclosure to be understood in more detail. It should be noted that the drawings illustrate only typical examples and therefore should not be considered to limit the scope of the subject matter of the claims. The drawings are incorporated to facilitate understanding of the present disclosure and are therefore not necessarily drawn to scale. Upon reading the specification in conjunction with the drawings, the advantages of the subject matter as claimed will become apparent to those skilled in the art.

[0079] The following description above provides only preferred exemplary embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. Instead, the following description of the preferred exemplary embodiments will provide those skilled in the art with an enabling description for implementing the preferred exemplary embodiments of the present disclosure, and it should be understood that various changes may be made in the function and arrangement of elements, including combinations of features from different embodiments, without departing from the scope of the present disclosure.

[0080] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise", "comprising", etc. should be interpreted in an inclusive sense, rather than in an exclusive or exhaustive sense; that is, in the sense of "including but not limited to". As used herein, the terms "connected", "coupled", or any variation thereof, mean any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements may be physical, logical, electromagnetic, or a combination thereof. In addition, the words "herein", "above", "below", and words of similar meaning, when used in this application, refer to this application as a whole, not to any particular part of this application. Where the context permits, words used in the singular or plural in the detailed description may also include the plural or singular, respectively. The word "or" when referring to a list of two or more items encompasses all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

[0081] According to the following detailed description, these and other changes can be made to the technology. Although the specification describes certain examples of the technology and describes the expected best mode, no matter how detailed the specification seems, the technology can be practiced in many ways. The details of the system can vary considerably in its specific implementation, while still being covered by the technology disclosed in this article. As mentioned above, the specific terms used when describing certain features or aspects of the technology should not be understood to imply that the term is redefined in this article to be limited to any specific characteristics, features or aspects of the technology associated with the term. In general, the terms used in the attached claims should not be interpreted as limiting the technology to the specific examples disclosed in the specification, unless such terms are clearly defined in the specific implementation section. Therefore, the actual scope of the technology not only covers the disclosed examples, but also covers all equivalent ways of practicing or realizing the technology under the claims.

[0082] Figure 1a A cross section 1 of an example of a semiconductor device according to the present disclosure is disclosed, and Figure 1b A top view of an example of a semiconductor device according to the present disclosure is disclosed.

[0083] The epitaxial layer is denoted by reference numeral 3. The active region is denoted by reference numeral 1. The termination region is denoted by reference numeral 8. The plurality of first regions are denoted by reference numeral 6. The oxide layer is denoted by reference numeral 7. The insulating material is denoted by reference numeral 5. The inversion protection layer is denoted by reference numeral 4.

[0084] It should be noted that in order to improve the readability of the present disclosure, the same reference numerals are used throughout the drawings.

[0085] The example shown in Figure 1 shows a P floating ring termination 6, where the ring is formed by etching a P-type layer defined by epitaxy or implantation. The depth of the recessed region is deeper than the depth of the P-type region in the termination.

[0086] This example also shows an N+ enriched layer 4 defined by implantation at the bottom of the trenches between adjacent P rings. The passivation layer 5 is formed by a stack of a thin SiO2 layer and an additional dielectric layer. The SiO2 layer is used to passivate the dangling bonds in the SiC recessed region after the etching process, while the external passivation layer (preferably SiN or SiON) protects the terminations from moisture and other external contaminants.

[0087] This termination design is compatible with the definition of P-doped regions by epitaxy, eliminating any limitations due to implantation processes on SiC, namely low implantation depths and poor implant doping activation, since the doping in the epitaxial layer does not need to be activated at high temperatures as for implant doping.

[0088] Furthermore, the structure can benefit from the integration of an N+ enriched layer at the bottom of the trenches between adjacent P rings, preventing inversion of the low-doped epilayer in the highly defective recessed areas defined by dry etching and in this way ensuring a higher intensity to the surface charge.

[0089] In this example, the trenches may have a depth between 0.5 μm and 1.5 μm and a spacing between 1 μm and 3 μm. The spacing of the trenches may increase from the active area to the saw street. Both the P-doped layer and the N+ enrichment may have a thickness in the range of 0.2 μm to 0.5 μm. The doping of both the P layer and the N+ enriched region may be 10 to 50 times higher than the epitaxial layer doping, in this example, the N epitaxial layer doping may be 1E16 cm-3, and both the P and N+ layer doping may be between 1E17 cm-3 and 5E17 cm-3, and preferably, the doping of the N+ layer is lower than the doping of the P-doped layer.

[0090] Figure 2a A cross section of another example 21 of a semiconductor device according to the present disclosure is disclosed, and Figure 2b A top view of another example of a semiconductor device according to the present disclosure is disclosed.

[0091] The example shown in FIG2 is characterized by the same features disclosed in the example shown in FIG1, with the addition of additional P+ doped enriched regions 22 on top of the floating ring. These regions prevent surface depletion and ultimately inversion of the P floating ring due to the surface charge caused by the passivation deposition. The P+ enriched layer can be defined by epitaxy or implantation and can have, for example, a thickness between 0.05 μm and 0.2 μm and a doping between 1E18 cm-3 and 5E19 cm-3.

[0092] The combination of an N+ rich layer in the recessed region on the epitaxial layer and a P+ rich layer on top of the P doped ring in the termination ensures a more stable termination behavior to surface charge, especially on high voltage devices and under harsh environmental conditions (i.e., high temperature and high humidity).

[0093] Figure 3a A cross section 41 of yet another example of a semiconductor device according to the present disclosure is disclosed, and Figure 3b A top view of yet another example of a semiconductor device according to the present disclosure is disclosed.

[0094] The example shown in FIG3 shows the same features as already disclosed in the example shown in FIG1. ​​However, in this case, the N+ regions are not defined between each pair of floating rings and may end up having different doping, for example, the doping may be higher close to the saw streets, i.e., an N++ layer doped in the range of 1E18 cm-3 to 5E19 cm-3. In this case, different implantation processes may be used to define N regions with different doping.

[0095] The structure disclosed in this example is also compatible with a P+ type enriched region on top of a P type floating ring. In this case, the P+ enriched region may not be defined on top of each floating ring, provided that the P+ layer is implanted. This embodiment is characterized by a smaller number of implanted regions, thereby having benefits in terms of relatively low implant damage.

[0096] Figures 4a-4j Method steps 61 , 62 , 63 , 64 , 65 , 66 , 67 and 68 for manufacturing a semiconductor device according to the present disclosure are disclosed.

[0097] First, provide the junction termination extension in the EPI layer ( Figure 4a Then, TEOS deposition and metal layer hard mask deposition are performed ( Figure 4b ). This is followed by photolithography, metal dry etching, TEOS dry etching and / or resist stripping to form a Figure 4c Next, an additional etching step is performed to etch the epi layer, which produces Figure 4d The intermediate product is shown. Then, a metal wet etch is performed ( Figure 4e ) and perform screen oxide TEOS deposition ( Figure 4f Finally, as shown in FIG. 4G , photolithography and poly spacer dry etching processes are performed, and Figure 4h As shown, an N-type implant may be performed.

[0098] In order to reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but applicants contemplate various aspects of the technology in any number of claim forms. For example, while some aspects of the technology may be recited as computer-readable medium claims, other aspects may also be embodied as computer-readable medium claims, or in other forms, such as in device-plus-function claims.

[0099] In the above description, for the purpose of explanation, many specific details are set forth in order to provide a comprehensive understanding of the implementation of the disclosed technology. However, it will be apparent to those skilled in the art that the embodiments of the disclosed technology can be practiced without some of these specific details.

[0100] Other variations of the disclosed embodiments may be understood and effected by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The recitation of certain measures in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope thereof.

Claims

1. A semiconductor device, comprising: a semiconductor body comprising a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, the epitaxial layer having a first conductivity type, and wherein an active region and a termination region adjacent to the active region are arranged in the epitaxial layer; The terminal area includes: a plurality of laterally spaced first regions, the first regions having a second conductivity type opposite to the first conductivity type, each of the plurality of first regions surrounding the active area when viewed from a top view of the semiconductor device; One or more second regions, wherein the second regions are respectively included between the plurality of spaced-apart first regions, wherein the one or more second regions extend deeper into the epitaxial layer than the plurality of spaced-apart first regions, and wherein the one or more second regions include insulating material for insulating the plurality of spaced-apart first regions from each other. 2 . The semiconductor device of claim 1 , wherein the second region extends at least 150% deeper into the epitaxial layer than the plurality of spaced-apart first regions. 3 . The semiconductor device of claim 1 , wherein the plurality of laterally spaced-apart first regions are floating. 4 . The semiconductor device of claim 1 , wherein each first region of the plurality of spaced-apart first regions is uniformly doped.

5. The semiconductor device according to any one of the preceding claims, wherein the semiconductor device further comprises: At least one inversion protection layer is respectively disposed on the bottom side of the one or more second regions, wherein the inversion protection layer has the first conductivity type, and wherein the doping concentration of the inversion protection layer is higher than the doping concentration of the epitaxial layer. 6 . The semiconductor device according to claim 1 , wherein the semiconductor device comprises at least two inversion protection layers, and wherein doping concentrations of the at least two inversion protection layers increase as they are away from the active region. 7 . The semiconductor device according to claim 1 , wherein the doping concentration of the at least two inversion protection layers increases by increasing the lateral distance from the active region. 8 . The semiconductor device of claim 1 , wherein at least one first region of the plurality of laterally spaced-apart first regions has a top side doping concentration that is higher than a bottom side doping concentration.

9. A semiconductor device according to any one of the preceding claims, wherein the insulating material is any one of the following: - thermal oxide; -Tetraethyl orthosilicate TEOS; - Silane oxides; -Silicon Oxynitride SiON -Silicon nitride SiN. 10 . The semiconductor device of claim 1 , wherein a spacing between the plurality of laterally spaced apart first regions increases in a lateral direction away from the active area.

11. A semiconductor device according to any one of the preceding claims, wherein the semiconductor device comprises any one of the following: -SiC power devices; -SiC combined with PIN Schottky diode; -SiC metal oxide semiconductor MOS field effect transistor FET, MOSFET; -SiC PN diode; -SiC barrier Schottky diode.

12. A method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the method comprises the following steps: - providing the plurality of laterally spaced apart first regions, the first regions having a second conductivity type opposite to the first conductivity type, each of the plurality of first regions surrounding the active area when viewed from a top view of the semiconductor device; -Providing the one or more second regions, wherein the second regions are respectively contained between the multiple spaced-apart first regions, wherein the one or more second regions extend deeper into the epitaxial layer than the multiple spaced-apart first regions, and wherein the one or more second regions include insulating material for insulating the multiple spaced-apart first regions from each other.

13. The method of claim 9, wherein each first region of the plurality of spaced-apart first regions is uniformly doped.

14. The method according to any one of claims 9 to 10, wherein the method further comprises the following steps: - providing at least one inversion protection layer at the bottom side of the one or more second regions, respectively, wherein the inversion protection layer has the first conductivity type, wherein the doping concentration of the inversion protection layer is higher than the doping concentration of the epitaxial layer. 15 . A power device comprising the semiconductor device according to claim 1 .

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