Semiconductor device
By setting an amorphous isolation layer between the active region of the semiconductor device and the first polycrystalline layer, the diffusion of doped elements is hindered, and the problem of performance degradation caused by diffusion of doped elements along the grain boundary into the active region is solved, and effective obstacles to the diffusion of doped elements are achieved, and device performance is improved.
Patent Information
- Application Number
- CN202411720355.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-02-28
AI Technical Summary
In the prior art, doped elements continue to diffuse along the grain boundary and penetrate the gate oxide layer into the active region, resulting in a degradation of semiconductor device performance.
An amorphous isolation layer is provided between the active region and the first polycrystalline layer, which includes a compound of a metal element, a group IVA element and a nitrogen element, and the diffusion of the doped elements is hindered by the amorphous properties of the amorphous isolation layer.
It effectively hinders the diffusion of doped elements, avoids the performance loss of semiconductor devices caused by the diffusion of doped elements to reach the active region, and improves the electrical performance of the device.
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Figure CN119545885A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art
[0002] Chips often refer to semiconductor discrete device chips and integrated circuit chips. Among them, semiconductor discrete devices include semiconductor devices, while integrated circuits refer to complete circuits with certain functions that are made of multiple semiconductor devices (such as transistors, resistors, capacitors, etc.) and their connections in a certain circuit form on one or several semiconductor substrates.
[0003] Semiconductor devices include diodes, triodes, non-volatile memories, thyristors, photonic devices, resistors and capacitors. Integrated circuits are made of multiple semiconductor devices and their connections in a certain circuit form on one or more semiconductor substrates. According to the structural type and process technology of active devices in integrated circuits, integrated circuits can be divided into bipolar integrated circuits, MOS integrated circuits and Bi-MOS (bipolar-MOS hybrid) integrated circuits. Among them, in MOS integrated circuits, the gate used to make MOS tubes is formed by diffusing (or injecting) doping elements into the polysilicon material layer.
[0004] In the prior art, polysilicon or amorphous silicon is deposited to prepare a polysilicon gate after the gate oxide film is prepared. Then, the polysilicon gate is diffused (or injected) with doping element B to prepare a PMOS transistor; after the doping element is injected, it diffuses along the gate polysilicon grain boundary. The doping element continues to diffuse along the grain boundary and penetrates the gate oxide layer into the channel region, which causes a large positive shift in the electrical performance of the semiconductor device, thereby reducing the performance of the semiconductor device. Summary of the invention
[0005] The main technical problem solved by the present application is to provide a semiconductor device to solve the problem that the doping elements continue to diffuse along the grain boundary, penetrate the gate oxide layer and enter the active area, so that the performance of the semiconductor device is reduced.
[0006] In order to solve the above-mentioned technical problems, a technical solution adopted in the present application is to provide a semiconductor device, including an active area and an electrode structure layer arranged on the active area, the electrode structure layer includes a gate electrode, the gate electrode includes an amorphous isolation layer and a first polycrystalline layer stacked in sequence in a direction away from the active area, the amorphous isolation layer includes a compound of a metal element, an IVA group element and a nitrogen element, and the metal element includes one or more of Ti, Co and Ni.
[0007] In some embodiments, the gate electrode further includes: a second polycrystalline layer between the amorphous isolation layer and the active region.
[0008] In some embodiments, the first polycrystalline layer is doped with boron.
[0009] In some embodiments, the semiconductor device is a PMOS transistor, the active region includes a channel region, and the electrode structure layer further includes a gate insulating layer located between the gate electrode and the channel region.
[0010] In some embodiments, the semiconductor device is a JFET transistor, the active region includes a gate region, and an ohmic contact is formed between the gate electrode and the gate region.
[0011] In some embodiments, the Group IVA element includes Si element.
[0012] In some embodiments, the amorphous isolation layer has a thickness of 100-300 angstroms.
[0013] In some embodiments, the material of the amorphous isolation layer is A x Si y N z , A is a metal element, x+y+z=1, 0.5 <y<0.9。
[0014] In some embodiments, the thickness of the first polycrystalline layer in the gate electrode accounts for greater than or equal to 70%.
[0015] In some embodiments, the first polycrystalline layer is doped with C element.
[0016] In some embodiments, the thickness of the second polycrystalline layer in the gate electrode accounts for less than or equal to 30%.
[0017] In some embodiments, the second polycrystalline layer is doped with C element.
[0018] In some embodiments, the gate electrode further includes a silicon oxide layer between the amorphous isolation layer and the second polycrystalline layer.
[0019] The beneficial effect of the present application is as follows: in the present application, an amorphous isolation layer is arranged between the active area and the first polycrystalline layer. The amorphous characteristics of the amorphous isolation layer hinder the diffusion of doping elements in the first polycrystalline layer along the grain boundaries of the first polycrystalline layer, thereby achieving the function of hindering the diffusion of doping elements and avoiding the performance loss of the semiconductor device due to the continuous diffusion of doping elements along the grain boundaries to reach the active area. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 is a schematic diagram of implanting a doping element B into a polysilicon layer in the prior art;
[0021] Figure 2 It is a schematic diagram of the doping element B starting to diffuse along the grain boundary in the polysilicon layer in the prior art;
[0022] Figure 3It is a schematic diagram of the continuous diffusion of the doping element B in the polysilicon layer along the grain boundary in the prior art;
[0023] Figure 4 It is a schematic diagram of the diffusion of the doping element B along the lower end of the grain boundary to the active region in the prior art;
[0024] Figure 5 is a schematic structural diagram after a gate insulating layer is formed in a method for manufacturing a PMOS transistor according to an embodiment of the present application;
[0025] Figure 6 is a schematic structural diagram after forming a second polycrystalline layer in a method for manufacturing a PMOS transistor according to an embodiment of the present application;
[0026] Figure 7 It is a schematic diagram of the structure after a silicon oxide layer is formed in a method for manufacturing a PMOS transistor according to an embodiment of the present application;
[0027] Figure 8 is a schematic structural diagram after an amorphous isolation layer is formed in a PMOS transistor manufacturing method according to an embodiment of the present application;
[0028] Fig. 9 is a schematic structural diagram after forming a first polycrystalline layer in a PMOS transistor manufacturing method according to an embodiment of the present application;
[0029] Fig.10 is a schematic diagram of implanting boron into a first polycrystalline layer in a method for manufacturing a PMOS transistor according to an embodiment of the present application;
[0030] Fig.11 is a schematic diagram of a PMOS transistor structure according to an embodiment of the present application;
[0031] Fig.12 is a schematic diagram of a JFET transistor structure according to another embodiment of the present application;
[0032] Fig.13 According to an embodiment A of the present application x Si y N z Schematic diagram of the effect of the proportion of y on the diffusion of boron;
[0033] Fig.14 This is a schematic diagram of the effect of the thickness of TiSiN on the diffusion of boron according to an embodiment of the present application. DETAILED DESCRIPTION
[0034] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of this application.
[0035] It should be noted that when an element is referred to as being "fixed on" or "set on" another component, it can be directly on the other component or indirectly set on the other component; when a component is referred to as being "connected to" another component, it can be directly connected to the other component or indirectly connected to the other component.
[0036] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "vertical", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0037] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" and "several" mean two or more, unless otherwise clearly and specifically defined.
[0038] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so that people familiar with this technology can understand and read them. They are not used to limit the conditions under which this application can be implemented, so they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in this application without affecting the effects and purposes that can be achieved by this application.
[0039] In the preparation of semiconductor devices, a semiconductor substrate is first provided, and an isolation structure (such as a shallow trench isolation structure, etc.) is formed in the provided semiconductor substrate. The isolation structure divides the semiconductor substrate into a plurality of independent regions, and each region of the semiconductor substrate can be defined as an active region. However, it is not limited to this, and the preparation method and structure of the active region can be selected according to actual needs.
[0040] Existing technologies such as Figure 1-Figure 4 As shown, the semiconductor device is a PMOS transistor. An oxide layer 10 and a polysilicon layer 20 can be stacked in sequence on the active region 1, and then the boron element B can be injected into the polysilicon layer 20. After the oxide layer 10 and the polysilicon layer 20 are patterned and etched, the electrode structure layer of the PMOS transistor can be formed. The PMOS transistor also includes a source and drain 30 located in the active region 1, and a channel region 50 located between the two source and drain electrodes 30. It can be understood that the oxide layer 10 is used as a gate insulating layer. After the boron element B is injected into the polysilicon layer 20 ( Figure 1 ), and gradually diffuses along the grain boundary 40 of the polysilicon layer 20 in the subsequent heat treatment ( Figure 2 , Figure 3 ), the boron element B eventually diffuses along the grain boundary 40, penetrates the oxide layer 10 and enters the channel region 50 ( Figure 4 ), causing a large positive offset in the semiconductor device, thus reducing the performance of the semiconductor device.
[0041] In order to solve the above problems, in one embodiment of the present application, an amorphous isolation layer 213 is set between the active area 1 and the first polycrystalline layer 214, and the amorphous isolation layer 213 includes a compound of metal elements, IVA group elements and nitrogen elements, and the metal elements include one or more of Ti, Co and Ni.
[0042] In the present application, an amorphous isolation layer 213 is arranged between the active area 1 and the first polycrystalline layer 214. The amorphous characteristics of the amorphous isolation layer 213 hinder the diffusion of the doping element B in the first polycrystalline layer 214 along the grain boundary 40 of the first polycrystalline layer 214, thereby achieving the function of hindering the diffusion of the doping element B and avoiding the performance loss of the semiconductor device due to the continuous diffusion of the doping element B along the grain boundary 40 to reach the active area 1.
[0043] In some embodiments, a method for manufacturing a semiconductor device as a PMOS transistor ( Figure 5-Figure 11 ) and the resulting PMOS transistor ( Fig.11 ) is used as an example for explanation. A material stack is formed on the active area 1, and the material stack includes a gate insulating material layer 111, a second polycrystalline material layer 112, a silicon oxide material layer 113, an amorphous isolation material layer 114, and a first polycrystalline material layer 115 stacked in sequence on the active area 1. The gate insulating material layer 111, the second polycrystalline material layer 112, the silicon oxide material layer 113, the amorphous isolation material layer 114, and the first polycrystalline material layer 115 are patterned and etched to form an electrode structure layer 2 above the channel area 11 of the active area 1. The electrode structure layer 2 includes a gate insulating layer 22 and a gate electrode 21 formed by stacking the active area 1 upwards in sequence. The gate electrode 21 includes a second polycrystalline layer 211, a silicon oxide layer 212, an amorphous isolation layer 213, and a first polycrystalline layer 214 stacked in sequence. Fig.10As shown, the doping of the first polycrystalline layer 214 may be performed by B ion implantation before pattern etching, but is not limited thereto. In some embodiments, B doping may be performed after pattern etching, depending on the specific circumstances.
[0044] A gate insulating material layer 111 , a second polycrystalline material layer 112 , an amorphous isolation material layer 114 and a first polycrystalline material layer 115 may be sequentially formed on the active region 1 by a deposition method to form a material stack.
[0045] The silicon oxide material layer 113 is formed by oxidation of the surface of the second polycrystalline material layer 112. The silicon oxide material layer 113 is an amorphous layer, which has a blocking effect on the doping element B, so that the stack of the silicon oxide layer 212 and the amorphous isolation layer 213 is used to block the diffusion of the doping element B into the channel, which can further improve the blocking effect. And the amorphous isolation material layer 114 is prepared on the surface of the amorphous silicon oxide material layer 113, which can reduce the difficulty of the preparation process.
[0046] In some embodiments not shown in the figure, the silicon oxide material layer 113 on the surface of the second polycrystalline material layer 112 is removed before depositing the amorphous isolation material layer 114, so that: the gate electrode 21 does not include the silicon oxide layer 212, that is, the gate electrode 21 includes the second polycrystalline layer 211, the amorphous isolation layer 213 and the first polycrystalline layer 214. The amorphous isolation layer 213 can block the diffusion of the doping element B into the channel, and removing the silicon oxide material layer 114 on the surface of the second polycrystalline material layer 113 can improve the conductive characteristics of the gate electrode 21 of the PMOS transistor.
[0047] The B-doped first polycrystalline layer 214 in the gate electrode 21 has good conductivity, while the undoped second polycrystalline layer 211 has weak conductivity. The conductivity of the gate electrode 21 can be adjusted by adjusting the thickness ratio of the first polycrystalline layer 214 and the second polycrystalline layer 211 in the gate electrode 21.
[0048] In some embodiments, the thickness of the formed second polycrystalline layer 211 in the gate electrode 21 is less than or equal to 30%, or the thickness of the first polycrystalline layer 214 in the gate electrode 21 is greater than or equal to 70%. This ensures that the amorphous isolation layer 213 can have a good barrier effect on the doping elements in the first polycrystalline layer 214, while the gate electrode 21 has a high conductivity.
[0049] In some embodiments, the electrode structure layer 2 does not include the second polycrystalline layer 211 and the silicon oxide layer 212, that is, the gate electrode 21 includes the amorphous isolation layer 213 and the first polycrystalline layer 214. At this time, the thickness of the second polycrystalline layer 211 in the gate electrode 21 accounts for 0%.
[0050] In some embodiments, the formed second polycrystalline layer 211 and / or the first polycrystalline layer 214 are doped with element C. For example, amorphous silicon used for crystallizing to form the second polycrystalline layer 211 and / or the first polycrystalline layer 214 is doped with C, or C is in-situ doped when the second polycrystalline layer 211 and / or the first polycrystalline layer 214 are deposited. Through the doping of element C, the diffusion ability of doping element B in the first polycrystalline layer 214 and / or the second polycrystalline layer 211 can be reduced.
[0051] In some embodiments, when forming the amorphous isolation layer 213, the Group IVA elements in the amorphous isolation layer 213 may include any one or more of the Group IVA elements. Preferably, it includes element Si. As the proportion of element Si in the amorphous isolation layer 213 increases, the crystallization temperature of the amorphous isolation layer 213 can be increased, so that a more stable amorphous phase can be obtained, blocking the diffusion of doping element B along the grain boundaries, thereby inhibiting the diffusion of doping element B to the channel region 11.
[0052] In some embodiments, the hindering effect on the doping element can be adjusted by adjusting the proportion of the Group IVA elements in the amorphous isolation layer.
[0053] As Fig.13 shown, Fig.13 is a schematic diagram of the influence of the size of y in A x Si y N z on the diffusion of boron element (where x + y + z = 1). Fig.13 In it, the abscissa represents the size of y in A x Si y N z ; the ordinate represents the boron content diffused into the active region through the amorphous isolation layer with the material of A x Si y N z compared with the amorphous isolation layer with y = 0. It can be seen from Fig.13 that as the proportion of Si in the amorphous isolation layer increases, the boron element diffused into the active region decreases, indicating that the diffusion ability of the amorphous isolation layer for the doping element increases. In application, the proportion of Si in the amorphous isolation layer can be flexibly adjusted as needed to flexibly adapt to different application scenarios.
[0054] In some embodiments, the material of the amorphous isolation layer 213 is A x Si y N z , A is a metal element, and x, y, and z are the proportions of A, Si, and N in the amorphous isolation layer 213 respectively, x + y + z = 1, and 0.5 < y < 0.9. At this proportion, the amorphous isolation layer 213 has a better hindering effect on the diffusion of doping element B.
[0055] In some embodiments, the metal element in the amorphous isolation layer 213 includes one or more of Ti, Co and Ni. The amorphous isolation layer 213 has amorphous characteristics, which improves the blocking effect of the amorphous isolation layer 213 on the diffusion of the doping element B.
[0056] In some embodiments, the amorphous isolation layer 213 may be TiSiN. It should be noted that for TiSiN, the atomic ratio thereof is not limited. x Si y N z In (x+y+z=1), the metal element A is Ti.
[0057] In some embodiments, the doping element in the first polycrystalline layer 214 may be boron, that is, the first polycrystalline layer 214 is boron-doped polycrystalline silicon.
[0058] In some embodiments, after forming the first polycrystalline layer 214, B element ( Fig.10 ). However, the method of doping B can be selected according to actual needs to obtain the first polysilicon 214, and the first polysilicon 214 is doped with B.
[0059] In some embodiments, the barrier effect on the doping elements can be adjusted by adjusting the thickness of the amorphous isolation layer.
[0060] like Fig.14 As shown, Fig.14 This is a schematic diagram of the effect of the thickness of the TiSiN layer on the diffusion of the boron element according to an embodiment of the present application. It can be understood that the material of the amorphous isolation layer is TiSiN, wherein the atomic ratio of each element is not limited; Fig.14 The horizontal axis represents the thickness of the TiSiN layer, and the vertical axis represents the boron content diffused into the active area through the TiSiN layer of corresponding thickness relative to the case where no amorphous isolation layer is used (i.e., the thickness of the TiSiN layer is 0). Fig.14 It can be seen that TiSiN can play a good barrier effect on doping elements in semiconductor devices. And as the thickness of TiSiN increases, the amount of boron diffused into the active area decreases, indicating that the barrier effect of the amorphous isolation layer on doping elements is enhanced.
[0061] In some embodiments, the thickness of the amorphous isolation layer 213 is 100-300 angstroms, for example, 100 angstroms, 150 angstroms, 200 angstroms, 250 angstroms, and 300 angstroms, etc. This ensures that the amorphous isolation layer 213 can have a good barrier effect on the doping elements in the first polycrystalline layer 214 .
[0062] In some embodiments, the semiconductor device may also be a JFET transistor (Junction Field-Effect Transistor, junction field effect transistor), such as Fig.12 The active region 1 includes a gate region 110, and an ohmic contact is formed between the gate electrode 21 and the gate region 110. For example, the gate electrode 21 includes a second polycrystalline layer 211, an amorphous isolation layer 213 and a first polycrystalline layer 214. The gate electrode 21 may have the same structure as the gate electrode 21 mentioned in the above embodiment, and will not be described in detail.
[0063] It can be seen that the present application discloses a semiconductor device, in which an amorphous isolation layer is arranged between the active area and the first polycrystalline layer. The amorphous characteristics of the amorphous isolation layer are used to hinder the diffusion of the doping element B in the first polycrystalline layer along the grain boundaries of the first polycrystalline layer, thereby achieving the function of hindering the diffusion of the doping element, thereby avoiding the performance loss of the semiconductor device due to the continuous diffusion of the doping element along the grain boundaries to reach the active area.
[0064] The above are merely embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structural transformations made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A semiconductor device, characterized in that: The invention comprises an active area and an electrode structure layer arranged on the active area, wherein the electrode structure layer comprises a gate electrode, and the gate electrode comprises an amorphous isolation layer and a first polycrystalline layer stacked in sequence in a direction away from the active area, wherein the amorphous isolation layer comprises a compound of a metal element, an IVA group element and a nitrogen element, and the metal element comprises one or more of Ti, Co and Ni.
2. The semiconductor device according to claim 1, wherein The gate electrode further includes: a second polycrystalline layer located between the amorphous isolation layer and the active region.
3. The semiconductor device according to claim 1, wherein The first polycrystalline layer is doped with boron.
4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The semiconductor device is a PMOS transistor, the active region includes a channel region, and the electrode structure layer further includes a gate insulating layer located between the gate electrode and the channel region.
5. The semiconductor device according to any one of claims 1 to 3, characterized in that: The semiconductor device is a JFET transistor, the active region includes a gate region, and an ohmic contact is formed between the gate electrode and the gate region.
6. The semiconductor device according to claim 1, wherein: The IVA group elements include Si elements.
7. The semiconductor device according to claim 1, wherein: The thickness of the amorphous isolation layer is 100-300 angstroms.
8. The semiconductor device according to claim 1, wherein The material of the amorphous isolation layer is A x Si y N z , A is the metal element, x+y+z=1, 0.5 <y<0.9。 9. The semiconductor device according to claim 1, wherein: The thickness of the first polycrystalline layer in the gate electrode accounts for greater than or equal to 70%.
10. The semiconductor device according to claim 1, wherein The first polycrystalline layer is doped with C element.
11. The semiconductor device according to claim 2, wherein: The thickness of the second polycrystalline layer in the gate electrode accounts for less than or equal to 30%.
12. The semiconductor device according to claim 2, wherein: The second polycrystalline layer is doped with C element.
13. The semiconductor device according to claim 2, wherein: The gate electrode further includes a silicon oxide layer between the amorphous isolation layer and the second polycrystalline layer.