Recessed via with conductive link to adjacent contacts

Abstract

Techniques for forming conductive interconnects of semiconductor devices with recessed vias having conductive links to adjacent contacts are disclosed herein. In an example, an integrated circuit includes a recessed via and a conductive bridge between a top surface of the recessed via and an adjacent source or drain contact. A transistor device includes: a semiconductor material extending from a source or drain region; a gate structure on the semiconductor material; and a contact on the source or drain region. Adjacent to the source or drain region, the deep via structure extends in a vertical direction through an entire thickness of the gate structure. The via structure includes a conductive via recessed below a top surface of the conductive contact. A conductive bridge extends between the contact and the conductive via such that the conductive bridge contacts a portion of the contact and at least a portion of a top surface of the conductive via.

Description

Technical Field

[0001] The present disclosure relates to integrated circuits, and more particularly, to contacts for semiconductor components. Background Art

[0002] As the size of integrated circuits continues to shrink, many challenges arise. For example, it becomes increasingly difficult to reduce the size of memory and logic cells, as does reducing the device spacing at the device layer. As transistors are arranged more and more densely, it may be challenging to form certain interconnect structures given the limited spacing and number of traces for a given interconnect layer. In addition, densely arranged components increase parasitic effects that impair transistor performance. Therefore, there are still many challenges with respect to forming semiconductor devices that cannot be ignored. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A and Figure 1B are cross-sectional views of some semiconductor devices according to embodiments of the present disclosure, showing recessed vias connected to adjacent source or drain contacts.

[0004] Figure 1C According to the embodiment of the present disclosure Figure 1A and Figure 1B A plan view of an integrated circuit in FIG.

[0005] Figure 2A and Figure 2B is a cross-sectional view illustrating a stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0006] Figure 3A and Figure 3B is a cross-sectional view illustrating another stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0007] Figure 4A and Figure 4B is a cross-sectional view illustrating another stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0008] Figure 5A and Figure 5B is a cross-sectional view illustrating another stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0009] Fig. 6A and Figure 6B is a cross-sectional view illustrating another stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0010] Fig. 7A and Figure 7B is a cross-sectional view illustrating another stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0011] Fig. 8A and Figure 8B is a cross-sectional view illustrating another stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0012] Fig. 9A and Fig. 9B is a cross-sectional view illustrating another stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0013] Fig. 10A and Fig. 10B is a cross-sectional view illustrating another stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0014] Fig.11A and Fig. 11B is a cross-sectional view illustrating another stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0015] Fig. 12A and Fig. 12B is a cross-sectional view illustrating another stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0016] Fig.13A and Fig. 13B is a cross-sectional view illustrating another stage in an exemplary process for forming a semiconductor device having a recessed via connected to an adjacent source or drain contact according to some embodiments of the present disclosure.

[0017] Fig.14A cross-sectional view of a chip package containing one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0018] Fig.15 is a flow chart of a manufacturing process for a semiconductor device having a recessed via connected to an adjacent source or drain contact according to an embodiment of the present disclosure.

[0019] Fig.16 A computing system including one or more integrated circuits as variously described herein is shown according to an embodiment of the present disclosure.

[0020] Although the following detailed description will be made with reference to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent in light of the present disclosure. It will be further understood that the drawings are not necessarily drawn to scale, nor are they intended to limit the present disclosure to the specific configurations shown. For example, although some of the drawings generally indicate ideal straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have less than ideal straight lines and right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topologies, or otherwise exhibit non-smoothness, given the practical limitations of the processing equipment and techniques used. DETAILED DESCRIPTION

[0021] Provided herein is a technique for forming a conductive contact portion of a semiconductor device. For example, the technique can be used to interconnect nodes or terminals of the same semiconductor device or different semiconductor devices. In an example, an integrated circuit includes a recessed via and a conductive bridge, which is located between the top surface of the recessed via and an adjacent source or drain contact. The technique can be used for any number of integrated circuit applications, and is particularly useful for device layer transistors such as finFETs or full surround gate transistors (e.g., ribbon FETs and nanowire FETs). In an example, a semiconductor device includes a gate structure located around or otherwise located on a semiconductor region (or channel region) . For example, the semiconductor region can be a fin of semiconductor material extending from a source or drain region, or one or more nanowires or nanobelts or nanosheets of semiconductor material extending from a source or drain region (more generally, a diffusion region). The conductive contact is formed above the source or drain region. Adjacent to the semiconductor region, the via structure extends vertically through the entire thickness of the gate structure. The via structure also extends in the same direction as the channel region, so that the via structure extends adjacent to the source or drain region. The via structure includes a conductive core (or simply a via) recessed below the top surface of the conductive contact. The conductive bridge extends between the contact and the conductive via, so that the conductive bridge contacts a portion of the contact and at least a portion of the top surface of the conductive via. Numerous variations and embodiments will be apparent in light of the present disclosure.

[0022] General Overview

[0023] As mentioned above, there are still multiple challenges that cannot be ignored about integrated circuit manufacturing. In more detail, as the device becomes smaller and more densely arranged, the manufacturing of these structures becomes more challenging because the critical dimensions (CD) of many structures exceed the limits of current manufacturing technology. Due to the number of connections to be realized and the limited occupied area, interconnection may be particularly challenging. Reducing the number of metal connections realized in the interconnection area above (or below) a given device layer can generate more space for forming other metal wiring layers and vias, which can reduce the overall complexity of the device. In addition, the densely arranged device of a given device layer has numerous closely spaced conductive elements that may generate parasitic capacitance, and parasitic capacitance can reduce transistor performance. Therefore, removing the portion of the conductive element located in the device layer or local interconnection while maintaining their electrical use is conducive to reducing parasitic capacitance.

[0024] Therefore, and in accordance with embodiments of the present disclosure, a conductive via adjacent to a contact located above a source or drain region is recessed below the top surface of the contact, and a conductive bridge is formed in the device layer to connect the contact to the via. According to some embodiments, the conductive via may be recessed until its top surface is lower than the top surface of the adjacent source or drain region. The via may extend along a first direction along one side of the source or drain region, and also extend along a side of a semiconductor region (channel region) extending from the source or drain region along the first direction. The via may also extend vertically through the entire thickness of a gate structure that extends across the semiconductor region in a second direction. Therefore, since the via passes through the gate structure in the first direction, the top surface of the via may also be recessed below the top surface of the gate structure.

[0025] According to some embodiments, the conductive bridge contacts both the sidewall portion of the conductive contact and at least a portion of the top surface of the conductive via. In this way, the conductive bridge is formed within the device layer (e.g., below any interconnect layer) and eliminates the need for a metal layer connecting the contact to the via in the interconnect region. The conductive bridge may include the same conductive material as the contact and / or via. In some such cases, although deposition of the same material at different times may produce visible seams between the bridge, the contact and / or the via, there is no visible seam between the conductive bridge and the place where the conductive bridge contacts both the contact and the via. In some other examples, the conductive bridge includes a conductive material different from the contact and / or the via. Exemplary conductive materials for any one of the contacts, conductive bridges or vias include cobalt, tungsten, molybdenum or ruthenium, but other conductive materials suitable for a given application may also be used.

[0026] In some embodiments, the dielectric wall extends between the source or drain region and an adjacent source or drain region on a side of the source or drain region opposite to the via. The dielectric wall may also extend between corresponding gate structures of adjacent devices. According to some embodiments, the conductive contact may extend through a portion of the dielectric wall to be disposed over an adjacent source or drain region. In some examples, portions of other dielectric walls may be removed so that the contact also extends between adjacent source or drain regions while contacting adjacent source or drain regions.

[0027] According to an embodiment, an integrated circuit includes: a semiconductor region extending from a source or drain region in a first direction; a gate electrode extending in a second direction over the semiconductor region; a dielectric layer located below the gate electrode; a contact located on a top surface of the source or drain region; a conductive via extending adjacent to the semiconductor region in the first direction, extending adjacent to the source or drain region in the first direction, and extending through a portion of the gate electrode and through the entire thickness of the dielectric layer in a third direction; and a conductive bridge located between the contact and the conductive via. The top surface of the conductive via is lower than the top surface of the contact, and the conductive bridge extends from a sidewall of the contact and is located on at least a portion of the top surface of the conductive via.

[0028] According to another embodiment, an integrated circuit includes: a semiconductor region extending from a source or drain region in a first direction; a gate electrode extending in a second direction over the semiconductor region; a dielectric layer located below the gate electrode; a conductive via extending adjacent to the semiconductor region in the first direction, extending adjacent to the source or drain region in the first direction, and extending through a portion of the gate electrode and through the entire thickness of the dielectric layer in a third direction; and a conductive contact located on a top surface of the source or drain region. The top surface of the conductive via is lower than the top surface of the gate electrode, and the conductive contact extends in the second direction to contact at least a portion of the top surface of the conductive via.

[0029] According to another embodiment, a method of forming an integrated circuit includes: forming a fin including a semiconductor material, the fin extending above a substrate and extending in a first direction; forming a gate electrode, the gate electrode extending in a second direction different from the first direction over the fin; forming a source or drain region at an end of the fin; forming a contact over the source or drain region; forming a recess through the gate electrode adjacent to the fin, the recess extending through the gate electrode in the first direction and adjacent to the source or drain region; forming a dielectric material within the recess; forming a conductive via within the recess, the The conductive via extends in a first direction so that the dielectric material is located between the conductive via and the gate electrode, and the dielectric material is located between the conductive via and the contact; the conductive via is recessed so that the top surface of the conductive via is lower than the top surface of the contact; a dielectric cap is formed over the top surface of the recessed conductive via; a portion of the dielectric material located between the dielectric cap and the contact is recessed, and at least a portion of the dielectric cap is recessed so that at least a portion of the top surface of the conductive via is exposed; and a conductive bridge is formed over at least a portion of the top surface of the conductive via, the conductive bridge abutting the contact.

[0030] The technology can be used for any type of non-planar transistor, including finFETs (sometimes called tri-gate transistors), nanowire and nanoribbon transistors (sometimes called all-around gate transistors), or fork-shaped sheet transistors, to name a few. The source and drain regions can be, for example, doped portions of a given fin or substrate, or can be epitaxial regions deposited during etching and replacement source / drain formation processes. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented using a gate-first process or a gate-last process (sometimes called a replacement metal gate or RMG process). Any number of semiconductor materials, such as Group IV materials (e.g., silicon, germanium, silicon germanium) or Group III-V materials (e.g., gallium arsenide, indium gallium arsenide) can be used to form transistors.

[0031] The use of the techniques and structures provided herein can be detected using tools such as: electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); compositional mapping; x-ray crystallography or diffraction (XRD); energy dispersive x-ray spectrometry (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, just to name a few suitable exemplary analytical tools. For example, in some exemplary embodiments, such a tool can indicate the presence of a recessed via having a conductive bridge between a portion of the top surface of the recessed via and an adjacent source or drain contact. Depending on the conductive materials and process flow used, there may or may not be a visible seam between each of the contact, the conductive bridge, and the via. The conductive bridge between the contact and the via can be observed in a device layer located below any interconnect layer.

[0032] It should be readily understood that the meaning of "above" and "on top of" in the present disclosure should be interpreted in the broadest manner, so that "above" and "on top of" not only mean "directly on something", but also include the meaning of "on top of something" and having intermediate features or layers therebetween. In addition, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", "top", "bottom", etc. may be used herein to describe the relationship between one element or feature and another (or multiple) element or feature as shown in the figure. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0033] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A monolayer is a layer consisting of a monolayer of atoms of a given material. A layer may extend over the entire underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. In addition, a layer may be an area of ​​a homogeneous or heterogeneous continuous structure, wherein the layer has a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A layer may be conformal to a given surface (whether flat or curved) and have a relatively uniform thickness across the entire layer.

[0034] As used herein, "compositionally different" or "compositionally dissimilar" materials refer to two materials having different chemical compositions. Such compositional differences may be due, for example, to an element in one material but not in the other (e.g., SiGe is compositionally different from silicon), or may be due to one material having all of the same elements as the second material, but at least one of those elements being intentionally provided in a different concentration in one material relative to the other (e.g., SiGe having 70 atomic percent germanium is compositionally different from SiGe having 25 atomic percent germanium). In addition to such chemical composition diversity, the materials may also have different dopants (e.g., gallium and magnesium) or the same dopants but in different concentrations. In yet another embodiment, compositionally dissimilar materials may also refer to two materials having different crystallographic orientations. For example, (110) silicon is compositionally dissimilar or different from (100) silicon. For example, blanket wafer layer transfer may be employed to accomplish the creation of stacks of different orientations. If two materials are elementally dissimilar, then one of the materials has an element that is not present in the other.

[0035] Architecture

[0036] Figure 1A 1 is a cross-sectional view taken along gate trenches of three exemplary semiconductor devices (a first semiconductor device 101 a , a second semiconductor device 101 b , and a third semiconductor device 101 c ) according to an embodiment of the present disclosure. Figure 1B Passing through and in and out Figure 1A Another cross-sectional view of the gate trench taken adjacent to the source / drain trenches or diffusion regions and contact trenches of the page. Figure 1C is along Figure 1A and Figure 1B The dashed line 1C-1C depicted in both diagrams is a top-down cross-sectional view of adjacent semiconductor devices 101a / 101b / 101c. Figure 1A Shown along Figure 1C A cross section taken along the dashed line 1A-1A depicted in FIG. 1A , and Figure 1B Shown along Figure 1C It should be noted that in Figure 1C In the top view of FIG. 1 , some of the material layers (eg, dielectric cap layer 136 ) are not visible given the location of the depicted cross-section.

[0037] Each of the semiconductor devices 101a / 101b / 101c can be, for example, a non-planar metal oxide semiconductor (MOS) transistor, such as a tri-gate (e.g., finFET) or a gate-all-around (GAA) transistor, but other transistor topologies and types can also benefit from the techniques provided herein. The exemplary embodiments shown use a GAA structure. The various shown semiconductor devices represent portions of an integrated circuit that may contain any number of similar semiconductor devices.

[0038] As can be seen, semiconductor devices 101a / 101b / 101c are formed on substrate 102. Any number of semiconductor devices may be formed on substrate 102, but three are shown here as examples. Substrate 102 may be, for example, a bulk substrate including a Group IV semiconductor material (e.g., silicon, germanium, or silicon germanium), a Group III-V semiconductor material (e.g., gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors may be formed. Alternatively, substrate 102 may be a semiconductor-on-insulator substrate having a desired semiconductor layer (e.g., silicon on silicon dioxide) above a buried insulator layer. Alternatively, substrate 102 may be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates may be used. In some embodiments, during the backside process, a lower portion (or all of the substrate) of substrate 102 is removed and replaced with one or more backside interconnect layers to form backside signal and power routing.

[0039] Each of the semiconductor devices 101a / 101b / 101c includes one or more corresponding nanoribbons 104a / 104b / 104c. Figure 1C As can be seen more clearly in FIG. 1 , one or more nanoribbons 104a / 104b / 104c extend along a direction (e.g., between corresponding source or drain regions) Figure 1A 101a / 101b / 101c extend parallel to each other. Thus, nanoribbon 104a extends between source or drain regions 110a, nanoribbon 104b extends between source or drain regions 110b, and nanoribbon 104c extends between source or drain regions 110c. Nanoribbon 104a / 104b / 104c is an example of a semiconductor region or semiconductor body extending between source or drain regions. The term "nanoribbon" may also encompass other similar shapes, such as nanowires or nanosheets. The semiconductor material of nanoribbon 104a / 104b / 104c may be formed by substrate 102. In some embodiments, semiconductor devices 101a / 101b / 101c may each include a semiconductor region in the shape of a fin, which may be, for example, native to substrate 102 (formed by the substrate itself), such as a silicon fin etched from a bulk silicon substrate. Alternatively, the fin may be formed by a material deposited onto an underlying substrate. In one such exemplary case, a blanket layer of silicon germanium (SiGe) may be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, non-native fins may be formed in a so-called aspect ratio capture-based process, wherein native fins are etched away to leave fin-shaped trenches, which may then be filled with alternative semiconductor materials (e.g., group IV or group III-V materials). In yet other embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate formation of the nanoribbons 104a / 104b / 104c shown during a gate formation process, wherein one type of alternating layers is selectively etched away to release another type of alternating layers within the channel region so that a gate-all-around (GAA) process may then be performed. Likewise, alternating layers may be blanket deposited and then etched into fins or deposited into fin-shaped trenches.

[0040] It can also be seen that adjacent semiconductor devices are separated by dielectric fill 106. Dielectric fill 106 provides shallow trench isolation (STI) between any adjacent semiconductor devices. Dielectric fill 106 can be any suitable dielectric material, such as silicon dioxide, aluminum oxide, or silicon oxynitride and carbonitride.

[0041] The semiconductor devices 101a / 101b / 101c each include a sub-fin region 108. According to some embodiments, the sub-fin region 108 includes the same semiconductor material as the substrate 102 and is adjacent to the dielectric fill 106. According to some embodiments, the nanoribbons 104a / 104b / 104c (or other semiconductor bodies) extend along a first direction between the source or drain regions 110a / 110b / 110c to provide an active region (sometimes referred to as a channel region) for the transistor (e.g., a semiconductor region located below the gate). It should be understood that Figure 1B The source or drain region 110a / 110b / 110c shown in the cross section is only along one side of the nanoribbon 104a / 104b / 104c (eg, away from Figure 1A ), and if Figure 1C As shown in , similar source and drain regions may exist along opposite sides of the nanoribbons 104a / 104b / 104c.

[0042] According to some embodiments, the source or drain region is an epitaxial region provided using an etching and replacement process. In other embodiments, the source or drain region may be, for example, an implanted doped native portion of a semiconductor fin or substrate. Any semiconductor material suitable for the source and drain regions (e.g., Group IV and Group III-V semiconductor materials) may be used. Depending on the polarity of the transistor, the composition and doping of the source or drain region may be the same or different. In an example, for example, one transistor is a p-type MOS (PMOS) transistor and the other transistor is an n-type MOS (NMOS) transistor. Therefore, the source or drain region 110a may have a different dopant type (n or p) than the source or drain region 110b. Any number of source or drain configurations and materials may be used.

[0043] According to some embodiments, a lower dielectric layer 112 is present below the source or drain region 110a / 110b / 110c. The lower dielectric layer 112 may include any suitable dielectric material, such as silicon dioxide or silicon nitride or silicon oxynitride, and may be provided to isolate the source or drain region 110a / 110b / 110c from the sub-fin region 108. According to some embodiments, after the epitaxial formation of the source / drain region is completed, another dielectric filler 114 is provided around and above the portion of the source or drain region 110a / 110b / 110c along the source / drain trench. Thus, each source or drain region may be isolated from any adjacent source or drain region by the dielectric filler 114. Although in some embodiments, the dielectric filler 114 includes the same dielectric material as the dielectric filler 106 or the lower dielectric layer 112, the dielectric filler 114 may be any suitable dielectric material. In one example, each of the dielectric filler 114 , the lower dielectric layer 112 , and the dielectric filler 106 includes silicon dioxide.

[0044] According to some embodiments, the gate structure spans Figure 1A The page extends in a second direction over the nanoribbon 104a / 104b / 104c of the semiconductor device 101a / 101b / 101c. The gate structure includes a gate dielectric 116 and a gate electrode 118. The gate dielectric 116 represents any number of dielectric layers present between the nanoribbon 104a / 104b / 104c and the gate electrode 118. The gate dielectric 116 may also be present on the surface of other structures within the gate trench, such as on the sub-fin region 108. The gate dielectric 116 may include any suitable (multiple) gate dielectric materials. In some embodiments, the gate dielectric 116 includes a layer of native oxide material (e.g., silicon dioxide) located on the nanoribbon or other semiconductor region that constitutes the channel region of the device and a layer of high-k dielectric material (e.g., hafnium oxide) located on the native oxide.

[0045] The gate electrode 118 may represent any number of conductive layers, such as any metal, metal alloy, or doped polysilicon layer. In some embodiments, the gate electrode 118 includes one or more work function metals around the nanoribbons 104a / 104b / 104c. In some embodiments, one of the semiconductor devices 101a / 101b / 101c is a p-channel device including a work function metal having titanium around its nanoribbons, and the other semiconductor device is an n-channel device including a work function metal having tungsten around its nanoribbons. The gate electrode 118 may also include a fill metal or other conductive material surrounding the work function metal to provide an overall gate electrode structure.

[0046] According to some embodiments, dielectric wall 120 exists between some adjacent semiconductor devices. In the example shown, a first gate structure exists on nanoribbon 104a, and a second gate structure exists on nanoribbon 104b, wherein dielectric wall 120 separates the two gate structures. Dielectric wall 120 extends in a first direction (e.g., in and out of the page) across the gate trench, and further extends along the source / drain trench to isolate adjacent source or drain regions from each other. In the example shown, a given dielectric wall 120 extends between source or drain region 110a and source or drain region 110b. Dielectric wall 120 can continue to extend in the first direction to separate any number of other devices from each other within the integrated circuit. Dielectric wall 120 extends through at least the entire thickness of the gate structure. In some examples, dielectric wall 120 also extends through the entire thickness of dielectric filler 106. Dielectric wall 120 can be formed of a sufficiently insulating material (e.g., a dielectric material). Exemplary materials for dielectric walls 120 include silicon nitride, silicon dioxide, or silicon oxynitride. According to some embodiments, dielectric walls 120 each have a width between about 10 nm and about 15 nm.

[0047] According to some embodiments, one or more via structures 122 extend between some adjacent semiconductor devices in a manner similar to the dielectric wall 120. In the example shown, the via structure 122 extends between a second gate structure located above the nanoribbon 104b and a third gate structure located above the nanoribbon 104c. Like the dielectric wall 120, the via structure 122 extends across the gate trench in a first direction (e.g., in and out of the page) and further extends along the source / drain trench to isolate adjacent source or drain regions from each other. In the example shown, the via structure 122 extends between the source or drain region 110b and the source or drain region 110c. The via structure 122 extends through at least the entire thickness of the gate structure and also through the entire thickness of the dielectric filler 106.

[0048] According to some embodiments, the via structure 122 includes a dielectric liner 124 along the sidewalls of the via structure 122, and a conductive via 126 (e.g., a conductive core of the via structure). The dielectric liner 124 may include any suitable dielectric material, such as silicon nitride, silicon dioxide, silicon oxycarbide, or silicon oxycarbon nitride, or a low-k version of any of these materials, to name a few. Low-k dielectric materials generally refer to materials having a dielectric constant lower than that of silicon dioxide (e.g., porous silicon dioxide) (or lower than 3.9). The dielectric liner 124 may represent any number of dielectric layers, such as a first dielectric layer directly on the gate electrode 118 including a high-k dielectric material (e.g., a dielectric constant of silicon nitride or higher) and a second dielectric layer on the first dielectric layer, wherein the second dielectric layer includes a low-k dielectric material. The conductive via 126 may include any suitable metal material, such as tungsten, cobalt, ruthenium, or molybdenum, to name a few. According to some embodiments, the via structure 122 also includes a dielectric cap 128 located on a top surface of the conductive via 126. The dielectric cap 128 may include any suitable dielectric material, and may be the same dielectric material as the dielectric liner 124.

[0049] According to some embodiments, the conductive contact 130 is formed on the source or drain regions 110a-110c, respectively. According to some embodiments, each conductive contact 130 includes a conductive filler and a conductive liner along the outer edge of the conductive filler. The conductive filler can be any suitable conductive material (e.g., tungsten). Other conductive materials can include ruthenium, cobalt, molybdenum, or any alloy thereof. For example, the conductive liner can be a barrier layer and / or a resistance reducing layer, which includes titanium or tantalum (e.g., titanium nitride or tantalum nitride), silicide, or some other suitable liner.

[0050] According to some embodiments, the top surface of the conductive via 126 is recessed below the top surface of the contact portion 130. Figure 1A and Figure 1B As shown in both, the conductive via 126 can be recessed along its entire length so that the top surface of the conductive via 126 is also recessed below the top surface of the gate electrode 118. In some examples, the top surface of the conductive via 126 is also lower than the top surface of the adjacent source or drain region 110b / 110c. A dielectric cap 128 can be formed in the cavity left after the conductive via 126 is recessed between the dielectric liners 124.

[0051] According to some embodiments, the conductive bridge 132 extends between the conductive via 126 and the adjacent contact 130. The conductive bridge 132 may contact at least a portion of the sidewall of the contact 130 and at least a portion of the top surface of the conductive via 126. In some embodiments, the top surface of the conductive bridge 132 is substantially coplanar (e.g., within 2 nm) with the top surface of the contact 130. The conductive bridge 132 may include any suitable conductive material, such as tungsten, cobalt, ruthenium, or molybdenum, to name a few. The conductive bridge 132 may include the same conductive material as the contact 130 and / or the conductive via 126. In an example where each of the contact 130, the conductive bridge 132, and the conductive via 126 includes the same conductive material, there is no visible seam between each of the conductive elements. According to some embodiments, the conductive bridge 132 may extend a distance below the top surface of the conductive via 126.

[0052] According to some embodiments, portions of dielectric wall 120 located between adjacent contacts 130 may be removed and replaced by conductive plugs 134. Conductive plugs 134 may extend along the second direction to contact the sides of two adjacent contacts. Conductive plugs 134 may include any suitable conductive material, such as tungsten, cobalt, ruthenium, or molybdenum, to name a few. Conductive plugs 134 may include the same conductive material as conductive bridge 132 and may be formed substantially simultaneously with conductive bridge 132 (e.g., during the same metal deposition process).

[0053] According to some embodiments, dielectric capping layer 136 extends along the top surface of the gate structure in the gate trench. Thus, dielectric capping layer 136 may extend along the second direction on the top surface of gate electrode 118 and be interrupted by any dielectric wall 120 and via structure 122. In some examples, dielectric capping layer 136 may include the same dielectric material as dielectric wall 120.

[0054] Figure 1C A plan view of an integrated circuit is shown showing how the nanoribbons 104a / 104b / 104c extend between corresponding source or drain regions 110a / 110b / 110c. In accordance with some embodiments, a spacer structure 138 extends along the sides of the gate trenches and isolates the gate trenches from the source / drain trenches (including the epitaxial regions and their corresponding contacts). The spacer structure 138 can include any suitable dielectric material, such as silicon nitride. The nanoribbons 104a / 104b / 104c (or other channel bodies) extend through the spacer structure 138 to contact the corresponding source or drain regions.

[0055] Manufacturing method

[0056] Figures 2A-13A and Figure 2B-Figure 13Bare cross-sectional views collectively illustrating a first exemplary process for forming an integrated circuit configured with a recessed via connected to an adjacent source or drain contact according to an embodiment of the present disclosure. Figures 2A-13A represents a cross-sectional view taken through a gate trench of an integrated circuit, and Figure 2B-Figure 13B represents a cross-sectional view taken in the same direction through a source / drain trench adjacent to a gate trench. Each figure shows an exemplary structure resulting from the process flow up to that point in time, and thus the depicted structure evolves as the process flow continues, ultimately forming Fig.13A and Fig. 13B The structures shown in Figure 1A and Figure 1B . Such a structure may be part of an entire integrated circuit (e.g., a processor or memory chip) that includes, for example, digital logic cells and / or memory cells and analog mixed signal circuits. Thus, the integrated circuit structure shown may be part of a larger integrated circuit that includes other integrated circuits not depicted. Exemplary materials and process parameters are given, but as will be understood, the present disclosure is not intended to be limited to any particular such materials or parameters. Figures sharing the same number (e.g., Figure 2A and Figure 2B ) shows different views of the structure at the same point in time during the process flow. Although the manufacture of a single via structure is shown in the foregoing figures, it should be understood that any number of similar via structures can be manufactured on an integrated circuit using the same process discussed herein.

[0057] Figure 2A and Figure 2B A parallel cross-sectional view taken through a stack of alternating semiconductor layers on a semiconductor substrate 102 is shown. Figure 2A is taken through the portion of the stack that will eventually become the gate trench, and Figure 2B The gate trench is cut through the stack and will eventually become a source / drain trench adjacent to and parallel to the gate trench. Alternating material layers may be deposited on the substrate 102, the alternating material layers including sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form a GAA transistor structure. Any number of alternating semiconductor layers 204 and sacrificial layers 202 may be deposited on the substrate 102.

[0058] According to some embodiments, sacrificial layer 202 has a different material composition than semiconductor layer 204. In some embodiments, sacrificial layer 202 is silicon germanium (SiGe), while semiconductor layer 204 includes a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a III-V material such as indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each of sacrificial layers 202 and in semiconductor layer 204, the germanium concentration is different between sacrificial layer 202 and semiconductor layer 204. For example, sacrificial layer 202 may include a higher germanium content than semiconductor layer 204. In some examples, semiconductor layer 204 may be doped with an n-type dopant (to produce a p-channel transistor) or a p-type dopant (to produce an n-channel transistor).

[0059] Although the dimensions may vary from one exemplary embodiment to the next, the thickness of each sacrificial layer 202 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is substantially the same (e.g., within 1-2 nm), and the thickness of each of the semiconductor layers 204 may be substantially the same as the thickness of each sacrificial layer 202 (e.g., about 5-20 nm). Each of the sacrificial layer 202 and the semiconductor layer 204 may be deposited using any known or proprietary material deposition technique, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0060] Figure 3A and Figure 3B 1 and 2 respectively depict the process of forming a cap layer 302 and subsequently forming a fin under the cap layer 302 according to an embodiment. Figure 2A and Figure 2B . The cap layer 302 may be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The cap layer 302 is patterned into rows to form corresponding rows of fins from the alternating layer stack of sacrificial layer 202 and semiconductor layer 204. The rows of fins extend longitudinally along a first direction (e.g., into and out of the page of each cross-sectional view).

[0061] In accordance with some embodiments, the anisotropic etching process through the layer stack continues into at least a portion of the substrate 102, wherein the unetched portion of the substrate 102 located below the fin forms a sub-fin region 304. The etched portion of the substrate 102 may be filled with a dielectric filler 306, which acts as a shallow trench isolation (STI) between adjacent fins. The dielectric filler 306 may be any suitable dielectric material (e.g., silicon dioxide) and may be recessed to the desired depth shown (in this exemplary case, recessed down to around the upper surface of the sub-fin region 304) to define the active portion of the fin that will be covered by the gate structure. In some embodiments, the dielectric filler 306 is recessed below the top surface of the sub-fin region 304.

[0062] Figure 4A and Figure 4B 4 and 4, respectively, depicting a sacrificial gate 402 extending across the fin in a second direction different from the first direction after forming the sacrificial gate 402 according to some embodiments. Figure 3A and Figure 3B . A sacrificial gate 402 may extend across the fin in a second direction orthogonal to the first direction. According to some embodiments, the sacrificial gate material is formed in parallel strips across the integrated circuit and is removed in all areas not protected by the gate mask layer. The sacrificial gate 402 may be any suitable material that may be selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gate 402 includes polysilicon.

[0063] As can be seen in the cross-sectional view, the sacrificial gate 402 is Figure 4A The gate trench cross section in FIG. 1 extends across the fin, but along Figure 4B There is no sacrificial gate 402 in the source / drain trench cross section. Figure 4B As seen in , sacrificial gate 402 (along with any gate spacers formed on the sidewalls of sacrificial gate 402) protects the underlying portion of the fin, while the exposed portion of the fin is etched away. According to some embodiments, both semiconductor layer 204 and sacrificial layer 202 are etched at substantially the same rate using an anisotropic RIE process. Figure 4B, above the sub-fin region 304, the fin is completely removed. In some embodiments, the RIE process may also etch into the sub-fin region 304, recessing the sub-fin region 304 below the top surface of the dielectric filler 306. In some embodiments, the internal gate spacer may be formed after etching the source / drain trenches and before any formation of the source or drain regions. For example, selective etching may be used to recess the sacrificial layer 202 laterally, and then, the recess may be filled with an internal gate spacer material (e.g., silicon nitride or silicon oxynitride). Any excess gate spacer material may be removed using directional etching.

[0064] Figure 5A and Figure 5B Depicted are the formation of source or drain regions 502a / 502b / 502c (extending into and out of) at the ends of each of the fins, respectively, in accordance with some embodiments. Figure 5A After the page in Figure 4A and Figure 4B . According to some embodiments, the source or drain regions 502a / 502b / 502c may be epitaxially grown from the exposed ends of the semiconductor layers 204 such that the materials grow together or otherwise merge toward the middle of the trenches between the fins. Note that the epitaxial growth on one semiconductor layer 204 may be fully or partially merged with the epitaxial growth on one or more other semiconductor layers 204 in the same vertical stack. The extent of any such merging may be different from one embodiment to the next. In the example of a PMOS device, a given source or drain region may be a semiconductor material (e.g., a Group IV or Group III-V semiconductor material) having a higher dopant concentration of a p-type dopant (compared to an n-type dopant). In the example of an NMOS device, a given source or drain region may be a semiconductor material (e.g., a Group IV or Group III-V semiconductor material) having a higher dopant concentration of an n-type dopant (compared to a p-type dopant). According to some embodiments, as Figure 5B As shown in , source or drain regions 502a / 502b / 502c grown from different semiconductor devices may be aligned along the source / drain trenches in the second direction.

[0065] According to some embodiments, a bottom dielectric layer 504 may be deposited before forming the source or drain region 502a / 502b / 502c. The bottom dielectric layer 504 may be any suitable dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. The bottom dielectric layer 504 may be included to provide isolation between the source or drain region 502a / 502b / 502c and the sub-fin region 304.

[0066] According to some embodiments, another dielectric filler 506 is provided along the source / drain trench. According to some embodiments, the dielectric filler 506 may extend between adjacent source or drain regions in the source or drain regions 502a / 502b / 502c along the second direction, and may also extend upward and over each source or drain region in the source or drain regions 502a / 502b / 502c. Thus, each source or drain region may be isolated from any adjacent source or drain region by the dielectric filler 506. The dielectric filler 506 may be any suitable dielectric material, but in some embodiments, the dielectric filler 506 includes the same dielectric material as the dielectric filler 306 or the bottom dielectric layer 504. In one example, each of the dielectric filler 506, the bottom dielectric layer 504, and the dielectric filler 306 includes silicon dioxide. In the case where it is desired that adjacent source or drain regions are electrically coupled together, there may be no dielectric filler 506 between some adjacent source or drain regions. According to some embodiments, the top surface of the dielectric filler 506 may be polished using, for example, chemical mechanical polishing (CMP). The top surface of the dielectric filler 506 may be polished until it is substantially coplanar with the top surface of the sacrificial gate 402.

[0067] Fig. 6A and Figure 6B 2 and 3 respectively depict the nanoribbons 602a / 602b / 602c after forming the nanoribbons 602a / 602b / 602c from the semiconductor layer 204 according to some embodiments. Figure 5A and Figure 5B . A cross-sectional view of the structure shown in . Depending on the size of the structure, the nanoribbons 602a / 602b / 602c may also be considered as nanowires or nanosheets. The sacrificial gate 402 may be removed using any wet or dry isotropic process, thereby exposing the alternating layer stack of fins within the trench left after the sacrificial gate 402 is removed. Once the sacrificial gate 402 is removed, the sacrificial layer 202 may also be removed using a selective isotropic etching process that removes the material of the sacrificial layer 202, but does not remove (or removes very little) the semiconductor layer 204 or any other exposed layers (e.g., internal gate spacers). At this point, the floating (sometimes referred to as released) semiconductor layer 204 forms nanoribbons 602a / 602b / 602c that extend in a first direction (in and out of the page) between the corresponding source or drain regions 502a / 502b / 502c.

[0068] Fig. 7A and Figure 7B 602a / 602b / 602c in the gate trenches after forming a gate structure around the nanoribbons 602a / 602b / 602c, respectively, according to some embodiments. Fig. 6A and Figure 6B . As described above, the gate structure includes a gate dielectric 702 and a gate electrode 704. The gate dielectric 702 can be conformally deposited around the nanoribbons 602a / 602b / 602c using any suitable deposition process (e.g., atomic layer deposition (ALD)). The gate dielectric 702 may include any suitable dielectric (e.g., silicon dioxide and / or a high-k dielectric material). For example, examples of high-k dielectric materials include hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to name a few. According to some embodiments, the gate dielectric 702 is hafnium oxide having a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric 702 may include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some examples, the gate dielectric 702 may be a multilayer structure. For example, the gate dielectric 702 may include a first layer located on the nanoribbons 602a / 602b / 602c, and a second layer located on the first layer. For example, the first layer may be an oxide of a semiconductor layer (e.g., silicon dioxide), and the second layer may be a high-k dielectric material (e.g., hafnium oxide). In some embodiments, when a high-k dielectric material is used, an annealing process may be performed on the gate dielectric 702 to improve its quality. In some embodiments, the high-k material may be nitrided to improve its aging resistance.

[0069] The gate electrode 704 can be deposited on the gate dielectric 702 and can be any conductive structure. In some embodiments, the gate electrode 704 includes doped polysilicon, a metal or a metal alloy. Exemplary suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides. For example, the gate electrode 704 can include one or more work function layers, resistance reduction layers and / or barrier layers. For example, the work function layer can include a p-type work function material (e.g., titanium nitride) for a PMOS gate or an n-type work function material (e.g., titanium aluminum carbide) for an NMOS gate.

[0070] According to some embodiments, the gate cap 706 may be formed by first recessing the gate electrode 704 and filling the recess with a dielectric material. The dielectric material may then be polished so that its top surface is substantially coplanar with any adjacent spacer structures or materials within the source / drain trenches. The gate cap 706 may be any suitable dielectric material, such as silicon nitride.

[0071] According to some embodiments, a portion of the dielectric fill 506 may be recessed within the source / drain trench to expose at least the top surface of the source or drain region 502a / 502b / 502c. A conductive contact 708 may be formed within the recess to contact at least the top surface of the source or drain region 502a / 502b / 502c. In some embodiments, the dielectric fill 506 is recessed sufficiently deep to expose one or more side surfaces of the source or drain region 502a / 502b / 502c, in which case the conductive contact 708 also contacts the exposed side surfaces of the source or drain region 502a / 502b / 502c. The conductive contact 708 may include any suitable conductive material (e.g., tungsten, cobalt, molybdenum, or ruthenium) for electrically contacting the underlying source or drain region 502a / 502b / 502c. The top surface of the conductive contact 708 may be polished to be substantially coplanar with the top surface of the gate cap 706. It should be appreciated that the conductive contact 708 may include any number of conductive layers (e.g., silicide layers or other similar resistance reducing layers) to provide better ohmic contact with the source or drain regions.

[0072] Fig. 8A and Figure 8B 802 extending along the first direction after forming a dielectric wall 802 between some adjacent devices according to some embodiments. Fig. 7A and Figure 7B . The dielectric wall 802 extends to a depth of at least through the entire thickness of the gate structure to isolate the separated gate structures along the second direction. In some embodiments, the dielectric wall 802 extends into at least a portion of the dielectric filler 306, or extends through the entire thickness of the dielectric filler 306. In some embodiments, the dielectric wall 802 extends completely through the dielectric filler 306 and extends into a portion of the substrate 102.

[0073] According to some embodiments, the dielectric wall 802 may be formed by first forming a corresponding gate cut recess through the gate cap 706, the contact 708, and the gate electrode 704 using any suitable metal gate etching process, which repeatedly etches through the portion of the gate electrode 704 while protecting the sidewalls of the recess from lateral etching, thereby providing a high aspect ratio recess (e.g., an aspect ratio of 5:1 or higher, or 10:1 or higher). The gate cut recess may extend through a plurality of gate trenches and source / drain trenches in a first direction to isolate adjacent gate structures from source or drain regions. The gate cut recess may be filled with one or more dielectric materials to form the dielectric wall 802. For example, the dielectric wall 802 may include only silicon dioxide or silicon nitride or silicon carbide. In some examples, the dielectric wall 802 includes a first dielectric layer deposited first and a second dielectric layer or dielectric filler formed on the first dielectric layer. The first dielectric layer may include a high-k dielectric material (e.g., a material having a dielectric constant higher than silicon dioxide or a dielectric constant higher than 3.9), while the second dielectric layer may include a low-k dielectric material (e.g., a material having a dielectric constant lower than silicon dioxide (e.g., porous silicon dioxide) or a dielectric constant lower than 3.9). In the example shown, a given dielectric wall 802 extends between nanoribbon 602a and nanoribbon 602b, and also extends between source or drain region 502a and source or drain region 502b. In some examples where the devices are closely arranged, dielectric wall 802 may contact one or more sidewalls of source or drain region 502a / 502b / 502c.

[0074] Fig. 9A and Fig. 9B The following diagrams respectively depict the steps after forming the via structure 901 according to some embodiments. Fig. 8A and Figure 8B The via structure 901 may extend to a depth that at least passes through the entire thickness of the gate structure. In some embodiments, the via structure 901 extends through the entire thickness of the dielectric filler 306.

[0075] Similar to the formation of the dielectric wall 802, the via structure 901 can be formed by first forming a corresponding via recess through the gate cap 706, the contact 708, and the gate electrode 704 using any suitable metal gate etching process that repeatedly etches through a portion of the gate electrode 704 while protecting the sidewalls of the recess from lateral etching. In some embodiments, the widest dimension of the via recess along the second direction (e.g., at the top of the via recess) is between about 20 nm and about 30 nm, so that the resulting via structure 901 has a widest dimension between about 20 nm and about 30 nm. The via recess can generally be wider along the second direction than the recess used to form the dielectric wall 802, and therefore can have a lower aspect ratio. In some examples, the via recess has an aspect ratio of about 4:1 to about 8:1.

[0076] According to some embodiments, once the via recess has been formed, a dielectric liner 902 is formed along at least the sidewalls of the recess (and may also be formed on the bottom of the recess). The dielectric liner 902 may be conformally deposited using an appropriate deposition technique (e.g., ALD, CVD, or PECVD). The dielectric liner 902 may be any appropriate dielectric material. In some examples, the dielectric liner 902 includes a dielectric material (e.g., silicon nitride, tin nitride, or tin oxide) or a low-k dielectric (e.g., porous silicon dioxide), to name a few. The dielectric liner 902 may be deposited within the via recess to a final thickness between about 2 nm and about 5 nm. The dielectric liner 902 may represent any number of deposited dielectric layers. In some examples, a first dielectric liner directly on the gate electrode 704 includes a high-k dielectric material, and a second dielectric liner on the first dielectric liner includes a low-k dielectric material.

[0077] According to some embodiments, a conductive via 904 is formed within the remaining volume of the via recess and on the dielectric liner 902. The conductive via 904 may include any suitable conductive material, such as tungsten, molybdenum, ruthenium, cobalt, or any alloy thereof. As described above, the conductive via 904 extends at least below the bottom surface of the gate structure and may also extend below the bottom surface of the dielectric filler 306. According to some embodiments, the conductive via 904 acts as a power line or a signal line between the topside interconnect and the backside interconnect on the die.

[0078] Fig. 10A and Fig. 10B and 904 respectively depict the conductive vias 904 after being recessed between the dielectric liner layers 902 according to some embodiments. Fig. 9A and Fig. 9B. The conductive via 904 may be recessed using any suitable metal etching process while protecting other metal elements (e.g., contact 708) using a hard mask layer or a photoresist layer. According to some embodiments, the conductive via 904 is recessed so that its top surface is lower than the top surface of the contact 708 and / or lower than the top surface of the gate electrode 704. In some examples, the top surface of the conductive via 904 is lower than the top surface of the adjacent source or drain region 502a / 502b / 502c.

[0079] Fig.11A and Fig. 11B 1 and 10 respectively depict the dielectric plug 1102 after being formed on the top surface of the conductive via 904 according to some embodiments. Fig. 10A and Fig. 10B . The dielectric plug 1102 may be any suitable dielectric material, such as silicon dioxide, silicon nitride, silicon oxycarbide, or silicon oxycarbon nitride. In some examples, the dielectric plug 1102 is the same dielectric material as the dielectric liner 902. The dielectric plug 1102 may substantially fill the cavity left after recessing the conductive via 904. The top surface of the dielectric plug 1102 may be polished to be substantially coplanar with the top surface of the dielectric cap layer 706.

[0080] Fig. 12A and Fig. 12B 1 and 12 respectively depict the first recess 1202 formed between the conductive via 904 and the adjacent contact 708 and the second recess 1204 formed between two adjacent contacts according to some embodiments. Fig.11A and Fig. 11B . A first recess 1202 may be formed through a portion of the dielectric liner 902 and a portion of the dielectric plug 1102 to expose at least a portion of the top surface 1206 of the conductive via 904. In some embodiments, the top portion of the dielectric liner 902 is completely removed so that at least a portion of the sidewall of the adjacent contact 708 is exposed, and a portion of the sidewall of the conductive via 904 may also be exposed. In some such cases, a portion of the dielectric plug 1102 remains (as shown), and in other cases, the dielectric plug 1102 is also completely or largely removed. Portions of the dielectric liner 902 and the plug 1102 adjacent to the gate electrode 704 remain intact (e.g., by way of a patterned mask layer). Any suitable anisotropic dielectric etching process may be used to remove portions of both the dielectric liner 902 and the dielectric plug 1102. In some examples, removal of a portion of the dielectric liner 902 exposes at least a portion of the adjacent source or drain region 502b. In this example, the portion of the dielectric liner 902 adjacent to the gate electrode 704 (eg, Fig. 12A) has a portion of the liner 902 adjacent to the source or drain region 502b (as shown Fig. 12B As shown in FIG. 1 , the top surface of the substrate is higher (eg, 2 to 4 nanometers, or higher). Fig. 12B As further shown in the example of , the portion of the dielectric liner 902 adjacent to the source or drain region 502b has a top surface that is lower (e.g., 1 to 2 nanometers, or lower) than the top surface 1206 of the conductive via 904. Such a structure allows the conductive bridge provided later to stably contact both the contact portion 708 and the via 904.

[0081] According to some embodiments, the second recess 1204 can be formed between adjacent contacts. In the example shown, the second recess 1204 is formed by removing portions of the dielectric wall 802 located between adjacent contacts 708 above the source or drain region 502a and the source or drain region 502b. The same mask layer or mask material can be used to expose various dielectric materials along the source / drain trenches so that the first recess 1202 and the second recess 1204 are formed simultaneously using the same etching process. Note that only the dielectric material within the source / drain trenches is exposed, while the mask layer protects the top side dielectric material within the gate trenches. The second recess 1204 can have a similar depth to the first recess 1202. According to some embodiments, any number of dielectric walls 802 can have their top portions removed to form recesses between any number of adjacent contacts along a given source / drain trench.

[0082] Fig.13A and Fig. 13B 1 and 12 respectively depict the conductive bridge 1302 formed in the first recess 1202 and the conductive plug 1304 formed in the second recess 1204 according to some embodiments. Fig. 12A and Fig. 12B. A conductive bridge 1302 extends between a conductive via 904 and an adjacent contact 708 and contacts both the conductive via 904 and the adjacent contact 708. According to some embodiments, the conductive bridge 1302 contacts at least a portion of the top surface of the conductive via 904 and at least a portion of the sidewall of the contact 708. The conductive bridge 1302 may also extend below the top surface of the conductive via 904 along one side of the conductive via 904. According to some embodiments, the conductive plug 1304 extends between adjacent contacts 708 along a second direction. Each of the conductive bridge 1302 and the conductive plug 1304 may include any suitable conductive material, such as tungsten, molybdenum, or other metals. In some examples, the conductive bridge 1302 and the conductive plug 1304 include the same conductive material as the contact 708 and / or the conductive via 904. According to some embodiments, the conductive bridge 1302 and the conductive plug 1304 are formed together during the same metal deposition process so that they include the same conductive material.

[0083] The contact 708, the conductive bridge 1302, and the conductive plug 1304 located above the source or drain regions 502a and 502b can together form a single conductive contact that contacts multiple source or drain regions within the device layer. For example, additional adjacent source or drain regions along the same source / drain trench can also be contacted by forming additional conductive plugs across adjacent dielectric walls 802. In some embodiments, depending on the materials used, there may not be any obvious seams or boundaries between any of the contacts 708, the conductive bridge 1302, and the conductive plug 1304. When different materials or deposition processes are used, the seams or boundaries between different conductive elements may be obvious. In some other embodiments, the contact 708 and the conductive bridge 1302 are formed simultaneously, for example in Fig. 12B After the process in Fig. 13B Execute before the process in Figure 7B 904. In some such cases, the monolithic conductive feature including both the conductive contact 708 and the conductive bridge 1302 (which may be more simply collectively referred to as a contact) extends along the second direction to contact at least a portion of the top surface and / or side surface of the conductive via 904. In some such cases, the length of the contacted portion of the side surface of the via 904 is about 2 to 4 nanometers, or longer. Likewise, such a structure or multi-surface topology allows for a robust conductive contact to the via 904.

[0084] Fig.14An exemplary embodiment of a chip package 1400 according to an embodiment of the present disclosure is shown. It can be seen that the chip package 1400 includes one or more dies 1402. The one or more dies 1402 may include at least one integrated circuit having a semiconductor device (e.g., any of the semiconductor devices disclosed herein). In some exemplary configurations, the one or more dies 1402 may include any other circuitry for interfacing with other devices formed on the die or connected to the chip package 1400.

[0085] It can also be seen that the chip package 1400 includes a housing 1404 bonded to a package substrate 1406. The housing 1404 can be any housing and can provide, for example, electromagnetic shielding and environmental protection for the components of the chip package 1400. One or more dies 1402 can be conductively coupled to the package substrate 1406 using connectors 1408, which can be implemented using any number of connection mechanisms, such as solder bumps, ball grid arrays (BGA), pins, or wire bonds, to name a few. The package substrate 1406 can be any package substrate, but in some cases includes a dielectric material having conductive paths (e.g., including conductive vias and conductive lines) extending through the dielectric material between the faces of the package substrate 1406 or between different locations on each face. In some embodiments, the package substrate 1406 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), although any number of package geometries can be used. Additional conductive contacts 1412 may be provided at the opposite side of the package substrate 1406 for conductive contact, such as a printed circuit board (PCB). One or more vias 1410 extend through the thickness of the package substrate 1406 to provide a conductive path between one or more of the connectors 1408 to one or more of the contacts 1412. For ease of illustration, the via 1410 is shown as a single straight column through the package substrate 1406, but other configurations may be used (e.g., inlays, dual inlays, through-silicon vias, or interconnect structures that meander through the thickness of the substrate 1406 to contact one or more intermediate locations therein). In yet other embodiments, the via 1410 is made of multiple smaller stacked vias, or is staggered at different locations across the package substrate 1406. In the illustrated embodiment, the contact 1412 is a solder ball (e.g., for a bump-based connector or ball grid array arrangement), but any suitable package engagement mechanism may be used (e.g., a pin in a pin grid array arrangement or a land in a land grid array arrangement). In some embodiments, solder resist is disposed between the contacts 1412 to inhibit short circuits.

[0086] In some embodiments, molding material 1414 may be disposed around one or more dies 1402 included within housing 1404 (e.g., as an underfill material between die 1402 and package substrate 1406, and as an overfill material between die 1402 and housing 1404). Although the size and quality of molding material 1414 may vary from one embodiment to the next, in some embodiments, the thickness of molding material 1414 is less than 1 millimeter. Exemplary materials that may be used for molding material 1414 include epoxy molding materials, if appropriate. In some cases, molding material 1414, in addition to being electrically insulating, is also thermally conductive.

[0087] Fig.15 is a flow chart of a method 1500 for forming at least a portion of an integrated circuit according to an embodiment. The various operations of the method 1500 may be performed in Figures 2A-13A and Figure 2B-Figure 13B 1500. However, the correlation of various operations of method 1500 with specific components shown in the aforementioned figures is not intended to imply any structural and / or use limitations. Instead, the aforementioned figures provide an exemplary embodiment of method 1500. Other operations may be performed before, during, or after any operation of method 1500. For example, method 1500 does not explicitly describe all processes performed to form a common transistor structure. Some of the operations of method 1500 may be performed in an order different from the order shown.

[0088] According to some embodiments, method 1500 begins at operation 1502, wherein any number of parallel semiconductor fins are formed. The semiconductor material in a given fin may be formed from a substrate such that the fin is an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fin may be formed from a material deposited onto an underlying substrate. In one such exemplary case, a uniform layer of silicon germanium (SiGe) may be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such embodiment, the fin includes alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons during a gate formation process, in which one type of alternating layer is selectively etched away to release another type of alternating layer in the channel region so that a full gate-around (GAA) process may then be performed. The alternating layers may be uniformly deposited and then etched into fins or deposited into fin-shaped trenches. The fin may also include a cap structure thereon for defining the position of the fin during, for example, an RIE process. The cap structure may be a dielectric material, such as silicon nitride.

[0089] According to some embodiments, a dielectric layer is formed around a sub-fin portion of a fin. In some embodiments, the dielectric layer extends between each pair of adjacent parallel fins and extends longitudinally in the same direction as the fins. In some embodiments, the anisotropic etching process that forms the fins also etches into a portion of the substrate, and the dielectric layer can be formed within a recessed portion of the substrate. Thus, the dielectric layer acts as a shallow trench isolation (STI) between adjacent fins. The dielectric layer can be any suitable dielectric material, such as silicon dioxide.

[0090] Method 1500 continues with operation 1504, where a sacrificial gate and a spacer structure are formed over the fin. The sacrificial gate may be patterned using a strip-shaped gate mask layer extending orthogonally over the fin (many gate mask layers and corresponding sacrificial gates may be formed parallel to each other (e.g., forming a cross-hatched pattern with any number of parallel fins)). The gate mask layer may be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate may be formed of any suitable material (which may be selectively removed at a later time without damaging the semiconductor material of the fin). In one example, the sacrificial gate includes polysilicon. The spacer structure may be deposited and then etched back so that a majority of the spacer structure remains only on the sidewalls of any exposed structure. According to some embodiments, the spacer structure may be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

[0091] Method 1500 continues with operation 1506, where a source or drain region is formed at an end of the semiconductor region of the fin. Any portion of the fin not protected by the sacrificial gate and spacer structures may be removed using, for example, an anisotropic etching process followed by epitaxial growth of the source or drain region from the exposed end of the semiconductor layer in the fin. In some exemplary embodiments, the source or drain region is an NMOS source or drain region (e.g., epitaxial silicon) or a PMOS source or drain region (e.g., epitaxial SiGe).

[0092] According to some embodiments, a dielectric filler is formed over the source or drain region. The dielectric filler may be formed adjacent to the respective source or drain region for additional electrical isolation between adjacent regions. The dielectric filler may also extend over the top surface of the source or drain region. According to some embodiments, the dielectric filler may occupy any remaining space along the source / drain trench. The dielectric filler may include any suitable dielectric material, such as silicon dioxide or silicon oxynitride.

[0093] Method 1500 continues with operation 1508, wherein a gate structure is used to replace the sacrificial gate. According to some embodiments, the sacrificial gate may be removed together with any sacrificial layer within the exposed fin between the spacer structures (in the case of a GAA structure). A gate structure may then be formed to replace the sacrificial gate. The gate structure may include both a gate dielectric and a gate electrode. According to some embodiments, the gate dielectric is first formed over the exposed semiconductor region between the spacer structures, followed by forming a gate electrode within the remainder of the trench between the spacer structures. The gate dielectric may include any number of dielectric layers deposited using a CVD process (e.g., ALD). The gate electrode may include any conductive material, such as a metal, a metal alloy, or polysilicon. The gate electrode may be deposited using electroplating, electroless plating, CVD, ALD, PECVD, or PVD (to name a few).

[0094] The method 1500 continues with operation 1510, where a contact is formed over one of the source or drain regions. In some embodiments, the contact may include any suitable conductive material, such as tungsten, molybdenum, ruthenium, or cobalt. The contact may represent any number of different conductive materials that may be deposited to form a conductive connection to an underlying source or drain region.

[0095] The method 1500 continues with operation 1512, wherein a deep recess is formed adjacent to the source or drain region and also adjacent to the semiconductor region in the gate trench. Thus, the recess can be a trench extending through any number of gate trenches and source / drain trenches in a first direction. The recess can also be deep enough to pass through the entire thickness of the gate structure and the entire thickness of the dielectric layer located below the gate structure. A reactive ion etching (RIE) process can be used to cut through various material layers and form a trench-shaped recess.

[0096] The method 1500 continues with operation 1514, where a dielectric liner is formed within the recess and subsequently a conductive via is formed within the recess. The dielectric liner may be conformally deposited using any suitable technique (e.g., CVD or ALD) to cover at least the sidewalls of the recess. The dielectric liner may include a dielectric material such as silicon nitride, tin nitride, tin oxide, or a low-k dielectric (a porous version of any of these materials, or other dielectric materials), to name a few. The dielectric liner may be deposited within the via recess to a final thickness of between about 2 nm and about 5 nm. The dielectric liner may represent any number of deposited dielectric layers.

[0097] According to some embodiments, the conductive via is formed in the remaining volume of the via recess and on the dielectric liner. There may be some voids in the conductive via. The conductive via may include any suitable conductive material, such as tungsten, molybdenum, ruthenium, cobalt or any alloy thereof.

[0098] Method 1500 continues with operation 1516, wherein the conductive via is recessed so that the top surface of the conductive via is lowered below the top surface of the adjacent contact portion. In some examples, the top surface of the conductive via is lowered below the top surface of the adjacent source or drain region. Any suitable metal etching process can be used to remove the top portion of the conductive via. The recessing of the conductive via leaves a cavity between the dielectric liner from which the portion of the conductive via is removed. The cavity can be filled or substantially filled (e.g., including a gap) with a dielectric plug. The dielectric plug can be any suitable dielectric material, such as silicon dioxide, silicon nitride, silicon oxycarbide, or silicon oxynitride and carbonitride. In some examples, the dielectric plug is the same dielectric material as the dielectric liner. The top surface of the dielectric plug can be polished to be substantially coplanar with the top surface of the dielectric liner.

[0099] The method 1500 continues with operation 1518, wherein at least a portion of both the dielectric liner and the dielectric plug are recessed to expose at least a portion of the top surface of the conductive via. An anisotropic etching process may be used to form a recess in the dielectric material through the dielectric liner and the dielectric plug. According to some embodiments, the recess has a depth that exposes a portion of the top surface of the conductive via and a portion of one of the sidewalls. According to some embodiments, due to the removal of the top portion of the dielectric liner, the recess also exposes a sidewall portion of the contact. In this way, a portion of the dielectric liner adjacent to the source or drain region may have a top surface that is lower (e.g., 1 to 2 nanometers, or lower) than the top surface of the conductive via, and a portion of the liner adjacent to the gate electrode has a top surface that is higher (e.g., 2 to 4 nanometers, or higher) than the top surface of the portion of the liner adjacent to the source or drain region. As described above, such a topological structure allows the conductive bridge formed at 1520 to firmly contact both the contact 708 and the via 904.

[0100] The method 1500 continues with operation 1520, wherein a conductive bridge is formed within the recess. The conductive bridge may be tungsten or any other suitable metal, such as ruthenium, cobalt, molybdenum, or any alloy thereof. According to some embodiments, the top surface of the conductive bridge is polished using, for example, CMP until it is substantially coplanar with the top surface of the contact in the source / drain trench. According to some embodiments, the conductive bridge contacts at least a portion of the top surface of the conductive via and at least a portion of the sidewall of the contact. The conductive bridge may also extend below the top surface of the conductive via along one side of the conductive via. The conductive bridge functions similarly to the interconnection between the contact and the conductive via, but is formed in a device layer below the interconnection region, thereby freeing up more space for other metal layers in the interconnection region.

[0101] Exemplary Systems

[0102] Fig.16 1600 is an exemplary computing system implemented using one or more of the integrated circuit structures disclosed herein according to some embodiments of the present disclosure. It can be seen that the computing system 1600 accommodates a motherboard 1602. The motherboard 1602 may include a plurality of components, including but not limited to a processor 1604 and at least one communication chip 1606, each of which may be physically and electrically coupled to the motherboard 1602, or otherwise integrated therein. It will be understood that the motherboard 1602 may be, for example, any printed circuit board (PCB), whether a motherboard, a daughterboard mounted on a motherboard, or the only board of the system 1600, etc.

[0103] Depending on its application, the computing system 1600 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1602. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), etc.). Any of the components included in the computing system 1600 may include one or more integrated circuit structures or devices configured according to exemplary embodiments (e.g., a module including an integrated circuit on a substrate having a semiconductor device including a recessed via connected to an adjacent source or drain contact). In some embodiments, various functions may be integrated into one or more chips (e.g., note that the communication chip 1606 may be part of the processor 1604 or otherwise integrated into the processor 1604).

[0104] The communication chip 1606 implements wireless communications for transmitting data to and from the computing system 1600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments, they may not contain wires. The communication chip 1606 may implement any of a variety of wireless standards or protocols, including but not limited to: Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. The computing system 1600 may include multiple communication chips 1606. For example, the first communication chip 1606 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, while the second communication chip 1606 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0105] The processor 1604 of the computing system 1600 includes an integrated circuit die packaged within the processor 1604. In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented using one or more semiconductor devices as described in various ways herein. The term "processor" may refer to any device or portion of a device that processes electronic data, for example, from registers and / or memory, thereby transforming the electronic data into other electronic data that may be stored in registers and / or memory.

[0106] The communication chip 1606 may also include an integrated circuit die packaged within the communication chip 1606. According to some such exemplary embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as described in various ways herein. It will be understood in accordance with the present disclosure that it is noted that multi-standard wireless capabilities can be integrated directly into the processor 1604 (e.g., where the functionality of any chip 1606 is integrated into the processor 1604, rather than having a separate communication chip). It is also noted that the processor 1604 can be a chipset with such wireless capabilities. In short, any number of processors 1604 and / or communication chips 1606 can be used. Similarly, any one chip or chipset can have multiple functions integrated therein.

[0107] In various embodiments, as variously described herein, computing system 1600 may be a laptop, a netbook, a notebook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques.

[0108] It will be appreciated that in some embodiments, the various components of computing system 1600 may be combined or integrated in a system-on-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0109] Other Exemplary Embodiments

[0110] The following examples relate to other embodiments from which numerous arrangements and configurations will be apparent.

[0111] Example 1 is an integrated circuit, which includes: a semiconductor region extending from a source or drain region in a first direction; a gate electrode extending above the semiconductor region and in a second direction different from the first direction; a contact portion located on a top surface of the source or drain region; a conductive via extending adjacent to the semiconductor region in the first direction, extending adjacent to the source or drain region in the first direction, and extending through a portion of the gate electrode in a third direction; and a conductive bridge located between the contact portion and the conductive via. The top surface of the conductive via is lower than the top surface of the contact portion. The conductive bridge extends from a sidewall of the contact portion and is located on at least a portion of the top surface of the conductive via.

[0112] Example 2 includes an integrated circuit according to Example 1, further comprising a liner extending in a first direction such that the liner is located between the conductive via and the gate electrode and is also located between the source or drain region and the conductive via. A portion of the liner adjacent to the source or drain region has a top surface that is at least 2 nanometers lower than a top surface of the conductive via.

[0113] Example 3 includes the integrated circuit of Example 2, wherein a portion of the liner adjacent to the gate electrode has a top surface that is at least 4 nanometers higher than a top surface of a portion of the liner adjacent to the source or drain region.

[0114] Example 4 includes the integrated circuit of Example 2 or 3, wherein the conductive via plus the liner has a maximum width along the second direction between about 20 nm and about 30 nm.

[0115] Example 5 includes the integrated circuit of any of Examples 1-4, wherein the semiconductor region includes a plurality of semiconductor nanoribbons.

[0116] Example 6 includes the integrated circuit of Example 5, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0117] Example 7 includes the integrated circuit of any of Examples 1-6, wherein the conductive via comprises tungsten, cobalt, molybdenum, or ruthenium.

[0118] Example 8 includes the integrated circuit of any of Examples 1-7, wherein the conductive bridge includes tungsten, cobalt, molybdenum, or ruthenium.

[0119] Example 9 includes the integrated circuit of any of Examples 1-8, wherein the conductive bridge and the conductive via include the same conductive material.

[0120] Example 10 includes the integrated circuit of any of Examples 1-9, further comprising a dielectric cap over a top surface of the conductive via, wherein a top surface of the dielectric cap is substantially coplanar with a top surface of the contact.

[0121] Example 11 includes the integrated circuit of any of Examples 1-10, wherein a top surface of the conductive via is lower than a top surface of the source or drain region.

[0122] Example 12 includes the integrated circuit of any of Examples 1-11, wherein a top surface of the conductive bridge is substantially coplanar with a top surface of the contact.

[0123] Example 13 includes an integrated circuit according to any of Examples 1-12, wherein the source or drain region is a first source or drain region, the contact is a first contact, and the conductive bridge is a first conductive bridge, and the integrated circuit further includes: a second source or drain region, the second source or drain region being adjacent to the first source or drain region along a second direction; a dielectric wall, the dielectric wall extending along the first direction between the first source or drain region and the second source or drain region; a second contact, the second contact being located on a top surface of the second source or drain region; and a second conductive bridge, the second conductive bridge being connected between the first contact and the second contact and being located above the dielectric wall. A top surface of the second conductive bridge is substantially coplanar with a top surface of the first contact and a top surface of the second contact.

[0124] Example 14 includes the integrated circuit of any of Examples 1-13, wherein the first direction is orthogonal to the second direction, and the third direction is orthogonal to the first direction and the second direction.

[0125] Example 15 includes the integrated circuit of any of Examples 1-14, further comprising a dielectric layer beneath the gate electrode, wherein the conductive via extends through an entire thickness of the dielectric layer in the third direction.

[0126] Example 16 is a printed circuit board comprising the integrated circuit according to any one of Examples 1-15.

[0127] Example 17 is an electronic device including a chip package having one or more dies. At least one of the one or more dies includes: a semiconductor region extending from a source or drain region in a first direction; a gate electrode extending above the semiconductor region and in a second direction different from the first direction; a dielectric layer located below the gate electrode; a contact located on a top surface of the source or drain region; a conductive via extending adjacent to the semiconductor region in the first direction, extending adjacent to the source or drain region in the first direction, and extending through a portion of the gate electrode and through the entire thickness of the dielectric layer in a third direction; and a conductive bridge located between the contact and the conductive via. The top surface of the conductive via is lower than the top surface of the contact. The conductive bridge abuts a portion of the contact and is located on at least a portion of the top surface of the conductive via.

[0128] Example 18 includes the electronic device of Example 17, wherein at least one of the one or more dies further includes a liner between the conductive via and the gate electrode.

[0129] Example 19 includes the electronic device of Example 18, wherein the liner includes a low-k dielectric material.

[0130] Example 20 includes the electronic device of Example 18 or 19, wherein the conductive via plus the liner has a maximum width along the second direction between about 20 nm and about 30 nm.

[0131] Example 21 includes an electronic device according to any of Examples 17-20, wherein the semiconductor region includes a plurality of semiconductor nanoribbons.

[0132] Example 22 includes an electronic device according to Example 21, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0133] Example 23 includes the electronic device of any of Examples 17-22, wherein the conductive via includes tungsten, cobalt, molybdenum, or ruthenium.

[0134] Example 24 includes the electronic device of any of Examples 17-23, wherein the conductive bridge includes tungsten, cobalt, molybdenum, or ruthenium.

[0135] Example 25 includes the electronic device of any of Examples 17-24, wherein the conductive bridge and the conductive via include the same conductive material.

[0136] Example 26 includes an electronic device according to any of Examples 17-25, wherein at least one of the one or more dies further includes a dielectric cap located over a top surface of the conductive via. The top surface of the dielectric cap is substantially coplanar with a top surface of the contact.

[0137] Example 27 includes the electronic device of any of Examples 17-26, wherein a top surface of the conductive via is lower than a top surface of the source or drain region.

[0138] Example 28 includes the electronic device of any of Examples 17-27, wherein a top surface of the conductive bridge is substantially coplanar with a top surface of the contact.

[0139] Example 29 includes an electronic device according to any one of Examples 17-28, wherein the source or drain region is a first source or drain region, the contact is a first contact, and the conductive bridge is a first conductive bridge. At least one of the one or more dies further includes: a second source or drain region, the second source or drain region being adjacent to the first source or drain region along a second direction; a dielectric wall, the dielectric wall extending along the first direction between the first source or drain region and the second source or drain region; a second contact, the second contact being located on a top surface of the second source or drain region; and a second conductive bridge, the second conductive bridge being connected between the first contact and the second contact and being located above the dielectric wall. The top surface of the second conductive bridge is substantially coplanar with the top surface of the first contact and the top surface of the second contact.

[0140] Example 30 includes an electronic device according to any of Examples 17-29, wherein the first direction is orthogonal to the second direction, and the third direction is orthogonal to the first direction and the second direction.

[0141] Example 31 includes the electronic device of any of Examples 17-30, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.

[0142] Example 32 is a method of forming an integrated circuit. The method includes: forming a fin including a semiconductor material, the fin extending above a substrate and extending in a first direction; forming a gate electrode, the gate electrode extending in a second direction different from the first direction over the fin; forming a source or drain region at an end of the fin; forming a contact over the source or drain region; forming a recess through the gate electrode adjacent to the fin, the recess extending through the gate electrode in the first direction and adjacent to the source or drain region; forming a dielectric material in the recess; forming a conductive via in the recess, the conductive via extending in the first direction; The method further comprises: extending the dielectric material between the conductive via and the gate electrode, so that the dielectric material is located between the conductive via and the contact portion; recessing the conductive via so that the top surface of the conductive via is lower than the top surface of the contact portion; forming a dielectric cap over the top surface of the recessed conductive via; recessing a portion of the dielectric material between the dielectric cap and the contact portion, and recessing at least a portion of the dielectric cap so that at least a portion of the top surface of the conductive via is exposed; and forming a conductive bridge over at least a portion of the top surface of the conductive via, the conductive bridge abutting the contact portion.

[0143] Example 33 includes the method of Example 32, further comprising: forming a gate dielectric layer around the semiconductor material before forming the gate electrode.

[0144] Example 34 includes the method of Example 32 or 33, wherein forming the dielectric material includes forming a dielectric liner along a sidewall of the recess.

[0145] Example 35 includes the method of Example 34, wherein forming the conductive via comprises forming a conductive material on the dielectric liner within a remaining volume of the recess.

[0146] Example 36 includes the method of any of Examples 32-35, wherein forming the dielectric material includes filling the volume within the recess with the dielectric material.

[0147] Example 37 includes the method of Example 36, wherein forming the conductive via comprises forming the conductive via through a thickness of the dielectric material within the recess.

[0148] Example 38 includes the method of any of Examples 32-37, wherein recessing the conductive via includes recessing the conductive via such that a top surface of the conductive via is lower than a top surface of the source or drain region.

[0149] Example 39 is an integrated circuit comprising: a semiconductor region extending from a source or drain region in a first direction; a gate electrode extending above the semiconductor region and in a second direction different from the first direction; a dielectric layer located below the gate electrode; a conductive via extending adjacent to the semiconductor region in the first direction, extending adjacent to the source or drain region in the first direction, and extending through a portion of the gate electrode and through the entire thickness of the dielectric layer in a third direction; and a conductive contact located on a top surface of the source or drain region. The top surface of the conductive via is lower than the top surface of the gate electrode. The conductive contact extends in the second direction to contact at least a portion of the top surface of the conductive via.

[0150] Example 40 includes the integrated circuit of Example 39, further comprising a liner layer between the conductive via and the gate electrode.

[0151] Example 41 includes the integrated circuit of Example 40, wherein the liner includes a low-k dielectric material.

[0152] Example 42 includes the integrated circuit of Example 40 or 41, wherein the conductive via plus the liner has a maximum width along the second direction between about 20 nm and about 30 nm.

[0153] Example 43 includes an integrated circuit according to any of Examples 39-42, wherein the semiconductor region includes a plurality of semiconductor nanoribbons.

[0154] Example 44 includes the integrated circuit of Example 43, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0155] Example 45 includes the integrated circuit of any of Examples 39-44, wherein the conductive via comprises tungsten, cobalt, molybdenum, or ruthenium.

[0156] Example 46 includes the integrated circuit of any of Examples 39-45, wherein the conductive contact includes tungsten, cobalt, molybdenum, or ruthenium.

[0157] Example 47 includes an integrated circuit according to any of Examples 39-46, further comprising a dielectric cap over a top surface of the conductive via, wherein a top surface of the dielectric cap is substantially coplanar with a top surface of the contact.

[0158] Example 48 includes the integrated circuit of any of Examples 39-47, wherein a top surface of the conductive via is lower than a top surface of the source or drain region.

[0159] Example 49 includes the integrated circuit of any of Examples 39-48, wherein the conductive contact extends along the second direction to contact at least a portion of a side surface of the conductive via.

[0160] Example 50 includes an integrated circuit according to any of Examples 39-49, wherein the source or drain region is a first source or drain region, and the integrated circuit further includes: a second source or drain region, the second source or drain region being adjacent to the first source or drain region along the second direction; and a dielectric wall extending along the first direction between the first source or drain region and the second source or drain region. The conductive contact also extends along the second direction over the dielectric wall and on at least a portion of a top surface of the second source or drain region.

[0161] Example 51 includes the integrated circuit of any of Examples 39-50, wherein the first direction is orthogonal to the second direction, and the third direction is orthogonal to the first direction and the second direction.

[0162] Example 52 is a printed circuit board comprising an integrated circuit according to any of Examples 39-51.

[0163] The foregoing description of the embodiments of the present disclosure has been presented for the purpose of illustration and description. The description is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Many modifications and variations are possible in accordance with the present disclosure. It is intended that the scope of the present disclosure is not limited by this specific embodiment, but by the appended claims.

Claims

1. An integrated circuit, comprising: a semiconductor region extending from a source or drain region along a first direction; a gate electrode extending above the semiconductor region in a second direction, the second direction being different from the first direction; a contact portion, the contact portion being located on a top surface of the source or drain region; a conductive via extending adjacent to the semiconductor region along the first direction, extending adjacent to the source or drain region along the first direction, and extending through a portion of the gate electrode along a third direction, wherein a top surface of the conductive via is lower than a top surface of the contact; and A conductive bridge is located between the contact portion and the conductive via, wherein the conductive bridge extends from a sidewall of the contact portion and is located on at least a portion of the top surface of the conductive via.

2. The integrated circuit according to claim 1, further comprising a liner extending along the first direction so that the liner is located between the conductive via and the gate electrode and also between the source or drain region and the conductive via, wherein A portion of the liner layer adjacent to the source or drain region has a top surface that is at least 2 nanometers lower than the top surface of the conductive via.

3. The integrated circuit according to claim 2, wherein: A portion of the liner layer adjacent to the gate electrode has a top surface that is at least 4 nanometers higher than the top surface of the portion of the liner layer adjacent to the source or drain region.

4. The integrated circuit according to claim 2, wherein: The conductive via plus the liner has a maximum width along the second direction between about 20 nm and about 30 nm.

5. The integrated circuit according to claim 1, wherein: The semiconductor region includes a plurality of semiconductor nanoribbons.

6. The integrated circuit according to claim 5, wherein: The plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

7. The integrated circuit according to claim 1, wherein: The conductive via includes tungsten, cobalt, molybdenum or ruthenium.

8. The integrated circuit of claim 1, wherein: The conductive bridge includes tungsten, cobalt, molybdenum or ruthenium.

9. The integrated circuit of claim 1, wherein: The conductive bridge and the conductive via include the same conductive material.

10. The integrated circuit of claim 1 further comprising a dielectric cap overlying the top surface of the conductive via, wherein: A top surface of the dielectric cap is substantially coplanar with a top surface of the contact.

11. The integrated circuit of claim 1, wherein: The top surface of the conductive via is lower than a top surface of the source or drain region.

12. The integrated circuit of claim 1, wherein: A top surface of the conductive bridge is substantially coplanar with a top surface of the contact.

13. An integrated circuit according to any one of claims 1 to 12, wherein: The source or drain region is a first source or drain region, the contact portion is a first contact portion, and the conductive bridge is a first conductive bridge, and the integrated circuit further includes: a second source or drain region, the second source or drain region is adjacent to the first source or drain region along the second direction; a dielectric wall, the dielectric wall extending along the first direction between the first source or drain region and the second source or drain region; a second contact portion, the second contact portion is located on a top surface of the second source or drain region; and a second conductive bridge, the second conductive bridge is connected between the first contact portion and the second contact portion and is located above the dielectric wall, and the top surface of the second conductive bridge is substantially coplanar with the top surface of the first contact portion and the top surface of the second contact portion.

14. The integrated circuit according to any one of claims 1 to 12, further comprising a dielectric layer located below the gate electrode, wherein The conductive via extends through the entire thickness of the dielectric layer along the third direction.

15. A printed circuit board comprising an integrated circuit according to any one of claims 1 to 12.

16. An electronic device comprising: A chip package, the chip package comprising one or more dies, at least one of the one or more dies comprising: a semiconductor region extending from a source or drain region along a first direction; a gate electrode extending above the semiconductor region in a second direction, the second direction being different from the first direction; a dielectric layer, the dielectric layer being located below the gate electrode; a contact portion, the contact portion being located on a top surface of the source or drain region; a conductive via extending adjacent to the semiconductor region along the first direction, extending adjacent to the source or drain region along the first direction, and extending through a portion of the gate electrode and through the entire thickness of the dielectric layer along a third direction, wherein a top surface of the conductive via is lower than a top surface of the contact; and A conductive bridge is located between the contact portion and the conductive via, wherein the conductive bridge abuts a portion of the contact portion and is located on at least a portion of the top surface of the conductive via.

17. The electronic device according to claim 16, wherein: The at least one die of the one or more dies further includes a liner layer between the conductive via and the gate electrode.

18. The electronic device according to claim 17, wherein: The liner includes a low-k dielectric material.

19. The electronic device according to claim 16, wherein: The at least one of the one or more dies further includes a dielectric cap over the top surface of the conductive via, wherein a top surface of the dielectric cap is substantially coplanar with a top surface of the contact.

20. The electronic device according to any one of claims 16 to 19, wherein: A top surface of the conductive bridge is substantially coplanar with a top surface of the contact.

21. The electronic device according to any one of claims 16 to 19, wherein: The source or drain region is a first source or drain region, the contact is a first contact, and the conductive bridge is a first conductive bridge, and the at least one die of the one or more dies further comprises: a second source or drain region, the second source or drain region being adjacent to the first source or drain region along the second direction; a dielectric wall extending along the first direction between the first source or drain region and the second source or drain region; a second contact located on a top surface of the second source or drain region; and A second conductive bridge is connected between the first contact portion and the second contact portion and is located on the dielectric wall, wherein a top surface of the second conductive bridge is substantially coplanar with a top surface of the first contact portion and a top surface of the second contact portion.

22. An integrated circuit comprising: a semiconductor region extending from a source or drain region along a first direction; a gate electrode extending above the semiconductor region in a second direction, the second direction being different from the first direction; a dielectric layer, the dielectric layer being located below the gate electrode; a conductive via extending adjacent to the semiconductor region along the first direction, extending adjacent to the source or drain region along the first direction, and extending through a portion of the gate electrode and through the entire thickness of the dielectric layer along a third direction, wherein a top surface of the conductive via is lower than a top surface of the gate electrode; as well as A conductive contact portion is located on a top surface of the source or drain region, and the conductive contact portion extends along the second direction to contact at least a portion of the top surface of the conductive via.

23. The integrated circuit of claim 22, further comprising a dielectric cap over the top surface of the conductive via, wherein: A top surface of the dielectric cap is substantially coplanar with a top surface of the contact.

24. An integrated circuit according to claim 22 or 23, wherein: The top surface of the conductive via is lower than a top surface of the source or drain region, and wherein the conductive contact portion extends along the second direction to contact at least a portion of a side surface of the conductive via.

25. An integrated circuit according to claim 22 or 23, wherein: The source or drain region is a first source or drain region, and the integrated circuit further comprises: a second source or drain region, the second source or drain region being adjacent to the first source or drain region along the second direction; and a dielectric wall extending along the first direction between the first source or drain region and the second source or drain region, The conductive contact portion further extends along the second direction over the dielectric wall and on at least a portion of a top surface of the second source or drain region.

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