Three-dimensional semiconductor device and method of manufacturing same

Abstract

A three-dimensional semiconductor device may include: a back metal layer; a lower channel pattern on the back surface metal layer; a first lower source / drain pattern and a second lower source / drain pattern spaced apart from each other in the first direction, the lower channel pattern being interposed between the first lower source / drain pattern and the second lower source / drain pattern, the first lower source / drain pattern being connected to the lower channel pattern; an upper channel pattern on the lower channel pattern; a first upper source / drain pattern on the first lower source / drain pattern, the first upper source / drain pattern being connected to the upper channel pattern; a second upper source / drain pattern on the second lower source / drain pattern; and a wide via electrically connecting the first upper source / drain pattern to the second lower source / drain pattern. The wide via may include a first via portion having a first top surface and a second via portion having a second top surface, and where the second top surface may be at a lower level than the first top surface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Korean Patent Application No. 10-2023-0111715 filed in the Korean Intellectual Property Office on August 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various example embodiments relate generally to a three-dimensional semiconductor device and / or a method of manufacturing the same, and particularly, to a three-dimensional semiconductor device including a field effect transistor and / or a method of manufacturing the same. Background Art

[0004] Semiconductor devices include integrated circuits composed of metal oxide semiconductor field effect transistors (MOSFETs). In order to meet or improve the growing demand for semiconductor devices with small pattern sizes and simplified design rules, the size of MOSFETs is being actively reduced. The reduction in the size of MOSFETs may cause the operating characteristics of semiconductor devices to deteriorate. Various studies are being conducted to overcome or help overcome the technical limitations associated with the reduction in the size of semiconductor devices and to achieve high-performance semiconductor devices. Summary of the invention

[0005] Various example embodiments provide a three-dimensional semiconductor device having improved electrical characteristics and / or a method of manufacturing the three-dimensional semiconductor device.

[0006] According to some example embodiments, a three-dimensional (3D) semiconductor device may include: a back metal layer; a lower channel pattern on the back metal layer; a first lower source / drain pattern and a second lower source / drain pattern spaced apart from each other in a first direction, the lower channel pattern being interposed between the first lower source / drain pattern and the second lower source / drain pattern, the first lower source / drain pattern being connected to the lower channel pattern; an upper channel pattern on the lower channel pattern; a first upper source / drain pattern on the first lower source / drain pattern, the first upper source / drain pattern being connected to the upper channel pattern; a second upper source / drain pattern on the second lower source / drain pattern; and a wide via electrically connecting the first upper source / drain pattern to the second lower source / drain pattern. The wide via may include a first via portion having a first top surface and a second via portion having a second top surface, the second top surface being at a lower level than the first top surface.

[0007] Alternatively or additionally, according to various example embodiments, a three-dimensional (3D) semiconductor device may include: a back metal layer; a lower channel pattern on the back metal layer; a first lower source / drain pattern and a second lower source / drain pattern spaced apart from each other in a first direction, the lower channel pattern being between the first lower source / drain pattern and the second lower source / drain pattern, the first lower source / drain pattern being connected to the lower channel pattern; an upper channel pattern on the lower channel pattern; a first upper source / drain pattern on the first lower source / drain pattern, the first upper source / drain pattern being connected to the upper channel pattern; a second upper source / drain pattern on the second lower source / drain pattern; and a wide via hole electrically connecting the first upper source / drain pattern to the second lower source / drain pattern. A lower portion of the wide via hole may protrude more than an upper portion of the wide via hole in the first direction.

[0008] Alternatively or additionally, according to various example embodiments, a three-dimensional (3D) semiconductor device may include: a back metal layer; a lower channel pattern and an upper channel pattern sequentially disposed on the back metal layer; a gate electrode intersecting the lower channel pattern and the upper channel pattern; a first lower source / drain pattern connected to the lower channel pattern in a first direction; a first upper source / drain pattern on the first lower source / drain pattern and connected to the upper channel pattern in the first direction; a cutting pattern adjacent to the gate electrode in a second direction intersecting the first direction; and a wide via in the cutting pattern and electrically connected to the first upper source / drain pattern. The cutting pattern may cover a portion of a top surface of the wide via.

[0009] Alternatively or additionally, according to various example embodiments, a three-dimensional (3D) semiconductor device may include: a back metal layer; a lower channel pattern on the back metal layer; a first lower source / drain pattern and a second lower source / drain pattern, spaced apart from each other in a first direction, the lower channel pattern being between the first lower source / drain pattern and the second lower source / drain pattern, the first lower source / drain pattern being connected to the lower channel pattern; an upper channel pattern on the lower channel pattern; a first upper source / drain pattern on the first lower source / drain pattern, the first upper source / drain pattern being connected to the upper channel pattern; and a second upper source / drain pattern, on the second lower source / drain pattern; a first upper active contact portion, electrically connected to the first upper source / drain pattern; a second upper active contact portion, electrically connected to the second upper source / drain pattern; a first lower contact portion, electrically connected to the first lower source / drain pattern; a second lower contact portion, electrically connected to the second lower source / drain pattern; a gate electrode, between the first upper source / drain pattern and the second upper source / drain pattern; a cutting pattern, adjacent to the gate electrode in a second direction intersecting the first direction; and a wide via hole, disposed in the cutting pattern to electrically connect the first upper active contact portion to the second lower contact portion. The wide via hole may include a first via hole portion having a first top surface and a second via hole portion having a second top surface, the second top surface being at a level lower than the first top surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a conceptual diagram illustrating a logic unit of a semiconductor device according to a comparative example.

[0011] Figure 2 is a conceptual diagram illustrating a logic unit of a semiconductor device according to various example embodiments.

[0012] Figure 3 is a plan view illustrating a three-dimensional semiconductor device according to various example embodiments.

[0013] Figure 4 It shows Figure 3 An enlarged plan view of the “P1” portion of FIG.

[0014] FIG. 5A to FIG. 5E Along Figure 3 Cross-sectional views taken along lines AA′, BB′, CC′, DD′ and EE′.

[0015] Figure 6 It shows Figure 3 An enlarged plan view of the “P1” portion of FIG.

[0016] Fig. 7A and Figure 7B Along Figure 3 A cross-sectional view taken along lines BB′ and EE′.

[0017] Figure 8 is a plan view illustrating a three-dimensional semiconductor device according to various example embodiments.

[0018] Fig.9A and Fig. 9B It shows Figure 8 An enlarged plan view of the “P2” portion of the device.

[0019] FIG. 10A to FIG. 15D are cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor device according to various example embodiments. DETAILED DESCRIPTION

[0020] Various example embodiments will now be described more fully with reference to the accompanying drawings, in which some example features are shown.

[0021] Figure 1 is a conceptual diagram illustrating a logic unit of a semiconductor device according to a comparative example.

[0022] Reference Figure 1, a single height cell SHC′ can be provided. Specifically, a first power line POR1 and a second power line POR2 may be disposed on the substrate 100. A drain voltage VDD (e.g., a power supply voltage) may be applied to one of the first power line POR1 and the second power line POR2. A source voltage VSS (e.g., a ground voltage) may be applied to the other of the first power line POR1 and the second power line POR2. In various example embodiments, a source voltage VSS may be applied to the first power line POR1, and a drain voltage VDD may be applied to the second power line POR2. The first power line POR1 and the second power line POR2 may extend in a first direction D1 parallel to the bottom surface of the substrate 100, and may be spaced apart from each other in a second direction D2, the second direction D2 being parallel to the bottom surface of the substrate 100 but not parallel to the first direction D1.

[0023] The single height cell SHC′ may be defined between the first power line POR1 and the second power line POR2. The single height cell SHC′ may include a first active area AR1 and a second active area AR2. One of the first active area AR1 and the second active area AR2 may be a PMOSFET area or may correspond to a PMOSFET area, and the other of the first active area AR1 and the second active area AR2 may be an NMOSFET area or may correspond to an NMOSFET area. For example, the first active area AR1 may be an NMOSFET area or may be included in an NMOSFET area, and the second active area AR2 may be a PMOSFET area or may be included in a PMOSFET area. For example, the single height cell SHC′ may include a CMOS structure disposed between the first power line POR1 and the second power line POR2.

[0024] The semiconductor device according to the comparative example may be a two-dimensional device or may correspond to a two-dimensional device in which transistors of a front-end-of-line (FEOL) layer are two-dimensionally arranged. For example, an NMOSFET of the first active region AR1 may be spaced apart from a PMOSFET of the second active region AR2 in the second direction D2.

[0025] Each of the first active region AR1 and the second active region AR2 may have a first width AW1 in the second direction D2, which may be the same as each other. In a comparative example, the length of the single height cell SHC′ in the second direction D2 may be defined as a first height CHT1. The first height CHT1 may be substantially equal to a distance (e.g., a pitch) between the first power line POR1 and the second power line POR2.

[0026] The single height cell SHC′ may constitute a single logic cell or may correspond to a single logic cell. As described herein, a logic cell may indicate a logic device configured to perform a specific function (e.g., a standard cell such as NAND, NOR, AND, OR, XOR, XNOR, inverter, etc.). For example, a logic cell may include transistors (such as one or more NMOS and / or PMOS transistors) constituting the logic device, and interconnect lines connecting the transistors to each other.

[0027] In the comparative example, since the single height cell SHC′ includes a two-dimensional device, the first active area AR1 and the second active area AR2 may not overlap with each other and may be spaced apart from each other in the second direction D2. Therefore, the first height CHT1 of the single height cell SHC′ should be defined as spanning both the first active area AR1 and the second active area AR2 spaced apart from each other in the second direction D2. Therefore, the first height CHT1 of the single height cell SHC′ may be given as being greater than at least twice the first width AW1. Therefore, the first height CHT1 of the single height cell SHC′ in the comparative example is greater than the second height CHT2 of the single height cell SHC to be described below. For example, the single height cell SHC′ in the comparative example may have a relatively large area.

[0028] Figure 2 is a conceptual diagram illustrating a logic unit of a semiconductor device according to various example embodiments.

[0029] Reference Figure 2 , a single height cell SHC including a three-dimensional device having stacked transistors may be provided. Specifically, a first power line POR1 and a second power line POR2 may be disposed on the substrate 100. The single height cell SHC may be defined between the first power line POR1 and the second power line POR2.

[0030] The single height cell SHC may include a lower active region LAR and an upper active region UAR. One of the lower active region LAR and the upper active region UAR may be a PMOSFET region or may include a PMOSFET region or be included in a PMOSFET region, and the other of the lower active region LAR and the upper active region UAR may be an NMOSFET region or may include an NMOSFET region or be included in an NMOSFET region.

[0031] In some example embodiments, the semiconductor device may be or may include a three-dimensional device in which transistors of the FEOL layer are stacked vertically. The lower active region LAR used as the bottom layer may be disposed on the substrate 100, and the upper active region UAR used as the top layer may be stacked on the lower active region LAR. For example, the PMOSFET of the lower active region LAR may be disposed on the substrate 100, and the NMOSFET of the upper active region UAR may be stacked on the PMOSFET; however, example embodiments are not limited thereto, and in some example embodiments, the PMOSFET may be stacked on the NMOSFET. The lower active region LAR and the upper active region UAR may be spaced apart from each other in a vertical direction (e.g., in a third direction D3 perpendicular to the bottom surface of the substrate 100).

[0032] Each of the lower active region LAR and the upper active region UAR may have a second width AW2 in the second direction D2. In some example embodiments, a length of the single height cell SHC in the second direction D2 may be defined as a second height CHT2.

[0033] Since the single height cell SHC according to various example embodiments includes a three-dimensional device (e.g., a stacked transistor), the lower active region LAR and the upper active region UAR may overlap each other. Therefore, the second height CHT2 of the single height cell SHC may have a size spanning a single active region or may be greater than the second width AW2. Therefore, the second height CHT2 of the single height cell SHC according to various example embodiments may be less than the second height CHT2 described above. Figure 1 The single height cell SHC′ has a first height CHT1. For example, the single height cell SHC in the present embodiment may have a relatively small area. In the three-dimensional semiconductor device according to various example embodiments, the integration density of the device may be increased by reducing the area of ​​the logic cell. In some example embodiments, one or more of yield, reliability, productivity, or efficiency may be improved.

[0034] Figure 3 is a plan view illustrating a three-dimensional semiconductor device according to various example embodiments. Figure 4 It shows Figure 3 An enlarged plan view of the “P1” portion of FIG. FIG. 5A to FIG. 5E Along Figure 3 Cross-sectional views taken along lines AA′, BB′, CC′, DD′ and EE′.

[0035] Reference Figures 3 to 5E, the single height cell SHC may be disposed on a substrate 100. In various example embodiments, the substrate 100 may be an insulating substrate or may include or be included in an insulating substrate formed of or including a silicon-based insulating material (e.g., silicon oxide and / or silicon nitride). In various example embodiments, the substrate 100 may be a semiconductor substrate or may include or be included in a semiconductor substrate made of one or more of silicon, germanium, or silicon germanium.

[0036] In various example embodiments, the substrate 100 may include a first lower insulating layer LIL1 and a second lower insulating layer LIL2. The first lower insulating layer LIL1 may be disposed on the second lower insulating layer LIL2. The first lower insulating layer LIL1 may be formed of or include at least one of a silicon-based insulating material (e.g., silicon oxide) and / or a semiconductor material (Si or SiGe). The second lower insulating layer LIL2 may be formed of or include at least one of a silicon-based insulating material (e.g., silicon oxide, silicon oxynitride, or silicon nitride).

[0037] The device isolation layer ST may be disposed in the substrate 100. The device isolation layer ST may define a single height cell SHC. The device isolation layer ST may be interposed between the back metal layer BSM and the first interlayer insulating layer 110, which will be described below. In various example embodiments, the device isolation layer ST may be formed of at least one of silicon-based insulating materials (e.g., one or more of silicon oxide, silicon oxynitride, or silicon nitride), or include at least one of silicon-based insulating materials (e.g., one or more of silicon oxide, silicon oxynitride, or silicon nitride).

[0038] In various example embodiments, each of the single height cells SHC may be a logic cell constituting a logic circuit or may correspond to a logic cell constituting a logic circuit. Each single height cell SHC may be a logic cell or may correspond to a logic cell including the previously referenced Figure 2 The single height cells SHC may be arranged along the second direction D2.

[0039] Each single height cell SHC may include a lower active region LAR and an upper active region UAR sequentially stacked on a substrate 100. One of the lower active region LAR and the upper active region UAR may be a PMOSFET region, and the other of the lower active region LAR and the upper active region UAR may be an NMOSFET region. The lower active region LAR may be set as the bottom layer of the FEOL layer, and the upper active region UAR may be set as the top layer of the FEOL layer. The NMOSFET and PMOSFET of the lower active region LAR and the upper active region UAR may be stacked vertically to constitute a three-dimensional stacked transistor. In various example embodiments, the lower active region LAR may be a PMOSFET region, and the upper active region UAR may be an NMOSFET region; however, example embodiments are not limited thereto. Each of the lower active region LAR and the upper active region UAR may be a strip or line region extending along the first direction D1 independently or simultaneously.

[0040] The lower active region LAR may include a lower channel pattern LCH and a lower source / drain pattern LSD. The lower channel pattern LCH may be interposed between a pair of lower source / drain patterns LSD. The lower channel pattern LCH may connect the pair of lower source / drain patterns LSD to each other.

[0041] The lower channel pattern LCH may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 stacked at intervals from each other. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe). In various example embodiments, each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be formed of or include crystalline silicon. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be a nanosheet. As an example, the lower channel pattern LCH may further include one or more semiconductor patterns stacked and spaced apart from the second semiconductor pattern SP2.

[0042] The lower source / drain patterns LSD may be disposed on the substrate 100. Each of the lower source / drain patterns LSD may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process such as a homogeneous or heterogeneous SEG process. In various example embodiments, a top surface of the lower source / drain pattern LSD may be higher than a top surface of the second semiconductor pattern SP2 of the lower channel pattern LCH.

[0043] The lower source / drain pattern LSD may be doped with impurities to have a first conductivity type. The first conductivity type may be an n-type or a p-type. In some example embodiments, the first conductivity type may be a p-type. The lower source / drain pattern LSD may be formed of or include silicon (Si) and / or silicon germanium (SiGe). In some example embodiments, the lower source / drain pattern LSD may be doped with n-type impurities at a high concentration, and may also be doped with p-type impurities at a low concentration (e.g., a much lower concentration); example embodiments are not limited thereto.

[0044] The first interlayer insulating layer 110 may be disposed on the lower source / drain pattern LSD. The first interlayer insulating layer 110 may cover the lower source / drain pattern LSD.

[0045] The lower active contact LAC may be disposed below the lower source / drain pattern LSD. The lower active contact LAC may be electrically connected to the lower source / drain pattern LSD. The lower active contact LAC may be buried in the substrate 100 or at least partially buried in the substrate 100. The lower active contact LAC may extend vertically from the top surface of the substrate 100 to the bottom surface. The lower active contact LAC may be formed of or include at least one metal material selected from the group consisting of at least one of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo), or selected from the group including at least one of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0046] The upper active region UAR may be disposed on the first interlayer insulating layer 110. The upper active region UAR may include an upper channel pattern UCH and an upper source / drain pattern USD. The upper channel pattern UCH may vertically overlap with the lower channel pattern LCH, respectively. The upper source / drain pattern USD may vertically overlap with the lower source / drain pattern LSD, respectively. The upper channel pattern UCH may be between a pair of upper source / drain patterns USD. The upper channel pattern UCH may connect a pair of upper source / drain patterns USD to each other.

[0047] The upper channel pattern UCH may include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 stacked at intervals from each other. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the upper channel pattern UCH may include the same semiconductor material as the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the lower channel pattern LCH. Each of the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 may be a nanosheet. As an example, the upper channel pattern UCH may also include one or more semiconductor patterns stacked and spaced apart from the fourth semiconductor pattern SP4. The number of semiconductor patterns SP3 and SP4 included in the upper channel pattern UCH may be the same as the number of semiconductor patterns SP1 and SP2 included in the lower channel pattern LCH, or greater than the number of semiconductor patterns SP1 and SP2 included in the lower channel pattern LCH, or less than the number of semiconductor patterns SP1 and SP2 included in the lower channel pattern LCH.

[0048] At least one dummy channel pattern DSP may be interposed between the lower channel pattern LCH and the upper channel pattern UCH thereon. A seed layer SDL may be interposed between the dummy channel pattern DSP and the upper channel pattern UCH.

[0049] The dummy channel pattern DSP may be spaced apart from the lower source / drain pattern LSD and the upper source / drain pattern USD. In some example embodiments, the dummy channel pattern DSP may not be connected to any source / drain pattern. The dummy channel pattern DSP may be formed of at least one of semiconductor materials (e.g., one or more of silicon (Si), germanium (Ge), or silicon germanium (SiGe)) or at least one of silicon-based insulating materials (e.g., silicon oxide or silicon nitride), or include at least one of semiconductor materials (e.g., one or more of silicon (Si), germanium (Ge), or silicon germanium (SiGe)) or at least one of silicon-based insulating materials (e.g., silicon oxide or silicon nitride). In various example embodiments, the dummy channel pattern DSP may be formed of at least one of silicon-based insulating materials or include at least one of silicon-based insulating materials. In some example embodiments, the dummy channel pattern DSP may provide mechanical support and / or may improve the manufacture of semiconductor devices.

[0050] The upper source / drain pattern USD may be disposed on the top surface of the first interlayer insulating layer 110. Each of the upper source / drain patterns USD may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process such as a homogeneous SEG process and / or a heterogeneous SEG process. In various example embodiments, the top surface of the upper source / drain pattern USD may be higher than the top surface of the fourth semiconductor pattern SP4 of the upper channel pattern UCH.

[0051] The upper source / drain pattern USD may be doped with impurities to have a second conductivity type. The second conductivity type may be different from the first conductivity type of the lower source / drain pattern LSD. The second conductivity type may be an n-type. In some example embodiments, the upper source / drain pattern USD may be doped with p-type impurities at a high concentration, and may also be doped with n-type impurities at a low concentration (e.g., a much lower concentration); example embodiments are not limited thereto. The upper source / drain pattern USD may be formed of or include at least one of silicon germanium (SiGe) and / or silicon (Si), and may include the same material as that included in the lower source / drain pattern LSD, or may not include the same material as that included in the lower source / drain pattern LSD.

[0052] A plurality of gate electrodes GE may be disposed on the single height cell SHC. Specifically, the gate electrode GE may be disposed on the stacked lower channel pattern LCH and the upper channel pattern UCH. When viewed in a plan view, the gate electrode GE may be a stripe pattern extending along the second direction D2. The gate electrode GE may vertically overlap and intersect the stacked lower channel pattern LCH and the upper channel pattern UCH.

[0053] The gate electrodes GE may be spaced apart from each other in the first direction D1 and the second direction D2. As an example, the gate electrodes GE on each single height cell SHC may be spaced apart from each other in the first direction D1. The gate electrodes GE may be arranged to form a plurality of gate groups that are spaced apart from each other in the first direction D1, and here, each gate group may consist of a plurality of gate electrodes GE arranged along the second direction D2.

[0054] The gate electrode GE may extend from the top surface of the substrate 100 to the gate capping pattern GP to be described below in a vertical direction (i.e., a third direction D3). The gate electrode GE may extend from the lower channel pattern LCH of the lower active region LAR to the upper channel pattern UCH of the upper active region UAR in the third direction D3. The gate electrode GE may extend from the lowermost first semiconductor pattern among the first semiconductor patterns SP1 to the uppermost fourth semiconductor pattern among the fourth semiconductor patterns SP4 in the third direction D3.

[0055] The gate electrode GE may be disposed on the top surface, the bottom surface, and the opposite side surfaces of each of the first to fourth semiconductor patterns SP1 to SP4. That is, the transistor according to the present embodiment may include a three-dimensional field effect transistor (eg, a multi-bridge channel FET (MBCFET)). TM ) and / or gate-all-around FET (GAAFET), in which the gate electrode GE is arranged to three-dimensionally surround the channel pattern.

[0056] The gate electrode GE may include a lower gate electrode LGE disposed in the bottom layer of the FEOL layer (i.e., the lower active region LAR), and an upper gate electrode UGE disposed in the top layer of the FEOL layer (e.g., the upper active region UAR). The lower gate electrode LGE and the upper gate electrode UGE may overlap each other vertically. In various example embodiments, the lower gate electrode LGE and the upper gate electrode UGE may be connected to each other. For example, the gate electrode GE according to various example embodiments may be a common gate electrode or may correspond to a common gate electrode, wherein the lower gate electrode LGE on the lower channel pattern LCH and the upper gate electrode UGE on the upper channel pattern UCH are connected to each other.

[0057] The lower gate electrode LGE may include a first internal electrode PO1 between the first lower insulating layer LIL1 and the first semiconductor pattern SP1 , a second internal electrode PO2 between the first and second semiconductor patterns SP1 and a third internal electrode PO3 between the second semiconductor pattern SP2 and the dummy channel pattern DSP.

[0058] The upper gate electrode UGE may include a fourth internal electrode PO4 between the dummy channel pattern DSP (or the seed layer SDL) and the third semiconductor pattern SP3 , a fifth internal electrode PO5 between the third and fourth semiconductor patterns SP3 and SP4 , and an external electrode PO6 on the fourth semiconductor pattern SP4 .

[0059] A pair of gate spacers GS may be respectively disposed on opposite side surfaces of the gate electrode GE. The pair of gate spacers GS may be respectively disposed on opposite side surfaces of the outer electrode PO6. The gate spacer GS may extend along the gate electrode GE and along the second direction D2. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE or above the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar or at the same level as the top surface of the second interlayer insulating layer 120. The gate spacer GS may be formed of at least one of SiCN, SiCON, or SiN, or include at least one of SiCN, SiCON, or SiN. In various example embodiments, the gate spacer GS may be a multilayer structure including at least two different materials selected from SiCN, SiCON, and SiN.

[0060] The gate capping pattern GP may be disposed on the top surface of the gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE or along the second direction D2. For example, the gate capping pattern GP may be formed of at least one of SiON, SiCN, SiCON, or SiN, or include at least one of SiON, SiCN, SiCON, or SiN.

[0061] The gate insulating layer GI may be interposed between the gate electrode GE and the first to fourth semiconductor patterns SP1 to SP4. The gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. The dielectric constant of the high-k dielectric layer may be greater than the dielectric constant of silicon oxide. In various example embodiments, the gate insulating layer GI may include a silicon oxide layer formed to directly cover the semiconductor patterns SP1 to SP4, and a high-k dielectric layer formed on the silicon oxide layer. In some example embodiments, the gate insulating layer GI may be a multilayer structure including a silicon oxide layer and a high-k dielectric layer.

[0062] The high-k dielectric layer may be formed of at least one of high-k dielectric materials having a higher dielectric constant than silicon oxide, or include at least one of high-k dielectric materials having a higher dielectric constant than silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0063] The second interlayer insulating layer 120 may be disposed on the upper source / drain pattern USD and the gate electrode GE. The second interlayer insulating layer 120 may cover the upper source / drain pattern USD. The third interlayer insulating layer 130 may be disposed to cover the second interlayer insulating layer 120 or at least partially cover the second interlayer insulating layer 120.

[0064] The upper active contact UAC may be disposed to penetrate the second and third interlayer insulating layers 120 and 130 and may be electrically connected to the upper source / drain patterns USD, respectively. In various example embodiments, the top surface of the upper active contact UAC may be coplanar or at the same level as the top surface of the third interlayer insulating layer 130.

[0065] The upper gate contact UGC may be disposed to penetrate the third interlayer insulating layer 130 and the gate capping pattern GP, ​​and may be electrically connected to the upper gate electrode UGE. Each of the upper active contact UAC and the upper gate contact UGC may be formed of or include at least one metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0066] The cutting pattern CT may be arranged to intersect the gate group arranged along the first direction D1. The cutting pattern CT may extend along the first direction D1. The cutting pattern CT may be arranged to separate the gate electrodes GE included in the gate group and adjacent to each other in the second direction D2 from each other. Adjacent ones of the gate electrodes GE may be spaced apart from each other in the second direction D2 by the cutting pattern CT. The cutting pattern CT may be formed of at least one of insulating materials (e.g., silicon oxide and / or silicon nitride), or include at least one of insulating materials (e.g., silicon oxide and / or silicon nitride).

[0067] The fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. The first metal layer M1 may be disposed in the fourth interlayer insulating layer 140. The first metal layer M1 may include an upper interconnect line UMI. The first metal layer M1 may also include an upper via UVI. The upper via UVI may electrically connect the upper interconnect line UMI to the upper active contact UAC or the upper gate contact UGC. Each of the upper interconnect line UMI and the upper via UVI may be formed of or include at least one metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0068] Additional metal layers (e.g., M2, M3, M4, etc. (not shown)) may be stacked on the first metal layer M1. The first metal layer M1 and the additional metal layers (e.g., M2, M3, M4, etc.) thereon may constitute or correspond to back-end-of-line (BEOL) layers of a semiconductor device. The additional metal layers (e.g., M2, M3, M4, etc.) on the first metal layer M1 may include routing wires for connecting logic cells to each other.

[0069] The lower interlayer insulating layer 210 may be disposed below the bottom surface of the substrate 100. A lower gate contact LGC electrically connected to the lower gate electrode LGE may be disposed between the lower interlayer insulating layer 210 and the lower gate electrode LGE. A back metal layer BSM may be disposed in the lower interlayer insulating layer 210. The back metal layer BSM may include a lower contact LC, a lower interconnection line LMI, and a lower via LVI. The lower contact LC may be electrically connected to the lower source / drain pattern LSD through the lower active contact LAC. The lower via LVI may electrically connect the lower interconnection line LMI to the lower active contact LAC, the lower contact LC, or the lower gate contact LGC.

[0070] Each of the lower gate contact LGC, the lower contact LC, the lower interconnect line LMI and the lower via LVI can be independently or simultaneously formed of or include a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W) and molybdenum (Mo).

[0071] The lower metal layer may be further stacked below the back metal layer BSM. In various example embodiments, the lower metal layer may include a power delivery network. The power delivery network may include a wiring network for applying a source voltage VSS and a drain voltage VDD to the back metal layer BSM.

[0072] The through via THV may be provided in the cutting pattern CT. The through via THV may be used to electrically connect the vertically stacked lower source / drain pattern LSD and the upper source / drain pattern USD to each other. Specifically, the through via THV may be electrically connected to the upper source / drain pattern USD through the upper active contact UAC, and may be electrically connected to the lower source / drain pattern LSD through the lower contact LC and the lower active contact LAC. The through via THV may be formed of or include at least one metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W) and molybdenum (Mo).

[0073] A wide via WV may be provided in the cutting pattern CT. The wide via WV may extend from the top surface of the cutting pattern CT to the bottom surface of the cutting pattern CT, and may extend along the first direction D1 when viewed in a plan view. When viewed in a cross-sectional view, the wide via WV may have an "L"-shaped profile. The wide via WV may be formed of at least one of a metal material (e.g., copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo)), or include at least one of a metal material (e.g., copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo)).

[0074] The top surface WVa of the wide via WV may include a first top surface W1a and a second top surface W2a, the second top surface W2a being located at a level lower than the first top surface W1a. The first top surface W1a may be a top surface of a first via portion W1 of the wide via WV, and the second top surface W2a may be a top surface of a second via portion W2 of the wide via WV. The first via portion W1 and the second via portion W2 may be adjacent to each other in the first direction D1. In various example embodiments, the second top surface W2a may be located at a level lower than the top surface of the upper active contact UAC.

[0075] The bottom surface WVb of the wide via WV may be substantially flat. In various example embodiments, the first via portion W1 and the second via portion W2 may have a first bottom surface W1b and a second bottom surface W2b, respectively, located at substantially the same level. Therefore, when measured in a vertical direction (e.g., a third direction D3), the height HT2 of the second via portion W2 may be less than the height HT1 of the first via portion W1. In various example embodiments, the height HT2 of the second via portion W2 may be in the range of 20% to 80% of the height HT1 of the first via portion W1; example embodiments are not limited thereto.

[0076] The lower portion of the wide via WV may protrude in the first direction D1 compared to the upper portion of the wide via WV. The lower portion of the wide via WV may be a portion located below the second top surface W2a of the wide via WV, and the upper portion of the wide via WV may be a portion located above the second top surface W2a. The lower portion of the wide via WV may include a lower portion of the first via portion W1 and a second via portion W2, and the upper portion of the wide via WV may include an upper portion of the first via portion W1. In the wide via WV, when measured along the first direction D1, the width of the lower portion may be greater than the width of the upper portion.

[0077] When viewed in a cross-sectional view, the wide via WV may have a first side surface WVc facing the first direction D1. The first side surface WVc of the wide via WV may include a first sub-side surface W1c as a side surface of the upper portion of the wide via WV (i.e., a side surface of the first via portion W1), and a second sub-side surface W2c as a side surface of the lower portion of the wide via WV (i.e., a side surface of the second via portion W2). The second sub-side surface W2c may deviate from the first sub-side surface W1c in the first direction D1. Therefore, the first side surface WVc of the wide via WV may extend discontinuously along the third direction D3. In various example embodiments, the first sub-side surface W1c, the second top surface W2a, and the second sub-side surface W2c of the wide via WV may be connected to each other to form a stepped profile.

[0078] The wide via WV may have a second side surface WVd opposite to the first side surface WVc. The second side surface WVd may include opposite side surfaces of the upper and lower portions of the wide via WV (e.g., opposite side surfaces of the first via portion W1). The second side surface WVd of the wide via WV may extend continuously along the third direction D3. In various example embodiments, the second side surface WVd of the wide via WV may extend straight along the third direction D3.

[0079] The wide via WV may electrically connect the lower source / drain pattern LSD horizontally spaced apart from each other with the upper source / drain pattern USD. Specifically, the lower source / drain pattern LSD may include a first lower source / drain pattern LSD1 and a second lower source / drain pattern LSD2 spaced apart from each other in the first direction D1, and the upper source / drain pattern USD may include a first upper source / drain pattern USD1 and a second upper source / drain pattern USD2 spaced apart from each other in the first direction D1. The first upper source / drain pattern USD1 may be vertically stacked on the first lower source / drain pattern LSD1, and the second upper source / drain pattern USD2 may be vertically stacked on the second lower source / drain pattern LSD2. The first lower active contact LAC1 and the first lower contact LC1 may be sequentially electrically connected to the first lower source / drain pattern LSD1, and the first upper active contact UAC1 may be electrically connected to the first upper source / drain pattern USD1. The second lower active contact LAC2 and the second lower contact LC2 may be sequentially electrically connected to the second lower source / drain pattern LSD2 , and the second upper active contact UAC2 may be electrically connected to the second upper source / drain pattern USD2 .

[0080] The wide via WV may electrically connect the first upper source / drain pattern USD1 to the second lower source / drain pattern LSD2. Specifically, the wide via WV may be electrically connected to the first upper source / drain pattern USD1 through the first upper active contact UAC1, and may be electrically connected to the second lower source / drain pattern LSD2 through the second lower contact LC2 and the second lower active contact LAC2. The wide via WV may be spaced apart from and electrically disconnected from the second upper active contact UAC2 and the first lower contact LC1. In various example embodiments, when measured along the second direction D2 and the third direction D3, the second via portion W2 of the wide via WV may be spaced apart from the second upper active contact UAC2. Therefore, the wide via WV may be electrically disconnected from the second upper source / drain pattern USD2 and the first lower source / drain pattern LSD1, respectively.

[0081] In various example embodiments, the first upper active contact UAC1 may vertically overlap with the first via portion W1 of the wide via WV, and the second via portion W2 of the wide via WV may vertically overlap with the second lower contact LC2. The first via portion W1 of the wide via WV may not vertically overlap with the first lower contact LC1, and the second upper active contact UAC2 may not vertically overlap with the second via portion W2 of the wide via WV.

[0082] The third upper source / drain pattern USD3 and the third lower source / drain pattern LSD3 may be spaced apart from the second upper source / drain pattern USD2 and the second lower source / drain pattern LSD2, with a wide via WV interposed therebetween. The third lower active contact LAC3 and the third lower contact LC3 may be electrically connected to the third lower source / drain pattern LSD3 in sequence, and the third upper active contact UAC3 may be electrically connected to the third upper source / drain pattern USD3. The wide via WV may be spaced apart from the third upper active contact UAC3 and the third lower contact LC3 (e.g., horizontally) and electrically disconnected. Therefore, the wide via WV may be electrically disconnected from the third upper source / drain pattern USD3 and the third lower source / drain pattern LSD3, respectively.

[0083] The gate electrode GE may be interposed between the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 and between the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2. The wide via WV may be spaced apart from the gate electrode GE in the second direction D2. When viewed in a plan view, the wide via WV may extend in the first direction D1 and the opposite direction thereof compared to the gate electrode GE.

[0084] The gate electrodes GE adjacent to each other in the second direction D2 may constitute a first gate group G1, and the wide via WV may be disposed to cross the first gate group G1. In various example embodiments, the second via portion W2 of the wide via WV may extend in the first direction D1 to cross the first gate group G1.

[0085] When measured along the first direction D1, the width L1 of the wide via WV may be greater than the width L3 of the gate electrode GE. Therefore, the wide via WV may span the first gate group G1 and may be electrically connected to the first upper active contact UAC1 and the second lower contact LC2. When measured along the first direction D1, the width L1 of the wide via WV may be equal to the pitch L2 of the gate electrode GE or different from the pitch L2 of the gate electrode GE. In various example embodiments, when measured along the first direction D1, the width L1 of the wide via WV may be greater than the pitch L2 of the gate electrode GE.

[0086] The cutting pattern CT may include a first cutting portion C1 and a second cutting portion C2, the first cutting portion C1 being arranged to surround the wide via WV, and the second cutting portion C2 being arranged to cover at least a portion of the top surface WVa of the wide via WV. In various exemplary embodiments, the first cutting portion C1 and the second cutting portion C2 may be different from each other and have an interface therebetween, or may be connected to each other without an interface therebetween. In various exemplary embodiments, the second cutting portion C2 may cover the second top surface W2a of the wide via WV, and the first cutting portion C1 may surround the wide via WV and the second cutting portion C2. The first cutting portion C1 may separate the wide via WV from the first gate group G1. The second cutting portion C2 may vertically overlap the second via portion W2. Therefore, the upper portion of the cutting pattern CT including the second cutting portion C2 may vertically overlap the lower portion of the wide via WV. The top surface of the cutting pattern CT and the first top surface W1a of the wide via WV may be located at substantially the same level and may be coplanar with each other.

[0087] According to various example embodiments, in a region adjacent to the second upper active contact UAC2, the wide via WV may be recessed to have a second top surface W2a located at a relatively low level. Therefore, the distance between the wide via WV and the second upper active contact UAC2 may be increased, and therefore, the formation of a short circuit between the wide via WV and the second upper active contact UAC2 may be prevented or the possibility of the formation of a short circuit between the wide via WV and the second upper active contact UAC2 may be reduced. Therefore, the electrical characteristics and / or reliability characteristics of the three-dimensional semiconductor device may be improved.

[0088] Alternatively or additionally, since the wide via WV is used to electrically connect the lower source / drain patterns LSD and the upper source / drain patterns USD (e.g., the second lower source / drain pattern LSD2 and the first upper source / drain pattern USD1) horizontally spaced apart from each other, the design freedom of the three-dimensional semiconductor device can be improved.

[0089] In the following, reference will be made to Figures 6 to 9B Various example embodiments are described in more detail. For the sake of brevity of description, previously described elements may be identified by the same reference numerals without repeating repeated descriptions of the elements.

[0090] Figure 6 It is shown Figure 3 An enlarged plan view of the “P1” portion of FIG. Fig. 7A and Figure 7B Along Figure 3 A cross-sectional view taken along lines BB′ and EE′.

[0091] Reference Figure 3 and Figures 6 to 7B, the wide via WV may be arranged to intersect the first gate group G1. Figures 4 to 5E Unlike the description, the first via portion W1 of the wide via WV may extend in the first direction D1 between the gate electrodes GE of the first gate group G1. The first via portion W1 may be spaced apart from the first gate group G1 in the second direction D2 with the cutting pattern CT interposed therebetween.

[0092] Figure 8 is a plan view illustrating a three-dimensional semiconductor device according to various example embodiments. Fig.9A and Fig. 9B It shows Figure 8 An enlarged plan view of the “P2” portion of the device.

[0093] Reference Figure 3 and Figures 8 to 9A , the fourth lower source / drain pattern LSD4 may be disposed between the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2, and the fourth upper source / drain pattern USD4 may be disposed between the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2. The fourth lower active contact (not shown) and the fourth lower contact LC4 may be sequentially electrically connected to the fourth lower source / drain pattern LSD4, and the fourth upper active contact UAC4 may be electrically connected to the fourth upper source / drain pattern USD4.

[0094] The first gate group G1 may be disposed between the first lower source / drain pattern LSD1 and the fourth lower source / drain pattern LSD4 and between the first upper source / drain pattern USD1 and the fourth upper source / drain pattern USD4. The second gate group G2 may be disposed between the second lower source / drain pattern LSD2 and the fourth lower source / drain pattern LSD4 and between the second upper source / drain pattern USD2 and the fourth upper source / drain pattern USD4. The fourth lower source / drain pattern LSD4 and the fourth upper source / drain pattern USD4 may be disposed between the first gate group G1 and the second gate group G2.

[0095] The wide via WV may be spaced apart from the fourth lower source / drain pattern LSD4 and the fourth upper source / drain pattern USD4 in the second direction D2. The wide via WV may be spaced apart from and electrically disconnected from the fourth upper active contact UAC4 and the fourth lower contact LC4 in the second direction D2. The wide via WV may be disposed to span across two or more gate groups, and may be electrically connected to the first upper active contact UAC1 and the second lower contact LC2. In various example embodiments, the wide via WV may be disposed to cross the first gate group G1 and the second gate group G2, and may be electrically connected to the first upper active contact UAC1 and the second lower contact LC2. Therefore, the wide via WV may electrically connect the lower source / drain pattern LSD and the upper source / drain pattern USD, which are horizontally spaced apart from each other and have two or more gate groups therebetween, to each other.

[0096] The disposition or arrangement of the first and second via portions W1 and W2 of the wide via hole WV may be variously changed. However, compared with the first via portion W1, the second via portion W2 may be disposed adjacent to the second lower source / drain pattern LSD2 and the second upper source / drain pattern USD2.

[0097] In various example embodiments, Fig.9A As shown, the second via portion W2 may extend between the first gate group G1 and the second gate group G2 along the first direction D1, and may be spaced apart from the first gate group G1 and the second gate group G2 and the fourth lower source / drain pattern LSD4 and the fourth upper source / drain pattern USD4 in the second direction D2. The first via portion W1 may be spaced apart from the first lower source / drain pattern LSD1 and the first upper source / drain pattern USD1 in the second direction D2, and may extend toward the second via portion W2 along the first direction D1.

[0098] In various example embodiments, Fig. 9B As shown, the first via portion W1 may extend between the first gate group G1 along the first direction D1 and may be spaced apart from the first gate group G1 in the second direction D2. The second via portion W2 may extend between the second gate group G2 along the first direction D1 and may be spaced apart from the second gate group G2 and the fourth lower source / drain pattern LSD4 and the fourth upper source / drain pattern USD4 in the second direction D2.

[0099] FIG. 9A to FIG. 9B An example of possible arrangements of the first and second via portions W1 and W2 is shown, and the inventive concept is not limited to this example.

[0100] FIG. 10A to FIG. 15D is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor device according to various example embodiments. In detail, Fig. 10A , Fig.11A , Fig. 12A and Fig.13A is along Figure 3 A cross-sectional view taken along line AA′. Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig.14A and Fig.15A is along Figure 3 A cross-sectional view taken along line BB′. Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14B and Fig. 15B is along Figure 3 A cross-sectional view taken along line CC′. Fig. 15Cis along Figure 3 A cross-sectional view taken along line DD′. Fig.11D , Fig.12D , Fig.13D , Fig. 14C and Fig.15D is along Figure 3 A cross-sectional view taken along line EE′.

[0101] In the following, reference will be made to FIG. 10A to FIG. 15D A method of manufacturing a three-dimensional semiconductor device according to various example embodiments is described in more detail. For brevity of description, previously described elements may be identified by the same reference numerals without repeating a repetitive description about the elements.

[0102] Reference FIG. 10A to FIG. 10C , a semiconductor substrate 105 may be provided. The semiconductor substrate 105 may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, the semiconductor substrate 105 may be a single crystal silicon wafer. In some example embodiments, the substrate 105 may be doped; however, example embodiments are not limited thereto.

[0103] A first lower insulating layer LIL1 may be formed on the semiconductor substrate 105. The first lower insulating layer LIL1 may be formed of or include at least one of a silicon-based insulating material (e.g., silicon oxide) and / or a semiconductor material (e.g., Si or SiGe).

[0104] The first sacrificial layer SAL1 and the first active layer ACL1 may be alternately formed on the first lower insulating layer LIL1, for example, using an atomic layer deposition (ALD) process. The first sacrificial layer SAL1 and the first active layer ACL1 may be formed of at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe), or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe), and may be formed of materials different from each other. For example, the first sacrificial layer SAL1 may be formed of silicon germanium (SiGe) or include silicon germanium (SiGe), and the first active layer ACL1 may be formed of silicon (Si) or include silicon (Si). The concentration of germanium (Ge) in each first sacrificial layer SAL1 may be in the range of 10 at% to 30 at%, and may be the same as or different from each other. The thickness of each first sacrificial layer SAL1 may be the same as each other, or at least one may be different from the other layers. The thickness of each first active layer ACL1 may be the same as each other, and may be the same as the thickness of the first sacrificial layer SAL1, or at least one may be different from the other layers.

[0105] A separation layer DSL may be formed on the uppermost first sacrificial layer among the first sacrificial layers SAL1. In various example embodiments, the thickness of the separation layer DSL may be greater than the thickness of the first sacrificial layer SAL1. The separation layer DSL may be formed of or include silicon (Si) or silicon germanium (SiGe). In the case where the separation layer DSL includes silicon germanium (SiGe), the germanium concentration of the separation layer DSL may be higher than the germanium concentration of the first sacrificial layer SAL1. For example, the germanium concentration of the separation layer DSL may be in the range of 40 at % to 90 at %.

[0106] A seed layer SDL may be formed on the separation layer DSL. The seed layer SDL may be formed of or include the same material as the first active layer ACL1. Second sacrificial layers SAL2 and second active layers ACL2 may be alternately stacked on the seed layer SDL. Each second sacrificial layer SAL2 may be formed of or include the same material as the first sacrificial layer SAL1, and each second active layer ACL2 may be formed of or include the same material as the first active layer ACL1. The separation layer DSL may be interposed between the first sacrificial layer SAL1 and the seed layer SDL. The thickness of each second sacrificial layer SAL2 may be the same as one another, or at least one may be different from the other layers. The thickness of each second active layer ACL2 may be the same as one another, and may be the same as the thickness of the second sacrificial layer SAL2, or at least one may be different from the other layers.

[0107] The stack pattern STP may be formed by patterning the stacked first and second sacrificial layers SAL1 and SAL2, the first and second active layers ACL1 and ACL2, and the separation layer DSL. The formation of the stack pattern STP may include: forming a hard mask pattern on the uppermost second active layer in the second active layer ACL2; and etching the layers SAL1, SAL2, ACL1, ACL2, SDL, and DSL stacked on the semiconductor substrate 105 using the hard mask pattern as an etching mask. During the formation of the stack pattern STP, the upper portion of the semiconductor substrate 105 may be patterned to form a first trench TR1 defining a single height cell SHC. The stack pattern STP may be a stripe or line pattern extending in the first direction D1.

[0108] The stack pattern STP may include a lower stack pattern STP1 on the first lower insulating layer LIL1, an upper stack pattern STP2 on the lower stack pattern STP1, and a separation layer DSL between the lower stack pattern STP1 and the upper stack pattern STP2. The lower stack pattern STP1 may include a first sacrificial layer SAL1 and a first active layer ACL1 alternately stacked. The upper stack pattern STP2 may include a seed layer SDL, and a second sacrificial layer SAL2 and a second active layer ACL2 alternately stacked on the seed layer SDL. A device isolation layer ST may be formed on the semiconductor substrate 105 to fill the first trench TR1.

[0109] Reference FIG. 11A to FIG. 11D , a plurality of sacrificial patterns PP may be formed to intersect the stacked pattern STP. Each sacrificial pattern PP may be formed to have a line shape extending along the second direction D2. Specifically, forming the sacrificial pattern PP may include: forming a sacrificial layer on the semiconductor substrate 105; forming a hard mask pattern MP on the sacrificial layer; and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer may be formed of amorphous silicon and / or polycrystalline silicon (such as doped and / or undoped polycrystalline silicon), or include amorphous silicon and / or polycrystalline silicon (such as doped and / or undoped polycrystalline silicon).

[0110] A pair of gate spacers GS may be formed on opposite side surfaces of the sacrificial pattern PP, respectively. Specifically, a spacer layer may be conformally formed on the semiconductor substrate 105. The spacer layer may cover the sacrificial pattern PP and the hard mask pattern MP. For example, the spacer layer may be formed of or include at least one of SiCN, SiCON, or SiN. The gate spacer GS may be formed by anisotropically etching the spacer layer.

[0111] An etching process may be performed on the stack pattern STP using the gate spacer GS and the hard mask pattern MP as an etching mask. As a result of the etching process, a second trench TR2 may be formed between adjacent sacrificial patterns PP. Due to the second trench TR2, the stack pattern STP may be formed to have a stick shape.

[0112] A sacrificial contact pattern PLH may be formed in the semiconductor substrate 105 exposed by the second trench TR2. The sacrificial contact pattern PLH may be formed in the form of a contact plug. The sacrificial contact pattern PLH may be arranged along the first direction D1. The sacrificial contact pattern PLH may be formed of a material having an etching selectivity relative to the semiconductor substrate 105 (e.g., silicon germanium (SiGe)), or include a material having an etching selectivity relative to the semiconductor substrate 105 (e.g., silicon germanium (SiGe)). The sacrificial contact pattern PLH may be formed by an epitaxial growth process. The second trench TR2 may be formed to expose the sacrificial contact pattern PLH. That is, the second trench TR2 may overlap with the sacrificial contact pattern PLH.

[0113] In the case where the separation layer DSL includes silicon germanium (SiGe), the separation layer DSL may be replaced with a silicon-based insulating material. For example, the separation layer DSL exposed by the second trench TR2 may be selectively removed to form an empty region, and then a silicon-based insulating material (e.g., silicon nitride) may be formed to fill the empty region.

[0114] Reference FIG. 12A to FIG. 12D , a lower source / drain pattern LSD may be formed in the second trench TR2. Specifically, the lower source / drain pattern LSD may be formed by performing a first SEG process using a side surface of the lower stack pattern STP1 exposed through the second trench TR2 as a seed layer. The lower source / drain pattern LSD may be grown using the first active layer ACL1 exposed through the second trench TR2 as a seed layer. As an example, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0115] As an example, impurities may be implanted or incorporated into the lower source / drain pattern LSD in an in-situ manner during the first SEG process. Alternatively or additionally, impurities may be implanted or implanted into the lower source / drain pattern LSD after forming the lower source / drain pattern LSD. The lower source / drain pattern LSD may be doped to have a first conductivity type.

[0116] The first active layer ACL1 between the pair of lower source / drain patterns LSD may constitute a lower channel pattern LCH. For example, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the lower channel pattern LCH may be formed by the first active layer ACL1. The lower channel pattern LCH and the lower source / drain pattern LSD may constitute a lower active region LAR serving as a bottom layer of a three-dimensional device.

[0117] The lower source / drain pattern LSD may be formed to completely fill the space between the pair of lower channel patterns LCH. For example, the first SEG process may be performed for a sufficient time until the lower source / drain pattern LSD grows to fill the space between the pair of lower channel patterns LCH and connects the pair of lower channel patterns LCH to each other.

[0118] The first interlayer insulating layer 110 may be formed to cover the lower source / drain pattern LSD. In various example embodiments, before forming the first interlayer insulating layer 110, an etch stop layer may be additionally formed to conformally cover the lower source / drain pattern LSD. In various example embodiments, a portion of the first interlayer insulating layer 110 may be formed under the lower source / drain pattern LSD before forming the lower source / drain pattern LSD, and another portion of the first interlayer insulating layer 110 may also be formed after forming the lower source / drain pattern LSD.

[0119] In the second trench TR2, the first interlayer insulating layer 110 may cover the side surface of the upper stack pattern STP2. Next, the upper portion of the first interlayer insulating layer 110 may be removed to expose the side surface of the upper stack pattern STP2 in the second trench TR2 again. An upper source / drain pattern USD may be formed on the exposed side surface of the upper stack pattern STP2. Specifically, the upper source / drain pattern USD may be formed by a second SEG process, wherein the side surface of the upper stack pattern STP2 exposed by the second trench TR2 is used as a seed layer. The upper source / drain pattern USD may be grown using the second active layer ACL2 exposed by the second trench TR2 as a seed layer. The upper source / drain pattern USD may be doped to have a second conductivity type different from the first conductivity type.

[0120] The second active layer ACL2 between the pair of upper source / drain patterns USD may be used as an upper channel pattern UCH. For example, the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the upper channel pattern UCH may be formed by the second active layer ACL2. The upper channel pattern UCH and the upper source / drain pattern USD may constitute an upper active region UAR as a top layer of a three-dimensional device. The second SEG process may also be performed for a sufficient time so that the space between the pair of upper channel patterns UCH is completely filled with the upper source / drain pattern USD.

[0121] The second interlayer insulating layer 120 may be formed to cover the upper source / drain pattern USD. In various example embodiments, before forming the second interlayer insulating layer 120, an etch stop layer may be further formed to conformally cover the upper source / drain pattern USD.

[0122] Thereafter, the second interlayer insulating layer 120 may be planarized to expose the top surface of the sacrificial pattern PP. The planarization of the second interlayer insulating layer 120 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, all of the hard mask patterns MP on the sacrificial pattern PP may be removed. Thus, the top surface of the second interlayer insulating layer 120 may be coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0123] Reference FIG. 13A to FIG. 13D , the exposed sacrificial pattern PP may be selectively removed. Removing the sacrificial pattern PP may include a wet etching process using an etching solution capable of selectively etching polysilicon. Due to the removal of the sacrificial pattern PP, the first sacrificial layer SAL1 and the second sacrificial layer SAL2 may be exposed.

[0124] An etching process selected to selectively etch the first sacrificial layer SAL1 and the second sacrificial layer SAL2 may be performed to leave the first to fourth semiconductor patterns SP1 to SP4 and the dummy channel pattern DSP and remove only the first and second sacrificial layers SAL1 and SAL2. The etching process may be selected to have a high etching rate for silicon germanium. For example, the etching process may be selected to have a high etching rate for a silicon germanium layer having a germanium concentration higher than 10 at%.

[0125] A gate insulating layer GI may be conformally formed in an empty space formed by removing the sacrificial pattern PP and the first and second sacrificial layers SAL1 and SAL2. A gate electrode GE may be formed on the gate insulating layer GI. The gate electrode GE may include first to fifth internal electrodes PO1 to PO5 between the first to fourth semiconductor patterns SP1 to SP4, and an external electrode PO6 in the empty space formed by removing the sacrificial pattern PP.

[0126] Forming the gate electrode GE may include: filling an empty space formed by removing the sacrificial pattern PP and the first and second sacrificial layers SAL1 and SAL2 with a gate electrode line; forming a recess in an upper portion of the gate electrode line; forming a gate capping line in the recess; forming a third interlayer insulating layer 130 to cover the gate electrode line and the second interlayer insulating layer 120; and forming a cutting groove CTR to cross the gate electrode line in the first direction D1. The gate electrode line may be divided into a plurality of gate electrodes GE by the cutting groove CTR, and the gate capping line may be divided into a plurality of gate capping patterns GP by the cutting groove CTR. The cutting groove CTR may be formed to have a line shape extending along the first direction D1.

[0127] The first cutting portion C1 of the cutting pattern CT may be formed in the cutting trench CTR. The first cutting portion C1 may fill the cutting trench CTR. The first cutting portion C1 may be formed to cross a region between the gate electrodes GE in the first direction D1.

[0128] Reference FIG. 14A to FIG. 14C , a preliminary wide via WVp may be formed in the first cutting portion C1 of the cutting pattern CT. The preliminary wide via WVp may be disposed to penetrate the first cutting portion C1 of the cutting pattern CT in a vertical direction (e.g., a third direction D3). Forming the preliminary wide via WVp may include: forming a first recess RS1 in the first cutting portion C1 of the cutting pattern CT; and filling the first recess RS1 with the preliminary wide via WVp. In various example embodiments, a through via THV may be formed together with the preliminary wide via WVp.

[0129] The preliminary wide via hole WVp may have a flat top surface. In various example embodiments, the top surface of the preliminary wide via hole WVp and the top surface of the first cutting portion C1 may be located at substantially the same level and may be coplanar with each other. The preliminary wide via hole WVp may be formed to completely fill the first recess RS1.

[0130] Reference FIG. 15A to FIG. 15D , the wide via WV may be formed by removing a portion of the preliminary wide via WVp. The empty area formed by removing a portion of the preliminary wide via WVp may be defined as a second recess RS2. The first via portion W1 and the second via portion W2 of the wide via WV may be defined by the second recess RS2. The second via portion W2 may be a portion of the wide via WV that vertically overlaps with the second recess RS2, and the first via portion W1 may be another portion of the wide via WV other than the second via portion W2. The second recess RS2 may be formed in the first recess RS1, and may be defined by the wide via WV and the first cutting portion C1 of the cutting pattern CT.

[0131] In various example embodiments, the height HT2 of the second via portion W2 may be in the range of 20% to 80% of the height HT1 of the first via portion W1. Since the height HT2 of the second via portion W2 is greater than or equal to 20% of the height HT1 of the first via portion W1, the process may be facilitated compared to a case where the second recess RS2 is formed deeper. Since the height HT2 of the second via portion W2 is less than or equal to 80% of the height HT1 of the first via portion W1, a short circuit between the second upper active contact UAC2 and the wide via WV may be effectively prevented.

[0132] As reference Figures 3 to 9BAs described, the first and second via portions W1 and W2 of the wide via WV may be formed to have various structures according to the positions of the first and second recesses RS1 and RS2. However, the structures of the first and second via portions W1 and W2 of the wide via WV are not limited to this example.

[0133] Return to reference Figures 3 to 5E , the second cutting portion C2 of the cutting pattern CT may be formed in the second recess RS2. The second cutting portion C2 may be formed on the second via portion W2 of the wide via WV and may cover the second via portion W2. The second cutting portion C2 may vertically overlap the second via portion W2.

[0134] An upper active contact UAC may be formed to penetrate the second interlayer insulating layer 120 and the third interlayer insulating layer 130, and the upper active contact UAC may be coupled to the upper source / drain pattern USD, respectively. In various example embodiments, a first upper active contact UAC1 may be formed to be electrically connected to the first upper source / drain pattern USD1 and the wide via WV. An upper gate contact UGC may be formed to penetrate the second interlayer insulating layer 120 and the third interlayer insulating layer 130, and the upper gate contact UGC may be coupled to the gate electrode GE.

[0135] A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A first metal layer M1 including an upper interconnect line UMI may be formed in the fourth interlayer insulating layer 140. An upper via UVI may be formed to electrically connect the first metal layer M1 to the gate contact GC and the upper active contact UAC. A BEOL layer including additional metal layers (e.g., M2, M3, M4, etc.) may be formed on the first metal layer M1.

[0136] Thereafter, the semiconductor substrate 105 may be turned over so that the rear surface of the semiconductor substrate 105 is exposed to the outside. The exposed semiconductor substrate 105 may be selectively removed. Thus, the sacrificial contact pattern PLH and the first lower insulating layer LIL1 may be exposed.

[0137] A second lower insulating layer LIL2 may be formed on the exposed sacrificial contact pattern PLH and the exposed first lower insulating layer LIL1. For example, the second lower insulating layer LIL2 may be formed of at least one of silicon-based insulating materials (e.g., silicon oxide, silicon oxynitride, or silicon nitride), or include at least one of silicon-based insulating materials (e.g., silicon oxide, silicon oxynitride, or silicon nitride). In various example embodiments, the second lower insulating layer LIL2 may be formed of the same material as the device isolation layer ST, or include the same material as the device isolation layer ST. The first lower insulating layer LIL1 and the second lower insulating layer LIL2 may constitute a substrate 100. A planarization process may be performed on the substrate 100 to expose the sacrificial contact pattern PLH.

[0138] The sacrificial contact pattern PLH may be replaced with a lower active contact LAC. Specifically, the sacrificial contact pattern PLH may be selectively removed. An etching process may be further performed on the area formed by removing the sacrificial contact pattern PLH to expose the lower source / drain pattern LSD. The lower active contact LAC may be formed to couple to the exposed lower source / drain pattern LSD. The lower active contact LAC may be formed by a self-alignment process using the sacrificial contact pattern PLH. The lower gate contact LGC may be formed to penetrate the substrate 100 and may be coupled to the gate electrode GE.

[0139] A back metal layer BSM may be formed on the lower active contact LAC. The back metal layer BSM may include a lower contact LC, a lower interconnect line LMI, and a lower via LVI. In various example embodiments, a second lower active contact LAC2 may be formed to be electrically connected to the second lower source / drain pattern LSD2 and the wide via WV. An additional back metal layer may be formed on the back metal layer BSM. In various example embodiments, the additional back metal layer may include a power delivery network layer.

[0140] The top surface of the wide via hole can be partially recessed to increase the distance from the wide via hole to the upper active contact portion, which should be disconnected from the wide via hole. Therefore, a short circuit can be prevented from forming between the wide via hole and the upper active contact portion, thereby improving the electrical characteristics and / or reliability characteristics of the three-dimensional semiconductor device.

[0141] Alternatively or additionally, a wide via hole may be used to electrically connect a lower source / drain pattern and an upper source / drain pattern that are horizontally spaced apart from each other, and this may make it possible to increase the degree of freedom in designing a three-dimensional semiconductor device.

[0142] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, the relevant numerical value is intended to include a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but the freedom of the shape is within the scope of the present disclosure. In addition, when the words "generally" and "substantially" are used in conjunction with a material composition, it is intended that the precision of the material is not required, but the freedom of the material is within the scope of the present disclosure.

[0143] In addition, regardless of whether a value or shape is modified as "approximately" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the described values ​​or shapes. Therefore, although the terms "same," "equal," or "equal" are used in the description of example embodiments, it should be understood that there may be some imprecision. Therefore, when an element or a value is referred to as being the same as or equal to another element or value, it should be understood that within the desired manufacturing or operating tolerance range (e.g., ±10%), an element or value is the same as another element or another value.

[0144] Although various example embodiments of the inventive concept have been specifically shown and described, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims. Furthermore, the exemplary embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more drawings, and may also include one or more other features described with reference to one or more other drawings.

Claims

1. A three-dimensional 3D semiconductor device, comprising: Back metal layer; a lower channel pattern on the back metal layer; A first lower source / drain pattern and a second lower source / drain pattern are spaced apart from each other in a first direction, the lower channel pattern is interposed between the first lower source / drain pattern and the second lower source / drain pattern, and the first lower source / drain pattern is connected to the lower channel pattern; an upper channel pattern on the lower channel pattern; a first upper source / drain pattern on the first lower source / drain pattern, the first upper source / drain pattern being connected to the upper channel pattern; a second upper source / drain pattern on the second lower source / drain pattern; as well as wide vias, electrically connecting the first upper source / drain pattern to the second lower source / drain pattern, The wide via includes a first via portion having a first top surface and a second via portion having a second top surface, the second top surface being at a lower level than the first top surface.

2. The 3D semiconductor device according to claim 1, wherein: When viewed in cross-section, the wide via has an "L" shaped profile.

3. The 3D semiconductor device according to claim 1, wherein: The first via portion has a first bottom surface, The second via portion has a second bottom surface, and The first bottom surface and the second bottom surface are at the same level.

4. The 3D semiconductor device according to claim 1, wherein: The first via portion has a first sub-side surface facing the first direction, The second via portion has a second sub-side surface facing the first direction, and The second sub-side surface is offset from the first sub-side surface in the first direction.

5. The 3D semiconductor device according to claim 1, wherein: The first via portion and the second via portion are arranged along the first direction.

6. The 3D semiconductor device according to claim 1, wherein: When measured in a vertical direction, a height of the second via portion is in a range of 20% to 80% of a height of the first via portion.

7. The 3D semiconductor device according to claim 1, further comprising: a first upper active contact electrically connecting the first upper source / drain pattern to the wide via; as well as a second upper active contact electrically connected to the second upper source / drain pattern and electrically disconnected from the wide via, Wherein, the second top surface is at a lower level than a top surface of the second upper active contact.

8. The 3D semiconductor device according to claim 1, further comprising: a gate electrode between the first upper source / drain pattern and the second upper source / drain pattern, The wide via hole is spaced apart from the gate electrode in a second direction intersecting the first direction.

9. The 3D semiconductor device according to claim 8, wherein: When measured along the first direction, the width of the wide via is greater than the width of the gate electrode.

10. The 3D semiconductor device according to claim 8, wherein: The gate electrode includes a plurality of gate electrodes spaced apart from each other in the first direction between the first upper source / drain pattern and the second upper source / drain pattern.

11. The 3D semiconductor device according to claim 1 , further comprising: A fourth upper source / drain pattern is between the first upper source / drain pattern and the second upper source / drain pattern.

12. The 3D semiconductor device according to claim 1, further comprising: Cut the pattern to surround the wide via, Wherein, the cutting pattern covers the second top surface of the second via portion.

13. A three-dimensional 3D semiconductor device, comprising: Back metal layer; a lower channel pattern on the back metal layer; A first lower source / drain pattern and a second lower source / drain pattern are spaced apart from each other in a first direction, the lower channel pattern is interposed between the first lower source / drain pattern and the second lower source / drain pattern, and the first lower source / drain pattern is connected to the lower channel pattern; an upper channel pattern on the lower channel pattern; a first upper source / drain pattern on the first lower source / drain pattern, the first upper source / drain pattern being connected to the upper channel pattern; a second upper source / drain pattern on the second lower source / drain pattern; as well as wide vias, electrically connecting the first upper source / drain pattern to the second lower source / drain pattern, Wherein, a lower portion of the wide via hole protrudes more than an upper portion of the wide via hole in the first direction.

14. The 3D semiconductor device according to claim 13, wherein: The side surface of the wide via hole extends discontinuously in the vertical direction, and The other side surface of the wide via hole extends continuously along the vertical direction.

15. The 3D semiconductor device according to claim 13, wherein: The upper portion of the wide via has a first sub-side surface facing the first direction, The lower portion of the wide via has a second sub-side surface facing the first direction, and The second sub-side surface is offset from the first sub-side surface in the first direction.

16. The 3D semiconductor device according to claim 13, wherein: When measured along the first direction, the width of the lower portion of the wide via is greater than the width of the upper portion.

17. The 3D semiconductor device according to claim 13, further comprising: a first upper active contact electrically connecting the first upper source / drain pattern to the wide via; as well as a second upper active contact electrically connected to the second upper source / drain pattern and electrically disconnected from the wide via, Wherein a top surface of the lower portion of the wide via is at a lower level than a top surface of the second upper active contact.

18. The 3D semiconductor device according to claim 13, further comprising: One or more gate electrodes are between the first upper source / drain pattern and the second upper source / drain pattern.

19. The 3D semiconductor device according to claim 13, further comprising: Cut the pattern to surround the wide via, Wherein, the cutting pattern vertically overlaps with the lower portion of the wide via hole.

20. A three-dimensional 3D semiconductor device, comprising: Back metal layer; A lower channel pattern and an upper channel pattern are sequentially arranged on the back metal layer; a gate electrode intersecting the lower channel pattern and the upper channel pattern; a first lower source / drain pattern connected to the lower channel pattern in a first direction; a first upper source / drain pattern on the first lower source / drain pattern and connected to the upper channel pattern in the first direction; a cutting pattern adjacent to the gate electrode in a second direction intersecting the first direction; as well as a wide via hole in the cutting pattern and electrically connected to the first upper source / drain pattern, The cutting pattern covers a portion of the top surface of the wide via hole.

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