Semiconductor device, semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device, a semiconductor apparatus, and a method for manufacturing the semiconductor device. The semiconductor device includes: a first electrode portion; the channel part is located above the first electrode part and electrically connected with the first electrode part, the channel part comprises a first channel part, and the cross section of the first channel part in the transverse direction is annular; the second electrode part is positioned above the channel part and is electrically connected with the channel part; the grid electrode part comprises a grid medium part and a grid electrode part, the grid medium part is in direct contact with the channel part, the grid electrode part is located on the side, opposite to the channel part, of the grid medium part, and the grid electrode part is located on at least one part of the side wall, extending in the vertical direction, of the channel part.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a semiconductor apparatus, and a method for manufacturing a semiconductor device. Background Art

[0002] With the development of integrated circuit technology, the size of basic devices continues to shrink, and the requirements for channel control capabilities are becoming increasingly higher. In order to keep up with the comprehensive requirements of Moore's Law for performance (speed), power consumption and area benefits, semiconductor devices with stronger short-channel control capabilities are needed to ensure that the channel length of the device can continue to shrink while improving device performance and reducing leakage current. Summary of the Invention

[0003] One of the objectives of the present disclosure is to provide a semiconductor device, a semiconductor apparatus, and a method for manufacturing the semiconductor device.

[0004] According to a first aspect of the present disclosure, there is provided a semiconductor device, comprising:

[0005] a first electrode portion;

[0006] a channel portion, the channel portion being located above the first electrode portion and electrically connected to the first electrode portion, wherein the channel portion includes a first channel portion, and a cross-section of the first channel portion in a transverse direction is annular;

[0007] a second electrode portion, the second electrode portion being located above the channel portion and electrically connected to the channel portion; and

[0008] A gate portion includes a gate dielectric portion directly in contact with the channel portion and a gate electrode portion located on a side of the gate dielectric portion opposite to the channel portion, wherein the gate portion is located on at least a portion of a sidewall of the channel portion extending in a vertical direction.

[0009] In some embodiments, a cross-section of the first channel portion in the transverse direction is in the shape of a circular ring, an elliptical ring, a polygonal ring, a rectangular ring, or a square ring.

[0010] In some embodiments, the gate dielectric portion includes a first gate dielectric portion covering an inner sidewall of the first channel portion extending in the vertical direction and a second gate dielectric portion covering an outer sidewall of the first channel portion extending in the vertical direction; and

[0011] The gate electrode portion at least covers an inner side of the first gate dielectric portion and an outer side of the second gate dielectric portion.

[0012] In some embodiments, inner sidewalls of the first channel portion are completely filled by the gate portion.

[0013] In some embodiments, the channel portion further includes a second channel portion, a cross section of the second channel portion in the lateral direction being located inside the cross section of the first channel portion in the lateral direction.

[0014] In some embodiments, a cross-section of the second channel portion in a lateral direction is circular, elliptical, polygonal, rectangular, or square.

[0015] In some embodiments, the second channel portion is located at the center of the first channel portion.

[0016] In some embodiments, the gate dielectric portion includes a third gate dielectric portion covering an outer sidewall of the second channel portion extending in a vertical direction; and

[0017] The gate electrode portion at least covers an outer side of the third gate dielectric portion.

[0018] In some embodiments, a space between an inner sidewall of the first channel portion and an outer sidewall of the second channel portion is completely filled by the gate portion.

[0019] In some embodiments, the semiconductor device further includes at least one of the following:

[0020] a first contact portion located between the channel portion and the first electrode portion and configured to electrically connect the channel portion and the first electrode portion;

[0021] a second contact portion located between the channel portion and the second electrode portion and configured to electrically connect the channel portion and the second electrode portion;

[0022] a first spacer portion located between the first electrode portion and the gate portion and configured to electrically isolate the first electrode portion from the gate portion; and

[0023] A second spacer is located on a sidewall of the second electrode portion extending in the vertical direction and is configured to electrically isolate the second electrode portion from the gate portion.

[0024] According to a second aspect of the present disclosure, a semiconductor apparatus is provided, comprising the semiconductor device described above.

[0025] In some embodiments, the semiconductor device includes an n-type semiconductor device and a p-type semiconductor device, and the n-type semiconductor device and the p-type semiconductor device are stacked in a vertical direction.

[0026] According to a third aspect of the present disclosure, there is provided a method for preparing a semiconductor device, comprising:

[0027] providing a substrate;

[0028] forming a first electrode material layer, a channel material layer, and a second electrode material layer in sequence on one side of the substrate;

[0029] forming a patterned first mask layer, wherein the first mask layer includes a first mask portion, and a cross section of the first mask portion in a transverse direction is annular;

[0030] Etching the second electrode material layer, the channel material layer, and the first electrode material layer under the protection of the first mask layer to form a second electrode portion, a channel portion, and a first electrode portion, respectively; and

[0031] A gate portion is formed, wherein the gate portion includes a gate dielectric portion directly contacting the channel portion and a gate electrode portion located on a side of the gate dielectric portion opposite to the channel portion, and the gate portion is located on at least a portion of a sidewall of the channel portion extending in a vertical direction.

[0032] In some embodiments, forming the patterned first mask layer includes:

[0033] forming a first sacrificial portion, wherein the first sacrificial portion is in a column shape extending in a vertical direction;

[0034] forming a first retaining portion around an outer sidewall of the first sacrificial portion; and

[0035] The first sacrificial portion is removed, and the first remaining portion is used as the first mask portion of the first mask layer.

[0036] In some embodiments, the first mask layer further includes a second mask portion, wherein a cross section of the second mask portion in the lateral direction is located inside a cross section of the first mask portion in the lateral direction.

[0037] In some embodiments, forming the patterned first mask layer includes:

[0038] forming a second reserved portion, wherein the second reserved portion is in a column shape extending in a vertical direction;

[0039] forming a second sacrificial portion around an outer side wall of the second retaining portion;

[0040] forming a third retaining portion around an outer side wall of the second sacrificial portion; and

[0041] The second sacrificial portion is removed, and the third reserved portion is used as the first mask portion of the first mask layer, and the second reserved portion is used as the second mask portion of the first mask layer.

[0042] In some embodiments, forming the patterned first mask layer includes:

[0043] forming a third sacrificial portion, wherein the third sacrificial portion is in a column shape extending in a vertical direction;

[0044] forming a fourth retaining portion around the outer side wall of the third sacrificial portion;

[0045] removing the third sacrificial portion and using the fourth reserved portion as the first mask portion of the first mask layer;

[0046] forming a fourth sacrificial portion around the inner and outer walls of the fourth retaining portion, wherein at least a portion of the space inside the fourth retaining portion is not filled by the fourth sacrificial portion to form an opening extending in the vertical direction;

[0047] forming a fifth retaining portion in the opening; and

[0048] The fourth sacrificial portion is removed, and the fifth remaining portion is used as the second mask portion of the first mask layer.

[0049] In some embodiments, the first electrode material layer, the channel material layer, and the second electrode material layer are formed of a silicon-based material or a silicon-germanium-based material, the first electrode material layer and the second electrode material layer have the same doping type, the channel material layer and the first electrode material layer have the same or opposite doping type, the channel material layer has a lower doping concentration than the first electrode material layer, and the channel material layer has a lower doping concentration than the second electrode material layer; or

[0050] The first electrode material layer and the second electrode material layer are formed of a metal material, and the channel material layer is formed of a metal oxide material.

[0051] In some embodiments, the method further comprises:

[0052] forming a first electrode material layer and a channel material layer on one side of the substrate, and forming a first contact material layer between the first electrode material layer and the channel material layer; and

[0053] forming a channel material layer and a second electrode material layer on one side of the substrate, and forming a second contact material layer between the channel material layer and the second electrode material layer;

[0054] Before etching the second electrode material layer and the channel material layer under the protection of the first mask layer, etching the second contact material layer to form a second contact portion, wherein the second contact portion is configured to electrically connect the channel portion and the second electrode portion; and

[0055] Before etching the channel material layer and the first electrode material layer under the protection of the first mask layer, the first contact material layer is etched to form a first contact portion, where the first contact portion is configured to electrically connect the channel portion and the first electrode portion.

[0056] In some embodiments, the method further comprises:

[0057] Before forming the gate portion, a patterned first spacer portion is formed, wherein a first spacer material of the first spacer portion covers a portion of the upper surface of the first electrode portion not covered by the channel portion, and the upper surface of the first spacer portion is substantially flush with the lower surface of the channel portion.

[0058] In some embodiments, forming the gate portion includes:

[0059] forming a gate dielectric material layer at least along exposed surfaces of the first spacer, the channel portion, and the second electrode portion, wherein at least a portion of the gate dielectric material layer serves as a gate dielectric portion directly contacting the channel portion;

[0060] A patterned gate electrode portion is formed, wherein the gate electrode portion is located on a side of the gate dielectric portion opposite to the channel portion, and an upper surface of the gate electrode portion is substantially flush with an upper surface of the channel portion.

[0061] In some embodiments, the method further comprises:

[0062] After forming the patterned gate electrode portion, a patterned second spacer is formed, wherein the second spacer material of the second spacer covers the portion of the sidewall extending in the vertical direction of the second electrode portion covered by the gate dielectric material layer.

[0063] In some embodiments, the method further comprises:

[0064] After forming the patterned second spacer, forming a patterned first passivation layer, wherein an upper surface of the first passivation layer is substantially flush with an upper surface of the second electrode portion;

[0065] forming a second passivation layer, wherein the second passivation layer covers the first passivation layer and the second electrode portion; and

[0066] A gate connection portion for electrical connection to the gate electrode portion is formed in the first passivation layer, and a second electrode connection portion for electrical connection to the second electrode portion is formed in the second passivation layer.

[0067] In some embodiments, the method further comprises:

[0068] After forming the patterned second spacers, forming a patterned first passivation layer, wherein an upper surface of the first passivation layer is substantially flush with an upper surface of the second spacers;

[0069] Partially etching the second electrode material so that the remaining second electrode material forms a second electrode portion, and a recessed space is formed between an upper surface of the second electrode portion and an upper surface of the first passivation layer;

[0070] forming a patterned second passivation layer in the recessed space, wherein an upper surface of the second passivation layer is substantially flush with an upper surface of the first passivation layer; and

[0071] A gate connection portion for electrical connection to the gate electrode portion is formed in the first passivation layer, and a second electrode connection portion for electrical connection to the second electrode portion is formed in the second passivation layer.

[0072] In some embodiments, the method further comprises:

[0073] After forming the patterned second spacer portion, forming an electrode connection material layer, wherein an upper surface of the electrode connection material layer is located above an upper surface of the second electrode portion;

[0074] forming a second passivation layer above the electrode connection material layer;

[0075] performing patterned etching on the second passivation layer and the electrode connection material layer to retain only portions of the second passivation layer and the electrode connection material layer located above the second electrode portion; and

[0076] A patterned first passivation layer is formed, wherein an upper surface of the first passivation layer is substantially flush with an upper surface of the second passivation layer.

[0077] In some embodiments, the method further comprises:

[0078] After forming the patterned second spacer, partially etching the second electrode material so that the remaining second electrode material forms a second electrode portion, and a recessed space is formed between an upper surface of the second electrode portion and an upper surface of the second spacer;

[0079] forming an electrode connection material layer, wherein an upper surface of the electrode connection material layer is substantially flush with an upper surface of the second spacer;

[0080] forming a second passivation layer above the electrode connection material layer, wherein the second passivation layer is in direct contact with the second spacer;

[0081] The second passivation layer is pattern-etched to form a gate connection portion connected to the gate electrode portion and a second electrode connection portion connected to the second electrode portion, which are insulated from each other.

[0082] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0084] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0085] Figure 1 FIG2 shows a schematic cross-sectional structure diagram of a semiconductor device in a vertical direction according to a first exemplary embodiment of the present disclosure;

[0086] Figure 2 Shown Figure 1 A schematic diagram of a cross-sectional structure of a channel portion and a gate portion of a semiconductor device in a lateral direction;

[0087] Figure 3 FIG2 shows a schematic cross-sectional structure diagram of a semiconductor device in a vertical direction according to a second exemplary embodiment of the present disclosure;

[0088] Figure 4 FIG2 shows a schematic cross-sectional structure diagram of a semiconductor device in a vertical direction according to a third exemplary embodiment of the present disclosure;

[0089] Figure 5 Shown Figure 4 A schematic diagram of a cross-sectional structure of a channel portion and a gate portion of a semiconductor device in a lateral direction;

[0090] Figure 6 FIG2 shows a schematic cross-sectional structure diagram of a semiconductor device in a vertical direction according to a fourth exemplary embodiment of the present disclosure;

[0091] Figure 7 FIG2 shows a schematic cross-sectional structure diagram of a semiconductor device in a vertical direction according to a fifth exemplary embodiment of the present disclosure;

[0092] Figure 8 FIG2 shows a schematic cross-sectional structure diagram of a semiconductor device in a vertical direction according to an exemplary embodiment of the present disclosure;

[0093] Figure 9 A schematic flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure is shown;

[0094] Figure 10 A schematic diagram of a process for forming a patterned first mask layer according to a specific embodiment of the present disclosure is shown;

[0095] Figure 11 FIG2 shows a schematic diagram of a process of forming a patterned first mask layer according to another specific embodiment of the present disclosure;

[0096] Figure 12 FIG2 shows a schematic diagram of a process of forming a patterned first mask layer according to another specific embodiment of the present disclosure;

[0097] Figure 13(a) to Figure 13(g) Shown for preparation Figure 1 Schematic diagram of part of the process of semiconductor devices;

[0098] Figure 14(a) to Figure 14(b) Shown for preparation Figure 3 Schematic diagram of part of the process of semiconductor devices;

[0099] Figure 15(a) to Figure 15(i) Shown for preparation Figure 4 Schematic diagram of part of the process of semiconductor devices;

[0100] Figure 16(a) to Figure 16(d) Shown for preparation Figure 6 Schematic diagram of part of the process of semiconductor devices;

[0101] Figure 17(a) to Figure 17(i) Shown for preparation Figure 7 Schematic diagram of part of the process of semiconductor devices.

[0102] Note that in the embodiments described below, the same reference numerals are sometimes used in common across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0103] To facilitate understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like may not always represent actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components. DETAILED DESCRIPTION

[0104] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0105] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the present disclosure and its application or use. Those skilled in the art will appreciate that these are merely exemplary, rather than exhaustive, descriptions of exemplary methods that may be used to implement the present disclosure.

[0106] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0107] At present, a variety of structures for semiconductor devices have been proposed to achieve the desired device performance. For example, in early semiconductor devices such as transistors, a single gate is usually used to control the channel. Then, it gradually evolved to use a double-gate or tri-gate to control the channel. The physical mechanism of this device structure evolution is to increase the number of gates from different directions to improve the control ability of the gate over the channel, so as to suppress the short channel effect and reduce the leakage current caused by the miniaturization of the channel length, while allowing the diversity and controllability of the threshold voltage to adapt to the power consumption and performance requirements of different types of circuits. However, at process nodes below 3nm, due to the high height of the fins in the fin transistor (FinFET) (in order to avoid the decrease in mobility, the width of the fin remains basically unchanged), the gate's control over the channel is weakened, resulting in excessive leakage current in the device and difficulty in further miniaturization of the channel length. Moreover, in FinFET, the process capability of manufacturing vertical channels has also reached its limit. The width fluctuation and edge roughness (LER) of the fins are high, and the channel aspect ratio is large, which makes the fins prone to bending or deformation, reducing the reliability of the device.

[0108] In order to solve the above problems, the structure of semiconductor devices has further evolved towards a gate-all-around (GAA) structure. Currently, the industry is mainly considering GAA devices with horizontal channels. In the exemplary embodiments of the present disclosure, Figures 1 to 7 As shown, a semiconductor device including a vertical channel may include a first electrode portion 110, a channel portion 200, a second electrode portion 120, and a gate portion 300. The channel portion 200 may be located above and electrically connected to the first electrode portion 110, the second electrode portion 120 may be located above and electrically connected to the channel portion 200, and the gate portion 300 may include a gate dielectric portion 310 directly in contact with the channel portion 200 and a gate electrode portion 320 located on a side of the gate dielectric portion 310 opposite the channel portion 200. The gate portion 300 may be located on at least a portion of a vertically extending sidewall of the channel portion 200. In other words, the first electrode portion 110, the channel portion 200, and the second electrode portion 120 may be stacked in sequence in the vertical direction, and the gate portion 300 may be disposed around at least a portion of the channel portion 200. The gate portion 300 may be used to control the on / off state of the channel portion 200 . In addition, current may flow in the channel portion 200 along a vertical direction under the action of the voltage difference between the first electrode portion 110 and the second electrode portion 120 .

[0109] In some embodiments of the present disclosure, Figures 1 to 3 As shown, the channel portion 200 may include a first channel portion 210, and the cross section of the first channel portion 210 in the transverse direction may be annular. Accordingly, at least the portion of the first electrode portion 110 and the second electrode portion 120 that is in direct contact with the first channel portion 210 may also be annular. Figure 1 and Figure 3 As shown, the gate dielectric portion 310 may include a first gate dielectric portion 311 covering the inner sidewall of the first channel portion 210 extending in the vertical direction and a second gate dielectric portion 312 covering the outer sidewall of the first channel portion 210 extending in the vertical direction. Accordingly, the gate electrode portion 320 may cover at least the inner side of the first gate dielectric portion 311 and the outer side of the second gate dielectric portion 312 to achieve enhanced control of the channel. Further, in some embodiments, as Figures 1 to 3 As shown, the inner sidewall of the first channel portion 210 can be completely filled with the gate portion 300. In other words, at least a portion of the gate portion 300 can fill the space inside the ring of the first channel portion 210. Figures 1 to 3As shown, the outer side of the annular first channel portion 210 may also be surrounded by a corresponding portion of the gate portion 300. In this way, the first channel portion 210 is controlled by the gate portion 300 both inside and outside the ring, thereby having a good gate control capability in the semiconductor device, helping to effectively shut down the semiconductor device, thereby reducing the leakage current of the semiconductor device in the off state, and further miniaturizing the vertical channel length.

[0110] In some embodiments, the cross-section of the first channel portion 210 in the lateral direction may be circular, elliptical, polygonal, rectangular, square, or other types of rings, without limitation. In addition, in some embodiments, the shape and size of the cross-section of the first channel portion 210 in the lateral direction may remain unchanged or substantially unchanged along the vertical direction, that is, the inner and outer sidewalls of the first channel portion 210 may extend vertically in the vertical direction to fully utilize the area in the semiconductor device or chip and improve the integration of the semiconductor device or chip. In some embodiments, the gate portion 300 may be symmetrically arranged around the channel portion 200, thereby achieving symmetrical control of the electric field and carrier concentration in the channel portion 200 and improving the channel control capability.

[0111] In some embodiments, the first channel portion 210 may be in the form of a nanoring. A characteristic dimension may be used to characterize the size of the cross-section of the first channel portion 210 in the lateral direction. For example, if the cross-section of the first channel portion 210 in the lateral direction is circular, the outer diameter of the circular ring may be used as the characteristic dimension; if the cross-section of the first channel portion 210 in the lateral direction is square, the side length of the square may be used as the characteristic dimension; if the cross-section of the first channel portion 210 in the lateral direction is other shapes, the corresponding characteristic dimension may be defined as needed. Furthermore, in some embodiments, the minimum distance between the outer sidewalls of two adjacent first channel portions 210 in the lateral direction may be used as the spacing between the two first channel portions 210 in the lateral direction. It will be appreciated that as the characteristic dimension of the cross-section of the first channel portion in the lateral direction or the spacing between two adjacent first channel portions in the lateral direction decreases, the integration density of a semiconductor device or chip containing such a semiconductor device may increase.

[0112] In other embodiments of the present disclosure, Figures 4 to 7 As shown, in addition to the first channel portion 210, the channel portion 200 may also include a second channel portion 220, the cross-section of which in the lateral direction may be located on the inner side of the cross-section of the first channel portion 210 in the lateral direction, or in other words, the first channel portion 210 may surround the outer side of the second channel portion 220.

[0113] Accordingly, if Figures 4 to 7 As shown, the gate dielectric portion 310 may include a third gate dielectric portion 313 that covers the outer sidewalls of the second channel portion 220 extending in the vertical direction, and the gate electrode portion 320 may at least cover the outer side of the third gate dielectric portion 313 to achieve control of the channel of the semiconductor device. Furthermore, in some embodiments, the gate portion 300 may completely fill the space between the inner sidewalls of the first channel portion 210 and the outer sidewalls of the second channel portion 220. In other words, at least a portion of the gate portion 300 may fill the space between the annular first channel portion 210 and the pillar-shaped second channel portion 220.

[0114] Furthermore, in some embodiments, the second channel portion 220 may be located at the center of the first channel portion 210. Thus, the spacing between the inner sidewall of the first channel portion 210 and the outer sidewall of the second channel portion 220 may be uniform or substantially uniform. Accordingly, the gate portion 300 may be symmetrically disposed between the first channel portion 210 and the second channel portion 220 and outside the first channel portion 210. This allows for symmetrical control of the electric field and carrier concentration in the channel portion 200, improving gate control capability and reducing the difficulty of device fabrication.

[0115] exist Figures 4 to 7 In the illustrated embodiment, the inner second channel portion 220 is primarily controlled by the portion of the gate portion 300 located between the first channel portion 210 and the second channel portion 220 (due to electromagnetic shielding, the second channel portion 220 is substantially uncontrolled by the portion of the gate portion 300 surrounding the outer portion of the first channel portion 210). The outer first channel portion 210, on the other hand, is controlled not only by the portion of the gate portion 300 located between the first channel portion 210 and the second channel portion 220, but also by the portion of the gate portion 300 surrounding the outer portion of the first channel portion 210. In this way, both channel portions (the first channel portion 210 and the second channel portion 220) in the semiconductor device can achieve a good gate control effect, thereby effectively reducing the total leakage current of the semiconductor device in the off state and further miniaturizing the vertical channel length. It is understood that the leakage current in a semiconductor device having both the first channel portion 210 and the second channel portion 220 may be slightly greater than the leakage current in a semiconductor device having only the first channel portion 210. However, at the same time, due to the presence of the second channel portion 220, compared with a semiconductor device having only the first channel portion 210, the on-state current of the semiconductor device having both the first channel portion 210 and the second channel portion 220 can be larger in the on state, thereby helping to improve the speed and other performance of the semiconductor device.

[0116] In some embodiments, the cross-section of the second channel portion 220 in the lateral direction may be circular, elliptical, polygonal, rectangular, square, or other shapes, without limitation. Alternatively, the second channel portion 220 may be in the shape of a solid column or line. Furthermore, in some embodiments, the cross-section shape and size of the second channel portion 220 in the lateral direction may remain unchanged or substantially unchanged along the vertical direction, i.e., the outer sidewalls of the second channel portion 220 may extend vertically in the vertical direction, thereby fully utilizing the area of ​​the semiconductor device or chip and improving the integration density of the semiconductor device or chip.

[0117] In some embodiments, the second channel portion 220 may be in the form of a nanowire or a nanopillar. Similarly, the characteristic dimension may be used to characterize the size of the cross-section of the second channel portion 220 in the lateral direction. For example, if the cross-section of the second channel portion 220 in the lateral direction is circular, the diameter of the circle may be used as the characteristic dimension; if the cross-section of the second channel portion 220 in the lateral direction is square, the side length of the square may be used as the characteristic dimension; if the cross-section of the second channel portion 220 in the lateral direction is other shapes, the corresponding characteristic dimension may be defined as needed. For example, the minimum distance in the lateral direction between the inner sidewall of the first channel portion 210 and the outer sidewall of the second channel portion 220 may be used as the spacing in the lateral direction between the adjacent sidewalls of the first channel portion 210 and the second channel portion 220. It is understood that as the characteristic dimension of the cross-section of the second channel portion in the lateral direction decreases, the spacing between the inner sidewall of the first channel portion and the outer sidewall of the second channel portion may increase, thereby helping to improve the structural reliability of the semiconductor device. However, due to the reduction in the characteristic dimension of the second channel portion, the on-state current of the semiconductor device in the on state may also decrease accordingly. Therefore, the relative dimensions and spacing between the first and second channel portions can be determined as needed.

[0118] In some embodiments, having Figures 1 to 3 The on-state current of the semiconductor device having only the first channel portion but no second channel portion as shown may be relatively small, and the semiconductor device can be used as a display device or a memory device, etc.; Figures 4 to 7 The on-state current in the semiconductor device shown, which has both the first channel portion and the second channel portion, may be relatively large, and accordingly the performance of the semiconductor device is good, and thus it can be used as a logic device, etc.

[0119] In some embodiments, the semiconductor device may be a device formed based on silicon (Si) or silicon germanium (SiGe). For example, the channel portion of the semiconductor device may be formed of a silicon or silicon germanium-based material having a first doping type (e.g., p-type or n-type) and a relatively low doping concentration, or may be formed of an undoped silicon or silicon germanium-based material; and the first electrode portion and the second electrode portion may be formed of a silicon or silicon germanium-based material having a second doping type (e.g., n-type or p-type) opposite to the first doping type and a relatively high doping concentration. In such a device, there is generally good contact between the first electrode portion, the second electrode portion and the channel portion, for example, substantially ohmic contact. Therefore, in such a semiconductor device, the channel portion can be made in direct contact with the first electrode portion and the second electrode portion, respectively, to obtain better performance.

[0120] In some other embodiments, the semiconductor device may be a junctionless device formed based on silicon (Si) or silicon germanium (SiGe). For example, the channel portion 200 of the semiconductor device may be formed of a silicon- or silicon-germanium-based material having a first doping type (e.g., p-type or n-type) and a high doping concentration; while the first electrode portion and the second electrode portion may be formed of a silicon- or silicon-germanium-based material having the same doping type as the first doping type (e.g., p-type or n-type) and a relatively higher doping concentration.

[0121] In other embodiments, semiconductor devices may also be formed based on other material systems. For example, the channel portion of a semiconductor device may be formed using materials such as metal oxides, which may include but are not limited to indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and the like. In addition, a first electrode portion and a second electrode portion of a semiconductor device may be formed using materials such as metals. However, in such a device, a Schottky barrier may exist between the first electrode portion, the second electrode portion, and the channel portion, resulting in less than ideal electrical contact between the channel portion and the electrode portion, thereby reducing the on-state current of the semiconductor device and affecting the performance of the semiconductor device.

[0122] In order to solve the above-mentioned contact problem, in some embodiments, as Figure 1 、 Figure 3 and Figure 7As shown, the semiconductor device may further include at least one of a first contact portion 410 and a second contact portion 420. The first contact portion 410 may be located between the channel portion 200 and the first electrode portion 110 and configured to electrically connect the channel portion 200 and the first electrode portion 110, thereby reducing the contact barrier between the first electrode portion 110 and the channel portion 200, improving the contact effect, and helping to increase the on-state current of the semiconductor device. Similarly, the second contact portion 420 may be located between the channel portion 200 and the second electrode portion 120 and configured to electrically connect the channel portion 200 and the second electrode portion 120, thereby reducing the contact barrier between the second electrode portion 120 and the channel portion 200, improving the contact effect, and helping to increase the on-state current of the semiconductor device. The material of the first contact portion 410 may depend on the materials of the channel portion 200 and the first electrode portion 110. Similarly, the material of the second contact portion 420 may depend on the materials of the channel portion 200 and the second electrode portion 120. In a specific example, the material of the first contact portion 410 and / or the second contact portion 420 may include, but is not limited to, titanium nitride.

[0123] In some embodiments, in order to prevent leakage between the source (one of the first electrode portion and the second electrode portion), the drain (the other of the first electrode portion and the second electrode portion) and the gate (gate portion) in the semiconductor device, corresponding spacers may be provided. Figure 1 、 Figure 3 、 Figure 4 、 Figure 6 and Figure 7 As shown, the semiconductor device may further include a first spacer 510, which may be located between the first electrode portion 110 and the gate portion 300 and configured to electrically isolate the first electrode portion 110 and the gate portion 300 to avoid undesirable leakage or breakdown. Figure 1 、 Figure 3 、 Figure 4 、 Figure 6 and Figure 7 As shown, the semiconductor device may further include a second spacer 520, which may be located on a vertically extending sidewall of the second electrode portion 120 and configured to electrically isolate the second electrode portion 120 from the gate portion 300 to prevent undesirable leakage or breakdown. It will be appreciated that the first spacer 510 and the second spacer 520 may be formed of a dielectric material to achieve the desired electrical isolation effect.

[0124] Furthermore, in some embodiments, Figure 1 、 Figure 3 、 Figure 4 、 Figure 6 and Figure 7As shown, in order to facilitate connecting the first electrode portion 110, the second electrode portion 120, and the gate portion 300 of the semiconductor device to an external circuit, corresponding first electrode connecting portions 810, second electrode connecting portions 820, and gate connecting portions 830 may be further provided. In addition, in order to protect the semiconductor device from the adverse effects of oxygen, water, dust, etc. in the air, corresponding passivation layers (for example, the first passivation layer 610 and / or the second passivation layer 620 described below) may be further provided to cover the exposed surface of the semiconductor device, thereby improving the reliability of the semiconductor device and extending its service life.

[0125] According to another aspect of the present disclosure, a semiconductor device is also provided, which may include the semiconductor device described above. Figure 8 As shown, the semiconductor device may include multiple semiconductor devices, which may be electrically connected to each other to achieve the desired function in a coordinated manner. In some embodiments, the semiconductor device may include different types of semiconductor devices, such as n-type semiconductor devices (e.g., NMOS) and p-type semiconductor devices (e.g., PMOS). In addition, in some embodiments, n-type semiconductor devices and p-type semiconductor devices may be stacked in a vertical direction. For example, Figure 8 The upper semiconductor device can be an n-type semiconductor device, and the lower semiconductor device can be a p-type semiconductor device, or vice versa. The different types of semiconductor devices can be electrically connected to each other in a desired manner (not shown in the figure) to form a circuit such as a CMOS, thereby achieving the desired function. Vertically stacking semiconductor devices helps improve the area utilization efficiency of semiconductor devices or chips, and realizes three-dimensional integrated semiconductor devices or devices.

[0126] In the process of preparing such a semiconductor device, two types of semiconductor devices can be prepared independently first, and then multiple devices can be stacked through a bonding process, or multiple devices can be stacked through non-bonding three-dimensional process integration (monolithic 3D integration), which is not limited here.

[0127] Furthermore, if it is necessary to insert conductive connections, such as metal, between semiconductor devices at different vertical locations, different methods can be employed for semiconductor devices or apparatuses made of different material systems. For example, for silicon-based devices, one can consider first epitaxially growing a sacrificial layer, such as a silicon-germanium layer, between an n-type semiconductor device and a p-type semiconductor device. Then, a hole can be excavated from the side to expose the silicon-germanium sacrificial layer. Lateral selective etching can then be used to hollow out the silicon-germanium sacrificial layer, and finally, a conductive material, such as metal, can be filled in. Similar operations can be performed for silicon-germanium-based devices, with the difference being that a silicon-germanium sacrificial layer with a higher germanium concentration must be selected to avoid undesirable attack on the silicon-germanium channel with a lower germanium concentration during lateral etching of the sacrificial layer.

[0128] Furthermore, if a dielectric layer needs to be inserted between semiconductor devices at different vertical locations, different methods can be used for semiconductor devices or apparatuses of different material systems. Similarly, for silicon-based devices, a Germanium-Si sacrificial layer can first be epitaxially grown between an n-type semiconductor device and a p-type semiconductor device. A hole can then be excavated from the side to expose the Germanium-Si sacrificial layer. The Germanium-Si sacrificial layer can then be hollowed out using lateral selective etching, and finally filled with dielectric material. Similar operations can be performed for Germanium-Si based devices, with the difference being that a Germanium-Si sacrificial layer with a higher Germanium concentration needs to be selected to avoid undesired attack on the Germanium-Si channel with a lower Germanium concentration during the lateral etching of the sacrificial layer.

[0129] According to another aspect of the present disclosure, a method for preparing a semiconductor device is also provided to prepare the semiconductor device or semiconductor apparatus as described above. In an exemplary embodiment of the present disclosure, as Figure 9 As shown, a method for preparing a semiconductor device may include:

[0130] Step S910, providing a substrate;

[0131] Step S920, forming a first electrode material layer, a channel material layer, and a second electrode material layer in sequence on one side of the substrate;

[0132] Step S930: forming a patterned first mask layer, wherein the first mask layer may include a first mask portion, wherein a cross-section of the first mask portion in a lateral direction is annular (it should be noted that, in this document, a mask refers to a thin layer used to provide protection, filling, or shielding in an etching process, and does not refer to a photomask used in a photolithography process to form a desired circuit layout);

[0133] Step S940, etching the second electrode material layer, the channel material layer, and the first electrode material layer under the protection of the first mask layer to form a second electrode portion, a channel portion, and a first electrode portion, respectively; and

[0134] In step S950, a gate portion is formed, wherein the gate portion may include a gate dielectric portion in direct contact with the channel portion and a gate electrode portion located on a side of the gate dielectric portion opposite to the channel portion, and the gate portion may be located on at least a portion of a sidewall of the channel portion extending in a vertical direction.

[0135] Furthermore, in some embodiments, if a first contact portion is required to be formed, the method may further include: forming a first contact material layer between the first electrode material layer and the channel material layer on one side of the substrate, thereby forming a first contact material layer located between the first electrode material layer and the channel material layer; and etching the first contact material layer under the protection of the first mask layer before etching the channel material layer and the first electrode material layer to form a first contact portion, wherein the first contact portion is configured to electrically connect the channel portion and the first electrode portion to improve contact therebetween. Similarly, in some embodiments, if a second contact portion is required to be formed, the method may further include: forming a second contact material layer between the channel material layer and the second electrode material layer on one side of the substrate, thereby forming a second contact material layer located between the channel material layer and the second electrode material layer; and etching the second contact material layer under the protection of the first mask layer before etching the second electrode material layer and the channel material layer to form a second contact portion, wherein the second contact portion is configured to electrically connect the channel portion and the second electrode portion to improve electrical contact therebetween.

[0136] In the process of forming a semiconductor device having a nanoring structure or having both a nanoring and a nanowire structure as described above, one of the key points is how to form nanorings and / or nanowires with desired sizes. In an exemplary embodiment of the present disclosure, the second electrode material layer, the second contact material layer (if present), the channel material layer, the first contact material layer (if present) and the first electrode material layer can be etched under the protection of the first mask layer to form a second electrode portion, a second contact portion (if present), a channel portion, a first contact portion (if present) and a first electrode portion, respectively. It is understandable that the structure and size of the second electrode portion, the second contact portion (if present), the channel portion, the first contact portion (if present) and the first electrode portion formed are directly related to the structure and size of the patterned first mask layer. A variety of methods can be used to form a first mask layer having a nanoring and / or nanowire structure, and the following three methods are described in detail herein.

[0137] Figure 10 FIG. 8 shows how a patterned first mask layer 892 is formed in a specific embodiment of the present disclosure, wherein Figure 10 The three figures in the middle and upper part respectively represent the top views during the process of forming the first mask layer, and Figure 10The three figures in the middle and lower parts respectively represent side views taken along the dotted lines in the corresponding top views (the bottommost box in the side views represents the substrate carrying the first mask layer 892). Figure 10 It can be seen that forming a patterned first mask layer 892 may include forming a first sacrificial portion 8921, wherein the first sacrificial portion 8921 may be in the shape of a column extending in the vertical direction. In order to form a plurality of first sacrificial portions 8921, each of which has a nanometer-scale size and can be arranged in a rectangular array, a "crossbar" process can be used. Then, forming a patterned first mask layer 892 may include forming a first reserved portion 8922 around the outer wall of the first sacrificial portion 8921. Finally, the first sacrificial portion 8921 may be removed, and the first reserved portion 8922 may be used as the first mask portion of the first mask layer 892. As shown in FIG. Figure 10 As shown, the cross section of the first mask portion in the lateral direction is ring-shaped. Accordingly, a semiconductor device having a nano-ring structure can be formed under its protection.

[0138] In some embodiments, in order to realize a semiconductor device having a hybrid channel including both a nanoring channel and a nanowire channel, the first mask layer 892 may further include a second mask portion, the cross-section of which in the lateral direction may be located on the inner side of the cross-section of the first mask portion in the lateral direction. Figure 11 FIG. 8 shows how to form a patterned first mask layer 892 in another embodiment of the present disclosure. Figure 10 similar, Figure 11 The four figures in the middle and upper part respectively represent the top views during the process of forming the first mask layer, and Figure 11 The four figures in the middle and lower parts respectively represent the side views taken along the dotted lines in the corresponding top views. Figure 11 As can be seen, forming a patterned first mask layer 892 can include forming a second retained portion 8923, wherein the second retained portion 8923 can be in the shape of a column extending in the vertical direction. Similarly, a crossbar process can be used to form an array of second retained portions 8923 having a desired size. Subsequently, forming a patterned first mask layer 892 can include: forming a second sacrificial portion 8924 around the outer sidewalls of the second retained portion 8923; forming a third retained portion 8925 around the outer sidewalls of the second sacrificial portion 8924; and removing the second sacrificial portion 8924, and using the third retained portion 8925 as the first mask portion of the first mask layer, and using the second retained portion 8923 as the second mask portion of the first mask layer. In this way, under the protection of the first mask portion, the nanoring structure portion of the semiconductor device can be formed, while under the protection of the second mask portion, the nanowire structure portion of the semiconductor device can be formed.

[0139] In another specific embodiment of the present disclosure, the following Figure 12 The patterned first mask layer 892 is formed in the manner shown, wherein Figure 12 The six figures in the two upper rows respectively represent top views during the process of forming the first mask layer, and Figure 12 The bottom picture shows the side view of the first mask layer finally formed. Figure 12 As can be seen, forming the patterned first mask layer 892 can include forming third sacrificial portions 8926, wherein the third sacrificial portions 8926 can be in the form of columns extending in the vertical direction. Similarly, a crossbar process can be used to form an array of third sacrificial portions 8926 having desired nanometer-scale dimensions. Subsequently, forming the patterned first mask layer 892 can further include: forming fourth reserved portions 8927 around the outer sidewalls of the third sacrificial portions 8926; removing the third sacrificial portions 8926 and using the fourth reserved portions 8927 as the first mask portion of the first mask layer. Further, forming the patterned first mask layer 892 can include forming fourth sacrificial portions 8928 around the inner and outer sidewalls of the fourth reserved portions 8927, wherein at least a portion of the space inside the fourth reserved portions 8927 is not filled by the fourth sacrificial portions 8927, thereby forming an opening extending in the vertical direction. For example, the fourth remaining portion 8927 can be used as a core, and fourth sacrificial portions 8928 can be grown on its inner and outer side walls, respectively. The opening can be retained by controlling the growth amount of the fourth sacrificial portions 8928. Finally, a fifth remaining portion 8929 can be formed in the opening; the fourth sacrificial portion 8927 can be removed, and the fifth remaining portion 8929 can be used as the second mask portion of the first mask layer.

[0140] The various retained portions described above may be formed of a mask material suitable for use as a mask, and these mask materials may be retained or at least partially retained in a subsequent etching process. As desired, the mask material may include a soft mask material (such as, but not limited to, photoresist) or a hard mask material (such as, but not limited to, silicon nitride). Furthermore, the various sacrificial portions described above may be formed of a sacrificial material different from the mask material, and the sacrificial material may be selectively removed by a corresponding etching method (such as, but not limited to, wet etching) to form the desired structure.

[0141] The following describes the methods for preparing Figure 1 、 Figure 3 、 Figure 4 、 Figure 6 and Figure 7 It is understood that, without any contradiction, some steps in the following specific method may be omitted or replaced, or, if necessary, additional steps may be added to complete the preparation of the semiconductor device, which is not limited here.

[0142] In order to prepare Figure 1 The semiconductor device shown in FIG13( a ) may be provided with a substrate 700. Then, a first electrode material layer 110 ′, a first contact material layer 410 ′, a channel material layer 200 ′, a second contact material layer 420 ′ and a second electrode material layer 120 ′ may be sequentially formed on one side of the substrate 700. Then, reference may be made to the above description of Figure 10 The patterned first mask layer 892 is formed in the manner shown. The first mask layer 892 may include a first mask portion, and the cross section of the first mask portion in the lateral direction may be annular. In some examples, the first mask layer 892 may be directly formed on the second electrode material layer 120' (i.e. Figure 10 The substrate shown in FIG can be the upper surface of the second electrode material layer 120 '). Alternatively, as shown in FIG13 (a), a second mask layer 891 (i.e. Figure 10 The substrate shown in FIG may be a second mask layer 891), and then a first mask layer 892 is formed on the upper surface of the second mask layer 891. Here, the second mask layer 891 may be formed of a hard mask material to enhance the selectivity of the subsequent etching process and improve the etching effect.

[0143] As shown in FIG13( b ), the second electrode material layer 120 ′, the second contact material layer 420 ′, the channel material layer 200 ′, the first contact material layer 410 ′, and the first electrode material layer 110 ′ can then be etched in sequence under the protection of the first mask layer 892 (and the second mask layer 891 (if present)) to form the second electrode portion 120 , the second contact portion 420 , the channel portion 200 , the first contact portion 410 , and the first electrode portion 110 , respectively. In the specific example shown in FIG13( b ), it can be seen that, after etching, the annular second electrode portion 120 , the second contact portion 420 , the channel portion 200 , and the first contact portion 410 are formed, and the upper portion of the first electrode portion 110 also presents an annular shape. To facilitate the subsequent electrical connection of the first electrode portion 110 to an external circuit, the lower portion of the first electrode portion 110 may not be etched and may remain in the form of a continuous thin film.

[0144] Next, if Figure 13(c) to Figure 13(e) As shown, a gate portion 300 can be formed, which may include a gate dielectric portion 310 directly in contact with the channel portion 200 and a gate electrode portion 320 located on an opposite side of the gate dielectric portion 310 and the channel portion 200, and the gate portion 300 may be located on at least a portion of the sidewall of the channel portion 200 extending in the vertical direction.

[0145] Specifically, as shown in FIG13( c ), before forming the gate portion 300, a patterned first spacer 510 can be formed. The first spacer material of the first spacer 510 can cover the portion of the upper surface of the first electrode portion 110 that is not covered by the channel portion 200, and the upper surface of the first spacer 510 can be flush or substantially flush with the lower surface of the channel portion 200. (Typically, the thickness of the first contact portion 410 is very small and can be ignored.) The provision of the first spacer 510 prevents direct conduction between the first electrode portion 110 and the gate electrode portion 320, thereby ensuring normal operation of the semiconductor device.

[0146] Then, as shown in FIG13( d ), forming the gate portion 300 may include forming a gate dielectric material layer 310 ′ along at least the exposed surfaces of the first spacer 510 , the channel portion 200 , and the second electrode portion 120 , wherein at least a portion of the gate dielectric material layer 310 ′ may serve as the gate dielectric portion 310 in direct contact with the channel portion 200 . The gate dielectric material layer 310 ′ may be formed using a suitable dielectric material, such as, but not limited to, silicon oxide, hafnium oxide, aluminum oxide, or the like. Furthermore, to ensure conformal growth of the gate dielectric material layer 310 ′, the gate dielectric material layer 310 ′ may be formed using methods such as atomic layer deposition (ALD).

[0147] Then, as shown in FIG13( e ), forming the gate portion 300 may include forming a patterned gate electrode portion 320. The gate electrode portion 320 may be located on a side of the gate dielectric portion 310 opposite the channel portion 200, and the upper surface of the gate electrode portion 320 may be flush or substantially flush with the upper surface of the channel portion 200 (typically, the thickness of the second contact portion 420 is very small and can be ignored). The gate electrode portion 320 may be formed of a suitable conductive material, such as a metal material.

[0148] Furthermore, in order to enable the semiconductor device to be electrically connected to an external circuit, a corresponding electrical connection portion may be formed as needed. In addition, in order to protect the semiconductor device from the adverse effects of substances such as oxygen, water, dust, etc. in the air, a corresponding passivation layer may be formed as needed. For example, as shown in FIG13(f), the method for preparing a semiconductor device may also include: after forming a patterned gate electrode portion 320, forming a patterned second spacer 520, wherein the second spacer material of the second spacer 520 can cover the portion of the sidewall extending in the vertical direction of the second electrode portion 120 covered by the gate dielectric material layer 310', and the second spacer 520 can effectively avoid direct conduction between the second electrode portion 120 and the gate electrode portion 320, thereby ensuring the normal operation of the semiconductor device.

[0149] Further, as shown in FIG13( g), after forming the patterned second spacer 520, the method for preparing a semiconductor device may further include: forming a patterned first passivation layer 610, wherein the upper surface of the first passivation layer 610 may be flush or substantially flush with the upper surface of the second electrode portion 120; forming a second passivation layer 620, wherein the second passivation layer 620 may cover above the first passivation layer 610 and the second electrode portion 120; and forming a gate connection portion 830 for electrically connecting to the gate electrode portion 320 in the first passivation layer 610, and forming a second electrode connection portion 820 for electrically connecting to the second electrode portion 120 in the second passivation layer 620, thereby obtaining the following. Figure 1 In addition, the first electrode portion 110 can also be electrically connected to an external circuit through the corresponding first electrode connecting portion 810. In some embodiments, as Figure 1 As shown, a backside power supply technology can be used to provide a first electrode connection portion 810 below the semiconductor device (e.g., in the substrate 700). Alternatively, in some other embodiments, a hole can be dug beside the semiconductor device, and a sidewall insulating material can be deposited and then filled with a conductive material such as metal to form the corresponding first electrode connection portion 810, which is not limited here.

[0150] In the second specific embodiment, the following method can be used to form Figure 3 The semiconductor device shown in FIG. The steps before forming the patterned second spacer 520 can refer to the steps of FIG. Figure 13(a) to Figure 13(f) As described. Then, as shown in FIG14( a), after forming the patterned second spacer 520, a patterned first passivation layer 610 can be formed, wherein the upper surface of the first passivation layer 610 can be flush or substantially flush with the upper surface of the second spacer 520. In addition, the second electrode material can be partially etched so that the remaining second electrode material is formed into the second electrode portion 120, and a recessed space can be formed between the upper surface of the second electrode portion 120 and the upper surface of the first passivation layer 610. Then, as shown in FIG14( b), a patterned second passivation layer 620 can be formed in the recessed space, wherein the upper surface of the second passivation layer 620 can be flush or substantially flush with the upper surface of the first passivation layer 610. Finally, a gate connection portion 830 for electrically connecting to the gate electrode portion can be formed in the first passivation layer 610, and a second electrode connection portion 820 for electrically connecting to the second electrode portion 120 can be formed in the second passivation layer 620 to form as shown. Figure 3The semiconductor device shown. Here, the first passivation layer 610 and the second passivation layer 620 can be formed with different dielectric materials, respectively, to have different etching selectivity ratios. In this way, before forming the gate connection portion 830 and the second electrode connection portion 820, when etching the corresponding holes to accommodate them in the first passivation layer 610 and the second passivation layer 620, respectively, it can be done based on a self-alignment process (achieved by utilizing the etching selectivity of different materials) without worrying about different holes being connected to each other due to insufficient alignment accuracy, resulting in a short circuit. In addition, the first electrode portion 110 can also be electrically connected to an external circuit through the corresponding first electrode connection portion 810. In some embodiments, as Figure 3 As shown, a backside power supply technology can be used to provide a first electrode connection portion 810 below the semiconductor device (e.g., in the substrate 700). Alternatively, in some other embodiments, a hole can be dug beside the semiconductor device, and a sidewall insulating material can be deposited and then filled with a conductive material such as metal to form the corresponding first electrode connection portion 810, which is not limited here.

[0151] In the third specific embodiment of the present disclosure, in order to form Figure 4 The semiconductor device shown can be used as follows Figure 15(a) to Figure 15(i) The method shown. As shown in FIG15( a ), a substrate 700 may be provided; a first electrode material layer 110 ′, a channel material layer 200 ′, and a second electrode material layer 120 ′ are sequentially formed on one side of the substrate 700 . In a silicon-based or silicon-germanium-based device, the first electrode material layer 110 ′, the channel material layer 200 ′, and the second electrode material layer 120 ′ may be formed respectively by epitaxial growth and doping. For example, the first electrode material layer 110 ′ and the second electrode material layer 120 ′ may be formed of heavily doped silicon or silicon-germanium, while the channel material layer 200 ′ may be formed of lightly doped or undoped silicon or silicon-germanium. Furthermore, the doping type of the first electrode material layer 110 ′ and the second electrode material layer 120 ′ may be opposite to the doping type of the channel material layer 200 ′. For example, the channel material of an n-type semiconductor device may be p-doped or undoped, while the electrode material may be formed of a heavily doped n-type material. In contrast, the channel material of a p-type semiconductor device is n-doped or undoped, while the electrode material is formed of a heavily doped p-type material.

[0152] Then, refer to the above Figure 11 or Figure 12A patterned first mask layer 892 is formed in the manner shown, and the first mask layer 892 may include a first mask portion and a second mask portion, wherein the cross-section of the first mask portion in the lateral direction may be annular, and the cross-section of the second mask portion in the lateral direction may be located inside the cross-section of the first mask portion in the lateral direction, thereby forming a semiconductor device having a hybrid channel having both a nanoring structure and a nanowire structure located inside the nanoring structure. In some examples, the first mask layer 892 can be formed directly on the upper surface of the second electrode material layer 120'. Alternatively, as shown in Figure 15(a), a second mask layer 891 can be formed on the upper surface of the second electrode material layer 120', and then the first mask layer 892 is formed on the upper surface of the second mask layer 891. Here, the second mask layer 891 can be formed of a hard mask material to improve the etching selectivity.

[0153] As shown in FIG15( b ), the second electrode material layer 120 ′, the channel material layer 200 ′, and the first electrode material layer 110 ′ can then be etched in sequence under the protection of the first mask layer 892 (and the second mask layer 891 (if present)) to form the second electrode portion 120 , the channel portion 200 , and the first electrode portion 110 , respectively. In the specific example shown in FIG13( b ), it can be seen that after etching, the second electrode portion 120 and the channel portion 200 having both an annular structure and a linear or columnar structure are formed, and the upper portion of the first electrode portion 110 also has both an annular structure and a linear or columnar structure. In order to facilitate the subsequent electrical connection of the first electrode portion 110 to an external circuit, the lower portion of the first electrode portion 110 may not be etched and remains in a continuous thin film.

[0154] Next, if Figure 15(c) to Figure 15(e) As shown, a gate portion 300 can be formed, which may include a gate dielectric portion 310 directly in contact with the channel portion 200 and a gate electrode portion 320 located on an opposite side of the gate dielectric portion 310 and the channel portion 200, and the gate portion 300 may be located on at least a portion of the sidewall of the channel portion 200 extending in the vertical direction.

[0155] Specifically, as shown in FIG15( c ), before forming the gate portion 300, a patterned first spacer 510 can be formed. The first spacer material of the first spacer 510 can cover the portion of the upper surface of the first electrode portion 110 that is not covered by the channel portion 200, and the upper surface of the first spacer 510 can be flush or substantially flush with the lower surface of the channel portion 200. The provision of the first spacer 510 can prevent direct conduction between the first electrode portion 110 and the gate electrode portion 320, thereby ensuring normal operation of the semiconductor device.

[0156] Then, as shown in FIG15( d ), forming the gate portion 300 may include forming a gate dielectric material layer 310 ′ along at least the exposed surfaces of the first spacer 510 , the channel portion 200 , and the second electrode portion 120 , wherein at least a portion of the gate dielectric material layer 310 ′ may serve as the gate dielectric portion 310 in direct contact with the channel portion 200 . The gate dielectric material layer 310 ′ may be formed using a suitable dielectric material, such as, but not limited to, silicon oxide, hafnium oxide, aluminum oxide, or the like. Furthermore, to ensure conformal growth of the gate dielectric material layer 310 ′, the gate dielectric material layer 310 ′ may be formed using methods such as atomic layer deposition (ALD).

[0157] Then, as shown in FIG15( e ), forming the gate portion 300 may include forming a patterned gate electrode portion 320. The gate electrode portion 320 may be located on a side of the gate dielectric portion 310 opposite the channel portion 200, and the upper surface of the gate electrode portion 320 may be flush or substantially flush with the upper surface of the channel portion 200. The gate electrode portion 320 may be formed of a suitable conductive material, such as a metal material.

[0158] As shown in Figure 15(f), after the patterned gate electrode portion 320 is formed, a patterned second spacer portion 520 can be formed, wherein the second spacer material of the second spacer portion 520 can cover the portion of the side wall extending in the vertical direction of the second electrode portion 120 covered by the gate dielectric material layer, so as to isolate the second electrode portion 120 and the gate electrode portion 320, thereby ensuring the normal operation of the semiconductor device.

[0159] Furthermore, in order to enable the semiconductor device to be electrically connected to an external circuit, a corresponding electrical connection portion can be formed as needed. In addition, in order to protect the semiconductor device from the adverse effects of substances such as oxygen, water, dust, etc. in the air, a corresponding passivation layer can also be formed as needed. For example, as shown in Figure 15(g), the method for preparing a semiconductor device can also include: after forming the patterned second spacer 520, forming an electrode connection material layer 850, wherein the upper surface of the electrode connection material layer 850 can be located above the upper surface of the second electrode portion 120; and forming a second passivation layer 620 above the electrode connection material layer 850. Then, as shown in Figure 15(h), the second passivation layer 620 and the electrode connection material layer 850 can be patterned and etched to retain only the second passivation layer 620 and the electrode connection material layer 850 located above the second electrode portion 120. Then, as shown in FIG15(i), a patterned first passivation layer 610 may be formed, wherein the upper surface of the first passivation layer 610 may be substantially flush with the upper surface of the second passivation layer 620. Finally, a gate connection portion 830 for electrically connecting to the gate electrode portion 320 may be formed in the first passivation layer 610, and a second electrode connection portion 820 for electrically connecting to the second electrode portion 120 may be formed in the second passivation layer 620, to form a gate electrode portion 320. Figure 4 The semiconductor device shown. Figure 3 Similar to the method of the semiconductor device shown in FIG. 1 , the first passivation layer 610 and the second passivation layer 620 can be formed of different dielectric materials, respectively, to have different etching selectivities. In this way, before forming the gate connection portion 830 and the second electrode connection portion 820, when etching the corresponding holes to accommodate them in the first passivation layer 610 and the second passivation layer 620, respectively, it can be done based on a self-alignment process without worrying about different holes being connected to each other due to insufficient alignment accuracy, resulting in a short circuit. In addition, the first electrode portion 110 can also be electrically connected to an external circuit through the corresponding first electrode connection portion 810. In some embodiments, as Figure 4 As shown, a backside power supply technology can be used to provide a first electrode connection portion 810 below the semiconductor device (e.g., in the substrate 700). Alternatively, in some other embodiments, a hole can be dug beside the semiconductor device, and a sidewall insulating material can be deposited and then filled with a conductive material such as metal to form the corresponding first electrode connection portion 810, which is not limited here.

[0160] In the fourth specific embodiment of the present disclosure, in order to form Figure 6 The semiconductor device shown in FIG. 1 can be constructed by the following method. The steps before forming the second spacer 520 can refer to the steps of FIG. Figure 15(a) to Figure 15(f)As described. Then, as shown in FIG16( a), the method for preparing a semiconductor device may further include: after forming the patterned second spacer 520, partially etching the second electrode material so that the remaining second electrode material is formed into the second electrode portion 120, and a recessed space is formed between the upper surface of the second electrode portion 120 and the upper surface of the second spacer 520. Then, as shown in FIG16( b) and FIG16( c), an electrode connecting material layer 850 may be formed, wherein the upper surface of the electrode connecting material layer 850 may be substantially flush with the upper surface of the second spacer 520. Here, as shown in FIG16( b), an electrode connecting material layer 580 having an upper surface higher than the second spacer 520 may be deposited first, and then, as shown in FIG16( c), the upper surface of the electrode connecting material layer 850 may be substantially flush with the upper surface of the second spacer 520 by, for example, etching or chemical mechanical polishing. Then, as shown in FIG16( d ), a second passivation layer 620 may be formed above the electrode connection material layer 850, wherein the second passivation layer 620 may be in direct contact with the second spacer 520 to isolate the gate connection portion 830 from the second electrode connection portion 820. Finally, the second passivation layer 620 may be patterned and etched to form a gate connection portion 830 for connecting to the gate electrode portion 320 and a second electrode connection portion 820 for connecting to the second electrode portion 120, which are insulated from each other, i.e., forming a gate connection portion 830 for connecting to the gate electrode portion 320 and a second electrode connection portion 820 for connecting to the second electrode portion 120, as shown in FIG16( d ). Figure 6 Similarly, the first electrode portion 110 can be connected to an external circuit (such as a first electrode connection portion 810) located in the substrate 700 by using a back-facing process. Figure 6 As shown), or it can be formed in other ways, which are not limited here.

[0161] In the fifth specific embodiment of the present disclosure, in order to achieve the following Figure 7 The semiconductor device shown can refer to Figure 17(a) to Figure 17(i) As shown in the process flow. As shown in FIG17 (a), a substrate 700 may be provided. Then, a first electrode material layer 110', a first contact material layer 410', a channel material layer 200', a second contact material layer 420' and a second electrode material layer 120' may be sequentially formed on one side of the substrate 700. Then, reference may be made to the above description of Figure 11 or Figure 12 The patterned first mask layer 892 is formed in the manner shown, and the first mask layer 892 may include a first mask portion and a second mask portion. In some examples, the first mask layer 892 may be directly formed on the second electrode material layer 120' (ie Figure 11 or Figure 12The substrate shown in FIG can be the upper surface of the second electrode material layer 120 '). Alternatively, as shown in FIG17 (a), a second mask layer 891 (i.e. Figure 11 or Figure 12 The substrate shown in FIG may be a second mask layer 891), and then a first mask layer 892 is formed on the upper surface of the second mask layer 891. Here, the second mask layer 891 may be formed of a hard mask material to enhance the selectivity of the subsequent etching process and improve the etching effect.

[0162] As shown in FIG17( b ), the second electrode material layer 120 ′, the second contact material layer 420 ′, the channel material layer 200 ′, the first contact material layer 410 ′, and the first electrode material layer 110 ′ can then be etched sequentially under the protection of the first mask layer 892 (and the second mask layer 891 (if present)) to form the second electrode portion 120 , the second contact portion 420 , the channel portion 200 , the first contact portion 410 , and the first electrode portion 110 , respectively. In the specific example shown in FIG17( b ), it can be seen that after etching, the second electrode portion 120 , the second contact portion 420 , the channel portion 200 , and the first contact portion 410 , which include both an annular structure and a columnar structure, are formed, while the upper portion of the first electrode portion 110 also includes both an annular structure and a columnar structure. To facilitate subsequent electrical connection of the first electrode portion 110 to an external circuit, the lower portion of the first electrode portion 110 may not be etched and may remain in the form of a continuous thin film.

[0163] Next, if Figure 17(c) to Figure 17(e) As shown, a gate portion 300 can be formed, which may include a gate dielectric portion 310 directly in contact with the channel portion 200 and a gate electrode portion 320 located on an opposite side of the gate dielectric portion 310 and the channel portion 200, and the gate portion 300 may be located on at least a portion of the sidewall of the channel portion 200 extending in the vertical direction.

[0164] Specifically, as shown in FIG17( c ), before forming the gate portion 300, a patterned first spacer 510 can be formed. The first spacer material of the first spacer 510 can cover the portion of the upper surface of the first electrode portion 110 that is not covered by the channel portion 200, and the upper surface of the first spacer 510 can be flush or substantially flush with the lower surface of the channel portion 200. (Typically, the thickness of the first contact portion 410 is very small and can be ignored.) The provision of the first spacer 510 can prevent direct conduction between the first electrode portion 110 and the gate electrode portion 320, thereby ensuring normal operation of the semiconductor device.

[0165] Then, as shown in FIG17( d ), forming the gate portion 300 may include forming a gate dielectric material layer 310 ′ along at least the exposed surfaces of the first spacer 510 , the channel portion 200 , and the second electrode portion 120 (here also including the first contact portion 410 and the second contact portion 420 ). At least a portion of the gate dielectric material layer 310 ′ may serve as the gate dielectric portion 310 in direct contact with the channel portion 200 . The gate dielectric material layer 310 ′ may be formed of a suitable dielectric material, such as silicon oxide, hafnium oxide, or aluminum oxide. Furthermore, to ensure conformal growth of the gate dielectric material layer 310 ′, the gate dielectric material layer 310 ′ may be formed using methods such as atomic layer deposition (ALD).

[0166] Then, as shown in FIG17( e ), forming the gate portion 300 may include forming a patterned gate electrode portion 320. The gate electrode portion 320 may be located on a side of the gate dielectric portion 310 opposite the channel portion 200, and the upper surface of the gate electrode portion 320 may be flush or substantially flush with the upper surface of the channel portion 200 (generally, the thickness of the second contact portion 420 is very small and can be ignored). The gate electrode portion 320 may be formed of a suitable conductive material, such as a metal material.

[0167] Furthermore, in order to enable the semiconductor device to be electrically connected to an external circuit, a corresponding electrical connection portion may be formed as needed. In addition, in order to protect the semiconductor device from the adverse effects of substances such as oxygen, water, dust, etc. in the air, a corresponding passivation layer may be formed as needed. For example, as shown in FIG17( f), the method for preparing a semiconductor device may also include: after forming a patterned gate electrode portion 320, forming a patterned second spacer 520, wherein the second spacer material of the second spacer 520 can cover the portion of the sidewall extending in the vertical direction of the second electrode portion 120 covered by the gate dielectric material layer 310 ', and the second spacer 520 can effectively avoid direct conduction between the second electrode portion 120 and the gate electrode portion 320, thereby ensuring the normal operation of the semiconductor device.

[0168] Furthermore, as shown in FIG17( g ), after forming the patterned second spacer 520, the method for manufacturing a semiconductor device may further include forming a patterned first passivation layer 610, wherein the upper surface of the first passivation layer 610 may be flush or substantially flush with the upper surface of the second electrode portion 120. Furthermore, as shown in FIG17( h ), the second electrode material may be partially etched so that the remaining second electrode material forms the second electrode portion 120, and a recessed space may be formed between the upper surface of the second electrode portion 120 and the upper surface of the first passivation layer 610. Then, as shown in FIG17( i ), a patterned second passivation layer 620 may be formed in the recessed space, wherein the upper surface of the second passivation layer 620 may be flush or substantially flush with the upper surface of the first passivation layer 610. Finally, a gate connection portion 830 for electrically connecting to the gate electrode portion may be formed in the first passivation layer 610, and a second electrode connection portion 820 for electrically connecting to the second electrode portion 120 may be formed in the second passivation layer 620 to form a gate electrode. Figure 7 The semiconductor device shown. Similarly, the first passivation layer 610 and the second passivation layer 620 can be formed with different dielectric materials, respectively, to have different etching selectivities. In this way, before forming the gate connection portion 830 and the second electrode connection portion 820, when etching the corresponding holes to accommodate them in the first passivation layer 610 and the second passivation layer 620, respectively, it can be done based on a self-alignment process without worrying about different holes being connected to each other due to insufficient alignment accuracy, resulting in a short circuit. In addition, the first electrode portion 110 can also be electrically connected to an external circuit through the corresponding first electrode connection portion 810. In some embodiments, as Figure 7 As shown, a backside power supply technology can be used to provide a first electrode connection portion 810 below the semiconductor device (e.g., in the substrate 700). Alternatively, in some other embodiments, a hole can be dug beside the semiconductor device, and a sidewall insulating material can be deposited and then filled with a conductive material such as metal to form the corresponding first electrode connection portion 810, which is not limited here.

[0169] The semiconductor devices and semiconductor devices disclosed in the present invention can be used in a variety of circuits, for example, in display circuits and storage circuits, for direct placement above logic circuits (for example, using a low-temperature process compatible with back-end BEOL metals to manufacture) to achieve the desired logical function, or for use in circuits such as storage and computing integrated circuits. In particular, the semiconductor devices based on epitaxially grown silicon or epitaxially grown silicon germanium proposed in the present invention can be used in logic circuits of future advanced nodes. The semiconductor device disclosed in the present invention having a vertical nanoring structure or having both a vertical nanowire and a nanoring structure is a multi-gate (for example, a dual-ring gate) device. Compared with devices with a single-ring gate structure, the device disclosed in the present invention can more effectively suppress the short channel effect, reduce leakage current and power consumption. From the perspective of device physics, the control ability of a device with only a nanoring structure to the short channel effect may be weaker than that of a device with only a nanowire structure. However, in the present application, by simultaneously providing a nanoring structure and a nanowire structure to form a hybrid channel, the overall control ability of the gate over the short channel can be enhanced compared to a device with only a nanoring structure, thereby suppressing the short channel effect. In addition, especially in a hybrid channel semiconductor device having both vertical nanowire and nanoring structures, the on-state current of the device can also be increased accordingly, thereby improving the performance of the device.

[0170] The words "left," "right," "front," "back," "top," "bottom," "up," "down," "high," "low," and the like, if any, in the specification and claims, are used for descriptive purposes and are not necessarily intended to describe invariant relative positions. It should be understood that the words so used are interchangeable under appropriate circumstances such that the embodiments of the present disclosure described herein, for example, are capable of operation in other orientations than those shown or otherwise described herein. For example, when the device in the figures is turned over, features previously described as "above" other features could now be described as "below" the other features. The device can also be otherwise oriented (rotated 90 degrees or in other orientations) and relative spatial relationships will be interpreted accordingly.

[0171] In the specification and claims, when an element is referred to as being "on," "attached," "connected," "coupled," or "in contact with," etc., another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly in contact with the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being "directly" "on," "directly attached," "directly connected," "directly coupled," or "in direct contact with" another element, there will be no intervening elements. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that the feature has a portion that overlaps with the adjacent feature or a portion that is located above or below the adjacent feature.

[0172] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be precisely copied. Any implementation described as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not to be bound by any expressed or implied theory presented in the technical field, background, summary, or detailed description.

[0173] As used herein, the term "substantially" is intended to encompass any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0174] Additionally, terms such as "first," "second," and the like may also be used herein for reference purposes only and are not intended to be limiting. For example, the terms "first," "second," and other numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0175] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0176] In this disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object, etc.

[0177] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0178] Those skilled in the art will appreciate that the boundaries between the above-mentioned operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and replacements are also possible. Aspects and elements of all embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be regarded as illustrative, not restrictive.

[0179] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art will appreciate that the above examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A semiconductor device, comprising: a first electrode portion; a channel portion, the channel portion being located above the first electrode portion and electrically connected to the first electrode portion, wherein the channel portion comprises a first channel portion, and a cross section of the first channel portion in a lateral direction is annular; a second electrode portion, the second electrode portion being located above the channel portion and electrically connected to the channel portion; and A gate portion includes a gate dielectric portion directly in contact with the channel portion and a gate electrode portion located on a side of the gate dielectric portion opposite to the channel portion, wherein the gate portion is located on at least a portion of a side wall of the channel portion extending in a vertical direction.

2. The semiconductor device according to claim 1, wherein The cross section of the first channel portion in the transverse direction is in the shape of a circular ring, an elliptical ring, a polygonal ring, a rectangular ring or a square ring.

3. The semiconductor device according to claim 1, wherein The gate dielectric portion includes a first gate dielectric portion covering an inner sidewall of the first channel portion extending in a vertical direction and a second gate dielectric portion covering an outer sidewall of the first channel portion extending in a vertical direction; and The gate electrode portion at least covers an inner side of the first gate dielectric portion and an outer side of the second gate dielectric portion.

4. The semiconductor device according to claim 1, wherein: The inner sidewall of the first channel portion is completely filled with the gate portion.

5. The semiconductor device according to claim 1, wherein The channel portion further includes a second channel portion having a cross section in the lateral direction located inside a cross section of the first channel portion in the lateral direction.

6. The semiconductor device according to claim 5, wherein: The cross section of the second channel portion in the transverse direction is circular, elliptical, polygonal, rectangular or square.

7. The semiconductor device according to claim 5, wherein: The second channel portion is located at the center of the first channel portion.

8. The semiconductor device according to claim 5, wherein: The gate dielectric portion includes a third gate dielectric portion covering an outer sidewall of the second channel portion extending in a vertical direction; and The gate electrode portion at least covers an outer side of the third gate dielectric portion.

9. The semiconductor device according to claim 5, wherein: A space between an inner sidewall of the first channel portion and an outer sidewall of the second channel portion is completely filled by the gate portion.

10. The semiconductor device according to claim 1, further comprising at least one of the following: a first contact portion, the first contact portion being located between the channel portion and the first electrode portion and configured to electrically connect the channel portion and the first electrode portion; a second contact portion, the second contact portion being located between the channel portion and the second electrode portion and configured to electrically connect the channel portion and the second electrode portion; a first spacer portion, the first spacer portion being located between the first electrode portion and the gate portion and configured to electrically isolate the first electrode portion from the gate portion; as well as A second spacer portion is located on a side wall of the second electrode portion extending in a vertical direction and is configured to electrically isolate the second electrode portion from the gate portion. 11 . A semiconductor device comprising the semiconductor device according to claim 1 .

12. The semiconductor device according to claim 11, wherein The semiconductor device includes an n-type semiconductor device and a p-type semiconductor device, and the n-type semiconductor device and the p-type semiconductor device are stacked in a vertical direction.

13. A method for preparing a semiconductor device, comprising: providing a substrate; sequentially forming a first electrode material layer, a channel material layer, and a second electrode material layer on one side of the substrate; forming a patterned first mask layer, wherein the first mask layer comprises a first mask portion, and a cross section of the first mask portion in a lateral direction is ring-shaped; etching the second electrode material layer, the channel material layer and the first electrode material layer under the protection of the first mask layer to form a second electrode portion, a channel portion and a first electrode portion respectively; and A gate portion is formed, wherein the gate portion includes a gate dielectric portion directly contacting the channel portion and a gate electrode portion located on a side of the gate dielectric portion opposite to the channel portion, and the gate portion is located on at least a portion of a side wall of the channel portion extending in a vertical direction.

14. The method according to claim 13, wherein: Forming a patterned first mask layer includes: forming a first sacrificial portion, wherein the first sacrificial portion is in a column shape extending in a vertical direction; forming a first retaining portion around an outer side wall of the first sacrificial portion; and The first sacrificial portion is removed, and the first reserved portion is used as the first mask portion of the first mask layer.

15. The method according to claim 13, wherein: The first mask layer further includes a second mask portion, a cross section of the second mask portion in the lateral direction being located inside a cross section of the first mask portion in the lateral direction.

16. The method according to claim 15, wherein: Forming a patterned first mask layer includes: forming a second reserved portion, wherein the second reserved portion is in the shape of a column extending in the vertical direction; forming a second sacrificial portion around an outer side wall of the second retaining portion; forming a third reserved portion around an outer side wall of the second sacrificial portion; and The second sacrificial portion is removed, and the third reserved portion is used as the first mask portion of the first mask layer, and the second reserved portion is used as the second mask portion of the first mask layer.

17. The method according to claim 15, wherein: Forming a patterned first mask layer includes: forming a third sacrificial portion, wherein the third sacrificial portion is in a column shape extending in a vertical direction; forming a fourth reserved portion around the outer side wall of the third sacrificial portion; removing the third sacrificial portion, and using the fourth reserved portion as the first mask portion of the first mask layer; forming a fourth sacrificial portion around the inner side wall and the outer side wall of the fourth reserved portion, wherein at least a portion of the space inside the fourth reserved portion is not filled by the fourth sacrificial portion to form an opening extending in the vertical direction; forming a fifth retaining portion in the opening; and The fourth sacrificial portion is removed, and the fifth remaining portion is used as the second mask portion of the first mask layer.

18. The method according to claim 13, wherein: The first electrode material layer, the channel material layer and the second electrode material layer are formed of a silicon-based material or a silicon-germanium-based material, the first electrode material layer and the second electrode material layer have the same doping type, the channel material layer and the first electrode material layer have the same or opposite doping type, the channel material layer has a lower doping concentration than the first electrode material layer, and the channel material layer has a lower doping concentration than the second electrode material layer; or The first electrode material layer and the second electrode material layer are formed of a metal material, and the channel material layer is formed of a metal oxide material.

19. The method according to claim 13, further comprising: forming a first contact material layer between the first electrode material layer and the channel material layer on one side of the substrate; as well as forming a channel material layer and a second electrode material layer on one side of the substrate, and forming a second contact material layer between the channel material layer and the second electrode material layer; Before etching the second electrode material layer and the channel material layer under the protection of the first mask layer, etching the second contact material layer to form a second contact portion, wherein the second contact portion is configured to electrically connect the channel portion and the second electrode portion; as well as Before etching the channel material layer and the first electrode material layer under the protection of the first mask layer, the first contact material layer is etched to form a first contact portion, wherein the first contact portion is configured to electrically connect the channel portion and the first electrode portion.

20. The method of claim 13, further comprising: Before forming the gate portion, a patterned first spacer portion is formed, wherein a first spacer material of the first spacer portion covers a portion of the upper surface of the first electrode portion not covered by the channel portion, and the upper surface of the first spacer portion is substantially flush with the lower surface of the channel portion.

21. The method according to claim 20, wherein: Forming the gate portion includes: forming a gate dielectric material layer at least along the exposed surfaces of the first spacer, the channel portion and the second electrode portion, wherein at least a portion of the gate dielectric material layer serves as a gate dielectric portion directly contacting the channel portion; A patterned gate electrode portion is formed, wherein the gate electrode portion is located on a side of the gate dielectric portion opposite to the channel portion, and an upper surface of the gate electrode portion is substantially flush with an upper surface of the channel portion.

22. The method according to claim 21, further comprising: After forming the patterned gate electrode portion, a patterned second spacer is formed, wherein a second spacer material of the second spacer covers a portion of a sidewall of the second electrode portion extending in a vertical direction and covered by the gate dielectric material layer.

23. The method according to claim 22, further comprising: After forming the patterned second spacer, forming a patterned first passivation layer, wherein an upper surface of the first passivation layer is substantially flush with an upper surface of the second electrode portion; forming a second passivation layer, wherein the second passivation layer covers the first passivation layer and the second electrode portion; and A gate connection portion for electrical connection to the gate electrode portion is formed in the first passivation layer, and a second electrode connection portion for electrical connection to the second electrode portion is formed in the second passivation layer.

24. The method of claim 22, further comprising: After forming the patterned second spacers, forming a patterned first passivation layer, wherein an upper surface of the first passivation layer is substantially flush with an upper surface of the second spacers; Partially etching the second electrode material so that the remaining second electrode material forms a second electrode portion, and a recessed space is formed between an upper surface of the second electrode portion and an upper surface of the first passivation layer; forming a patterned second passivation layer in the recessed space, wherein an upper surface of the second passivation layer is substantially flush with an upper surface of the first passivation layer; and A gate connection portion for electrical connection to the gate electrode portion is formed in the first passivation layer, and a second electrode connection portion for electrical connection to the second electrode portion is formed in the second passivation layer.

25. The method of claim 22, further comprising: After forming the patterned second spacer portion, forming an electrode connection material layer, wherein an upper surface of the electrode connection material layer is located above an upper surface of the second electrode portion; forming a second passivation layer above the electrode connection material layer; performing patterned etching on the second passivation layer and the electrode connection material layer to retain only portions of the second passivation layer and the electrode connection material layer located above the second electrode portion; and A patterned first passivation layer is formed, wherein an upper surface of the first passivation layer is substantially flush with an upper surface of the second passivation layer.

26. The method of claim 22, further comprising: After forming the patterned second spacer, partially etching the second electrode material so that the remaining second electrode material forms a second electrode portion, and a recessed space is formed between an upper surface of the second electrode portion and an upper surface of the second spacer; forming an electrode connection material layer, wherein an upper surface of the electrode connection material layer is substantially flush with an upper surface of the second spacer; forming a second passivation layer above the electrode connection material layer, wherein the second passivation layer is in direct contact with the second spacer; The second passivation layer is pattern-etched to form a gate connection portion connected to the gate electrode portion and a second electrode connection portion connected to the second electrode portion, which are insulated from each other.

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