Semiconductor device and method of manufacturing the same, electronic device

Abstract

The application relates to a semiconductor device and a preparation method thereof and an electronic device. The preparation method of the semiconductor device comprises the following steps: forming a via in a stack structure, the via penetrating through a second source / drain electrode and an interlayer dielectric layer in a direction perpendicular to a substrate and extending to at least a first source / drain electrode; exposing a sidewall of the via to at least the interlayer dielectric layer, forming a self-assembled monolayer in adsorption with the interlayer dielectric layer on the sidewall, so that the first source / drain electrode and the second source / drain electrode exposed to the self-assembled monolayer are exposed in the via; taking the self-assembled monolayer as a mask, forming a contact layer on the first source / drain electrode and the second source / drain electrode; removing the self-assembled monolayer; the contact layer on the first source / drain electrode and the contact layer on the second source / drain electrode are isolated by the interlayer dielectric layer; and forming a semiconductor layer on the sidewall in the via, and the semiconductor layer is connected with the contact layers on the first source / drain electrode and the second source / drain electrode. The process is simple and low in cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device, a preparation method thereof and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production can affect the performance of the device.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0004] Therefore, the embodiments of the present application provide a semiconductor device, a preparation method thereof and an electronic device, which can avoid surface oxidation of the source / drain, and the process is simple and low in cost.

[0005] A preparation method of a semiconductor device is provided, comprising:

[0006] providing a stack structure comprising at least a first source / drain, an interlayer dielectric layer and a second source / drain formed in sequence in a direction perpendicular to the substrate;

[0007] forming a via hole in the stack structure, the via hole penetrating the second source / drain and the interlayer dielectric layer in the direction perpendicular to the substrate, and extending to at least the first source / drain;

[0008] exposing at least a sidewall of the via hole to the interlayer dielectric layer, and forming a self-assembled monolayer in adsorption with the interlayer dielectric layer on the sidewall, so that the first source / drain and the second source / drain exposed by the self-assembled monolayer in the via hole are not covered;

[0009] forming a contact layer on the first source / drain and the second source / drain by taking the self-assembled monolayer as a mask;

[0010] removing the self-assembled monolayer, and the contact layer on the first source / drain and the contact layer on the second source / drain are isolated by the interlayer dielectric layer;

[0011] forming a semiconductor layer on the sidewall in the via hole, and the semiconductor layer is connected to the contact layer on the first source / drain and the second source / drain.

[0012] In some embodiments, the contact layer is an oxidation-resistant conductive layer and / or a film layer for reducing the Schottky barrier.

[0013] In some embodiments, the self-assembled monolayer comprises long-chain organic molecules; and the long-chain organic molecules are chemically bonded to molecules of the interlayer dielectric layer.

[0014] In some embodiments, the long-chain organic molecules comprise at least a fluoroalkyl group, and the fluoroalkyl group is a tail group of the long-chain organic molecules.

[0015] The contact layer is formed by an atomic layer deposition process; and the interlayer dielectric layer comprises a non-metal oxide layer.

[0016] In some embodiments, the surface of the interlayer dielectric layer has at least hydroxyl groups.

[0017] The fluoroalkyl group in the long-chain organic molecules is chemically bonded to the hydroxyl groups on the surface of the interlayer dielectric layer.

[0018] In some embodiments, the interlayer dielectric layer comprises a silicon oxide film layer having hydroxyl groups on the surface.

[0019] In some embodiments, the self-assembled monolayer comprises 1H, 1H, 2H, 2H- perfluorooctyltrichlorosilane and / or (heptadecafluoro-1, 1, 2, 2-tetrahydrodecyl) triethoxysilane.

[0020] In forming the self-assembled monolayer in adsorption with the interlayer dielectric layer, a first reaction gas comprises at least ammonia.

[0021] In some embodiments, in forming the contact layer in the via hole using the self-assembled monolayer as a mask, a reaction precursor comprises at least pentamethyldiamine tantalum complex, a second reaction gas comprises at least ammonia, and a reaction temperature is 225-300°C.

[0022] In some embodiments, the self-assembled monolayer is removed by a water vapor hydrolysis process or a silane pyrolysis process.

[0023] In some embodiments, the contact layer comprises a tantalum metal nitride layer.

[0024] A semiconductor device is provided, which is prepared by the method of any of the above embodiments.

[0025] In some embodiments, the semiconductor layer has the same thickness in each region.

[0026] In some embodiments, a pattern of the contact layer on the first source / drain electrode overlaps a pattern of the first source / drain electrode.

[0027] A pattern of the contact layer on the second source / drain electrode overlaps a pattern of the second source / drain electrode.

[0028] In some embodiments, the contact layer comprises a tantalum metal nitride layer.

[0029] In some embodiments, the interlayer dielectric layer comprises a silicon oxide film layer.

[0030] An electronic device is provided, comprising the semiconductor device of any of the above embodiments.

[0031] The semiconductor device and the preparation method thereof, and the semiconductor device provided by the present application can have at least the following advantages:

[0032] In the embodiments of the present application, the self-assembled monolayer adsorbed to the interlayer dielectric layer is formed on the sidewall of the via to which the interlayer dielectric layer is exposed, and the self-assembled monolayer is used as a mask to form the contact layer on the sidewall of the via to which the first source / drain electrode and the second source / drain electrode are exposed. Therefore, the contact layer is formed between the semiconductor layer and the source electrode or the drain electrode by using the embodiments of the present application, and the process is simple and the cost is low. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0034] Figure 1 A cross-sectional structure schematic diagram of a semiconductor device provided by some embodiments of the present application is shown in the figure. Figure 1 A cross-sectional structure schematic diagram of a structure obtained after forming an oxidation-resistant conductive layer in a preparation method of a semiconductor device provided by some embodiments of the present application is shown in the figure.

[0035] Figure 2 A cross-sectional structure schematic diagram of a semiconductor device provided by some other embodiments of the present application is shown in the figure.

[0036] Figure 3 A cross-sectional structure schematic diagram of a semiconductor device provided by some other embodiments of the present application is shown in the figure.

[0037] Figure 4 A flowchart of a preparation method of a semiconductor device provided by some embodiments of the present application is shown in the figure.

[0038] Figure 5 A cross-sectional structure schematic diagram of a structure obtained after forming an insulating dielectric layer and a first source / drain electrode in a preparation method of a semiconductor device provided by some embodiments of the present application is shown in the figure.

[0039] Figure 6A cross-sectional structure schematic diagram of a structure obtained after forming an interlayer dielectric layer in a method for manufacturing a semiconductor device provided in some embodiments of the present application;

[0040] Figure 7 A cross-sectional structure schematic diagram of a structure obtained after forming a second source / drain in a method for manufacturing a semiconductor device provided in some embodiments of the present application;

[0041] Figure 8 A cross-sectional structure schematic diagram of a structure obtained after forming a via in a method for manufacturing a semiconductor device provided in some embodiments of the present application;

[0042] Figure 9 A cross-sectional structure schematic diagram of a structure obtained after forming a self-assembled monolayer in a method for manufacturing a semiconductor device provided in some embodiments of the present application;

[0043] Figure 10 (a) of FIG. 1 is a chemical proportion model diagram of FOTS; Figure 10 (b) of FIG. 1 is a chemical proportion model diagram of HDFTEOS;

[0044] Figure 11 A cross-sectional structure schematic diagram of a structure obtained after forming an oxidation-resistant conductive layer in a method for manufacturing a semiconductor device provided in some embodiments of the present application;

[0045] Figure 12 (a) of FIG. 1 is a chemical proportion model diagram of FOTS; x (a) of FIG. 1 is a chemical proportion model diagram of FOTS; x A curve showing the relationship between the number of atomic layer deposition cycles and the initial growth rate; Figure 12 (b) of FIG. 1 is a chemical proportion model diagram of HDFTEOS; x (b) of FIG. 1 is a chemical proportion model diagram of HDFTEOS; x A curve showing the relationship between the number of atomic layer deposition cycles and the initial growth rate;

[0046] Figure 13 (a) of FIG. 1 is a chemical proportion model diagram of FOTS; x (a) of FIG. 1 is a chemical proportion model diagram of FOTS; x A curve showing the relationship between the thickness of atomic layer deposition and the content of Ta element; Figure 13 (b) of FIG. 1 is a chemical proportion model diagram of HDFTEOS; x (b) of FIG. 1 is a chemical proportion model diagram of HDFTEOS; x A curve showing the relationship between the thickness of atomic layer deposition and the content of Ta element.

[0047] Reference Signs List:

[0048] 1, first source / drain; 2, second source / drain; 3, contact layer; 4, semiconductor layer; 5, interlayer dielectric layer; 6, self-assembled monolayer; T, via; 7, gate dielectric layer; 8, gate; 9, insulating dielectric layer; 10, substrate. DETAILED DESCRIPTION

[0049] For the purposes of this application, the application will now be described in more detail with reference to the enclosed drawings. In the drawings, the preferred embodiments of the application are shown. The application may, however, be carried out in many different ways, of which the embodiments described below are merely exemplary. Rather, the embodiments are presented so that the disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0051] It should be understood that when an element or layer is referred to as being "on" or "at" another element or layer, it can be directly on or at the other element or layer or intervening elements or layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly at" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0052] It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described herein is turned over on its side, a relative directional term such as "front" or "back" can be used to describe the device as oriented in the new direction. The spatially relative terms therefore, are used only for the purpose of illustrating certain embodiments of the application and should not be a limitation on the present application. Other embodiments of the application will occur to those skilled in the art upon consideration of this description. Therefore, the description and drawings are illustrative and do not restrict the scope of the application. All changes and modifications that come within the meaning and range of equivalents of the claims are to be embraced within their scope.

[0053] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" as used in this specification, is intended to mean that the features, integers, steps, components or elements of which it precedes are included. Additionally, it should be understood that depending on the specific context, the term "comprising" can include other items not specifically described or included. Further, it should be understood that the term "comprising" is not intended to exclude other features, integers, steps, components or elements from the claimed subject matter.

[0054] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic and many of the regions are not drawn to scale. The same reference numerals can be used in different figures to indicate the same or similar elements.

[0055] The application provides a semiconductor device and a method for manufacturing the same, and a semiconductor device, in which a contact layer is formed on a source electrode and a drain electrode in one process when forming the contact layer between a semiconductor layer and the source or drain electrode, so that the process is simple and the manufacturing cost is low. The detailed content will be described in the subsequent embodiments.

[0056] In one aspect, the application provides a semiconductor device according to some embodiments.

[0057] Please refer to Figure 1 In some embodiments, the semiconductor device can specifically include a first source / drain electrode 1, a second source / drain electrode 2, a via T, a contact layer 3, a semiconductor layer 4, and an interlayer dielectric layer 5.

[0058] The first source / drain electrode 1, the interlayer dielectric layer 5, and the second source / drain electrode 2 are stacked in sequence in a direction perpendicular to the substrate; the via T penetrates the second source / drain electrode 2 and the interlayer dielectric layer 5 in the direction perpendicular to the substrate and extends to the first source / drain electrode 1; the contact layer 3 is located on the side wall of the first source / drain electrode 1 and the second source / drain electrode 2 exposed to the via T; and the semiconductor layer 4 is located on the surface of the contact layer 3 and the interlayer dielectric layer 5 exposed to the via T.

[0059] The semiconductor device is formed by the following method. A stack structure including at least a first source / drain, an interlayer dielectric layer and a second source / drain is provided, which are sequentially formed in a direction perpendicular to a substrate. A via hole is formed in the stack structure, which penetrates the second source / drain and the interlayer dielectric layer in a direction perpendicular to the substrate and extends to at least the first source / drain. A self-assembled monolayer in adsorption relation with the interlayer dielectric layer is formed on the sidewall of the via hole exposed to at least the interlayer dielectric layer, so that the first source / drain and the second source / drain exposed by the self-assembled monolayer in the via hole are exposed. A contact layer is formed on the first source / drain and the second source / drain exposed in the via hole by using the self-assembled monolayer as a mask. The self-assembled monolayer is removed. The contact layer on the first source / drain and the contact layer on the second source / drain are separated by the interlayer dielectric layer. A semiconductor layer is formed on the sidewall in the via hole, which is connected to the contact layer on the first source / drain and the second source / drain.

[0060] In the semiconductor device and the method provided in the above embodiments, the contact layer 3 is selectively formed only on the first source / drain 1 and the second source / drain 2 exposed by the sidewall in the via hole, and the self-assembled monolayer is formed in other regions. The self-assembled monolayer is used as a mask for forming the contact layer 3 on the first source / drain 1 and the second source / drain 2. The contact layer 3 can be arranged only on the first source / drain 1 or the second source / drain 2 to be in contact with the semiconductor layer. The process can simultaneously form the contact layer with the same pattern as the first source / drain 1 or the second source / drain 2 without a complex process.

[0061] It should be noted that in the embodiments of the present application, one of the first source / drain 1 and the second source / drain 2 is a source electrode, and the other is a drain electrode. Specifically, the first source / drain 1 can be a source electrode, and the second source / drain 2 can be a drain electrode. Alternatively, the first source / drain 1 can be a drain electrode, and the second source / drain 2 can be a source electrode.

[0062] The material of the first source / drain 1 and the second source / drain 2 is not limited in the embodiments of the present application. The material of the first source / drain 1 and the second source / drain 2 can be the same or different. The first source / drain 1 and the second source / drain 2 can be a single layer or a stacked multi-layer structure. The material of each layer can be the same or different.

[0063] As an example, the material of the first source / drain 1 and the second source / drain 2 can be metal, metal alloy, conductive metal oxide or conductive metal nitride, etc. Specifically, the metal material can be tungsten (W), molybdenum (Mo), nickel (Ni), copper (Cu), tantalum (Ta), titanium (Ti) or aluminum (Al), for example; the metal alloy material can be an alloy including two or more of the above-mentioned metals, such as an alloy material TiAl composed of two elements of titanium and aluminum; the conductive metal oxide can be indium tin oxide (ITO), for example; and the conductive metal nitride can be titanium nitride (TiN), for example.

[0064] The contact layer is an oxidation-resistant conductive layer and / or a film layer for reducing the Schottky barrier.

[0065] The contact layer can be a double layer or a single layer. If it is a double layer, the second layer is formed after the first layer is formed, and then the self-assembled monolayer is removed before the semiconductor layer is formed.

[0066] As an example, the single-layer contact layer can only have the function of oxidation-resistant conductivity, or can have the functions of oxidation-resistant conductivity and reducing the Schottky barrier between the source or drain electrode and the semiconductor layer.

[0067] The double layer can have only the function of oxidation-resistant conductivity or only the function of reducing the Schottky barrier, or have the functions of oxidation-resistant conductivity and reducing the Schottky barrier, respectively.

[0068] In the above-mentioned embodiments, the upper surface of the second source / drain 2 has no protective layer, and the upper surface and the sidewall are exposed at the same time. At this time, the exposed area forms a contact layer.

[0069] The present application is not limited to the above-mentioned embodiments. For example, the first source / drain 1 and the second source / drain 2 in the stack structure include a laminated layer, and the second source / drain 2 has a dielectric layer thereon. The via hole penetrates the dielectric layer, the second source / drain 2 and the interlayer dielectric layer 5 to expose the first source / drain 1. The self-assembled monolayer is provided on the exposed dielectric layer or insulating layer in the hole, and the other areas are the first source / drain 1 and the second source / drain 2 complementary to the pattern of the dielectric layer or insulating layer.

[0070] The extension position of the via hole has different embodiments. The via hole can extend to the upper surface of the first source / drain 1, or extend into the first source / drain 1 while exposing the sidewall, or penetrate the first source / drain 1 to expose the dielectric layer or substrate below the first source / drain 1. The non-conductive layer exposed can form a self-assembled monolayer as a mask for forming the contact layer on the first source / drain 1 and the second source / drain 2.

[0071] For ease of understanding and description, please refer to Figure 1It is understood that the surface of the contact layer 3 in contact with the first source / drain 1 is defined as a first contact surface, and the surface connected to the first contact surface is defined as a first end surface; meanwhile, the surface of the contact layer 3 in contact with the second source / drain 2 is defined as a second contact surface, and the surface connected to the second contact surface is defined as a second end surface. As an example, the contact layer 3 can be a conductive thin film, which extends along the sidewall of the via T and has two opposite end surfaces in the extending direction; that is, the first end surface and the second end surface are opposite end surfaces.

[0072] For further understanding Figure 1 In some embodiments, the first end surface of the contact layer 3 can be flush with the surface of the first source / drain 1 close to the second source / drain 2. In some embodiments, the second end surface of the contact layer 3 can be flush with the surface of the second source / drain 2 close to the first source / drain 1. The one end or the other end of the contact layer is an end surface between the main surfaces of the contact film layer.

[0073] As an example, the first end surface of the contact layer 3 can be flush with the surface of the first source / drain 1 close to the second source / drain 2; meanwhile, the second end surface of the contact layer 3 can also be flush with the surface of the second source / drain 2 close to the first source / drain 1. At this time, as Figure 1 shown, the pattern of the contact layer 3 overlaps with the pattern of the first source / drain 1 and the second source / drain 2, and is complementary to the pattern of the interlayer dielectric layer 5 exposed to the via T.

[0074] It can be understood that the contact layer between the first source / drain 1 and the semiconductor layer overlaps with the pattern of the first source / drain 1 exposed in the via. The contact layer between the second source / drain 2 and the semiconductor layer overlaps with the pattern of the second source / drain 2 exposed in the via.

[0075] The application does not make specific limitations on the material constituting the contact layer 3. As an example, in the application, the contact layer 3 can be constituted by a conductive material with high oxidation resistance; wherein the conductive material with high oxidation resistance refers to a conductive material with higher oxidation resistance than the conductive material of the first source / drain 1 and the second source / drain. As an example, the conductive material with high oxidation resistance can include a conductive transition metal nitride material. The conductive transition metal nitride material can be, for example, tantalum metal nitride (TaN x ), vanadium (V) metal nitride, chromium (Cr) metal nitride, manganese (Mn) metal nitride, iron (Fe) metal nitride, cobalt (Co) metal nitride, nickel (Ni) metal nitride, etc.

[0076] As an example, the conductive material with high oxidation resistance can also include a tantalum metal oxide (TaO x). The bond energy of the tantalum metal oxide is greater than the bond energy of the tantalum metal nitride, and thus the tantalum metal oxide has more stable chemical properties than the tantalum metal nitride; and the tantalum metal oxide is a high dielectric constant material (high-k material), which is also conducive to improving the electrical performance of the semiconductor device.

[0077] Please continue to refer to Figure 1 In some embodiments, the thickness of the semiconductor layer 4 formed by the ALD method and exposed on the surface of the via T is equal to the thickness of the semiconductor layer 4 exposed on the surface of the contact layer 3.

[0078] Please refer to Figure 2 In some embodiments, the semiconductor device can further include a gate dielectric layer 7 and a gate electrode 8.

[0079] The gate dielectric layer 7 is conformally coated on the semiconductor layer 4; and the gate electrode 8 is located on the gate dielectric layer 7 and fills the hole

[0080] As shown in Figure 2 In some embodiments, the channel direction between the first source / drain electrode 1 and the second source / drain electrode 2 extends generally along a direction perpendicular to the substrate.

[0081] It should be noted that when the channel direction between the first source / drain electrode 1 and the second source / drain electrode 2 extends generally along a direction perpendicular to the substrate, the semiconductor layer 4 can be formed, for example, as shown in Figure 2 The gate electrode 8 is surrounded by the semiconductor layer 4 and at least fills the via T; or the gate electrode 8 can be formed on the outer sidewall of the semiconductor layer 4, and the via T can be filled with an insulating layer, a barrier layer, and / or a back gate, etc.

[0082] In other embodiments, please refer to Figure 3 The gate electrode 8 is located on the substrate 10 and extends along a direction perpendicular to the substrate 10. The semiconductor layer 4 surrounds the gate electrode 8, and the gate dielectric layer 7 is located between the gate electrode 8 and the semiconductor layer 4 to insulate the gate electrode 8 and the semiconductor layer 4 from each other.

[0083] As an example, as shown in Figure 3 The channel direction between the first source / drain electrode 1 and the second source / drain electrode 2 can extend generally along a direction parallel to the substrate 10. For example, the first source / drain electrode 1 and the second source / drain electrode 2 can be arranged in the same layer in a direction parallel to the substrate 10, and the first source / drain electrode 1 and the second source / drain electrode 2 have a spacing in the direction parallel to the substrate 10.

[0084] In another aspect, the present application provides, according to some embodiments, a method for manufacturing a semiconductor device. It should be noted that the method for manufacturing a semiconductor device in the embodiments of the present application can be used to manufacture the corresponding semiconductor device, and thus the technical features of the method embodiments and the structure embodiments can be replaced and supplemented with each other without conflict, so as to enable those skilled in the art to understand the technical content of the present application.

[0085] Please refer to Figure 4 In some embodiments, the method for manufacturing a semiconductor device can specifically include the following steps:

[0086] S100: providing a first source / drain, an interlayer dielectric layer and a second source / drain which are stacked in sequence in a direction perpendicular to the substrate.

[0087] Of course, the formation of the stacked structure at least includes the stacked first source / drain, interlayer dielectric layer and second source / drain, and can also include an insulating layer below the first source / drain and an insulating layer above the second source / drain. Both the insulating layer and the interlayer dielectric layer can be silicon oxide.

[0088] S200: forming a via hole which penetrates the second source / drain and the interlayer dielectric layer in a direction perpendicular to the substrate and extends to the first source / drain. Of course, it can be a hole which penetrates the stacked structure, and the hole can extend to the first source / drain layer, or penetrate the first source / drain layer, or only extend into part of the first source / drain layer.

[0089] S300: forming a self-assembled monolayer in an adsorption relationship with the interlayer dielectric layer on the side wall of the via hole exposed to the interlayer dielectric layer.

[0090] Of course, it can be that the self-assembled monolayer is formed in the stacked structure in the insulating layer region of the first source / drain and the second source / drain inside the via hole.

[0091] S400: using the self-assembled monolayer as a mask to form a contact layer on the region of the first source / drain and the second source / drain exposed to the side wall of the via hole, and the contact layer has the same pattern as the corresponding first source / drain or second source / drain.

[0092] S500: removing the self-assembled monolayer.

[0093] S600: forming a semiconductor layer on the surface of the contact layer and the interlayer dielectric layer exposed to the via hole.

[0094] The semiconductor layer is formed in the via hole and covers the regions connected to the contact layer. A channel is formed between the two spaced contact layers.

[0095] In the preparation method provided in the above embodiments, the self-assembled monolayer is formed by selectively exposing the interlayer dielectric layer to the sidewall of the via hole, and the self-assembled monolayer is used as a mask to form the contact layer on the sidewall of the via hole exposed to the first source / drain electrode and the second source / drain electrode. The process is simple and low in cost.

[0096] It should be understood that, although Figure 4 the steps in the flowchart of the method are shown in sequence according to the arrows, the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other sequences. Moreover, Figure 4 at least part of the steps in the method can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of the steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0097] In order to more clearly illustrate the preparation method in some of the above embodiments, the following please combine Figures 1 to 3 and Figures 5 to 13 understand some embodiments of the present application.

[0098] In step S100, referring to Figures 5 to 7 , a first source / drain electrode 1, an interlayer dielectric layer 5 and a second source / drain electrode 2 are provided which are insulated in a direction perpendicular to the substrate.

[0099] As an example, in the embodiments of the present application, the substrate can be made of semiconductor material, insulating material, conductor material or any combination of material types thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrate or II / VI semiconductor substrate. Or, for example, the substrate can be a layered substrate including a stack such as Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) or a silicon-on-silicon germanium.

[0100] The embodiments of the present application do not make specific limitations on the way of forming the first source / drain electrode 1, the interlayer dielectric layer 5 and the second source / drain electrode 2 in step S100. As an example, the first source / drain electrode 1, the interlayer dielectric layer 5 and the second source / drain electrode 2 can be formed by the following steps, such as:

[0101] A first conductive material layer, an interlayer dielectric material layer, and a second conductive material layer are sequentially formed in a direction perpendicular to the substrate; then, the second conductive material layer, the interlayer dielectric material layer, and the first conductive material layer are patterned simultaneously or sequentially to form a second source / drain 2, an interlayer dielectric layer 5, and a first source / drain 1, respectively.

[0102] This step allows a larger film layer to form multiple source and drain electrodes corresponding to multiple memory cells, with the source and drain electrodes isolated between different memory cells. The source and drain electrodes can be block or strip structures of different layers. The source and drain electrodes can be an initial pattern, which will be further patterned subsequently.

[0103] In some embodiments, such as Figure 5 As shown, an insulating dielectric layer 9 can be formed on one side surface of the substrate. Based on this, in step S100, the first source / drain 1 and the second source / drain 2 can be formed on the surface of the insulating dielectric layer 9 away from the substrate.

[0104] In the fabrication method provided in the above embodiments, the substrate is isolated from the first source / drain 1 by forming an insulating dielectric layer 9 to prevent direct current flow. This helps reduce short circuits and leakage in the semiconductor device and ensures that the current flows along the designed circuit path. Furthermore, the insulating dielectric layer 9 can prevent electrons from escaping from the substrate or entering the substrate from the first source / drain 1, thereby improving the reliability of the semiconductor device.

[0105] This application does not specifically limit the constituent materials of the insulating dielectric layer 9. As an example, the insulating dielectric layer 9 may include, but is not limited to, a non-metallic oxide layer. The non-metallic oxide layer may, for example, be a silicon oxide (SiO2) layer.

[0106] It can be understood that the interlayer dielectric layer 5 is formed between the first source / drain 1 and the second source / drain 2 to achieve mutual insulation between the first source / drain 1 and the second source / drain 2.

[0107] This application does not specifically limit the material of the interlayer dielectric layer 5. As an example, the material of the interlayer dielectric layer 5 may include, but is not limited to, low-k materials. The interlayer dielectric layer 5 may be a single layer or a multilayer structure with stacked layers, and the material of each layer may be the same or different.

[0108] This application does not specifically limit the constituent materials of the interlayer dielectric layer 5. In some embodiments, the interlayer dielectric layer 5 may include, but is not limited to, a non-metallic oxide layer. The non-metallic oxide layer may be, for example, a silicon oxide layer.

[0109] As an example, the surface of interlayer dielectric layer 5 may have at least hydroxyl groups.

[0110] Exemplarily, the interlayer dielectric layer 5 can include a silicon oxide film layer with hydroxyl groups on the surface. It can be understood that the surface of the silicon oxide film layer will react with moisture in the environment to form hydrogen bonds and adsorb water molecules, so that a large number of hydroxyl groups (-OH) are formed on the surface of the silicon oxide film layer. In some embodiments, the surface hydroxyl groups of the interlayer dielectric layer 5 can be naturally adsorbed in the environment without additional processing. In addition, after the self-assembled monolayers (SAM) are removed, the hydroxyl groups are also treated and will not be in contact with the metal oxide semiconductor layer.

[0111] As an example, after the interlayer dielectric layer 5 is formed on the surface of the first source / drain electrode 1, and before the second source / drain electrode 2 is formed, a step of planarizing the surface of the interlayer dielectric layer 5 away from the first source / drain electrode 1 can be further included. The planarization process can eliminate the unevenness and non-uniformity of the surface of the interlayer dielectric layer 5, so that the interface between the second source / drain electrode 2 and the surface of the interlayer dielectric layer 5 is formed in a better topography, which is beneficial to improve the production yield of the preparation method and the use reliability of the semiconductor device.

[0112] In step S200, please refer to Figure 8 , a through hole T is formed through the second source / drain electrode 2 and the interlayer dielectric layer 5 in a direction perpendicular to the substrate, and at least extends to the first source / drain electrode 1. At this time, the source electrode and the drain electrode formed in the last step are patterned to form the final electrode structure, and the electrode away from the substrate is penetrated to form a ring-shaped electrode, or an electrode with a through hole. Whether the electrode close to the substrate is penetrated or partially penetrated, or only stays on the surface of the film layer depends on the requirement.

[0113] The embodiments of the present application do not make specific limitations on the way of forming the through hole T in the above steps. As an example, but not limited to, a photolithography etching process can be used to etch the second source / drain electrode 2, the interlayer dielectric layer 5 and the first source / drain electrode 1 to form the through hole T.

[0114] As an example, a photolithography etching process can be used to etch the second source / drain electrode 2, the interlayer dielectric layer 5 and the first source / drain electrode 1 to form the through hole T.

[0115] It should be noted that in some embodiments, the through hole T can only extend to the top surface of the film layer of the first source / drain electrode 1; in other embodiments, as shown in Figure 8 , the through hole T can extend into the film layer of the first source / drain electrode 1, but not penetrate the first source / drain electrode 1; in yet other embodiments, the through hole T can penetrate the upper and lower surfaces of the film layer of the first source / drain electrode 1, at this time, the first source / drain electrode 1 has a ring-shaped through hole, which surrounds the semiconductor layer on the side wall of the through hole.

[0116] In step S300, please refer to Figure 9 A self-assembled monolayer 6 is formed on the sidewall of the via T exposed to the interlayer dielectric layer 5.

[0117] In the above step S300, by forming the self-assembled monolayer 6 on the sidewall of the via T exposed to the interlayer dielectric layer 5, the self-assembled monolayer 6 is generally not reacted with the precursor used when forming the contact layer in the subsequent process, so that the contact layer is not formed on the surface of the interlayer dielectric layer 5 exposed to the via T, thereby realizing selective deposition of the contact layer and ensuring that the contact layer can be accurately formed on the sidewall of the first source / drain 1 and the second source / drain 2 exposed to the via T.

[0118] Self-assembled monolayer (SAM) refers to a thin film or coating with a monomolecular thickness. Specifically, it refers to a monolayer with specific structure and function formed on a solid surface by using the interaction between molecules and self-assembly properties. Self-assembled monolayer is usually constructed using surface active molecules (such as fatty acids, phospholipids, etc.) or organic molecules with self-assembly properties.

[0119] SAM generally includes a head group and a tail group (referred to as a tail group). The tail group of the embodiment of the present application will be adsorbed with the interlayer dielectric layer 5.

[0120] The embodiment of the present application does not make specific limitation on the constituent material of the self-assembled monolayer 6. In some embodiments, the self-assembled monolayer 6 can include long-chain organic molecules. The long-chain organic molecules can be combined with the molecules (such as silicon oxide) of the interlayer dielectric layer 5 through chemical adsorption.

[0121] As an example, the long-chain organic molecule contains at least a fluorinated alkyl group, which is the tail group of the long-chain organic molecule, referred to as a fluorinated (F) alkyl tail group.

[0122] For example, the organic molecules of the self-assembled monolayer 6 can include 1H, 1H, 2H, 2H-perfluorooctyltrichlorosilane ((Cl)3Si(CH2)2(CF2)5CF3, abbreviated as FOTS), Figure 10 (a) of FIG. 1 shows a chemical ratio model of FOTS. For another example, the organic molecules of the self-assembled monolayer 6 can include (heptadecafluoro-1, 1, 2, 2-tetrahydrodecyl) triethoxysilane ((CH3CH2O)3Si(CH2)2(CF2)7CF3, abbreviated as HDFTEOS), Figure 10 (b) of FIG. 1 shows a chemical ratio model of HDFTEOS.

[0123] In some embodiments, the F-alkyl tail group in the long-chain organic molecules can be chemically adsorbed to the hydroxyl groups on the surface of the ILD layer 5.

[0124] The ILD layer 5 is exemplarily illustrated as a silicon oxide film layer with hydroxyl groups. Both FOTS and HDFTEOS contain F-alkyl tail groups, and thus can be combined with the silicon oxide film layer with hydroxyl groups of the silicon oxide layer rich in hydroxyl groups, but not with the materials constituting the first source / drain 1 and the second source / drain 2, so as to form a self-assembled monolayer 6 on the surface of the silicon oxide layer with hydroxyl groups exposed to the gate via T.

[0125] In addition, neither FOTS nor HDFTEOS reacts with the precursors (e.g., Ta[N(CH3)2]5) used in most atomic layer deposition processes, and thus the self-assembled monolayer 6 is not formed on the surface of the first source / drain 1 exposed to the gate via T, the surface of the second source / drain 2 exposed to the gate via T, or the surface of the second source / drain 2, and the contact layer 3 can be selectively deposited on the surface of the first source / drain 1 exposed to the via T and the surface of the second source / drain 2 exposed to the via T.

[0126] As an example, ammonia can be used as the first reaction gas in the process of forming the self-assembled monolayer 6 in step S300, but is not limited thereto. The first reaction gas is used to provide a suitable environment and conditions to promote the adsorption and chemical reaction of the organic molecules, and to regulate the properties and structure of the self-assembled monolayer 6.

[0127] In step S400, please refer to Figure 11 It is understood that the self-assembled monolayer 6 is used as a mask to form the contact layer 3 on the sidewalls of the first source / drain 1 and the second source / drain 2 exposed to the via T.

[0128] In the above step S400, the contact layer 3 is only formed on the sidewalls of the first source / drain 1 and the second source / drain 2 exposed to the via T, and is not formed on the ILD layer covered by the self-assembled monolayer 6. As an example, the self-assembled monolayer 6 can be a long-chain organic molecule containing a F-alkyl tail group, which does not react with most precursors, so as to realize the selective deposition of the contact layer 3; that is, the contact layer 3 is only deposited on the sidewalls of the first source / drain 1 and the second source / drain 2 exposed to the via T.

[0129] The embodiments of the present application do not make specific limitations on the method of forming the contact layer 3 in the above steps. In some embodiments, the atomic layer deposition (ALD) process can be used to form the contact layer 3 on the sidewalls of the first source / drain 1 and the second source / drain 2 exposed to the via T, but is not limited thereto.

[0130] As mentioned above, in the embodiments of this application, the contact layer 3 can be made of a conductive transition metal nitride material. The conductive transition metal nitride material can be, for example, tantalum metal nitride, vanadium metal nitride, chromium metal nitride, manganese metal nitride, iron metal nitride, cobalt metal nitride, nickel metal nitride, etc.

[0131] The transition metals indicate transition metal elements in the periodic table.

[0132] The constituent materials of contact layer 3 include tantalum metal nitride (TaN). x Materials containing Ir, such as TaN, are also included. x For example, the process of forming contact layer 3 using atomic layer deposition (ALD) may specifically include the following steps:

[0133] A precursor and a second reactant gas are alternately introduced into the reaction chamber, causing the precursor and the second reactant gas to be chemically adsorbed onto the surface of the first source / drain 1 exposed to the via T and the surface of the second source / drain 2 exposed to the via T. The precursor can be, for example, tantalum nitride precursor Ta[N(CH3)2]5, and the second reactant gas can be, for example, ammonia (NH3).

[0134] This application does not specifically limit the reaction temperature in the above-described atomic layer deposition process. As an example, in the formation of TaN using atomic layer deposition... x During the process, the reaction temperature can be 225℃~300℃; for example, the reaction temperature can be 225℃, 250℃, 275℃ or 300℃, etc.

[0135] In step S500, please refer to... Figure 1 Remove the self-assembled monolayer 6.

[0136] This application does not specifically limit the method of removing the self-assembled monolayer 6 in step S320. As an example, water vapor hydrolysis or silane pyrolysis can be used to remove the self-assembled monolayer 6, while simultaneously removing the hydroxyl groups.

[0137] Please combine Figures 12 to 13 Understood, the following describes materials formed using atomic layer deposition (ALD) processes, including TaN. x The contact layer 3 is used as an example. In this example, the interlayer dielectric layer 5 includes a host structure, such as silicon dioxide or low-K materials containing carbon, and may also include an isolation layer between the silicon dioxide and the semiconductor layer, such as an H-blocking or O-blocking isolation layer, which can adsorb and self-assemble monolayers.

[0138] The first source / drain 1 and the second source / drain 2 are both made of materials including copper, Ni, Mo, Ti, TiN, etc.

[0139] exist Figure 12 Figure (a) and Figure 12 In Figure (b), the horizontal axis "Number of ALD cycles" represents the number of contact layers 3 (TaN) formed using atomic layer deposition (ALD) technology. x The number of atomic layer deposition cycles during the process, with the vertical axis representing the initial growth rate (A-cycle). -1 ) represents the initial growth rate.

[0140] exist Figure 12 In Figure (a), bare SiO2 represents TaN. x The curve showing the relationship between the number of atomic layer deposition cycles and the initial growth rate during atomic layer deposition on an untreated silicon oxide layer; FOTS|SiO2 shows the formation of a self-assembled monolayer 6 of organic molecules including FOTS on the surface of the silicon oxide layer exposed to the via T, and the TaN x The curve showing the relationship between the number of atomic layer deposition cycles and the initial growth rate; HDFTEOS|SiO2 shows the formation of a self-assembled monolayer 6 of organic molecules including HDFTEOS on the surface of the silicon oxide layer exposed to the via T, and the TaN x The relationship between the number of atomic layer deposition cycles and the initial growth rate is shown in the curve.

[0141] exist Figure 12 In Figure (b), bare Cu represents TaN. x The curve showing the relationship between the number of atomic layer deposition cycles and the initial growth rate during atomic layer deposition on copper; FOTS|Cu shows the formation of a self-assembled monolayer 6 containing organic molecules including FOT S, and TaN. x The curve showing the relationship between the number of atomic layer deposition cycles and the initial growth rate during atomic layer deposition on copper; HDFTEOS|Cu shows the formation of a self-assembled monolayer of organic molecules including HDFTEOS 6, TaN x The curve showing the relationship between the number of atomic layer deposition cycles and the initial growth rate during atomic layer deposition on a copper layer.

[0142] contrast Figure 12 Figure (a) in the middle and Figure 12As shown in Figure (b), the formation of the self-assembled monolayer 6 has virtually no impact on the initial growth rate of the contact layer 3 on the surfaces of the first source / drain 1 exposed to the via T and the second source / drain 2 exposed to the via T; however, the growth of the contact layer 3 is hindered at the self-assembled monolayer 6. Therefore, in this embodiment, the formation of the self-assembled monolayer 6 can suppress the growth of the contact layer 3 on the surface exposed to the interlayer dielectric layer 5, thereby achieving selective deposition of the contact layer 3 on the inner sidewall of the via.

[0143] exist Figure 13 Figure (a) and Figure 13 In Figure (b), the horizontal axis is TaN x thickness This represents the contact layer 3 (TaN) formed using atomic layer deposition technology. x The thickness of ) on the ordinate is Ta LEISS(eV-counts-s -1 It can be used to characterize the content of Ta element.

[0144] exist Figure 13 In Figure (a), bare SiO2 represents TaN. x When performing atomic layer deposition on an untreated silicon oxide layer, the resulting TaN... x The curve showing the relationship between thickness and Ta element content; FOTS|SiO2 shows the TaN obtained by atomic layer deposition when a self-assembled monolayer 6 of organic molecules including FOTS is formed on the surface of the silicon oxide layer exposed to the via T. x The curve showing the relationship between thickness and Ta element content; HDFTEOS|SiO2 shows the TaN obtained by atomic layer deposition when a self-assembled monolayer 6 of organic molecules including HDFTEOS is formed on the surface of the silicon oxide layer exposed to the via T. x The curve showing the relationship between the thickness and the Ta element content.

[0145] exist Figure 13 In Figure (b), bare Cu represents TaN. x When performing atomic layer deposition on a copper layer, the TaN obtained by atomic layer deposition x The curve showing the relationship between thickness and Ta element content; FOTS|Cu shows the TaN obtained by atomic layer deposition after the formation of a self-assembled monolayer containing organic molecules including FOTS. x The curve showing the relationship between thickness and Ta element content; HDFTEOS|Cu shows the TaN obtained by atomic layer deposition after the formation of a self-assembled monolayer containing organic molecules including HDFTEOS. x The curve showing the relationship between the thickness and the Ta element content.

[0146] By contrast Figure 13 Fig. (a) in Figure 13 Fig. (b) in It can be further seen that the formation of the self-assembled monolayer 6 has substantially no effect on the Ta element content of the surface of the via T exposed to the contact layer 3 at the first source / drain 1 and the surface of the via T exposed to the contact layer 3 at the second source / drain 2; however, the growth of the contact layer 3 at the self-assembled monolayer 6 is hindered. Thus, the embodiments of the present application can achieve selective deposition of the contact layer 3 by forming the self-assembled monolayer 6 to inhibit the growth of the contact layer 3 on the surface exposed by the interlayer dielectric layer 5.

[0147] In step S600, please refer to Figure 2 , the semiconductor layer 4 is formed on the surface of the via exposed to both the contact layer 3 and the interlayer dielectric layer 5.

[0148] The embodiments of the present application do not make specific limitations on the constituent material of the semiconductor layer 4. As an example, the semiconductor layer 4 can be a single-layer structure or a multi-layer structure. For example, the constituent material of the semiconductor layer 4 can include but is not limited to metal oxide. The material of the metal oxide can be Indium Gallium Zinc Oxide (IGZO). When the material of the metal oxide is IGZO, the leakage current of the semiconductor device is small (for example, the leakage current can be less than or equal to 15 A), thereby ensuring the low refresh rate of the semiconductor device. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnO x , InO x , In2O3, InWO, SnO2, TiO x , InSnO x , Zn x O y N z , Mg x Zn y O z , In x Zn y O z , In x Ga y Zn z O a , Zr x In y Zn z O a , Hf x In y Zn z O a , Sn x In y Zn z Oa Al x Sn y In z Zn a O d Si x In y Zn z O a Zn x Sn y O z Al x Zn y Sn z O a Ga x Zn y Sn z O a Zr x Zn y Sn z O a IZO, IZOx, and the like, as long as the leakage current of the semiconductor device can meet the requirements. The specific material can be adjusted according to the actual situation.

[0149] The embodiments of the present application do not make specific limitation on the way of forming the semiconductor layer 4. As an example, the semiconductor layer 4 can be formed on the surface of the contact layer 3 and the interlayer dielectric layer 5 exposed to the via by atomic layer deposition process, but is not limited to this.

[0150] It can be understood that when the first source / drain 1 and / or the second source / drain 2 is penetrated, a closed ring is formed in the corresponding first source / drain 1 and / or the second source / drain 2, and the first source / drain 1 and / or the second source / drain 2 can completely surround the semiconductor layer 4.

[0151] In some embodiments, after the semiconductor layer 4 is formed in step S600, the method for manufacturing the semiconductor device can further include the following steps:

[0152] The surface of the semiconductor layer 4 away from the contact layer 3 is covered with the gate dielectric layer 7, and the surface of the gate dielectric layer 7 away from the semiconductor layer 4 is formed with the gate 8.

[0153] As an example, the gate 8 can at least fill the via T. In some embodiments, the top surface of the gate 8 can also be higher than the top surface of the gate dielectric layer 7.

[0154] The embodiment of the present application does not make specific limitation on the material of the gate dielectric layer 7. As an example, the material of the gate dielectric layer 7 can include but is not limited to high dielectric constant material. The high-k material can be, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), etc.

[0155] The embodiment of the present application does not make specific limitation on the material of the gate electrode 8. As an example, the material of the gate electrode 8 can include but is not limited to indium zinc oxide (IZO), indium tin oxide, titanium nitride, tungsten, etc.

[0156] In another aspect, the present application also provides an electronic device according to some embodiments. The semiconductor device can include the semiconductor device provided in any of the foregoing embodiments.

[0157] The electronic device can include a smart phone, a computer, a tablet computer, an artificial intelligence, a wearable device, or a smart mobile terminal, etc.

[0158] It can be understood that the structure of the semiconductor device can refer to the related description in some of the foregoing embodiments. The semiconductor device can further include other necessary elements or components, which are not limited in the embodiments of the present application.

[0159] In the embodiments of the present application, the semiconductor device adopts the semiconductor device provided in some of the foregoing embodiments, which can avoid the decrease of the on-state current and is beneficial to improve the electrical performance of the semiconductor device. It can be understood that the semiconductor device can achieve the technical effects of the foregoing semiconductor device, and thus the description is not repeated here.

[0160] The technical features of the above-described embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features of the above-described embodiments are not described, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0161] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A stacked structure comprising at least a first source / drain, an interlayer dielectric layer, and a second source / drain is provided, which are sequentially formed in a direction perpendicular to the substrate. A via is formed in the stacked structure, the via penetrating the second source / drain and the interlayer dielectric layer in a direction perpendicular to the substrate, and extending at least to the first source / drain; At least the interlayer dielectric layer is exposed on the sidewall of the via, and a self-assembled monolayer with an adsorption relationship with the interlayer dielectric layer is formed on the sidewall, such that the first source / drain electrode and the second source / drain electrode not covered by the self-assembled monolayer are exposed inside the via. Using the self-assembled monolayer as a mask, contact layers are formed on the first source / drain and the second source / drain. Remove the self-assembled monolayer; the contact layers on the first source / drain electrode and the second source / drain electrode are isolated by the interlayer dielectric layer; A semiconductor layer is formed on the sidewall inside the via, and the semiconductor layer is connected to the contact layer on the first source / drain and the second source / drain.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The contact layer includes an antioxidant conductive layer and / or a film layer that lowers the Schottky barrier.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The self-assembled monolayer comprises long-chain organic molecules; the long-chain organic molecules are bonded to the molecules of the interlayer medium layer through chemisorption.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The long-chain organic molecule contains at least a fluorinated alkyl group, wherein the fluorinated alkyl group is the tail group of the long-chain organic molecule; The contact layer is formed using atomic layer deposition (ALD); the interlayer dielectric layer includes a non-metallic oxide layer.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The surface of the interlayer dielectric layer has at least hydroxyl groups; The fluoroalkyl groups in the long-chain organic molecules are bonded to the hydroxyl groups on the surface of the interlayer medium layer via chemisorption.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The interlayer dielectric layer includes a silicon oxide film layer with hydroxyl groups on its surface.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The components of the self-assembled monolayer include 1H,1H,2H,2H-perfluorooctyltrichlorosilane and / or (heptadecylfluoro-1,1,2,2-tetrahydrodecyl)triethoxysilane. In the process of forming the self-assembled monolayer that is adsorbed onto the interlayer medium layer, the first reaction gas includes at least ammonia.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, In the process of forming the contact layer in the through-hole using the self-assembled monolayer as a mask, the reaction precursor includes at least a pentamethyldiamine tantalum complex, the second reaction gas includes at least ammonia, and the reaction temperature is 225℃~300℃.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The self-assembled monolayer is removed using a steam hydrolysis process or a silane pyrolysis process.

10. The method for fabricating a semiconductor device according to claim 2, characterized in that, The contact layer comprises a tantalum metal nitride layer.

11. A semiconductor device, characterized in that, The semiconductor device is prepared by the preparation method as described in any one of claims 1 to 10.

12. The semiconductor device according to claim 11, characterized in that, The semiconductor layer has the same thickness in all regions.

13. The semiconductor device according to claim 11, characterized in that, The pattern of the contact layer on the first source / drain overlaps with the pattern of the first source / drain; The pattern of the antioxidant conductive layer on the second source / drain overlaps with the pattern of the second source / drain.

14. The semiconductor device according to claim 11, characterized in that, The contact layer includes a tantalum metal nitride layer.

15. The semiconductor device according to claim 11, characterized in that, The interlayer dielectric layer comprises a silicon oxide film layer.

16. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 11 to 15.

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