Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes: a substrate; a first magnetic tunnel junction structure disposed over a portion of the substrate and including a first free layer; a first hard mask layer disposed over the first free layer; a second magnetic tunnel junction structure disposed over another portion of the substrate and including a second free layer having a thickness less than a thickness of the first free layer; a second hard mask layer disposed over the second free layer; and a doped layer interposed between the second free layer and the second hard mask layer and having conductivity.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0115232, filed on August 31, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology disclosed in this patent document relates to semiconductor technology, and in particular, to a semiconductor device including a magnetic tunnel junction and a method for manufacturing the semiconductor device. Background Art

[0004] Recent trends in the electrical and electronic industries toward miniaturization, low power consumption, high performance, and multifunctionality have forced semiconductor manufacturers to focus on high-performance, high-capacity semiconductor devices. Examples of such high-performance, high-capacity semiconductor devices include semiconductor devices that can store data by switching between different resistance states according to an applied voltage or current, such as RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), and electronic fuses (E-fuse). Summary of the invention

[0005] In one embodiment, a semiconductor device may include: a substrate; a first magnetic tunnel junction structure, which is disposed over a portion of the substrate and includes a first free layer; a first hard mask layer, which is disposed over the first free layer; a second magnetic tunnel junction structure, which is disposed over another portion of the substrate and includes a second free layer, the second free layer having a thickness less than that of the first free layer; a second hard mask layer, which is disposed over the second free layer; and a doped layer, which is interposed between the second free layer and the second hard mask layer and has conductivity.

[0006] In another embodiment, a semiconductor device may include: a substrate; a first magnetic tunnel junction structure, which is disposed above a portion of the substrate and includes a first free layer; a first hard mask layer, which is disposed above the first free layer; a second magnetic tunnel junction structure, which is disposed above another portion of the substrate and includes a second free layer, the second free layer having a thickness less than the thickness of the first free layer; and a second hard mask layer, which is disposed above the second free layer, wherein the thickness of the first hard mask layer is less than the thickness of the second hard mask layer.

[0007] In another embodiment, a method for manufacturing a semiconductor device may include: forming a magnetic tunnel junction layer above a substrate, the magnetic tunnel junction layer including a pinned layer, a tunnel barrier layer and a free layer; forming a sacrificial hard mask layer above the free layer to at least cover a first region in which a first magnetic tunnel junction structure is to be formed and to expose at least a second region in which a second magnetic tunnel junction structure is to be formed; forming a doped region by doping a portion of the free layer exposed by the sacrificial hard mask layer with a dopant that reduces the magnetic properties of the free layer, the doped region having a thickness less than that of the free layer; removing the sacrificial hard mask layer; forming a hard mask layer above the free layer and the doped region to cover the first region and the second region; and etching the doped region, the free layer, the tunnel barrier layer and the pinned layer using the hard mask layer.

[0008] In another embodiment, a method for manufacturing a semiconductor device may include: forming a magnetic tunnel junction layer above a substrate, the magnetic tunnel junction layer including a pinned layer, a tunnel barrier layer, and a free layer; forming a sacrificial hard mask layer above the free layer to at least cover a first region in which a first magnetic tunnel junction pattern is to be formed and to expose at least a second region in which a second magnetic tunnel junction structure is to be formed; etching a portion of the free layer exposed by the sacrificial hard mask layer to reduce the thickness of the portion of the free layer; removing the sacrificial hard mask layer; forming a hard mask layer above the free layer to cover the first region and the second region; and using the hard mask layer to etch the free layer, the tunnel barrier layer, and the pinned layer.

[0009] In another embodiment, a method for manufacturing a semiconductor device may include: forming a magnetic tunnel junction layer above a substrate, the magnetic tunnel junction layer including a pinned layer, a tunnel barrier layer and a free layer; forming a sacrificial hard mask layer above the free layer to at least cover a first area where a first magnetic tunnel junction layer is to be formed and to expose at least a second area where a second magnetic tunnel junction pattern is to be formed; etching a portion of the free layer exposed by the sacrificial hard mask layer to reduce the thickness of the portion of the free layer; forming a metal oxide layer above the sacrificial hard mask layer and the free layer; removing the sacrificial hard mask layer and a portion of the metal oxide layer formed above the sidewalls and upper surface of the sacrificial hard mask layer to form a metal oxide layer; forming a hard mask layer above the free layer and the metal oxide layer to cover the first area where the first magnetic tunnel junction layer is to be formed and the second area where the second magnetic tunnel junction pattern is to be formed; and using the hard mask layer to etch the free layer, the tunnel barrier layer, the pinned layer and the metal oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A and Figure 1B are views illustrating semiconductor devices based on some embodiments of the disclosed technology.

[0011] Figures 2A to 2Gis a cross-sectional view illustrating a method for manufacturing a semiconductor device based on some embodiments of the disclosed technology.

[0012] FIG. 3A to FIG. 3F is a cross-sectional view illustrating a method for manufacturing a semiconductor device based on some embodiments of the disclosed technology.

[0013] FIG. 4A to FIG. 4E is a cross-sectional view illustrating a method for manufacturing a semiconductor device based on some embodiments of the disclosed technology. DETAILED DESCRIPTION

[0014] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0015] The drawings do not have to be drawn to scale. In some cases, the proportions of at least some of the structures in the drawings may have been exaggerated in order to clearly illustrate certain features of the described embodiments. When a specific example with two or more layers in a multilayer structure is presented in the drawings or descriptions, the relative positioning relationship of these layers as shown or the order in which the layers are arranged reflect the specific implementation of the described or illustrated example, and different relative positioning relationships or the order in which the layers are arranged may be possible. In addition, the described or illustrated examples of multilayer structures may not reflect all the layers present in the particular multilayer structure (for example, one or more additional layers may be present between the two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, but may also represent a structure in which one or more other intermediate layers may be present between the first layer and the second layer or substrate.

[0016] Figure 1A and Figure 1B are views illustrating semiconductor devices based on some embodiments of the disclosed technology. Figure 1A is a plan view, and Figure 1B is along Figure 1A A cross-sectional view taken along line A-A'.

[0017] refer to Figure 1A and Figure 1B, a semiconductor device of some embodiments may include: a substrate 100; a plurality of first conductive lines 110, which are disposed above the substrate 100 and extend in a first direction; a plurality of second conductive lines 140, which are disposed above the first conductive lines 110 and extend in a second direction intersecting the first direction; and a stacked structure of a selector pattern 120 and a magnetic tunnel junction pattern (magnetic tunnel junction structure) 130, which is disposed between the first conductive lines 110 and the second conductive lines 140, at each intersection region of the first conductive lines 110 and the second conductive lines 140. Here, the first direction and the second direction may correspond to directions substantially parallel to the surface of the substrate 100. A direction substantially perpendicular to the surface of the substrate 100 will be referred to as a vertical direction hereinafter. In some embodiments of the disclosed technology, the term "pattern" may be used to indicate a material layer arranged in a specific manner. In some embodiments of the disclosed technology, the term "pattern" may be used to indicate a patterned layer, in which a certain layer is selectively etched or patterned.

[0018] The substrate 100 may include a semiconductor material such as silicon. In addition, a desired lower structure (not shown) may be formed in the substrate 100. For example, an integrated circuit for driving the first conductive line 110 and / or the second conductive line 140 may be formed in the substrate 100.

[0019] A plurality of first conductive lines 110 may be arranged to be spaced apart from each other in the second direction. The first conductive line 110 may include at least one of various conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti), metal nitrides such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof, and the first conductive line 110 may have a single-layer structure or a multi-layer structure.

[0020] A plurality of second conductive lines 140 may be arranged to be spaced apart from each other in the first direction. The second conductive line 140 may include at least one of various conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti), metal nitrides such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof, and the second conductive line 140 may have a single-layer structure or a multi-layer structure.

[0021] The selector pattern 120 may have a column shape overlapping an intersection area of ​​the first conductive line 110 and the second conductive line 140. In some embodiments, the selector pattern 120 may have a circular shape in a plan view, but the disclosed technology is not limited thereto, and the selector pattern 120 may have one of various shapes in a plan view, such as an elliptical shape, a rectangular shape, or a square shape.

[0022] The selector pattern 120 can control access to the magnetic tunnel junction pattern (magnetic tunnel junction structure) 130, and can prevent or reduce current leakage that may occur between the magnetic tunnel junction patterns 130 that share the first conductive line 110 or the second conductive line 140. To this end, the selector pattern 120 can have the following threshold switching characteristics: (1) blocking or reducing / minimizing the flowing current when the amplitude of the voltage applied to the upper and lower ends of the selector pattern 120 is less than a predetermined threshold voltage, and (2) allowing the current to increase rapidly at a voltage equal to or greater than the threshold voltage. That is, the selector pattern 120 can be turned on at a voltage equal to or greater than the threshold voltage, and can be turned off when it is lower than the threshold voltage.

[0023] The selector pattern 120 may include a diode, an o-threshold switch (OTS) material (such as a chalcogenide-based material), a mixed ion-electronic conduction (MIEC) material (such as a metal-containing chalcogenide-based material), a metal-insulator transition (MIT) material (such as NbO2 or VO2), or a tunneling insulating material with a relatively wide bandgap (such as SiO2 or Al2O3).

[0024] In some implementations, the selector pattern 120 may include an insulating material layer doped with a dopant. Here, the insulating material layer may include a silicon-containing insulating material (such as silicon oxide, silicon nitride, or silicon oxynitride), an insulating metal oxide, an insulating metal nitride, or a combination thereof. In some implementations, deep traps may exist in the insulating material layer. The energy level of the deep trap may be closer to the energy level of the valence band of the insulating material layer, rather than closer to the energy level of the conduction band of the insulating material layer. The dopant may be used to generate a shallow trap that provides a path for charge carriers (such as electrons or holes) to move within the insulating material layer. The energy level of the shallow trap may be closer to the energy level of the conduction band, rather than closer to the energy level of the valence band of the insulating material layer. As an example, if the insulating material layer contains silicon, the dopant may include a metal having a different valence from silicon, such as gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), tungsten (W), or a combination thereof. Alternatively, when the insulating material layer includes a metal, the dopant may include another metal or silicon having a different valence from the metal. As an example, the selector pattern 120 may include arsenic (As)-doped silicon oxide, such as arsenic (As)-doped silicon dioxide (SiO2). When a voltage equal to or greater than the threshold voltage is applied to the selector pattern 120, the charge carriers trapped in the deep traps may jump into the shallow traps by thermal emission or tunneling, and the charge carriers may move through the shallow traps, and thus the selector pattern 120 may be in an open state (on state) allowing current to flow through the selector pattern 120. On the other hand, when no voltage or a voltage less than the threshold voltage is applied to the selector pattern 120, no charge carriers or fewer charge carriers may jump into the shallow traps, and thus the selector pattern 120 may be transformed into a disconnected state (off state) that does not allow current to flow through the selector pattern 120.

[0025] The magnetic tunnel junction pattern 130 may have a columnar shape overlapping the intersection area of ​​the first conductive line 110 and the second conductive line 140. In some embodiments, the magnetic tunnel junction pattern 130 may have a circular shape in a plan view, but the disclosed technology is not limited thereto, and the magnetic tunnel junction pattern 130 may have one of various shapes in a plan view, such as an elliptical shape, a rectangular shape, or a square shape. In addition, in some embodiments, the selector pattern 120 and the magnetic tunnel junction pattern 130 may be formed by separate patterning processes using different masks. In this case, the selector pattern 120 and the magnetic tunnel junction pattern 130 may overlap each other, but their side walls may not be aligned with each other. However, the disclosed technology is not limited thereto, and in another embodiment, the selector pattern 120 and the magnetic tunnel junction pattern 130 may be formed by a single patterning process using a single mask, and therefore, the selector pattern 120 and the magnetic tunnel junction pattern 130 may overlap each other, and their side walls may be aligned with each other.

[0026] The magnetic tunnel junction pattern 130 may include a stacked structure of a pinning pattern (pinning layer pattern) 131, a tunnel barrier pattern (tunnel barrier layer pattern) 133, and a free pattern (free layer pattern) 135. Unlike the magnetization direction of the free pattern (free layer pattern) 135, the pinning pattern (pinning layer pattern) 131 may be a layer having a fixed magnetization direction. In this regard, the pinning pattern (pinning layer pattern) 131 may also be referred to as a reference layer. The free pattern (free layer pattern) 135 may be a layer having a changeable magnetization direction to store different data, and may also be referred to as a storage layer. The pinning pattern (pinning layer pattern) 131 and the free pattern (free layer pattern) 135 may have a magnetization direction substantially parallel to the surface of the layer, or may have a magnetization direction substantially perpendicular to the surface of the layer. The tunnel barrier pattern (tunnel barrier layer pattern) 133 can physically separate the pinning pattern (pinning layer pattern) 131 from the free pattern (free layer pattern) 135, and can enable electrons to tunnel between the pinning pattern (pinning layer pattern) 131 and the free pattern (free layer pattern) 135. The pinning pattern (pinning layer pattern) 131 and the free pattern (free layer pattern) 135 can independently have a single-layer structure or a multi-layer structure including a ferromagnetic material. As an example, the pinning pattern (pinning layer pattern) 131 and the free pattern (free layer pattern) 135 can independently include: an alloy containing Fe, Ni or Co as a main component, such as Fe-Pt alloy, Fe-Pd alloy, Co-Pd alloy, Co-Pt alloy, Fe-Ni-Pt alloy, Co-Fe-Pt alloy, Co-Ni-Pt alloy and Co-Fe-B alloy; or a stacked structure of Co / Pt or Co / Pd. The tunnel barrier pattern (tunnel barrier layer pattern) 133 may have a single-layer structure or a multi-layer structure including an insulating material. As an example, the tunnel barrier pattern (tunnel barrier layer pattern) 133 may include an insulating oxide such as MgO, CaO, SrO, TiO, VO, or NbO. The magnetic tunnel junction pattern (magnetic tunnel junction structure) 130 may store different data values ​​by switching between different resistance states depending on a voltage or current applied through the first conductive line 110 and the second conductive line 140. More specifically, when the magnetization direction of the free pattern (free layer pattern) 135 changes depending on a voltage or current applied to the magnetic tunnel junction pattern 130 and becomes parallel to the magnetization direction of the pinning pattern (pinning layer pattern) 131, the magnetic tunnel junction pattern 130 may have a low resistance state, and, for example, a data bit "1" may be stored. On the other hand, when the magnetization direction of the free pattern (free layer pattern) 135 changes depending on the voltage or current applied to the magnetic tunnel junction pattern 130 and becomes antiparallel to the magnetization direction of the pinned pattern (pinned layer pattern) 131, the magnetic tunnel junction pattern 130 can have a high resistance state and, for example, can store a data bit "0".

[0027] The structure of the magnetic tunnel junction pattern (magnetic tunnel junction structure) 130 may be modified in various ways as long as the magnetic tunnel junction pattern (magnetic tunnel junction structure) 130 includes a pinning pattern (pinning layer pattern) 131, a free pattern (free layer pattern) 135 disposed above the pinning pattern (pinning layer pattern) 131, and a tunnel barrier pattern (tunnel barrier layer pattern) 133 between the pinning pattern (pinning layer pattern) 131 and the free pattern (free layer pattern) 135. As an example, the free pattern (free layer pattern) 135 may be disposed above the pinning pattern (pinning layer pattern) 131, and the tunnel barrier pattern (tunnel barrier layer pattern) 133 may be disposed between the pinning pattern (pinning layer pattern) 131 and the free pattern (free layer pattern) 135. Alternatively, as an example, the magnetic tunnel junction pattern (magnetic tunnel junction structure) 130 may further include one or more layers for improving its characteristics. For example, the magnetic tunnel junction pattern 130 may also include one or more pinning patterns, which are antiferromagnetically coupled to the pinning pattern (pinning layer pattern) 131 to form a synthetic antiferromagnetic (SAF) structure. The SAF coupling pattern containing a non-magnetic material may be inserted between the pinning pattern (pinning layer pattern) 131 and an adjacent pinning pattern (pinning layer pattern), and / or between two adjacent pinning patterns. Alternatively, for example, the magnetic tunnel junction pattern 130 may also include one or more conductive patterns, which are inserted between the pinning pattern (pinning layer pattern) 131 and the first conductive line 110 and / or between the free pattern (free layer pattern) 135 and the second conductive line 140. Depending on its function, the conductive pattern may be referred to as an electrode layer, a hard mask layer, or a capping layer.

[0028] In the magnetic tunnel junction pattern 130, when the free pattern (free layer pattern) 135 has a magnetization direction substantially perpendicular to the surface of the layer, the perpendicular magnetic anisotropy of the free pattern (free layer pattern) 135 may be inversely proportional to the thickness of the free pattern (free layer pattern) 135. That is, as the thickness of the free pattern (free layer pattern) 135 increases, the perpendicular magnetic anisotropy of the free pattern (free layer pattern) 135 may decrease. On the other hand, as the thickness of the free pattern (free layer pattern) 135 decreases, the perpendicular magnetic anisotropy of the free pattern (free layer pattern) 135 may increase. When the perpendicular magnetic anisotropy increases, the data retention characteristics may be improved, but the operating speed may be reduced and the power consumption may be increased. Therefore, by varying the thickness of the free pattern (free layer pattern) 135 in the magnetic tunnel junction pattern 130, a magnetic tunnel junction pattern 130 having different characteristics may be formed over a single substrate 100. That is, it may be possible to realize a semiconductor device that simultaneously includes: a magnetic tunnel junction pattern 130 having excellent data retention characteristics due to the relatively small thickness of the free pattern (free layer pattern) 135, and a magnetic tunnel junction pattern 130 having high operating speed and low power consumption due to the relatively large thickness of the free pattern (free layer pattern) 135.

[0029] As will be discussed below, a semiconductor device may be formed by adjusting the thickness of a free pattern included in a plurality of magnetic tunnel junction patterns.

[0030] Figures 2A to 2G is a cross-sectional view illustrating a method for manufacturing a semiconductor device based on some embodiments of the disclosed technology. Specifically, Figures 2A to 2G is along Figure 1A A cross-sectional view taken along line AA' in FIG.

[0031] In some embodiments of the disclosed technology, the method for manufacturing the semiconductor device discussed above may include the following steps.

[0032] refer to Figure 2A , a first conductive line 210 extending in a first direction may be formed over the substrate 200. Although not shown, a plurality of first conductive lines 210 may be arranged in parallel with each other and spaced apart from each other in a second direction passing through the cross section. The first conductive lines 210 may be formed by depositing a conductive material and patterning the conductive material. In addition, the spaces between the first conductive lines 210 in the second direction may be filled with an insulating material (not shown).

[0033] Subsequently, a plurality of selector patterns 220 and a first interlayer insulating layer 225 may be disposed over the first conductive lines 210 and the insulating material disposed between the first conductive lines 210, and the first interlayer insulating layer 225 may be formed in the spaces between the selector patterns 220. In some embodiments, the selector patterns 220 and the first interlayer insulating layer 225 may be formed by forming a selector material for forming the selector patterns 220 over the first conductive lines 210 and the insulating material, selectively etching the selector material to form the selector patterns 220, forming the first interlayer insulating material having a thickness sufficient to fill the spaces between the selector patterns 220, and performing a planarization process such as chemical mechanical polishing (CMP) such that the upper surfaces of the selector patterns 220 are exposed. In this case, the selector patterns 220 may have a width that gradually narrows from the bottom to the top in the vertical direction. However, the disclosed technology is not limited thereto, and in another embodiment, the selector pattern 220 and the first interlayer insulating layer 225 may be formed by forming a first interlayer insulating material over the first conductive line 210 and the insulating material therebetween, selectively etching the first interlayer insulating material to form the first interlayer insulating layer 225 providing a space for the selector pattern 220 to be formed, forming the selector material having a thickness sufficient to fill the space, and performing a planarization process such that the upper surface of the first interlayer insulating layer 225 is exposed. In this case, unlike Figure 2A , the selector pattern 220 may have a width that gradually narrows from top to bottom in the vertical direction.

[0034] refer to Figure 2B A magnetic tunnel junction layer may be formed over the selector pattern 220 and the first interlayer insulating layer 225 , the magnetic tunnel junction layer including the pinned layer 230 , the tunnel barrier layer 240 , and the free layer 250 .

[0035] Subsequently, a sacrificial hard mask pattern 260 may be formed over the free layer 250. The sacrificial hard mask pattern 260 may at least cover the region where the first magnetic tunnel junction pattern (see Figure 2F MTJ-A in the embodiment, and may expose at least a region where a second magnetic tunnel junction pattern is to be formed (see Figure 2F The first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern may be spaced apart from each other, and the sacrificial hard mask pattern 260 may not cover the space between the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern, or may cover a portion of the space between the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern. Under this premise, the horizontal width of the sacrificial hard mask pattern 260 (or the size of the sacrificial hard mask pattern 260) may be modified in various ways.

[0036] The sacrificial hard mask pattern 260 may include Figure 2C At least one of various materials used as an etch barrier during a subsequent etching process of the free layer 250 of the sacrificial hard mask pattern 260. In addition, the sacrificial hard mask pattern 260 may include a material that is easily removed. For example, the sacrificial hard mask pattern 260 may include a photoresist that is easily removed by a stripping process or a cleaning process.

[0037] refer to Figure 2C , the initial free pattern 252 may be formed by etching the free layer 250 to a predetermined depth using the sacrificial hard mask pattern 260 as an etch barrier. Here, the etching depth of the free layer 250 may be less than the thickness of the free layer 250. Therefore, a portion of the initial free pattern 252 overlapping the sacrificial hard mask pattern 260 may have a first thickness T1, and another portion of the initial free pattern 252 exposed by the sacrificial hard mask pattern 260 may have a second thickness T2, which is less than the first thickness T1 and greater than 0. The first thickness T1 may be substantially the same as the thickness of the free layer 250.

[0038] refer to Figure 2D After removing the sacrificial hard mask pattern 260, a hard mask layer 270 may be formed over the preliminary free pattern 252. The hard mask layer 270 may be formed to cover all of a portion having the first thickness T1 and a portion having the second thickness T2 of the preliminary free pattern 252.

[0039] refer to Figure 2E , an initial hard mask pattern 272 may be formed by patterning the hard mask layer 270 .

[0040] The initial hard mask pattern 272 may be used to form a magnetic tunnel junction pattern (see Figure 2F The initial hard mask pattern 272 is used as an etching barrier during a subsequent etching process of the MTJ-A and MTJ-B in the initial free pattern 252, and can be formed to cover the area where the magnetic tunnel junction pattern is to be formed. Here, the horizontal width of the initial hard mask pattern 272 (or the size of the initial hard mask pattern 272) can be smaller than the horizontal width of the sacrificial hard mask pattern 260 (or the size of the sacrificial hard mask pattern 260). In addition, the initial hard mask pattern 272 can be retained after the etching process and can be used as a capping layer above the magnetic tunnel junction pattern, which protects the magnetic tunnel junction pattern or improves the characteristics of the magnetic tunnel junction pattern. The initial hard mask pattern 272 may include a conductive material. For example, the initial hard mask pattern 272 may include a metal, a conductive metal oxide, or a conductive metal nitride. The thickness of the initial hard mask pattern 272 above the portion of the initial free pattern 252 having the first thickness T1 may be less than the thickness of the initial hard mask pattern 272 above the portion of the initial free pattern 252 having the second thickness T2.

[0041] refer to Figure 2F, the initial free pattern 252, the tunnel barrier layer 240, and the pinning layer 230 may be etched using the initial hard mask pattern 272 as an etch barrier to form magnetic tunnel junction patterns MTJ-A and MTJ-B including free patterns 254A and 254B, tunnel barrier patterns 242A and 242B, and pinning patterns 232A and 232B. In this process, a portion of the initial hard mask pattern 272 may be etched away to form hard mask patterns 274A and 274B.

[0042] Here, one of the free patterns 254A and 254B may have a first thickness T1 and may be referred to as a first free pattern 254A, and the other of the free patterns 254A and 254B may have a second thickness T2 and may be referred to as a second free pattern 254B. One of the tunnel barrier patterns 242A and 242B may overlap with the first free pattern 254A and may be referred to as a first tunnel barrier pattern 242A, and the other of the tunnel barrier patterns 242A and 242B may overlap with the second free pattern 254B and may be referred to as a second tunnel barrier pattern 242B. One of the pinning patterns 232A and 232B may overlap with the first free pattern 254A and may be referred to as a first pinning pattern 232A, and the other of the pinning patterns 232A and 232B may overlap with the second free pattern 254B and may be referred to as a second pinning pattern 232B. The first free pattern 254A, the first tunnel barrier pattern 242A, and the first pinning pattern 232A may form a first magnetic tunnel junction pattern MTJ-A, and the second free pattern 254B, the second tunnel barrier pattern 242B, and the second pinning pattern 232B may form a second magnetic tunnel junction pattern MTJ-B. In addition, one of the hard mask patterns 274A and 274B may overlap with the first magnetic tunnel junction pattern MTJ-A and may be referred to as a first hard mask pattern 274A, and the other of the hard mask patterns 274A and 274B may overlap with the second magnetic tunnel junction pattern MTJ-B and may be referred to as a second hard mask pattern 274B.

[0043] A height of an upper surface of the first hard mask pattern 274A and a height of an upper surface of the second hard mask pattern 274B from the surface of the substrate 200 may be substantially the same as each other. Since the first thickness T1 of the first free pattern 254A is greater than the second thickness T2 of the second free pattern 254B, the third thickness T3 of the first hard mask pattern 274A may be less than the fourth thickness T4 of the second hard mask pattern 274B.

[0044] refer to Figure 2G , by forming a covering Figure 2FAs a result of the process, a second interlayer insulating layer 280 may be formed by performing a planarization process so that upper surfaces of the first hard mask pattern 274A and the second hard mask pattern 274B are exposed.

[0045] Subsequently, a plurality of second conductive lines 290 extending in the second direction may be formed over the first and second hard mask patterns 274A and 274B and the second interlayer insulating layer 280 .

[0046] In this way, you can Figure 2G A semiconductor device is implemented as shown.

[0047] Reference again Figure 2G , a semiconductor device implemented based on some embodiments may include: a substrate 200; a plurality of first conductive lines 210, which are arranged above the substrate 200 and extend in a first direction; a plurality of second conductive lines 290, which are arranged above the first conductive lines 210 and extend in a second direction intersecting the first direction; and magnetic tunnel junction patterns MTJ-A and MTJ-B and a selector pattern 220, which are arranged between the first conductive lines 210 and the second conductive lines 290 and overlap with the intersection area of ​​the first conductive lines 210 and the second conductive lines 290.

[0048] The magnetic tunnel junction patterns MTJ-A and MTJ-B may include a first magnetic tunnel junction pattern MTJ-A including a first free pattern 254A having a first thickness T1 at an uppermost portion thereof and a second magnetic tunnel junction pattern MTJ-B including a second free pattern 254B having a second thickness T2 at an uppermost portion thereof. The second thickness T2 may be less than the first thickness T1.

[0049] A first hard mask pattern 274A having a third thickness T3 may be interposed between the first magnetic tunnel junction pattern MTJ-A and the second conductive line 290, and a second hard mask pattern 274B having a fourth thickness T4 greater than the third thickness T3 may be interposed between the second magnetic tunnel junction pattern MTJ-B and the second conductive line 290. The sum of the first thickness T1 and the third thickness T3 may be substantially equal to the sum of the second thickness T2 and the fourth thickness T4.

[0050] In some embodiments, since the first magnetic tunnel junction pattern MTJ-A includes the first free pattern 254A having a relatively large thickness and the second magnetic tunnel junction pattern MTJ-B includes the second free pattern 254B having a relatively small thickness, the first magnetic tunnel junction pattern MTJ-A and the second magnetic tunnel junction pattern MTJ-B may have different characteristics from each other. For example, the first magnetic tunnel junction pattern MTJ-A may have a faster operating speed and lower power consumption than the second magnetic tunnel junction pattern MTJ-B, and the second magnetic tunnel junction pattern MTJ-B may have excellent data retention characteristics compared to the first magnetic tunnel junction pattern MTJ-A. As a result, a semiconductor device including magnetic tunnel junction patterns MTJ-A and MTJ-B having different characteristics may be implemented through a simple process.

[0051] FIG. 3A to FIG. 3F is a cross-sectional view illustrating a method for manufacturing a semiconductor device based on some embodiments of the disclosed technology. Specifically, FIG. 3A to FIG. 3F is along Figure 1A A cross-sectional view taken along line AA' in FIG.

[0052] In some embodiments of the disclosed technology, the method for manufacturing the semiconductor device discussed above may include the following steps.

[0053] refer to Figure 3A , first conductive lines 310 extending in the first direction may be formed over the substrate 300. Although not shown, a plurality of first conductive lines 310 may be arranged in parallel with each other and spaced apart from each other in a second direction passing through the cross section.

[0054] Subsequently, over the first conductive lines 310 and the insulating material filled between the first conductive lines 310 , a selector pattern 320 and a first interlayer insulating layer 325 filled between the selector patterns 320 may be formed.

[0055] refer to Figure 3B , a magnetic tunnel junction layer including a pinned layer 330 , a tunnel barrier layer 340 , and a free layer 350 may be formed over the selector pattern 320 and the first interlayer insulating layer 325 .

[0056] Subsequently, a sacrificial hard mask pattern 360 may be formed over the free layer 350. The sacrificial hard mask pattern 360 may at least cover the region where the first magnetic tunnel junction pattern (see Figure 3E MTJ-A') in the region, and may expose at least a region where a second magnetic tunnel junction pattern is to be formed (see Figure 3E Under this premise, the horizontal width of the sacrificial hard mask pattern 360 (and / or the size of the sacrificial hard mask pattern 360) may be modified in various ways.

[0057] The sacrificial hard mask pattern 360 may include Figure 3C At least one of various materials that protects the portion covered by the sacrificial hard mask pattern 360 from the doping chemicals during the subsequent doping process of the sacrificial hard mask pattern 360. In addition, the sacrificial hard mask pattern 360 may include a material that is easily removed, such as a photoresist that is easily removed by a stripping process or a cleaning process.

[0058] refer to Figure 3C By doping a predetermined dopant into the free layer 350 using the sacrificial hard mask pattern 360 as a doping mask, a doping layer 355 may be formed in the free layer 350. The remaining portion of the free layer 350 except the doping layer 355 will be referred to as an initial free pattern 352 hereinafter.

[0059] Here, the doping depth and thickness of the doping layer 355 thus formed may be less than the thickness of the free layer 350. Therefore, a portion of the initial free pattern 352 overlapping the sacrificial hard mask pattern 360 may have a first thickness T1', and another portion of the initial free pattern 352 exposed by the sacrificial hard mask pattern 360 and located under the doping layer 355 may have a second thickness T2', which is less than the first thickness T1' and greater than 0. The first thickness T1' may be substantially the same as the thickness of the free layer 350.

[0060] In some implementations, an ion implantation process may be used as a doping method. The predetermined dopant may include an element that can maintain the conductivity of the free layer 350 while reducing, removing or minimizing the magnetism of the free layer 350. Therefore, the doped layer 355 may be formed of a material containing the constituent elements of the free layer 350 and the element used as the dopant, and may be a magnetic loss region and a conductive region. As an example, the dopant may include an inert element such as Ar. In some implementations, the doped layer 355 may be in an amorphous state.

[0061] refer to Figure 3D After removing the sacrificial hard mask pattern 360, an initial hard mask pattern 370 may be formed over the initial free pattern 352 and the doping layer 355. In some implementations, in order to flatten the surface of the initial free pattern 352 and the surface of the doping layer 355, a planarization process may be further performed before the formation process of the initial hard mask pattern 370.

[0062] The initial hard mask pattern 370 may be used to form a magnetic tunnel junction pattern (see Figure 3EThe initial hard mask pattern 370 may be used as an etching barrier during an etching process of the MTJ-A' and MTJ-B' in the initial free pattern 352, and may be formed to cover an area in which a magnetic tunnel junction pattern is to be formed. In addition, the initial hard mask pattern 370 may remain after the etching process, and may be used as a capping layer to protect the magnetic tunnel junction pattern or improve the characteristics of the magnetic tunnel junction pattern. The initial hard mask pattern 370 may be located above a portion of the initial free pattern 352 having the first thickness T1' and the doping layer 355, and may have a substantially constant thickness.

[0063] refer to Figure 3E , the doping layer 355, the initial free pattern 352, the tunnel barrier layer 340, and the pinning layer 330 may be etched using the initial hard mask pattern 370 as an etch barrier to form magnetic tunnel junction patterns MTJ-A' and MTJ-B' including free patterns 354A and 354B, tunnel barrier patterns 342A and 342B, and pinning patterns 332A and 332B. In this process, a portion of the initial hard mask pattern 370 may be etched away to form hard mask patterns 372A and 372B.

[0064] Here, one of the free patterns 354A and 354B may have a first thickness T1' and may be referred to as a first free pattern 354A, and the other of the free patterns 354A and 354B may have a second thickness T2' and may be referred to as a second free pattern 354B. One of the tunnel barrier patterns 342A and 342B may overlap with the first free pattern 354A and may be referred to as a first tunnel barrier pattern 342A, and the other of the tunnel barrier patterns 342A and 342B may overlap with the second free pattern 354B and may be referred to as a second tunnel barrier pattern 342B. One of the pinning patterns 332A and 332B may overlap with the first free pattern 354A and may be referred to as a first pinning pattern 332A, and the other of the pinning patterns 332A and 332B may overlap with the second free pattern 354B and may be referred to as a second pinning pattern 332B. The first free pattern 354A, the first tunnel barrier pattern 342A, and the first pinning pattern 332A may form a first magnetic tunnel junction pattern MTJ-A', and the second free pattern 354B, the second tunnel barrier pattern 342B, and the second pinning pattern 332B may form a second magnetic tunnel junction pattern MTJ-B'. In addition, one of the hard mask patterns 372A and 372B may overlap with the first magnetic tunnel junction pattern MTJ-A' and may be referred to as a first hard mask pattern 372A, and the other of the hard mask patterns 372A and 372B may overlap with the second magnetic tunnel junction pattern MTJ-B' and may be referred to as a second hard mask pattern 372B. The first free pattern 354A and the first hard mask pattern 372A may be in direct contact with each other. On the other hand, a doping pattern or a doping layer 357 may be interposed between the second free pattern 354B and the second hard mask pattern 372B. The doping pattern 357 may be made or constructed to be conductive to provide an electrical connection between the second free pattern 354B and the second hard mask pattern 372B. In some implementations, the doping pattern 357 may be configured to be non-magnetic and in an amorphous state, and thus even if it is disposed on the second free pattern 354B, it may have no negative impact on the characteristics of the second free pattern 354B (such as the perpendicular magnetic anisotropy of the second free pattern 354B).

[0065] refer to Figure 3F , by forming a covering Figure 3E As a result of the process, an insulating material is formed, and a planarization process is performed so that upper surfaces of the first hard mask pattern 372A and the second hard mask pattern 372B are exposed, and a second interlayer insulating layer 380 may be formed.

[0066] Subsequently, a plurality of second conductive lines 390 extending in the second direction may be formed over the first and second hard mask patterns 372A and 372B and the second interlayer insulating layer 380 .

[0067] In this way, you can Figure 3F A semiconductor device is implemented as shown.

[0068] Reference again Figure 3F , the semiconductor device of some embodiments may include: a substrate 300; a plurality of first conductive lines 310, which are arranged above the substrate 300 and extend in a first direction; a plurality of second conductive lines 390, which are arranged above the first conductive lines 310 and extend in a second direction; and a selector pattern 320 and magnetic tunnel junction patterns MTJ-A' and MTJ-B', which are arranged between the first conductive lines 310 and the second conductive lines 390 and overlap with the intersection area of ​​the first conductive lines 310 and the second conductive lines 390.

[0069] The magnetic tunnel junction patterns MTJ-A' and MTJ-B' may include a first magnetic tunnel junction pattern MTJ-A' and a second magnetic tunnel junction pattern MTJ-B', the first magnetic tunnel junction pattern MTJ-A' including a first free pattern 354A having a first thickness T1' at its uppermost portion, and the second magnetic tunnel junction pattern MTJ-B' including a second free pattern 354B having a second thickness T2' at its uppermost portion, the second thickness T2' being less than the first thickness T1'.

[0070] The first hard mask pattern 372A and the second hard mask pattern 372B may be interposed between the first magnetic tunnel junction pattern MTJ-A' and the second conductive line 390 and between the second magnetic tunnel junction pattern MTJ-B' and the second conductive line 390, respectively. In addition, the doping pattern 357 may also be interposed between the second magnetic tunnel junction pattern MTJ-B' and the second hard mask pattern 372B. The doping pattern 357 may include constituent elements of the free patterns 354A and 354B and dopants, and may have non-magnetic and conductive properties. The sum of the second thickness T2' of the second free pattern 354B and the thickness of the doping pattern 357 may be substantially equal to the first thickness T1' of the first free pattern 354A.

[0071] The disclosed technology may be implemented in some embodiments to provide a semiconductor device including magnetic tunnel junction patterns MTJ-A′ and MTJ-B′ having different characteristics through a simple process.

[0072] FIG. 4A to FIG. 4E is a cross-sectional view illustrating a method for manufacturing a semiconductor device based on some embodiments of the disclosed technology. Specifically, FIG. 4A to FIG. 4E is along Figure 1A A cross-sectional view taken along line AA' in FIG.

[0073] In some embodiments of the disclosed technology, the method for manufacturing the semiconductor device discussed above may include the following steps.

[0074] refer to Figure 4A , first conductive lines 410 extending in the first direction may be formed over the substrate 400. Although not shown, a plurality of first conductive lines 410 may be arranged in parallel with each other and spaced apart from each other in a second direction passing through the cross section.

[0075] Subsequently, over the first conductive lines 410 and the insulating material filled between the first conductive lines 410 , a selector pattern 420 and a first interlayer insulating layer 425 may be disposed, the first interlayer insulating layer 425 being formed in a space between the selector patterns 420 .

[0076] Subsequently, a magnetic tunnel junction layer including a pinned layer 430, a tunnel barrier layer 440, and a free layer may be formed over the selector pattern 420 and the first interlayer insulating layer 425, a sacrificial hard mask pattern 460 may be formed over the free layer, and the free layer may be etched to a predetermined depth using the sacrificial hard mask pattern 460 as an etch barrier to form an initial free pattern 452. The sacrificial hard mask pattern 460 may at least cover the region where the first magnetic tunnel junction pattern (see Figure 4D MTJ-A"), and may expose at least a region where a second magnetic tunnel junction pattern is to be formed (see Figure 4D The initial free pattern 452 may have a first thickness T1″, and another portion of the initial free pattern 452 exposed by the sacrificial hard mask pattern 460 may have a second thickness T2″, which is less than the first thickness T1″ and greater than 0.

[0077] Subsequently, a metal oxide layer 462 may be formed over the initial free pattern 452 and the sacrificial hard mask pattern 460 along the contour of the structure thereunder. The metal oxide layer 462 may be deposited by at least one of various deposition methods and may include a non-magnetic metal element and oxygen. As an example, the non-magnetic metal element of the metal oxide layer 462 may include at least one of Ta, Ti, Mg, Hf, Zr, W, and Mo. The metal oxide layer 462 may have a thickness equal to or greater than the difference between the first thickness T1" and the second thickness T2". In addition, the metal oxide layer 462 may have a conductive property.

[0078] refer to Figure 4B, a planarization process such as CMP may be performed to expose an upper surface of a portion of the initial free pattern 452 having the first thickness T1". As a result, the sacrificial hard mask pattern 460 and a portion of the metal oxide layer 462 located above the upper surface and sidewalls of the sacrificial hard mask pattern 460 may be removed, and an additional portion of the metal oxide layer 462 located above a portion of the initial free pattern 452 having the second thickness T2" may be retained to form an initial metal oxide pattern 464. An upper surface of the portion of the initial free pattern 452 having the first thickness T1" and an upper surface of the initial metal oxide pattern 464 may be located at substantially the same height.

[0079] refer to Figure 4C , a preliminary hard mask pattern 470 may be formed over the preliminary free pattern 452 and the preliminary metal oxide pattern 464 .

[0080] The initial hard mask pattern 470 may be used to form a magnetic tunnel junction pattern (see Figure 4D The initial hard mask pattern 470 may be used as an etching barrier during the etching process of the MTJ-A", and the MTJ-B") in the initial free pattern 452, and may be formed to cover the area in which the magnetic tunnel junction pattern is to be formed. In addition, the initial hard mask pattern 470 may remain after the etching process, and may be used as a capping layer that protects the magnetic tunnel junction pattern or improves the characteristics of the magnetic tunnel junction pattern. The initial hard mask pattern 470 may be located over a portion of the initial free pattern 452 having the first thickness T1" and the initial metal oxide pattern 464, and may have a substantially constant thickness.

[0081] refer to Figure 4D , the initial metal oxide pattern 464, the initial free pattern 452, the tunnel barrier layer 440, and the pinning layer 430 may be etched using the initial hard mask pattern 470 as an etch barrier to form magnetic tunnel junction patterns MTJ-A" and MTJ-B" including free patterns 454A and 454B, tunnel barrier patterns 442A and 442B, and pinning patterns 432A and 432B. In this process, a portion of the initial hard mask pattern 470 may be etched away to form hard mask patterns 472A and 472B.

[0082] Here, one of the free patterns 454A and 454B may have a first thickness T1″ and may be referred to as a first free pattern 454A, and the other of the free patterns 454A and 454B may have a second thickness T2″ and may be referred to as a second free pattern 454B. One of the tunnel barrier patterns 442A and 442B may overlap with the first free pattern 454A and may be referred to as a first tunnel barrier pattern 442A, and the other of the tunnel barrier patterns 442A and 442B may overlap with the second free pattern 454B and may be referred to as a second tunnel barrier pattern 442B. One of the pinning patterns 432A and 432B may overlap with the first free pattern 454A and may be referred to as a first pinning pattern 432A, and the other of the pinning patterns 432A and 432B may overlap with the second free pattern 454B and may be referred to as a second pinning pattern 432B. The first free pattern 454A, the first tunnel barrier pattern 442A, and the first pinning pattern 432A may form a first magnetic tunnel junction pattern MTJ-A", and the second free pattern 454B, the second tunnel barrier pattern 442B, and the second pinning pattern 432B may form a second magnetic tunnel junction pattern MTJ-B". In addition, one of the hard mask patterns 472A and 472B may overlap with the first magnetic tunnel junction pattern MTJ-A" and may be referred to as a first hard mask pattern 472A, and the other of the hard mask patterns 472A and 472B may overlap with the second magnetic tunnel junction pattern MTJ-B", and may be referred to as a second hard mask pattern 472B. The first free pattern 454A and the first hard mask pattern 472A may be in direct contact with each other. On the other hand, the metal oxide pattern 466 may be interposed between the second free pattern 454B and the second hard mask pattern 472B. Since the metal oxide pattern 466 is conductive, it can provide electrical connection between the second free pattern 454B and the second hard mask pattern 472B. In addition, the metal oxide pattern 466 can be bonded to the second free pattern 454B to improve the perpendicular magnetic anisotropy of the second free pattern 454B. The perpendicular magnetic anisotropy can be generated by the combination of the metal element (such as iron (Fe)) of the second free pattern 454B and the oxygen of the metal oxide pattern 466.

[0083] refer to Figure 4E , by forming a covering Figure 4D The insulating material of the process result is formed, and a planarization process is performed until upper surfaces of the first hard mask pattern 472A and the second hard mask pattern 472B are exposed, and a second interlayer insulating layer 480 may be formed.

[0084] Subsequently, a plurality of second conductive lines 490 extending in the second direction may be formed over the first and second hard mask patterns 472A and 472B and the second interlayer insulating layer 480 .

[0085] In this way, you can Figure 4E A semiconductor device is implemented as shown.

[0086] Reference again Figure 4E , the semiconductor device of some embodiments may include: a substrate 400; a plurality of first conductive lines 410, which are arranged above the substrate 400 and extend in a first direction; a plurality of second conductive lines 490, which are arranged above the first conductive lines 410 and extend in a second direction; and a selector pattern 420 and magnetic tunnel junction patterns MTJ-A" and MTJ-B", which are inserted between the first conductive lines 410 and the second conductive lines 490 and overlap with the intersection area of ​​the first conductive lines 410 and the second conductive lines 490.

[0087] The magnetic tunnel junction patterns MTJ-A" and MTJ-B" may include a first magnetic tunnel junction pattern MTJ-A" and a second magnetic tunnel junction pattern MTJ-B", the first magnetic tunnel junction pattern MTJ-A" including a first free pattern 454A having a first thickness T1" at its uppermost portion, and the second magnetic tunnel junction pattern MTJ-B" including a second free pattern 454B having a second thickness T2" at its uppermost portion, the second thickness T2" being less than the first thickness T1".

[0088] The first hard mask pattern 472A and the second hard mask pattern 472B may be respectively interposed between the first magnetic tunnel junction pattern MTJ-A" and the second conductive line 490 and between the second magnetic tunnel junction pattern MTJ-B" and the second conductive line 490. In addition, the metal oxide pattern 466 may also be interposed between the second magnetic tunnel junction pattern MTJ-B" and the second hard mask pattern 472B. The metal oxide pattern 466 may be conductive and may improve the perpendicular magnetic anisotropy of the second free pattern 454B. The sum of the second thickness T2" of the second free pattern 454B and the thickness of the metal oxide pattern 466 may be substantially the same as the first thickness T1" of the first free pattern 454A.

[0089] In some embodiments, it may be possible to realize a semiconductor device including magnetic tunnel junction patterns MTJ-A" and MTJ-B" having different characteristics through a simple process.

[0090] The disclosed technology may be implemented in some embodiments to provide a semiconductor device and a method for manufacturing the semiconductor device, which may variously adjust the thickness of a free pattern included in a plurality of magnetic tunnel junction patterns through a simple process.

[0091] Although the disclosed technology has been illustrated and described with respect to specific embodiments, it should be understood that various enhancements and modifications can be made to the disclosed embodiments and other embodiments based on what is described and illustrated in this patent document.

Claims

1. A semiconductor device comprising: substrate; a first magnetic tunnel junction structure disposed over a portion of the substrate and including a first free layer; a first hard mask layer disposed over the first free layer of the first magnetic tunnel junction structure; a second magnetic tunnel junction structure disposed over another portion of the substrate and comprising a second free layer having a thickness less than a thickness of the first free layer; a second hard mask layer disposed over the second free layer of the second magnetic tunnel junction structure; as well as A doping layer is interposed between the second free layer and the second hard mask layer of the second magnetic tunnel junction structure and is configured to exhibit conductivity. 2 . The semiconductor device of claim 1 , wherein the first free layer and the first hard mask layer are in direct contact with each other. 3 . The semiconductor device according to claim 1 , wherein the doping layer includes a dopant and a constituent element of the first free layer, the dopant reducing magnetism of the first free layer or causing a loss of magnetism of the first free layer. The semiconductor device of claim 3 , wherein the dopant comprises an inert element. The semiconductor device according to claim 1 , wherein the doped layer has an amorphous state. 6 . The semiconductor device of claim 1 , wherein a thickness of the first free layer is equal to a sum of a thickness of the second free layer and a thickness of the doped layer.

7. The semiconductor device according to claim 1, further comprising: a plurality of first conductive lines disposed above the substrate and extending in a first direction; as well as a plurality of second conductive lines disposed above the first conductive lines and extending in a second direction intersecting the first direction, wherein a first stacked structure of the first magnetic tunnel junction structure and the first hard mask layer is disposed between the first conductive line and the second conductive line and overlaps with an intersection region among a plurality of intersection regions between the first conductive line and the second conductive line, and A second stack structure of the second magnetic tunnel junction structure, the doping layer, and the second hard mask layer is disposed between the first conductive line and the second conductive line and overlaps with another intersection region among the plurality of intersection regions between the first conductive line and the second conductive line.

8. The semiconductor device according to claim 7, further comprising: A selector layer is disposed between the first conductive line and the first magnetic tunnel junction structure, and between the first conductive line and the second magnetic tunnel junction structure.

9. A semiconductor device comprising: substrate; a first magnetic tunnel junction structure disposed over a portion of the substrate and including a first free layer; a first hard mask layer disposed over the first free layer; a second magnetic tunnel junction structure disposed over another portion of the substrate and comprising a second free layer having a thickness less than a thickness of the first free layer; as well as a second hard mask layer disposed over the second free layer, The thickness of the first hard mask layer is smaller than the thickness of the second hard mask layer. 10 . The semiconductor device of claim 9 , wherein a sum of a thickness of the first free layer and a thickness of the first hard mask layer is equal to a sum of a thickness of the second free layer and a thickness of the second hard mask layer.

11. The semiconductor device according to claim 9, further comprising: a plurality of first conductive lines disposed above the substrate and extending in a first direction; as well as a plurality of second conductive lines disposed above the first conductive lines and extending in a second direction intersecting the first direction, wherein a first stacked structure of the first magnetic tunnel junction structure and the first hard mask layer is disposed between the first conductive line and the second conductive line and overlaps with an intersection region among a plurality of intersection regions between the first conductive line and the second conductive line, and A second stack structure of the second magnetic tunnel junction structure and the second hard mask layer is disposed between the first conductive line and the second conductive line, and overlaps with another intersection region among the plurality of intersection regions between the first conductive line and the second conductive line.

12. The semiconductor device according to claim 11, further comprising: A selector layer is disposed between the first conductive line and the first magnetic tunnel junction structure, and between the first conductive line and the second magnetic tunnel junction structure.

13. A method for manufacturing a semiconductor device, comprising: forming a magnetic tunnel junction layer above the substrate, the magnetic tunnel junction layer comprising a pinned layer, a tunnel barrier layer and a free layer; forming a sacrificial hard mask layer over the free layer to cover at least a first region where a first magnetic tunnel junction structure is to be formed and to expose at least a second region where a second magnetic tunnel junction structure is to be formed; forming a doped region by doping a portion of the free layer exposed by the sacrificial hard mask layer with a dopant that reduces the magnetic properties of the free layer, the doped region having a thickness less than a thickness of the free layer; removing the sacrificial hard mask layer; forming a hard mask layer over the free layer and the doped region to cover the first region and the second region; as well as The doped region, the free layer, the tunnel barrier layer, and the pinned layer are etched using the hard mask layer. The method of claim 13 , wherein the dopant comprises an inert element. The method according to claim 13 , wherein the doped region has an amorphous state.

16. The method according to claim 13, wherein the first magnetic tunnel junction structure comprises the pinned layer, the tunnel barrier layer and the free layer, and The second magnetic tunnel junction structure includes the pinned layer, the tunnel barrier layer, the free layer and the doped region.

17. A method for manufacturing a semiconductor device, comprising: forming a magnetic tunnel junction layer above the substrate, the magnetic tunnel junction layer comprising a pinned layer, a tunnel barrier layer and a free layer; forming a sacrificial hard mask layer over the free layer to cover at least a first region where a first magnetic tunnel junction structure is to be formed and to expose at least a second region where a second magnetic tunnel junction structure is to be formed; etching a portion of the free layer exposed by the sacrificial hard mask layer to reduce a thickness of the portion of the free layer; removing the sacrificial hard mask layer; forming a hard mask layer over the free layer to cover the first region and the second region; as well as The free layer, the tunnel barrier layer, and the pinned layer are etched using the hard mask layer.

18. The method according to claim 17, wherein a thickness of the free layer of the first magnetic tunnel junction structure is greater than a thickness of the free layer of the second magnetic tunnel junction structure, and A thickness of the hard mask layer overlapping the first magnetic tunnel junction structure is less than a thickness of the hard mask layer overlapping the second magnetic tunnel junction structure.

19. A method for manufacturing a semiconductor device, comprising: forming a magnetic tunnel junction layer above the substrate, the magnetic tunnel junction layer comprising a pinned layer, a tunnel barrier layer and a free layer; forming a sacrificial hard mask layer over the free layer to cover at least a first region where a first magnetic tunnel junction layer is to be formed and to expose at least a second region where a second magnetic tunnel junction layer is to be formed; etching a portion of the free layer exposed by the sacrificial hard mask layer to reduce a thickness of the portion of the free layer; forming a metal oxide layer over the sacrificial hard mask layer and the free layer; removing the sacrificial hard mask layer and portions of the metal oxide layer formed over sidewalls and an upper surface of the sacrificial hard mask layer to form a metal oxide layer; forming a hard mask layer over the free layer and the metal oxide layer to cover a first region where the first magnetic tunnel junction layer is to be formed and a second region where the second magnetic tunnel junction layer is to be formed; as well as The free layer, the tunnel barrier layer, the pinned layer, and the metal oxide layer are etched using the hard mask layer.

20. The method according to claim 19, wherein the first magnetic tunnel junction layer comprises the pinned layer, the tunnel barrier layer and the free layer, and The second magnetic tunnel junction layer includes the pinned layer, the tunnel barrier layer, the free layer and the metal oxide layer.

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