Improved performance and reliability of processor storage operational data transfer

Abstract

A processor includes a load and store unit (LSU) and a cache memory, and transmits data information from a store queue in the LSU to the cache memory. When the cache memory determines that there is an available entry in a storage queue within the cache memory, the cache memory requests a packet from the LSU. The LSU acknowledges the request and transmits an information packet to the cache memory. Before receiving an additional request from the cache memory, the LSU anticipates that there is an additional available entry in the cache memory, transmits an additional acknowledgement to the cache memory, and transmits an additional packet. If there are additional available entries in the cache store queue, the cache memory stores additional packets. If there is no additional available entry in the cache store queue, the cache memory rejects the additional packet. When the cache memory subsequently requests an additional packet, the LSU then must retry the transfer of the additional packet. The cache memory may set or reset the time latency to request subsequent packets based on several factors within the cache memory and the processor, including the number of available entries within the cache store queue. A corresponding method and computer program product are also disclosed.

Description

Technical Field

[0001] The present invention relates generally to computer processor systems and, more particularly, to systems and methods for improving the performance and reliability of data transfers for storage operations between a processor and a processor cache memory. Background Art

[0002] In a computer processing system, a processor serves as a central processing unit and performs many important functions, such as arithmetic and logic operations, program instruction execution, data transfer, and other processing system control and logic functions. The processor includes a cache to assist in transferring data between the processor core and the processing system memory. The cache typically includes multiple levels or layers, with a smaller, faster level one (L) cache and a larger, relatively slower level two (L2) cache. The processor includes a relatively small storage queue to temporarily store data, and each layer of the cache includes a queue to hold data before storing it in the larger cache memory.

[0003] A communication protocol exists between the processor cache (L2) store queue and the processor core store queue to control the transfer of data between the processor core and the cache. The processor cache indicates that space is available in its storage by sending a request signal to the processor core for each available entry in the cache queue. The processor core responds to the cache with an acknowledgment signal and transfers the data packet from the processor queue to the cache. The cache accepts the data packet with the acknowledgment and stores the data packet in the cache store queue. The LSU waits until the cache sends additional requests before sending additional data packets to the cache.

[0004] In view of the foregoing, what is needed is a system and method for improving the performance and reliability of data transfers between a processor core and a processor cache. Processor systems attempt to improve processor performance by anticipating empty entries in a processor cache storage queue. In addition, multiple threads in a processor core share a processor cache and compete for entries in the cache storage queue and cause a loss of synchronization in the communication protocol between the processor core storage queue and the processor cache storage queue. The present invention prevents the processor cache from rejecting data transfers and minimizes the loss of synchronization in the communication protocol between the processor core and the processor cache storage queue. Summary of the invention

[0005] The present invention has been developed in response to the current state of the art, and in particular, in response to problems and needs in the art that have not yet been fully solved by currently available systems and methods. The features and advantages of the present invention will become more fully apparent from the following description and appended claims, or may be understood by the practice of the present invention as described below.

[0006] According to an embodiment of the present invention described herein, a processor for improving the performance of storage operation data transfer in a computer processing system is provided. In an embodiment, the computer processing system includes a processor, a memory, and a plurality of components for performing computer processing system functions. In an embodiment, the processor includes a load and store unit (LSU) and a cache memory for storing data information to be transferred to the memory and / or other components in the computer processing system. In an embodiment, the LSU includes a storage queue having a plurality of entries for storing a plurality of information packets. In an embodiment, the cache memory includes a storage queue having a plurality of entries for storing a plurality of information packets. In an embodiment, the cache memory determines that the cache storage queue contains available entries. The cache memory transmits a request to the LSU to transfer the information packet to the cache memory. In an embodiment, the LSU transmits an acknowledgment in response to the cache request and transfers the information packet from the entry in the LSU storage queue to the cache memory. In an embodiment, the cache memory receives the information packet from the LSU and stores the information packet in the available entry in the cache storage queue.

[0007] In an embodiment, the LSU anticipates the presence of additional available entries in the cache memory, transmits additional confirmation signals to the cache memory, and transmits additional packets from the additional entries in the LSU storage queue to the cache memory. The cache memory determines that there are additional available entries in the cache storage queue, receives the packet from the LSU, and stores the packet in the additional available entry in the cache storage queue. In an embodiment, the cache memory delays a subsequent request for a subsequent packet, wherein the subsequent request also serves as confirmation that the cache of the LSU successfully stored the additional packet in the cache storage queue. In an embodiment, the cache memory determines that there are no additional available entries in the cache storage queue, and rejects the additional packet transmitted from the LSU. The LSU must wait for the cache memory to transmit a new request before retrying the transmission of the additional information from the LSU storage queue to the cache memory.

[0008] In an embodiment, the cache memory calculates a time delay (subsequent request delay) for sending a subsequent request for a subsequent information packet to the LSU based on the number of available entries in the cache storage queue. In an embodiment, the cache memory calculates the subsequent request delay based on a recent average time of transmitting information packets from the LSU storage queue to the cache storage queue. In an embodiment, the cache memory sets and resets the subsequent request delay based on a threshold value, wherein the threshold value is based on the number of available entries in the cache storage queue. When the number of available entries in the cache storage queue is less than the threshold value, the cache memory sets the subsequent request delay to a determined time interval. When the number of available entries in the cache storage queue is greater than or equal to the threshold value, the cache memory resets the subsequent request delay to no time delay.

[0009] According to another embodiment of the invention described herein, a method for improving performance of storage operation data transfer in a computer processing system is provided, wherein the computer processing system includes a processor and a cache memory, the processor including a load and store unit (LSU) having a storage queue, and the cache memory including the storage queue. In an embodiment, the method includes storing a packet in an entry in the LSU storage queue. In an embodiment, the method includes: the cache memory determines that there is an available entry in the cache storage queue and requests the packet from the LSU. In an embodiment, the method includes: the LSU acknowledges the request from the cache memory and transfers the packet from the entry in the LSU storage queue to the cache memory. In an embodiment, the method includes: the cache memory receives the packet from the LSU and stores the packet in an available entry in the cache storage queue.

[0010] In an embodiment, the method includes the LSU anticipating that the cache memory has an additional available entry in the cache storage queue. In an embodiment, the method includes the LSU transmitting an additional confirmation to the cache memory before the cache memory requests the additional information packet, and transmitting the additional information packet to the cache memory. In an embodiment, the method includes: the cache memory determining that there is an additional available entry in the cache storage queue; receiving the additional information packet from the LSU; and storing the additional information packet in the additional available entry in the cache storage queue. In an embodiment, the method includes: the cache memory delaying a subsequent request to the LSU for a subsequent information packet, wherein the subsequent request serves as a confirmation that the additional information packet is stored in the cache memory. In an embodiment, the method may alternatively include the cache memory determining that there is no additional available entry in the cache storage queue, and rejecting the transmission of the additional information packet from the LSU, thereby requiring the LSU to retry the transmission of the additional information packet when it receives another request from the cache memory.

[0011] In an embodiment, the method includes: the cache memory calculating a time delay (subsequent request delay) for sending a subsequent request for a subsequent information packet to the LSU based on the number of available entries in the cache storage queue. In an embodiment, the method includes: the cache memory calculating the subsequent request delay based on a recent average time of transmitting information packets from the LSU storage queue to the cache storage queue. In an embodiment, the method includes the cache memory setting and resetting the subsequent request delay based on a threshold value, wherein the threshold value is based on the number of available entries in the cache storage queue. The method includes when the number of available entries in the cache storage queue is less than the threshold value, the cache memory setting the subsequent request delay to a determined time interval. The method includes when the number of available entries in the cache storage queue is greater than or equal to the threshold value, the cache memory resetting the subsequent request delay to no time delay.

[0012] According to another embodiment of the present invention described herein, there is provided a computer program product for improving the performance of storage operation data transfer in a computer processing system, wherein the computer processing system includes a processor and a cache memory, the processor including a load and store unit (LSU) having a storage queue, and the cache includes the storage queue. In an embodiment, the computer program product includes a non-transitory computer-readable storage medium containing a computer-usable program code. In an embodiment, the computer-usable program code is configured to perform operations when executed by the processor. In an embodiment, the computer program product operation includes storing a packet in an entry in the LSU storage queue. In an embodiment, the computer program product operation includes: the cache memory determines that there is an available entry in the cache storage queue, and requests a packet from the LSU. In an embodiment, the computer program product operation includes the LSU confirming the request from the cache memory and transferring the packet from the entry in the LSU storage queue to the cache memory. In an embodiment, the computer program product operation includes: the cache memory receives the packet from the LSU and stores the packet in an available entry in the cache storage queue.

[0013] In an embodiment, the computer program product operation includes the LSU anticipating that the cache memory has an additional available entry in the cache storage queue. In an embodiment, the computer program product operation includes the LSU transmitting an additional confirmation to the cache memory before the cache memory requests an additional packet, and transmitting the additional packet to the cache memory. In an embodiment, the computer program product operation includes: the cache memory determining that there is an additional available entry in the cache storage queue; receiving the additional packet from the LSU; and storing the additional packet in the additional available entry in the cache storage queue. In an embodiment, the computer program product operation includes: the cache memory delaying a subsequent request to the LSU for a subsequent packet, wherein the subsequent request serves as a confirmation that the additional packet is stored in the cache memory. In an embodiment, the computer program product operation may alternatively include the cache memory determining that there is no additional available entry in the cache storage queue, and denying transmission of the additional packet from the LSU, thereby requiring the LSU to retry transmission of the additional packet when it receives another request from the cache memory.

[0014] In an embodiment, the computer program product operation includes: the cache memory calculating a time delay (subsequent request delay) for sending a subsequent request for a subsequent information packet to the LSU based on the number of available entries in the cache storage queue. In an embodiment, the computer program product operation includes: the cache memory calculating the subsequent request delay based on a recent average time of transmitting information packets from the LSU storage queue to the cache storage queue. In an embodiment, the computer program product operation includes the cache memory setting and resetting the subsequent request delay based on a threshold value, wherein the threshold value is based on the number of available entries in the cache storage queue. The computer program product operation includes when the number of available entries in the cache storage queue is less than the threshold value, the cache memory setting the subsequent request delay to a determined time interval. The computer program product operation includes when the number of available entries in the cache storage queue is greater than or equal to the threshold value, the cache memory resetting the subsequent request delay to no time delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to easily understand the advantages of the present invention, a more particular description of the present invention briefly described above will be presented by reference to specific embodiments shown in the accompanying drawings. It should be understood that these drawings depict only typical embodiments of the present invention and are not to be considered limiting of its scope. Embodiments of the present invention will be described and explained in more detail through the use of the accompanying drawings, in which:

[0016] Figure 1 is a high-level block diagram representing an example of a computer processing system in which systems and methods according to embodiments of the present invention may be implemented;

[0017] Figure 2 is a high-level block diagram representing a processor or central processing unit within a computer processing system according to an embodiment of the present invention;

[0018] Figure 3 is a high-level block diagram representing a processor and cache memory components within the processor according to an embodiment of the present invention; and

[0019] Figure 4 is a high-level block diagram representing an improved system and computer-implemented method for transferring information within a computer processing system using cache memory within a processor core in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0020] It is readily understood that the components of the present invention, as generally described and illustrated in the drawings herein, may be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of the embodiments of the present invention, as represented in the drawings, is not intended to limit the scope of the invention as claimed, but is merely representative of certain examples of embodiments currently contemplated according to the present invention. The presently described embodiments will be better understood by reference to the drawings, in which like parts are represented by like reference numerals.

[0021] This article describes an exemplary embodiment of improving the performance and reliability of data transmission for storage operations within a computer processing system. A computer processing system includes one or more processors, a memory, and multiple components that perform computer processing functions and control. The processor includes a load and store unit (LSU) and a cache memory. The LSU and the cache memory include a storage queue having entries for storing information packets. The LSU transmits the information packet to the cache memory, where the information packet is stored until the information needs to be transferred from the cache memory to the main memory and / or other components within the computer processing system. When the cache determines that there is an available entry in the cache storage queue, the cache memory requests the information packet from the LSU. The LSU confirms the request and transfers the information packet from the LSU storage queue to the cache memory. The LSU accelerates data transmission by expecting the cache memory to have an available entry in the cache storage queue and transmitting additional confirmations and additional information packets to the cache memory. If the cache memory has an available entry in the cache storage queue, the cache memory accepts the additional information packet. Alternatively, if the cache memory does not have an additional entry in the cache storage queue, the cache memory refuses the transmission of the additional information packet. The LSU must then retry transmission of the additional packets. The cache memory delays transmitting subsequent requests for subsequent packets to the LSU to avoid requiring the cache to reject additional packets transmitted from the LSU and requiring the LSU to retry the additional packet transmissions.

[0022] refer to Figure 1, generally showing a computer processing system 100 according to an embodiment. The computer processing system 100 may be an electronic computer framework that includes and / or employs any number of computing devices and networks utilizing various communication technologies and combinations thereof, as described herein. In some embodiments, the computer processing system 100 may be easily scalable, extensible, and modular, with the ability to change to different services or reconfigure some features independently of other features. In some embodiments, the computer processing system 100 may be, for example, a server, a desktop computer, a laptop computer, a tablet computer, or a smart phone. In addition, the computer processing system 100 may be a cloud computing node. In some embodiments, the computer processing system 100 may be described in the general context of computer system executable instructions, such as program modules executed by a computer system. In general, a program module may include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. In some embodiments, the computer processing system 100 may be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

[0023] like Figure 1 As shown, the computer processing system 100 has one or more central processing units (CPUs) 101 (collectively or generally referred to as processors 101). In some embodiments, the processor 101 may be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. The processor 101 (also referred to as a processing circuit) may also include one or more accelerators (e.g., a graphics processing unit or GPU). In one embodiment, the processor includes a cache 109 and a controller 108 to assist in performing processor-related functions, such as arithmetic and logic operations, program instruction execution, data transfer, and other processing system control and logic functions. In some embodiments, the processor 101 is coupled to the system memory 103 and various other components via the system bus 102. The system memory 103 may include a read-only memory (ROM) 104 and a random access memory (RAM) 105. The ROM 104 is coupled to the system bus 102 and may include a basic input / output system (BIOS), which controls certain basic functions of the computer system 100. The RAM is a read-write memory coupled to the system bus 102 for use by the processor 101. In some embodiments, the system memory 103 provides temporary storage space for the operation of the instructions during operation. The system memory 103 may include random access memory (RAM), read-only memory, flash memory, or any other suitable memory system.

[0024] In some embodiments, the computer processing system 100 includes an input / output (I / O) adapter 106 and a communication adapter 107 coupled to the system bus 102. The I / O adapter 106 may be a small computer system interface (SCSI) adapter that communicates with a hard disk 108 and / or any other similar components. The I / O adapter 106 and the flash memory (DRAM) 118 and / or hard disk drive 118 are collectively referred to herein as mass storage 110. In some embodiments, software 111 for execution on the computer processing system 100 may be stored in the mass storage 110. The mass storage 110 is an example of a tangible storage medium readable by the processor 101, wherein the software 111 is stored as instructions executed by the processor 101 to cause the computer system 100 to operate, such as described herein below with respect to the various figures. Examples of computer program products and execution of such instructions are discussed in more detail herein.

[0025] In some embodiments, communication adapter 107 interconnects system bus 102 with network 112, which may be an external network, to enable computer processing system 100 to communicate with other systems. In one embodiment, system memory 103 and portions of mass storage 110 together store an operating system, which may be any suitable operating system, such as z / OS or AIX operating systems from IBM Corporation, to coordinate Figure 1 The functions of the various components are shown in .

[0026] In some embodiments, additional input / output devices are connected to the system bus 102 via a display adapter 115 and an interface adapter 116. In an embodiment, adapters 106, 107, 115, and 116 may be connected to one or more I / O buses that are connected to the system bus 102 via an intermediate bus bridge (not shown). In an embodiment, a display 119 (e.g., a display screen or monitor) is connected to the system bus 102 via a display adapter 115, which may include a graphics controller to improve the performance of graphics-intensive applications and video controllers. In an embodiment, a keyboard 121, a mouse 122, a speaker 123, and / or other devices may be interconnected to the system bus 102 via an interface adapter 116, which may include, for example, a Super 1 / 0 (Super I / O) chip that integrates multiple device adapters into a single integrated circuit. In some embodiments, a suitable I / O bus for connecting peripheral devices such as a hard disk controller, a network adapter, and a graphics adapter typically includes a common protocol, such as a peripheral component interconnect (PCI). Therefore, as Figure 1As configured, computer processing system 100 includes processing capabilities in the form of processor 101, as well as storage capabilities including system memory 103 and mass storage 110, input devices such as keyboard 121 and mouse 122, and output capabilities including speakers 123 and display 119.

[0027] In some embodiments, the communication adapter 107 can use any suitable interface or protocol to transmit data, such as an Internet Small Computer System Interface, etc. The network 112 can be a cellular network, a radio network, a wide area network (WAN), a local area network (LAN), or the Internet, etc. An external computing device can be connected to the computing system 100 through the network 112. In some embodiments, the external computing device can be an external network server or a cloud computing node.

[0028] It should be understood that Figure 1 The block diagram is not intended to indicate that the computer processing system 100 will include Figure 1 Instead, the computer processing system 100 may include Figure 1 Any suitable fewer or additional components not shown in the computer processing system 100 (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.) may be omitted. In addition, the embodiments described herein with respect to the computer processing system 100 may be implemented with any suitable logic, wherein the logic as mentioned herein may include any suitable hardware (e.g., a processor, an embedded controller or an application-specific integrated circuit, etc.), software (e.g., an application, etc.), firmware, or any suitable combination of hardware, software, and firmware in various embodiments.

[0029] Figure 2A block diagram of a processor or central processing unit 101 according to an embodiment of the present invention is shown. In an embodiment, the processor includes one or more processor cores 200, 201. In an embodiment, the processor cores 200, 201 include load-store units (LSUs) 210, 211 and multiple levels of cache memory 109. In an embodiment, the cache memory 109 of each processor core includes a level one (L1) cache 220, 221 and a level two (L2) cache 230, 231. The level one (L1) cache 220, 221 typically includes a memory with the fastest access time and is smaller in size. The level two (L2) cache 230, 231 typically includes a memory with a slower access time than the L1 cache 220, 221 and is much larger in size. As previously described, the processor cores 200, 201 perform processor-related functions such as arithmetic and logical operations, program instruction execution, data transfer, and other processing system control and logic functions. In order to perform these functions, the processor cores 200, 201 need to access information, instructions and / or data from the processor memory 103 via the system bus 102. In an embodiment, the processor cores 200, 201 utilize load-store units 210, 211 and multiple levels of cache memory 220, 221, 230, 231 to transfer information more efficiently and quickly. Information including instructions and data can be pre-fetched from the system memory 103 and stored in the L1 cache 220 or the L2 cache 230 based on an algorithm within the processor core 200 that predicts which information is likely to be accessed from the system memory 103.

[0030] It should be understood that Figure 2 The block diagram is not intended to show all components included in the processor cores 200 , 201 . Figure 2 Two processor cores 200, 201 are included, but this is intended only to illustrate an exemplary embodiment. The central processing unit 101 may include a single processor core 200 or multiple (more than two) processor cores 200, 201. As previously described, the processor cores 200, 201 perform many processing-related functions and may include Figure 2Additional components and control logic not shown in the figure assist in performing these functions. In addition, specific embodiments of the processor cores 200, 201 include more than two levels of cache memory 108. In an embodiment, the processor cores 200, 201 include a level three (L3) cache and a level four (L4) cache to improve the performance and efficiency of accessing information from the system memory 103. In addition, the embodiments described herein with respect to the processor cores 200, 201 may be implemented with any appropriate logic, wherein the logic as mentioned herein may include any appropriate hardware (e.g., a processor, an embedded controller or an application-specific integrated circuit, etc.), software (e.g., an application, etc.), firmware, or any appropriate combination of hardware, software, and firmware in various embodiments.

[0031] Figure 3 A block diagram of a processor core according to an embodiment of the present invention is shown. In an embodiment, the processor core 200 includes a load-store unit (LSU) 210, an L1 cache memory 220, and an L2 cache memory 230. In an embodiment, the LSU 210 includes a store queue 250 and a load queue 255, which send and receive information to and from the L1 220 and L2 230 cache memories. The information includes data to be transferred, instructions to be executed, addresses to be accessed, or other information necessary for the processor 200 to perform its operations. In an embodiment, the L2 cache 230 includes a corresponding store queue 260 and a load queue 265. In an embodiment, the LSU 210 is coupled to the L1 cache 220 and the L2 cache 230 to transfer and receive information. Similarly, the L2 cache 260 is coupled to the LSU 210 and the L1 cache 220 to transfer and receive information. In an embodiment, the L2 cache 230 is coupled to the system bus 102 to transfer and receive information from components within the processor system 100. In an embodiment, LSU 210, L1 cache 220, and L2 cache 230 include logic for communicating and controlling the transfer of information between components.

[0032] It should be understood that Figure 3 The block diagram of is not intended to show all components included in processor core 200 , but rather is intended to show only exemplary embodiments of components in processor core 200 that facilitate the transfer of information within processor core 200 and within processor system 100 . Figure 3 A single processor core 200 is included with a single LSU 210, a single L1 cache 220, and a single L2 cache 230. In an alternative embodiment, the L1 cache 220 and the L2 cache 230 may be divided into multiple cache segments. In this case, a separate LSU 210 may be implemented to communicate with the partitioned L1 cache 220 and L2 cache 230 segments and control information transfer. In addition, Figure 3The embodiments described in the specification include control signals for communicating and transferring data between LSU 210, L1 cache 220, and L2 cache 230. In various embodiments, such control signals may be implemented with any suitable logic, wherein logic as referred to herein may include any suitable hardware (e.g., a processor, an embedded controller, or an application specific integrated circuit, etc.), software (e.g., an application, etc.), firmware, or any suitable combination of hardware, software, and firmware.

[0033] Figure 4 A block diagram is shown of an improved system and computer-implemented method for transferring data information within a computer processing system 100 using an LSU 210 and an L2 cache memory 230 within a processor core 200. In an embodiment, the processor core includes an LSU 210 coupled to an L2 cache 230. In an embodiment, the LSU includes a store queue 250 that stores data information and a control module 270 that transmits control and communication signals. In an embodiment, the L2 cache 230 includes a store queue that stores data information and a control module 280 that transmits control and communication signals. In an embodiment, the LSU control module 270 is coupled to the L2 cache control module 280 via a control bus 275 and a data bus 285. In an embodiment, the LSU control module 270 and the L2 cache control module include logic, wherein the logic may include hardware, software, firmware, or a combination of hardware, software, and firmware.

[0034] In an embodiment, when an entry in the L2 store queue 260 is available, the L2 cache control module 280 transmits a POP signal along the control bus 275 to the LSU control module 270. In an embodiment, when data information is ready to be transferred from the LSU store queue 250 to the L2 cache store queue 260, the LSU control module 270 transmits a PUSH signal along the control bus 275. The LSU 210 then initiates the transfer of the data information from the LSU store queue 250 to the L2 cache store queue 260 via the data bus 285 until the data transfer is complete. In an embodiment, the L2 cache control module 280 transmits continuous POP signals along the control bus 275 to indicate that additional entries are available in the L2 cache store queue 260. The process is then repeated when the LSU control module 275 transmits a PUSH signal along the control bus 275 to indicate that additional data information is ready to be transferred from the LSU store queue 250 to the L2 cache store queue 260 and initiates the transfer of the data information from the LSU store queue 250 to the L2 cache store queue 260 via the data bus 285.

[0035] In further embodiments, the LSU 210 accelerates data information transfers to the L2 cache 230 in anticipation that the L2 cache store queue has additional available entries. In embodiments, the LSU control module 270 responds to a POP signal from the L2 cache control module 280 by transmitting a PUSH signal along the control bus 275 and initiating a transfer of data information from the LSU store queue 250 to the L2 cache store queue 260. In embodiments, the LSU control module 270 transmits additional PUSH signals to the L2 cache control module 280 along the control bus 275 when the previous data information transfer is complete and before receiving additional POP signals from the L2 cache control module 280. As previously described, the LSU control module 270 initiates subsequent data information transfers from the LSU store queue to the L2 cache store queue 260 along the data bus 285. Therefore, the LSU 210 anticipates that the L2 cache 230 contains additional available entries in the L2 cache store queue 260, and increases the transfer speed and performance between the LSU store queue 250 and the L2 cache store queue 260. In an embodiment, the L2 cache control module 280 transmits a POP signal to the LSU control module 270 along the control bus 275, indicating that the L2 cache control store 260 contains available entries and receives data information transfers from the LSU store queue 250. In an embodiment, the L2 cache control module 280 transmits a BOUNCE signal to the LSU control module 270 along the control bus 275, indicating that the L2 cache control store 260 does not contain available entries and rejects the data information transfer from the LSU store queue 250. In this case, the LSU 210 must wait for available entries in the L2 cache 230 to retry the data information transfer, and therefore, the LSU control module 270 must wait to receive a subsequent POP signal from the L2 cache control module 280 along the control bus 275. Therefore, the LSU erroneously expects that there are available entries in the L2 cache store queue 260, and reduces the store queue transfer performance between the LSU 210 and the L2 cache 230 in the processor core 200. In addition, if the LSU 210 releases data information transferred in a subsequent PUSH signal from the LSU store queue 250 before the LSU control module 270 receives the BOUNCE signal from the L2 cache control module 280, the risk of losing the data information increases.

[0036] In further embodiments, the L2 cache 230 may delay indicating to the LSU 210 that an entry is available in the L2 cache store queue 260. As previously described, the L2 cache control module 280 transmits a POP signal when an entry in the L2 cache store queue 260 becomes available. In an embodiment, the L2 delays transmitting the POP signal when an entry in the L2 cache store queue 260 becomes available. In an embodiment, the delay may be a time delay of an interval of fixed duration. In an embodiment, the delay may be a time delay that may vary in length based on certain factors and / or metrics measured within the processor core 200. In an embodiment, the delay may be calculated based on a time interval for transmitting data information from the LSU store queue 250 to the L2 cache store queue 260. In an embodiment, the delay may be a time interval that is adjusted based on the number of available entries in the L2 cache store queue 260. In an embodiment, the delay may be calculated using an algorithm based on a combination of factors and metrics within the processor core, including, but not limited to, the number of available entries in the L2 store queue 260, free space in the L2 cache 230 or L1 cache 220, the average time to transfer data information between the LSU 230 and the L2 cache 250, and the frequency of store operations within the processor core. By delaying the transmission of the POP signal from the L2 cache control module 280 to the LSU control module 270, the L2 cache control module 280 ensures that the L2 cache store queue 260 can successfully complete the additional data information transfer in the event that the LSU 210 attempts to speed up the transfer of data information to the L2 cache 230 by anticipating that the L2 store queue 260 contains additional available entries.

[0037] In other embodiments, the delay may be a fixed time interval that is turned on and off or set and reset based on a threshold, or a variable time interval that is periodically calculated based on factors and metrics measured within the processor core 200. In an exemplary embodiment, the delay is set or reset based on the number of available entries in the L2 cache store queue 260. The L2 cache control module 280 turns on or sets the delay if the number of available entries in the L2 cache store queue is less than the threshold, and turns off or resets the delay if the number of available entries in the L2 cache store queue exceeds the threshold. As an example, the L2 cache 230 delays sending a POP signal to the LSU 210 if the number of available entries in the L2 cache store queue 260 is less than four entries, and does not delay sending a POP signal to initiate data information transmission from the LSU 210 if the number of available entries in the L2 cache store queue 260 is greater than or equal to four entries. In another exemplary embodiment, the time delay is calculated to be longer or shorter based on certain performance metrics in the processor core, including but not limited to the number of available entries in the L2 cache store queue 260, the recent average of the transfer time or transfer rate of data information transferred from the LSU store queue 250 to the L2 cache store queue 260, and / or the recent frequency of memory operations or storage operations occurring within the processor core 200. The ability to strategically set or reset, or variably adjust the time interval of the delay enhances the performance of data information transfer between the LSU store queue 250 and the L2 cache store queue 260 by maximizing the opportunity for the L2 cache 230 to accept accelerated data information transfer from the LSU 210. When the L2 store queue 260 is close to capacity and has few available entries, or when other factors indicate that the processor core 200 environment is tight, the L2 cache control module 280 delays transmitting the POP signal to the LSU control module 270. Alternatively, when the L2 store queue 260 has several available entries, or when other factors indicate that the processor core 200 environment is not stressed, the L2 cache control module 280 does not delay transmitting the POP signal to the LSU control module 270. By strategically implementing a time delay for the L2 cache 230 to initiate a data information transfer from the LSU store queue 250 to the L2 cache store queue, the L2 cache 230 can successfully process additional requests from the LSU 210 to receive additional data information transfers and avoid having to reject such requests because the L2 cache store queue 260 has no available entries.

[0038] The present invention may be implemented as a system, method, and / or computer program product. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform various aspects of the present invention.

[0039] Computer readable storage medium can be a tangible device capable of holding and storing instructions used by an instruction execution device. Computer readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer readable storage medium includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove with instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer readable storage medium should not be interpreted as a temporary signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0040] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0041] Computer readable program instructions for performing operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as the "C" programming language or similar programming languages).

[0042] The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, in order to perform various aspects of the present invention, an electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit.

[0043] Various aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It will be understood that each block of the flowchart illustration and / or block diagram and the combination of blocks in the flowchart illustration and / or block diagram can be implemented by computer-readable program instructions.

[0044] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0045] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0046] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention.In this regard, each frame in the flow chart or block diagram can represent a module, segment or part of a code, which includes one or more executable instructions for realizing the specified (one or more) logical functions.It should also be noted that in some alternative implementations, the function marked in the frame may not occur in the order marked in the figure.For example, the two frames shown in succession can actually be performed substantially at the same time, or these frames can sometimes be performed in reverse order, depending on the functions involved.Other implementations may not require all disclosed steps to realize the desired functions.It will also be noted that the combination of the frames in each frame illustrated in the block diagram and / or flow chart and the block diagram and / or flow chart can be realized by a combination of a system based on special-purpose hardware or special-purpose hardware and computer instructions that performs a specified function or action.

Claims

1. A processor included in a central processing unit (CPU), the CPU included in a computer processor system, the CPU coupled to a memory, the processor comprising: a load and store unit (LSU), the LSU comprising a control module and a store queue, the store queue comprising a plurality of entries for storing a plurality of packets; a cache memory (L2 cache), the L2 cache coupled to the LSU, the L2 cache comprising a control module and a store queue, the store queue comprising a plurality of entries for storing a plurality of packets; wherein the L2 cache determines that there is an available entry in the L2 cache storage queue and transmits a request to the LSU to transmit a packet; wherein the LSU transmits an acknowledgment from the L2 cache and transmits the packet from the entry in the LSU store queue via a data bus coupled to the L2 cache; wherein the L2 cache receives the packet from the LSU store queue and stores the packet in the available entry in the L2 cache store queue; and The LSU anticipates that the L2 cache store queue has additional available entries, transmits additional acknowledgments to the L2 cache before the L2 cache requests additional packets, and transmits additional packets from the additional entries in the LSU store queue.

2. The processor of claim 1 , wherein the L2 cache determines that there are additional available entries in the L2 cache store queue, receives the additional packets from the LSU store queue, and stores the additional packets in the additional available entries in the L2 cache store queue; and in, The L2 cache delays transmitting a subsequent request to the LSU for a subsequent packet to be transmitted from the LSU, the subsequent request also serving as a confirmation to the LSU to store the additional packet in the L2 cache.

3. The processor of claim 1 , wherein the L2 cache requests a packet by transmitting a POP signal from the L2 cache control module along a control bus coupled to the LSU control module, and wherein the LSU acknowledges the request from the L2 cache by transmitting a PUSH signal from the LSU control module along the control bus coupled to the L2 cache control module.

4. The processor of claim 2, wherein the L2 cache control module determines a delay in requesting a subsequent packet (a subsequent request delay), and the subsequent request delay is calculated based on a number of available entries within the L2 cache storage queue.

5. The processor of claim 4, wherein the L2 cache control module calculates the subsequent request delay based on an average time to transfer the packet from the LSU store queue to the L2 cache store queue.

6. The processor of claim 4, wherein the L2 cache control module sets and resets the subsequent request delay based on a threshold, wherein the threshold is a number of available entries in the L2 cache store queue; wherein when the number of available entries in the L2 cache storage queue is less than the threshold, the L2 control module sets the subsequent request delay to a fixed time interval; and When the number of available entries in the L2 cache storage queue is greater than or equal to the threshold, the L2 cache control module resets the subsequent request delay to no time delay.

7. The processor of claim 1 , wherein the L2 cache determines that there are no additional available entries in the L2 cache store queue; wherein the L2 cache control module transmits a BOUNCE signal along the control bus to the LSU control module to indicate that the additional packet is rejected and not stored in the L2 cache storage queue; and The LSU must wait for a subsequent request from the L2 cache before retrying the transmission of the additional packet.

8. A method for improving performance of storage operation data information transfer within a computer processing system, the computer processing system comprising a processor and a memory, the processor comprising a cache memory and a load and store unit, the computer processing system further comprising a computer readable storage medium having a computer usable program code embodied therein, the computer usable program code being configured to perform operations when executed by the processor, the method comprising: storing a packet in a load and store unit (LSU), the packet to be transferred to the cache memory (L2 cache), the LSU including a store queue having a plurality of entries to store the plurality of packets, the L2 cache including a store queue having a plurality of entries to store the plurality of packets; When the L2 cache determines that there is an available entry in the L2 cache store queue, transmitting a request from the L2 cache to the LSU to transfer the packet to the L2 cache; transmitting an acknowledgment from the LSU to the L2 cache and transferring the packet from the entry in the LSU storage queue to the L2 cache; receiving the packet in the L2 cache and storing the packet in the available entry in the L2 cache storage queue; as well as Prior to the L2 cache requesting additional packets, in anticipation that the L2 cache has additional available entries in the L2 cache store queue, additional acknowledgments are communicated from the LSU to the L2 cache, and additional packets are transferred from the additional entries in the LSU store queue to the L2 cache.

9. The method according to claim 8, further comprising: determining, by the L2 cache, that there are additional available entries in the L2 cache store queue; storing the additional packets from the LSU store queue in the additional available entries in the L2 cache store queue; as well as Transmission of a subsequent request to the LSU for a subsequent packet to be transmitted from the LSU is delayed, the subsequent request also serving as a confirmation to the LSU to store the additional packet in the L2 cache.

10. The method of claim 8, wherein the L2 cache comprises a control module, and transmitting the request by the L2 cache further comprises the L2 cache control module transmitting a POP signal along a control bus coupled to the LSU; and Wherein the LSU includes a control module, and transmitting the acknowledgement by the LSU further comprises the LSU control module transmitting a PUSH signal along the control bus coupled to the L2 cache.

11. The method of claim 10, wherein a delay of a request for a subsequent information packet (a subsequent request delay) is determined by the L2 cache control module, the L2 cache control module calculating the subsequent request delay based on a number of available entries within the L2 cache storage queue.

12. The method of claim 11, wherein the L2 cache control module calculates the subsequent request delay based on an average time to transfer the packet from the LSU store queue to the L2 cache store queue.

13. The method of claim 11, wherein the L2 cache control module sets and resets the subsequent request delay based on a threshold, wherein the threshold is a number of available entries in the L2 cache storage queue; wherein when the number of available entries in the L2 cache storage queue is less than the threshold, the L2 control module sets the subsequent request delay to a fixed time interval; and When the number of available entries in the L2 cache storage queue is greater than or equal to the threshold, the L2 cache control module resets the subsequent request delay to no time delay.

14. The method according to claim 10, further comprising: rejecting the additional packet when the L2 cache determines that there are no additional available entries in the L2 cache store queue, wherein the L2 cache control module transmits a BOUNCE signal along the control bus to the LSU control module to indicate that the additional packet is rejected and not stored in the L2 cache store queue; as well as When the L2 cache sends a subsequent request to the LSU, the transmission of the additional packets is retried by the LSU.

15. A computer program product for improving performance of storage operation data information transfer within a computer processing system, the computer processing system comprising a processor and a memory, the processor comprising a cache memory and a load and store unit, the computer program product comprising a non-transitory computer readable storage medium having computer usable program code embodied therein, the computer usable program code being configured to, when executed by at least one processor, perform operations comprising: storing a packet in a load and store unit (LSU), the packet to be transferred to the cache memory (L2 cache), the LSU including a store queue having a plurality of entries to store the plurality of packets, the L2 cache including a store queue having a plurality of entries to store the plurality of packets; When the L2 cache determines that there is an available entry in the L2 cache store queue, transmitting a request from the L2 cache to the LSU to transfer the packet to the L2 cache; transmitting an acknowledgment from the LSU to the L2 cache and transferring the packet from the entry in the LSU storage queue to the L2 cache; receiving the packet in the L2 cache and storing the packet in the available entry in the L2 cache storage queue; as well as Prior to the L2 cache requesting additional packets, in anticipation that the L2 cache has additional available entries in the L2 cache store queue, additional acknowledgments are communicated from the LSU to the L2 cache, and additional packets are transferred from the additional entries in the LSU store queue to the L2 cache.

16. The computer program product of claim 15, further comprising: determining, by the L2 cache, that there are additional available entries in the L2 cache store queue; storing the additional packets from the LSU store queue in the additional available entries in the L2 cache store queue; as well as Transmission of a subsequent request from the L2 cache for a subsequent packet to be transmitted from the LSU is delayed, the subsequent request also serving as a confirmation to the LSU to store the additional packet in the L2 cache.

17. The computer program product of claim 15, wherein the L2 cache comprises a control module, and transmitting, by the L2 cache, the request further comprises the L2 cache control module transmitting a POP signal along a control bus coupled to the LSU; and Wherein the LSU includes a control module, and transmitting the acknowledgement by the LSU further comprises the LSU control module transmitting a PUSH signal along the control bus coupled to the L2 cache.

18. The computer program product of claim 17, wherein a delay of a request for a subsequent information packet (a subsequent request delay) is determined by the L2 cache control module, the L2 cache control module calculating the subsequent request delay based on a number of available entries within the L2 cache storage queue.

19. The computer program product of claim 17, wherein the L2 cache control module sets and resets the subsequent request delay based on a threshold, wherein the threshold is a number of available entries in the L2 cache storage queue; wherein when the number of available entries in the L2 cache storage queue is less than the threshold, the L2 control module sets the subsequent request delay to a fixed time interval; and When the number of available entries in the L2 cache storage queue is greater than or equal to the threshold, the L2 cache control module resets the subsequent request delay to no time delay.

20. The computer program product of claim 17, further comprising: rejecting the additional packet when the L2 cache determines that there are no additional available entries in the L2 cache store queue, wherein the L2 cache control module transmits a BOUNCE signal along the control bus to the LSU control module to indicate that the additional packet is rejected and not stored in the L2 cache store queue; as well as When the L2 cache sends a subsequent request to the LSU, the transmission of the additional packets is retried by the LSU.

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