Display device and analysis method

Abstract

The display device includes: a pixel array including a plurality of pixels; a control unit including a plurality of output terminals outputting a video signal; a plurality of selectors, each selector being disposed between the pixel array and the control unit to electrically connect or disconnect a corresponding output terminal of the control unit and a corresponding pixel of the pixel array; and a plurality of paths, one end of each path being connected to a corresponding output terminal. The plurality of paths includes: a plurality of connection paths, the other end of each connection path being connected to a corresponding selector; and virtual paths, the other end of each virtual path being not connected to a corresponding selector.

Description

Technical Field

[0001] The present disclosure relates to a display device and an analysis method. Background Art

[0002] For example, the display device of Patent Document 1 includes a display panel provided with a pixel array including an organic light emitting diode (OLED) as a light emitting element.

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: WO 2016 / 072139 A Summary of the invention

[0006] Technical issues

[0007] A control unit such as a display driver IC (DDIC) may be provided on the display panel. An output terminal of the control unit is connected to a corresponding pixel in a pixel array via a selector provided on the display panel. There is a possibility that a defect occurs in a path between the output terminal of the control unit and the selector. If a defective portion of the path can be specified, it is useful for defect analysis, etc.

[0008] One aspect of the present disclosure provides for a defective portion of a path between an output terminal of a control unit and a selector.

[0009] Solution to the problem

[0010] A display device according to one aspect of the present disclosure includes: a pixel array including a plurality of pixels; a control unit including a plurality of output terminals for outputting video signals; a plurality of selectors arranged between the pixel array and the control unit, each selector electrically connecting or disconnecting a corresponding output terminal of the control unit and a corresponding pixel of the pixel array to each other; and a plurality of paths connected to the output terminals corresponding to one end of the corresponding paths, wherein the plurality of paths include: a plurality of connection paths connected to the selectors corresponding to the other ends of the corresponding paths; and a virtual path not connected to the selector corresponding to the other ends of the corresponding paths.

[0011] An analysis method according to one aspect of the present disclosure is a method for a display device, which includes: a pixel array including multiple pixels; a control unit including multiple output terminals for outputting video signals; multiple selectors arranged between the pixel array and the control unit, each selector electrically connecting or disconnecting a corresponding output terminal of the control unit with a corresponding pixel of the pixel array; and multiple paths connected to an output terminal corresponding to one end of the corresponding path, the multiple paths including: multiple connection paths connected to the selectors corresponding to the other end of the corresponding path; and a virtual path not connected to the selector corresponding to the other end of the corresponding path, the analysis method including: for each of the multiple paths, assuming that the current loads of the corresponding output terminals are equal to each other, outputting a video signal so that the current of the corresponding one output terminal is greater than the current of the other output terminal, and measuring the consumption current of the control unit; and specifying a defective portion of at least one of the multiple connection paths based on the measurement result. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 : is a diagram showing an example of a schematic configuration of a display device 1 according to an embodiment.

[0013] Figure 2 is a diagram showing an example of a schematic configuration of the selector 51 .

[0014] Figure 3 is a diagram showing an example of a schematic configuration of a plurality of paths P.

[0015] Figure 4 is a diagram showing an example of a schematic configuration of a connection path CP.

[0016] Figure 5 is a diagram showing an example of a schematic configuration of a connection path CP.

[0017] Figure 6 is a diagram showing an example of a schematic configuration of a virtual path DP.

[0018] Figure 7 is a diagram showing an example of a schematic configuration of a virtual path DP.

[0019] Figure 8 is a diagram showing an example of a schematic configuration of a virtual path DP.

[0020] Fig. 9 is a diagram showing an example of a schematic configuration of a virtual path DP.

[0021] Fig.10 is a diagram showing an example of specifying a disconnected portion.

[0022] Fig.11is a diagram showing an example of the consumption current I of each path P.

[0023] Fig.12 is a flowchart illustrating an example of an analysis method.

[0024] Fig.13 2 is a diagram showing a modified example.

[0025] Fig.14 2 is a diagram showing a modified example.

[0026] Fig.15 2 is a diagram showing a modified example.

[0027] Fig.16 is a diagram showing a configuration example of a pixel PIX.

[0028] Fig.17 is a diagram showing another configuration example of the pixel PIX.

[0029] Fig.18 is a diagram showing another configuration example of the pixel PIX.

[0030] Fig.19 is a diagram showing another configuration example of the pixel PIX.

[0031] Fig. 20 is a diagram showing another configuration example of the pixel PIX.

[0032] Fig.21 is a diagram showing another configuration example of the pixel PIX.

[0033] Fig. 22 is a diagram showing another configuration example of the pixel PIX.

[0034] Fig.23 is a diagram showing another configuration example of the pixel PIX.

[0035] Fig.24 is a diagram showing an example of the appearance of the head mounted display 110 .

[0036] Fig.25 is a diagram showing an example of the appearance of another head mounted display 120 .

[0037] Fig.26 is a diagram showing an example of the external appearance of the digital camera 130 .

[0038] Fig. 27 is a diagram showing an example of the external appearance of the digital camera 130 .

[0039] Fig.28 is a diagram showing an example of the appearance of the television device 140 .

[0040] Fig.29 is a diagram showing an example of the appearance of the smartphone 150 .

[0041] Fig.30 is a diagram showing a configuration example of a vehicle to which the technology of the present disclosure is applied.

[0042] Fig.31 It is a diagram showing a configuration example of a vehicle to which the technology of the present disclosure is applied. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in the following embodiments, the same elements are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0044] The present disclosure will be described according to the following item order.

[0045] 1. Implementation Method

[0046] 2. Modifications

[0047] 3. Example of the effect

[0048] 4. Example of pixel circuit

[0049] 5. Examples of Use Cases

[0050] 1. Implementation Method

[0051] Figure 1 1 is a diagram showing an example of a schematic configuration of a display device 1 according to an embodiment. The display device 1 includes a display panel 2, a pixel array 3, a vertical driver 4, a horizontal driver 5, a DDIC 6, and a plurality of paths P.

[0052] The display panel 2 is provided with a pixel array 3, a vertical driver 4, a horizontal driver 5, a DDIC 6, and a plurality of paths P. For example, the pixel array 3, the vertical driver 4, the horizontal driver 5, and the plurality of paths P are formed in the display panel 2 by a semiconductor process or the like. The DDIC 6 is an example of a control unit in the display device 1, and is, for example, manufactured separately from the display panel 2 and mounted on the display panel 2. A circuit or the like having a function similar to that of the DDIC 6 may be directly formed on the display panel 2 as a control unit. As long as there is no contradiction, the DDIC 6 and the control unit may be appropriately read interchangeably. It should be noted that the arrangement of the elements in the display panel 2 is not limited to Figure 1 The example shown in .

[0053] The pixel array 3 includes a plurality of pixels 31. The plurality of pixels 31 are arranged two-dimensionally in the horizontal direction and the vertical direction. One pixel 31 may be a sub-pixel that emits one of red light (R), green light (G), and blue light (B). Each pixel 31 includes, for example, a light emitting element, a transistor, a capacitor (capacitor), etc. An example of a light emitting element is an OLED. Various known pixel configurations may be employed, and reference will be made later. Figures 16 to 23 Some specific examples are described.

[0054] The vertical driver 4 selects and drives the pixels 31 corresponding to the display lines in the horizontal direction. The vertical driver 4 is connected to the pixel array 3 via a plurality of control lines WSL. For example, one control line WSL is connected to each pixel 31 arranged in the horizontal direction. The vertical driver 4 selects the control line WSL and supplies a control signal WS for controlling light emission and non-light emission of the corresponding pixel 31 to the selected control line WSL.

[0055] It should be noted that “connection” may be understood to mean “electrical connection” as long as there is no contradiction. “Electrical connection” may be understood to include an aspect in which another element is interposed between elements to be connected to each other as long as the functions of the elements to be connected to each other are not hindered.

[0056] The horizontal driver 5 selects and drives the pixels 31 corresponding to the display lines in the vertical direction. The horizontal driver 5 is connected to the pixel array 3 via a plurality of signal lines SGL. For example, one signal line SGL is connected to each pixel 31 arranged in the vertical direction. The horizontal driver 5 selects the signal line SGL and supplies a pixel signal SG for controlling the light emission amount (brightness, etc.) of the corresponding pixel 31 to the selected signal line SGL.

[0057] The horizontal driver 5 includes a plurality of selectors 51 disposed between the pixel array 3 and the DDIC 6. Each selector 51 connects or disconnects a corresponding output terminal 62 of the DDIC 6 and a corresponding pixel 31 of the pixel array 3 to each other. Figure 2 Further details of the selector 51 are described.

[0058] The DDIC 6 is a display driver integrated circuit (IC) that drives the display device 1 . The DDIC 6 is connected to each of the vertical driver 4 and the horizontal driver 5 .

[0059] The DDIC 6 supplies a control signal for controlling the selection of the pixel 31 by the vertical driver 4 and the like to the vertical driver 4. The vertical driver 4 supplies a control signal WS to each pixel 31 based on the control signal from the DDIC 6.

[0060] The DDIC 6 supplies a control signal for controlling the selection of the pixels 31 by the horizontal driver 5 and the like to the horizontal driver 5. The horizontal driver 5 selects the pixels 31 corresponding to the display lines in the vertical direction based on the control signal from the DDIC 6.

[0061] In addition, the DDIC 6 supplies the video signal FS to the horizontal driver 5. Specifically, the DDIC 6 includes a plurality of output terminals 62 capable of outputting the video signal FS. The video signal FS from each output terminal 62 is supplied to the horizontal driver 5. The horizontal driver 5 supplies the video signal FS from the DDIC 6 to the selected pixel 31 via the corresponding signal line SGL. The video signal FS supplied to the pixel 31 via the signal line SGL is referred to as a pixel signal SG and is shown. The pixel signal SG is a voltage signal (e.g., a pulse voltage) for charging the capacitor in the pixel 31. A current for charging is supplied from the output terminal 62 of the DDIC 6.

[0062] The plurality of paths P include a plurality of connection paths CP and one or more dummy paths DP. The connection path CP among the connection path CP and the dummy path DP connects the output terminal 62 of the DDIC 6 and the selector 51 to each other. That is, the selector 51 is connected to the output terminal 62 of the DDIC 6 via the connection path CP. Figure 2 Give a description.

[0063] Figure 2 is a diagram showing an example of a schematic configuration of a selector 51. One selector 51 and its peripheral parts are schematically shown. In this example, the selector 51 is a demultiplexer configured to receive one video signal FS as an input and output a plurality of pixel signals SG. The selector 51 includes a plurality of switches 52 that can be individually on-off controlled. The plurality of switches 52 are, for example, field effect transistors (FETs) connected in parallel.

[0064] One end of each switch 52 is connected to the same connection path CP. The other end of each switch 52 is connected to a signal line SGL (22) pointing to the corresponding pixel 31. Figure 1 ).exist Figure 2 In the example shown in , one selector 51 includes six switches 52 , and corresponding six signal lines SGL are connected to the pixels 31 constituting two display lines.

[0065] The DDIC 6 includes an amplifier 61 corresponding to the selector 51. The output end of the amplifier 61 is connected to the output terminal 62. The video signal FS is output via the amplifier 61 and the output terminal 62. The amplifier 61 uses the signal from the display panel 2 ( Figure 1) to operate with the voltage and current (power) of the power supply 21 in DDIC 6. Although not shown, the power supply 21 is also connected to another part of the DDIC 6, for example, an amplifier different from the amplifier 61 shown, and provides power consumption of the DDIC 6. The current flowing from the power supply 21 to the DDIC 6 is referred to as the consumption current I of the DDIC 6 and is shown.

[0066] For example, the selector 51 as described above is connected to the corresponding output terminal 62 of the DDIC 6 via the connection path CP. Figure 3 A plurality of paths P including connection paths CP and virtual paths DP are described.

[0067] Figure 3 is a diagram showing an example of a schematic configuration of a plurality of paths P. In this example, the plurality of paths P include a plurality of connection paths CP and a plurality of dummy paths DP. One end of each connection path CP and each dummy path DP is connected to a corresponding output terminal 62 of the DDIC 6.

[0068] The other end of the connection path CP is connected to the corresponding selector 51 of the horizontal driver 5. The connection path CP is connected between the output terminal 62 and the selector 51, and supplies the video signal FS from the output terminal 62 to the selector 51.

[0069] The other end of the virtual path DP is not connected to any selector 51. The virtual path DP is designed so that the current load of the output terminal 62 of the DDIC 6 to which the virtual path DP is connected is smaller than the current load of the output terminal 62 to which the connection path CP is connected. The larger the current load, the larger the current of the output terminal 62 when the same video signal FS is output. It can also be said that the larger the current load, the larger the capacitance when the path P is viewed from the output terminal 62.

[0070] exist Figure 3 In the example shown, the plurality of paths P include a plurality of virtual paths DP having different lengths from each other. Each virtual path DP is shorter than the connection path CP, and the other end of the virtual path DP is open. The shorter the virtual path DP is, the smaller the current load of the output terminal 62 is due to the fact that the wiring capacitance of the virtual path DP is reduced.

[0071] Reference Figures 4 to 9 An example of a specific configuration of the connection path CP and the virtual path DP is described.

[0072] Figure 4 and Figure 5 is a diagram showing an example of a schematic configuration of a connection path CP. Figure 4 The plan layout of the connection path CP is schematically shown. Figure 5 The side layout of the connection path CP is schematically shown.

[0073] The connection path CP includes a plurality of wirings L and one or more vias V. The plurality of wirings L are connected in series between the output terminal 62 of the DDIC 6 and the selector 51. Adjacent wirings L among the plurality of wirings L are connected to each other via the vias V to extend in different wiring layers. The wiring layer is, for example, a wiring layer of a multilayer substrate constituting the display panel 2.

[0074] Specifically, in Figure 4 and Figure 5 , the wiring L1, the wiring L2, the wiring L3, and the wiring L4 are exemplified as the wiring L. As the via V, the via V12, the via V23, and the via V34 are exemplified. The wiring L1, the via V12, the wiring L2, the via V23, the wiring L3, the via V34, and the wiring L4 are connected to each other in this order from the output terminal 62 of the DDIC 6 toward the selector 51.

[0075] For example, the wiring L1 is provided on the surface layer of the display panel 2 on which the DDIC 6 is mounted. The wiring L2, the wiring L3, and the wiring L4 are provided on the inner layer of the display panel 2. The via V12 connects the wiring L1 and the wiring L2 to each other. The via V23 connects the wiring L2 and the wiring L3 to each other. The via V34 connects the wiring L3 and the wiring L4 to each other.

[0076] Figures 6 to 9 is a diagram showing an example of a schematic configuration of a virtual path DP. A side layout of a virtual path DP having different lengths is schematically shown. In the example, the virtual path DP includes a smaller number of wirings L than the plurality of wirings L of the connection path CP. The wiring L located closest to the selector 51 in the virtual path DP may be shorter than the corresponding wiring L of the connection path CP.

[0077] Specifically, in Figure 6 In the example shown in FIG. 1 , the virtual path DP and the connection path CP ( Figure 5 ) is that wiring L4 and via V34 are not included. Figure 7 In the example shown, the virtual path DP does not include the wiring L3 or the via V23. Figure 8 In the example shown in FIG. 1 , the wiring L located closest to the selector 51 in the virtual path DP is the wiring L2, and the wiring L2 is closer to the wiring L2 of the connection path CP ( Figure 5 ) is short. Fig. 9 In the example shown in , the dummy path DP does not include the wiring L2 or the via V12 .

[0078] According to the display device 1 having the above configuration, even in the case where a defect occurs in any of the plurality of connection paths CP, the connection path CP in which the defect occurs and its defective portion can be specified. Hereinafter, description will be made assuming that the defect is disconnection.

[0079] Fig.10 is a diagram showing an example of specifying a disconnected portion. A plurality of connection paths CP are respectively referred to as connection paths CP-1 to CP18 and are shown to be distinguishable from each other. Virtual paths DP are respectively referred to as virtual paths DP-1 to DP-10 and are shown to be distinguishable from each other.

[0080] First, assuming that the current loads of the output terminals 62 are the same as each other, the video signal FS is output so that the current of one output terminal 62 is larger than the current of the other output terminals 62. For example, the output terminal 62 of the DDIC 6 outputs the video signal FS so that only the display line (pixel 31 of the pixel array 3) corresponding to the connection path CP of the one output terminal 62 emits white light. In this state, the consumption current I ( Figure 2 ).

[0081] Next, the video signal FS is output so that the current of the other output terminal 62 is larger than the current of the other output terminals 62, and the consumption current I of the DDIC 6 is measured. Similar measurement is performed on all the output terminals 62. That is, the consumption current I of the DDIC 6 is measured for each of the plurality of paths P corresponding to the plurality of output terminals 62.

[0082] Fig.11 : is a graph showing an example of the consumption current I of each path P. The horizontal axis of the graph represents the path P. The vertical axis of the graph indicates the magnitude of the consumption current I. The magnitude of the consumption current I of each path P is represented by a circular graph.

[0083] Regarding the connection path CP, in this example, among the connection paths CP-1 to CP-18, only the consumption current I of the connection path CP-5 is small. That is, among the multiple output terminals 62 connected to the connection paths CP-1 to CP-18, only the current load of the output terminal 62 connected to the connection path CP-5 is small. This means that when the connection path CP-5 is viewed from the output terminal 62, the capacitance is small, that is, the connection path CP-5 is open in the middle. Thus, it can be specified that a disconnection has occurred in the connection path CP-5.

[0084] Regarding the dummy path DP, the consumption current I of the dummy paths DP-1 to DP-10 is smaller than the consumption current I of the connection paths CP-1 to CP-4 and the connection paths CP-6 to CP-10 where no disconnection occurs. In addition, the magnitude of the consumption current I is different for each dummy path DP.

[0085] Here, it should be noted that the size of the consumption current I of the connection path CP-5 is close to the size of the consumption current I of the virtual path DP-4. Thus, it can be estimated that the connection path CP-5 is disconnected like the virtual path DP-4. That is, it can be estimated that the disconnection occurs at the position of the connection path CP-5 corresponding to the other end (open end) of the virtual path DP-4. Therefore, this position can be specified as the disconnected portion of the connection path CP-5.

[0086] For example, as described above, it is possible to specify a connection path CP in which disconnection has occurred among a plurality of connection paths CP, and further specify a disconnected portion of the connection path CP.

[0087] Fig.12 : is a flowchart showing an example of the analysis method. The analysis method is used, for example, when testing the production of the display device 1, when analyzing returned products, etc. The details of each step have been described above, so the detailed description will not be repeated.

[0088] In step S1, for each channel P, the video signal FS is outputted so that the current of the corresponding output terminal 62 is greater than the current of other output terminals 62. At the same time, the consumption current I of the DDIC 6 is measured. For example, the above reference is outputted from the corresponding output terminal 62 of the DDIC 6 Fig.10 Described video signal FS.

[0089] In step S2, a connection path CP is specified in which the consumption current I is small. Fig.11 As described above, among the plurality of connection paths CP, a connection path CP whose consumption current I is smaller than the consumption current I of the other connection paths CP is designated.

[0090] In step S3, based on the virtual path DP having a consumption current I having a magnitude close to the consumption current I of the designated connection path CP, the disconnected portion of the connection path CP is designated. Fig.11 As described above, the position of the connection path CP corresponding to the open end of the virtual path DP is designated as the disconnected portion.

[0091] For example, as described above, a connection path CP that has been disconnected among a plurality of connection paths CP can be specified, and the disconnected portion can be further specified. The specification of the disconnected portion can be used for subsequent defect analysis, etc. For example, by narrowing the cut portion, defect analysis, etc. can be performed efficiently.

[0092] Note that the DDIC 6 may be designed to facilitate the above-described analysis method. For example, the DDIC 6 may be designed to switch to a dedicated mode (analysis mode) in which, in the above-described step S1, the video signal FS corresponding to each path P is output at high speed. In this analysis mode, power consumption other than the output of the video signal FS may be suppressed so that the magnitude of the current of each output terminal 62 of the DDIC 6 is easily reflected in the magnitude of the consumption current I of the DDIC 6.

[0093] 2. Modifications

[0094] The configuration of the plurality of paths P including the virtual path DP is not limited to the above-described embodiment. Some modifications will be described.

[0095] Figures 13 to 15 is a diagram showing a modified example. Fig.13 In the example shown, the connection path CP is also a virtual path DP. Fig.13 In the example shown in (A) of FIG. 1 , any one of the plurality of connection paths CP is also used as a virtual path DP. Fig.13 As shown in (B) of FIG. 1 , the connection path CP includes switches SW connected in series in the connection path CP. As the switches SW, switches SW1, SW2, and SW3 are exemplified. By turning off (non-conducting state) any one of the switches SW, the connection path CP can be used as a virtual path DP shorter than the connection path CP. The number of paths P can be reduced.

[0096] It should be noted that only some of the connection paths CP among the plurality of connection paths CP may have Fig.13 The configuration shown in (B) can be used as a virtual path DP.

[0097] exist Fig.14 In the example shown, the virtual path DP includes switches SW connected in series in the virtual path DP. As the switches SW, switches SW1, SW2, and SW3 are exemplified. By turning off the switches SW, the corresponding positions in the virtual path DP can be opened. The length of the virtual path DP connected to the output terminal 62 can be changed by a combination of on / off of the switches SW. That is, one virtual path DP can be used as a plurality of virtual paths DP having different lengths from each other. Therefore, the number of virtual paths DP can be reduced.

[0098] exist Fig.15In the example shown in , the virtual path DP includes a capacitor C. The other end of the virtual path DP is connected to the ground line GND via the capacitor C. The capacitor C is connected to the virtual path DP, so that the capacitance when the virtual path DP is viewed from the output terminal 62 increases. By changing the capacitance of the capacitor C, the same effect as changing the length of the virtual path DP can be obtained. The capacitor C is designed to have, for example, the same capacitance as the wiring capacitance of the wiring L described above. The capacitance of the capacitor C may be different, so that the wiring capacitance is different for each virtual path DP. The wiring capacitance of the virtual path DP is implemented by the capacitor C, whereby the virtual path DP can be shortened.

[0099] In an embodiment, the defect of the connection path CP may be a short circuit. In this case, the other end of the virtual path DP may be short-circuited. Fig.11 In the example, the consumption current I of the connection path CP where the short circuit has occurred is greater than the consumption current I of other connection paths CP, thereby specifying the connection path CP where the short circuit has occurred. The consumption current I of the virtual path DP is greater than the consumption current I of the connection path CP where the short circuit has not occurred, and the short-circuited portion of the connection path CP where the short circuit has occurred can be specified by comparing with such a virtual path DP.

[0100] 3. Example of the effect

[0101] For example, the above technology is defined as follows. One of the disclosed technologies is a display device 1. As shown in reference Figure 1 , Figure 3 As described in the above, the display device 1 includes a pixel array 3, a DDIC 6 (an example of a control unit), a plurality of selectors 51, and a plurality of paths P. The pixel array 3 includes a plurality of pixels 31. The DDIC 6 includes a plurality of output terminals 62 for outputting a video signal FS. Each of the plurality of selectors 51 is provided between the pixel array 3 and the DDIC 6 to electrically connect or disconnect a corresponding output terminal 62 of the DDIC 6 and a corresponding pixel 31 of the pixel array 3. One end of each of the plurality of paths P is connected to the corresponding output terminal 62. The plurality of paths P include: a plurality of connection paths CP connected to the selectors 51 corresponding to the other ends of the corresponding paths P; and a dummy path DP not connected to the selectors 51 corresponding to the other ends of the corresponding paths P. According to such a display device 1, for example, as described above with reference to Figures 10 to 12 As described in FIG. 1 , etc., a defective portion of the connection path CP between the output terminal 62 of the DDIC 6 and the switch 52 can be specified.

[0102] As reference Figure 1 , Figures 3 to 9As described in, for example, the virtual path DP may be shorter than the connection path CP. The plurality of paths P may include a plurality of virtual paths DP having different lengths from each other. For example, the connection path CP may include a plurality of wirings L connected in series between the output terminal 62 and the selector 51, and the virtual path DP may include a smaller number of wirings L than the plurality of wirings L of the connection path CP. Adjacent wirings L among the plurality of wirings L may be connected to each other via vias V to extend in different wiring layers. The wiring L located closest to the selector 51 in the virtual path DP may be shorter than the corresponding wiring L of the connection path CP. The other end of the virtual path DP may be open. For example, by using such a virtual path DP, a disconnected portion of the connection path CP may be specified.

[0103] As reference Fig.13 As described in , at least some of the connection paths CP among the plurality of connection paths CP may include switches SW connected in series in the connection paths CP, and at least some of the connection paths CP may be virtual paths DP. As a result, the number of paths P can be reduced.

[0104] As reference Fig.14 As described in , etc., the virtual path DP may include switches SW connected in series in the virtual path DP. As a result, one virtual path DP can be used as a plurality of virtual paths DP having different lengths from each other. Therefore, the number of virtual paths DP can be reduced.

[0105] As reference Fig.15 As described in , the other end of the dummy path DP may be connected to the ground line GND via the capacitor C. The wiring capacitance of the dummy path DP is implemented by the capacitor C, whereby the dummy path DP may be shortened.

[0106] refer to Figures 10 to 12 The analysis method described in, etc. is also one of the disclosed technologies. The analysis method is an analysis method for the display device 1 having the above configuration, and includes: for each of the plurality of paths P, assuming that the current loads of the corresponding output terminals 62 are equal to each other, outputting the video signal FS so that the current of the corresponding output terminal 62 is greater than the current of the other output terminals 62, and measuring the consumption current I of the DDIC 6 (step S1); and specifying the defective portion of at least one connection path CP among the plurality of connection paths CP based on the measurement result (steps S2 to S3). For example, the specifying includes: specifying the connection path CP with a smaller consumption current I based on the measurement result (step S2), and specifying the disconnected portion of the connection path CP based on the virtual path DP whose consumption current I has a size close to the consumption current I of the specified connection path CP (step S3). By this analysis method, the defective portion of the connection path CP between the output terminal 62 of the DDIC 6 and the switch 52 can be specified.

[0107] Note that the above effects are examples. There may be other effects.

[0108] 4. Example of pixel circuit

[0109] Reference Figures 16 to 23 Some examples of pixel circuits are described. Note that in these figures, pixels are indicated as pixels PIX.

[0110] Fig.16 is a diagram showing a configuration example of a pixel PIX. The pixel PIX includes a capacitor C01, transistors MN02 to MN03, and a light-emitting element EL. The transistors MN02 to MN03 are N-type metal oxide semiconductor field effect transistors (MOSFETs). The gate of the transistor MN02 is connected to the control line WSL, the drain is connected to the signal line SGL, and the source is connected to the gate of the transistor MN03 and the capacitor C01. One end of the capacitor C01 is connected to the source of the transistor MN02 and the gate of the transistor MN03, and the other end is connected to the source of the transistor MN03 and the anode of the light-emitting element EL. The gate of the transistor MN03 is connected to the source of the transistor MN02 and one end of the capacitor C01, the drain is connected to the power supply line VCCP, the source is connected to the other end of the capacitor C01 and the anode of the light-emitting element EL. The light-emitting element EL is, for example, an organic EL light-emitting element, the anode is connected to the source of the transistor MN03 and the other end of the capacitor C01, and the cathode is connected to the power supply line Vcath.

[0111] With this configuration, in the pixel PIX, the transistor MN02 enters the on state, thereby setting the voltage across the capacitor C01 based on the pixel signal supplied from the signal line SGL. The transistor MN03 causes a current corresponding to the voltage across the capacitor C01 to flow through the light emitting element EL. The light emitting element EL emits light based on the current supplied from the transistor MN03. In this way, the pixel PIX emits light having a brightness corresponding to the pixel signal.

[0112] Fig.17: is a diagram showing another configuration example of pixel PIX. Pixel PIX includes capacitors C11 and C12, transistors MP12 to MP15, and light emitting elements EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to the control line WSL, the source is connected to the signal line SGL, and the drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to the power line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, the source is connected to the power line VCCP, and the drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of the transistor MP14 is connected to the drain of the transistor MP12 and the other end of the capacitor C12, the source is connected to the drain of the transistor MP13, the other end of the capacitor C11 and one end of the capacitor C12, the drain is connected to the anode of the light emitting element EL and the source of the transistor MP15. The gate of the transistor MP15 is connected to the control line AZSL, the source is connected to the drain of the transistor MP14 and the anode of the light emitting element EL, and the drain is connected to the power supply line VSS.

[0113] With this configuration, in the pixel PIX, the transistor MP12 enters the on state, thereby setting the voltage across the capacitor C12 based on the pixel signal provided from the signal line SGL. The transistor MP13 is turned on and off based on the signal of the control line DSL. During the period in which the transistor MP13 is in the on state, the transistor MP14 causes a current corresponding to the voltage across the capacitor C12 to flow through the light emitting element EL. The light emitting element EL emits light based on the current provided from the transistor MP14. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. The transistor MP15 is turned on and off based on the signal of the control line AZSL. During the period in which the transistor MP15 is in the on state, the voltage of the anode of the light emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0114] Fig.18is a diagram showing another configuration example of a pixel PIX. The pixel PIX includes a capacitor C21, transistors MN22 to MN25, and a light emitting element EL. The transistors MN22 to MN25 are N-type MOSFETs. The gate of the transistor MN22 is connected to the control line WSL, the drain is connected to the signal line SGL, and the source is connected to the gate of the transistor MN24 and the capacitor C21. One end of the capacitor C21 is connected to the source of the transistor MN22 and the gate of the transistor MN24, and the other end is connected to the source of the transistor MN24, the drain of the transistor MN25, and the anode of the light emitting element EL. The gate of the transistor MN23 is connected to the control line DSL, the drain is connected to the power supply line VCCP, and the source is connected to the drain of the transistor MN24. The gate of the transistor MN24 is connected to the source of the transistor MN22 and one end of the capacitor C21, the drain is connected to the source of the transistor MN23, and the source is connected to the other end of the capacitor C21, the drain of the transistor MN25, and the anode of the light emitting element EL. The gate of the transistor MN25 is connected to the control line AZSL, the drain is connected to the source of the transistor MN24, the other end of the capacitor C21, and the anode of the light emitting element EL, and the source is connected to the power supply line VSS.

[0115] With this configuration, in the pixel PIX, the transistor MN22 enters the on state, thereby setting the voltage across the capacitor C21 based on the pixel signal provided from the signal line SGL. The transistor MN23 is turned on and off based on the signal of the control line DSL. During the period when the transistor MN23 is in the on state, the transistor MN24 causes a current corresponding to the voltage across the capacitor C21 to flow through the light emitting element EL. The light emitting element EL emits light based on the current provided from the transistor MN24. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. The transistor MN25 is turned on and off based on the signal of the control line AZSL. During the period when the transistor MN25 is in the on state, the voltage of the anode of the light emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0116] Fig.19is a diagram showing another configuration example of a pixel PIX. The pixel PIX includes a capacitor C31, transistors MP32 to MP36, and a light emitting element EL. The transistors MP32 to MP36 are P-type MOSFETs. The gate of the transistor MP32 is connected to the control line WSL, the source is connected to the signal line SGL, and the drain is connected to the gate of the transistor MP33, the drain of the transistor MP34, and the capacitor C31. One end of the capacitor C31 is connected to the power supply line VCCP, and the other end is connected to the drain of the transistor MP32, the gate of the transistor MP33, and the drain of the transistor MP34. The gate of the transistor MP34 is connected to the control line AZSL1, the source is connected to the drain of the transistor MP33 and the source of the transistor MP35, and the drain is connected to the drain of the transistor MP32, the gate of the transistor MP33, and the other end of the capacitor C31. The gate of the transistor MP35 is connected to the control line DSL, the source is connected to the drain of the transistor MP33 and the source of the transistor MP34, and the drain is connected to the source of the transistor MP36 and the anode of the light emitting element EL. The gate of the transistor MP36 is connected to the control line AZSL2 , the source is connected to the drain of the transistor MP35 and the anode of the light emitting element EL, and the drain is connected to the power supply line VSS.

[0117] With this configuration, in the pixel PIX, the transistor MP32 enters the on state, thereby setting the voltage across the capacitor C31 based on the pixel signal provided from the signal line SGL. The transistor MP35 is turned on and off according to the signal of the control line DSL. The transistor MP33 causes a current corresponding to the voltage across the capacitor C31 to flow through the light emitting element EL during the period in which the transistor MP35 is in the on state. The light emitting element EL emits light based on the current provided from the transistor MP33. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. The transistor MP34 is turned on and off based on the signal of the control line AZSL1. During the period in which the transistor MP34 is in the on state, the drain and gate of the transistor MP33 are connected to each other. The transistor MP36 is turned on and off based on the signal of the control line AZSL2. During the period in which the transistor MP36 enters the on state, the voltage of the anode of the light emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0118] Fig. 20 is a diagram showing another configuration example of the pixel PIX. One end of the capacitor C48 is connected to the signal line SGL1, and the other end is connected to the power supply line VSS. One end of the capacitor C49 is connected to the signal line SGL1, and the other end is connected to the signal line SGL2. The transistor MP49 is a P-type MOSFET, and the gate is connected to the control line WSL2, the source is connected to the signal line SGL1, and the drain is connected to the signal line SGL2.

[0119] The pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light emitting element EL. The transistors MP42 to MP46 are P-type MOSFETs. The gate of the transistor MP42 is connected to the control line WSL1, the source is connected to the signal line SGL2, and the drain is connected to the gate of the transistor MP43 and the capacitor C41. One end of the capacitor 41 is connected to the power line VCCP, and the other end is connected to the drain of the transistor MP42 and the gate of the transistor MP43. The gate of the transistor MP43 is connected to the drain of the transistor MP42 and the other end of the capacitor C41, the source is connected to the power line VCCP, and the drain is connected to the sources of the transistors MP44 and MP45. The gate of the transistor MP44 is connected to the control line AZSL1, the source is connected to the drain of the transistor MP43 and the source of the transistor MP45, and the drain is connected to the signal line SGL2. The gate of the transistor MP45 is connected to the control line DSL, the source is connected to the drain of the transistor MP43 and the source of the transistor MP44, and the drain is connected to the source of the transistor MP46 and the anode of the light emitting element EL. The gate of the transistor MP46 is connected to the control line AZSL2 , the source is connected to the drain of the transistor MP45 and the anode of the light emitting element EL, and the drain is connected to the power supply line VSS.

[0120] With this configuration, in the pixel PIX, the transistor MP42 enters the on state, thereby setting the voltage across the capacitor C41 based on the pixel signal provided from the signal line SGL1 via the capacitor C49. The transistor MP45 is turned on and off based on the signal of the control line DSL. During the period in which the transistor MP45 is in the on state, the transistor MP43 causes a current corresponding to the voltage across the capacitor C41 to flow through the light emitting element EL. The light emitting element EL emits light based on the current provided from the transistor MP43. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. The transistor MP44 is turned on and off based on the signal of the control line AZSL1. During the period in which the transistor MP44 is in the on state, the drain of the transistor MP43 and the signal line SGL2 are connected to each other. The transistor MP46 is turned on and off based on the signal of the control line AZSL2. During the period in which the transistor MP46 enters the on state, the voltage of the anode of the light emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0121] Fig.21 2 is a diagram showing another configuration example of the pixel PIX. A plurality of pixels PIX are arranged in a matrix form in the display region 100, and the display region 100 is provided between the first control unit 40 and the second control unit 70.

[0122] The first control unit 40 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and capacitor C61. Transistors MP56 to MP57 are P-type MOSFETs. The pixel signal is provided to the input end of the transmission gate TG45, and the output end of the transmission gate TG45 is connected to one end of the signal line 14a. The input end of the transmission gate TG46 is connected to the signal line 14b, and the output end of the transmission gate TG46 is connected to the power line Vorst. One end of the capacitor C61 is connected to the signal line 14a, and the other end is connected to the power line VSS1. The gate of the transistor MP56 is connected to the control line, the source is connected to the power line Vini, and the drain is connected to the signal line 14b. The gate of the transistor MP57 is connected to the control line, the source is connected to the power line Vel, and the drain is connected to the signal line 14b.

[0123] The second control unit 70 includes a transmission gate TG72, a transistor MP73 and a capacitor C82. The transistor MP73 is a P-type MOSFET. The input end of the transmission gate TG72 is connected to the other end of the signal line 14a, and the output end is connected to the drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line, the source is connected to the power supply line Vref, and the drain is connected to the output end of the transmission gate MP72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the output end of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of the signal line 14b.

[0124] The pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light emitting element EL. The transistors MP121 to MP125 are P-type MOSFETs. The gate of the transistor MP122 is connected to the control line WSL, the source is connected to the signal line 14b, and the drain is connected to the gate of the transistor MP121 and the capacitor C132. One end of the capacitor C132 is connected to the power line Vel, and the other end is connected to the drain of the transistor MP122 and the gate of the transistor MP121. The gate of the transistor MP121 is connected to the drain of the transistor MP122 and the other end of the capacitor C132, the source is connected to the power line Vel, and the drain is connected to the sources of the transistors MP123 and MP124. The gate of the transistor MP123 is connected to the control line AZSL, the source is connected to the drain of the transistor MP121 and the source of the transistor MP124, and the drain is connected to the signal line 14b. The gate of the transistor MP124 is connected to the control line, the source is connected to the drain of the transistor MP121 and the source of the transistor MP123, and the drain is connected to the drain of the transistor MP125 and the anode of the light emitting element EL. The gate of the transistor MP125 is connected to the control line AZSL, the source is connected to the power supply line Vorst, and the drain is connected to the drain of the transistor MP124 and the anode of the light emitting element EL.

[0125] With this configuration, in the pixel PIX, the transistor MP122 enters the on state, thereby setting the voltage across the capacitor C132 based on the pixel signal provided via the transmission gate TG45, the signal line 14a, the transmission gate TG72, the capacitor C82, and the signal line 14b. The transistor MP124 is turned on and off based on the signal of the control line. During the period in which the transistor MP124 is in the on state, the transistor MP121 causes a current corresponding to the voltage across the capacitor C132 to flow through the light emitting element EL. The light emitting element EL emits light based on the current provided from the transistor MP121. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. The transistors MP123 and MP125 are turned on and off based on the signal of the control line AZSL. During the period in which the transistor MP123 is in the on state, the drain of the transistor MP121 and the source of the transistor MP124 are connected to the signal line 14b. During the period in which the transistor MP125 enters the on state, the voltage of the anode of the light emitting element EL is initialized by setting it to the voltage Vorst of the power supply line. In addition, the transistor MP56 is turned on and off based on the signal of the control line, the transistor MP57 is turned on and off based on the signal of the control line, and the transistor MP73 is turned on and off based on the signal of the control line. When the transistor MP56 enters the on state, the signal line 14b is set to the voltage of the power line Vini, and when the transistor MP57 enters the on state, the signal line 14b is set to the voltage of the power line Vel. When the transistor MP73 enters the on state, one end of the capacitor C82 is initialized by being set to the voltage of the power line Vref.

[0126] Fig. 22is a diagram showing another configuration example of a pixel PIX. The pixel PIX includes a capacitor C51, transistors MP52 to MP60, and a light emitting element EL. The transistors MP52 to MP60 are P-type MOSFETs. The gate of the transistor MP52 is connected to the control line WSL, the source is connected to the signal line SGL, and the drain is connected to the drain of the transistor MP53 and the source of the transistor MP54. The gate of the transistor MP53 is connected to the control line DSL, the source is connected to the power line VCCP, and the drain is connected to the drain of the transistor MP52 and the source of the transistor MP54. The gate of the transistor MP54 is connected to the source of the transistor MP55, the drain of the transistor MP57, and the capacitor C51, the source is connected to the drains of the transistors MP52 and MP53, and the drain is connected to the sources of the transistors MP58 and MP59. One end of the capacitor C51 is connected to the power line VCCP, and the other end is connected to the gate of the transistor MP54, the source of the transistor MP55, and the drain of the transistor MP57. The capacitor C51 may include two capacitors connected in parallel to each other. The gate of the transistor MP55 is connected to the control line AZSL1, the source is connected to the gate of the transistor MP54, the drain of the transistor MP57, and the other end of the capacitor C51, and the drain is connected to the source of the transistor MP56. The gate of the transistor MP56 is connected to the control line AZSL1, the source is connected to the drain of the transistor MP55, and the drain is connected to the power supply line VSS. The gate of the transistor MP57 is connected to the control line WSL, the drain is connected to the gate of the transistor MP54, the source of the transistor MP55, and the other end of the capacitor C51, and the source is connected to the drain of the transistor MP58. The gate of the transistor MP58 is connected to the control line WSL, the drain is connected to the source of the transistor MP57, and the source is connected to the drain of the transistor MP54 and the source of the transistor MP59. The gate of the transistor 59 is connected to the control line DSL, the source is connected to the drain of the transistor MP54 and the source of the transistor MP58, and the drain is connected to the source of the transistor MP60 and the anode of the light emitting element EL. The gate of the transistor MP60 is connected to the control line AZSL2 , the source is connected to the drain of the transistor MP59 and the anode of the light emitting element EL, and the drain is connected to the power supply line VSS.

[0127] With this configuration, in the pixel PIX, the transistors MP52, MP54, MP58, and MP57 enter the on state, thereby setting the voltage across the capacitor C51 based on the pixel signal provided from the signal line SGL. The transistors MP53 and MP59 are turned on and off based on the signal of the control line DSL. During the period in which the transistors MP53 and MP59 are in the on state, the transistor MP54 causes a current corresponding to the voltage across the capacitor C51 to flow through the light emitting element EL. The light emitting element EL emits light based on the current provided from the transistor MP54. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. The transistors MP55 and MP56 are turned on and off based on the signal of the control line AZSL1. During the period in which the transistors MP55 and MP56 are in the on state, the gate voltage of the transistor MP54 is initialized by setting the gate voltage of the transistor MP54 to the voltage of the power supply line VSS. The transistor MP60 is turned on and off based on the signal of the control line AZSL2. While the transistor MP60 is in the on state, the voltage of the anode of the light emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0128] Fig.23 2 is a diagram showing another configuration example of the pixel PIX. The signal of the control line WSNL and the signal of the control line WSPL are opposite signals to each other.

[0129] The pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light emitting element EL. The transistors MN63 and MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to the control line WSNL, the drain is connected to the signal line SGL and the source of the transistor MP64, and the source is connected to the drain of the transistor MP64, the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to the control line WSPL, the source is connected to the signal line SGL and the drain of the transistor MN63, and the drain is connected to the source of the transistor MN63, the capacitors C61 and C62, and the gate of the transistor MN65. For example, the capacitor C61 includes a metal oxide metal (MOM) capacitor, and one end is connected to the source of the transistor MN63, the drain of the transistor MP64, the capacitor C62, and the gate of the transistor MN65, and the other end is connected to the power supply line VSS2. Note that the capacitor C61 may include, for example, a MOS capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 includes, for example, a MOS capacitor, and one end is connected to the source of the transistor MN63, the drain of the transistor MP64, one end of the capacitor C61, and the gate of the transistor MN65, and the other end is connected to the power supply line VSS2. Note that the capacitor C62 may include, for example, a MOM capacitor or a MIM capacitor. The gate of the transistor MN65 is connected to the source of the transistor MN63, the drain of the transistor MP64, and one end of the capacitors C61 and C62, the drain is connected to the power supply line VCCP, and the source is connected to the drains of the transistors MN66 and MN67. The gate of the transistor MN66 is connected to the control line AZL, the drain is connected to the source of the transistor MN65 and the drain of the transistor MN67, and the source is connected to the power supply line VSS1. The gate of the transistor MN67 is connected to the control line DSL, the drain is connected to the source of the transistor MN65 and the drain of the transistor MN66, and the source is connected to the anode of the light emitting element EL.

[0130] With this configuration, in the pixel PIX, at least one of the transistors MN63 and MP64 enters the on state, thereby setting the voltage across the capacitors C61 and C62 based on the pixel signal provided from the signal line SGL. The transistor MN67 is turned on and off according to the signal of the control line DSL. The transistor MN65 causes a current corresponding to the voltage across the capacitors C61 and C62 to flow through the light-emitting element EL during the period when the transistor MN67 is in the on state. The light-emitting element EL emits light based on the current provided from the transistor MP65. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. The transistor MN66 can be turned on and off based on the signal of the control line AZL. In addition, the transistor MN66 can be used as a resistance element having a resistance value corresponding to the signal of the control line AZL. In this case, the transistor MN65 and the transistor MN66 constitute a so-called source follower circuit.

[0131] 5. Examples of Use Cases

[0132] Reference Figures 24 to 31 Examples of some usage cases (applications) of the display device 1 are described.

[0133] (Application example 1)

[0134] Fig.24 1 is a diagram showing an example of the appearance of the head-mounted display 110. For example, the head-mounted display 110 includes ear hooks 112 worn on the user's head on both sides of a glasses-shaped display unit 111. The technology according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0135] (Application Example 2)

[0136] Fig.25 1 is a diagram showing an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a transmissive head-mounted display including a main body 121, an arm 122, and a lens barrel 123. The head-mounted display 120 is mounted on glasses 128. The main body 121 includes a control panel and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light that displays an image. The arm 122 connects the main body 121 and the lens barrel 123 together and supports the lens barrel 123. The lens barrel 123 projects the image light provided from the main body 121 via the arm 122 toward the eyes of the user via the lens 129 of the glasses 128. The technology according to the above-mentioned embodiment and the like can be applied to such a head-mounted display 120.

[0137] It should be noted that the head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited thereto, and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent reflector. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent reflector are partially transparent. Therefore, light from the surrounding environment reaches the user's eyes.

[0138] (Application example 3)

[0139] Fig.26 and Fig. 27 is a diagram showing an example of the external appearance of the digital camera 130 . Fig.26 shows a front view, Fig. 27 A rear view is shown. The digital camera 130 is a single-lens reflex camera of an interchangeable lens, and includes a camera body (camera body) 131, an imaging lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The imaging lens unit 1312 is an interchangeable lens unit, and is disposed near the approximate center of the front portion of the camera body 311. The grip 133 is disposed on the left side of the front surface of the camera body 311, and the photographer grips the grip 133. The monitor 134 is disposed on the left side of the approximate center of the rear portion of the camera body 131. The electronic viewfinder 135 is disposed on the upper portion of the monitor 14 located behind the camera body 131. By observing the electronic viewfinder 135, the photographer can visually recognize the optical image of the subject guided from the imaging lens unit 132 and determine the composition. The technology according to the above-mentioned embodiment and the like can be applied to the electronic viewfinder 135.

[0140] (Application example 4)

[0141] Fig.28 140 is a diagram showing an example of the appearance of a television device 140. The television device 140 includes a video display screen unit 141 including a front panel 142 and a filter glass 143. The technology according to the above-described embodiments and the like can be applied to the video display screen unit 141.

[0142] (Application Example 5)

[0143] Fig.29 1 is a diagram showing an example of the appearance of the smartphone 150. The smartphone 150 includes a display unit 151 that displays various types of information and an operation unit 152 that includes buttons and the like that receive user's operation input. The technology according to the above-described embodiments and the like can be applied to the display unit 151.

[0144] (Application Example 6)

[0145] Fig.30 and Fig.31 is a diagram showing a configuration example of a vehicle to which the technology of the present disclosure is applied. Fig.30 An example of the interior of a vehicle viewed from the rear of the vehicle is shown, and Fig.31 An example of the vehicle interior viewed from the left rear of the vehicle is shown.

[0146] Fig.30 and Fig.31 The vehicle includes a central display 201 , a console display 202 , a head-up display 203 , a digital rearview mirror 204 , a steering wheel display 205 , and a rear entertainment display 106 .

[0147] The central display 201 is arranged on the instrument panel 261 at a position facing the driver's seat 262 and the passenger seat 263. In the figure, an example of the central display 201 having a horizontally long shape extending from the driver's seat 262 side to the passenger seat 263 side is shown, but the screen size and arrangement position of the central display 201 are not limited thereto. The central display 201 can display information detected by various sensors. As a specific example, the central display 201 can display a captured image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, a body temperature of an occupant detected by an infrared sensor, etc. The central display 201 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, or entertainment-related information.

[0148] Safety related information is information about drowsiness detection, averted gaze detection, detection of pranks of children riding together, whether to wear seat belts, detection of passengers' departure, etc. based on sensor detection results. Operation related information is information about gestures of passengers' operations detected by using sensors. Gestures may include operations on various facilities in the vehicle, such as operations on air conditioning facilities, navigation devices, audio-visual (AV) devices, lighting devices, etc. Life logs include life logs of all residents. For example, a life log includes a record of actions of each occupant. By acquiring and storing life records, the state of the passenger when an accident occurs can be confirmed. Health related information includes information about the body temperature of the passenger detected by using a temperature sensor and the health status of the passenger estimated based on the detected body temperature. Alternatively, information about the health status of the occupant can be estimated based on the face of the occupant imaged by an image sensor. In addition, information about the health status of the occupant can be estimated based on the content of the occupant's answer obtained by having a conversation with the occupant using automatic voice. Authentication / recognition related information includes information about a keyless entry function that performs face authentication by using a sensor, an automatic adjustment function of seat height and position by face recognition, etc. The entertainment-related information includes operation information of the AV device of the occupant detected by the sensor, information on content to be displayed suitable for the occupant detected and identified by the sensor, and the like.

[0149] For example, the console display 202 may be used to display life log information. The console display 202 is arranged near the shift lever 265 in the center console 264 between the driver's seat 262 and the passenger seat 263. The console display 202 may also display information detected by different sensors. In addition, the console display 202 may display an image of the vehicle's periphery captured by an image sensor, or may display an image of the distance to obstacles around the vehicle.

[0150] The head-up display 203 is virtually displayed behind the windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, or entertainment-related information. Because the head-up display 203 is generally virtually set in front of the driver's seat 262, it is suitable for displaying information directly related to the operation on the vehicle, such as the speed of the vehicle, the remaining amount of fuel, and the remaining amount of the battery.

[0151] The digital rearview mirror 204 can display not only the rear of the vehicle but also the status of rear seat passengers, and thus can be used to display life log information of rear seat passengers, for example.

[0152] The steering wheel display 205 is provided near the center of the steering wheel 267 of the vehicle. The steering wheel display 205 may be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, or entertainment-related information. Specifically, the steering wheel display 205 is close to the driver's hand, and therefore, is suitable for displaying life log information such as the driver's body temperature, or is suitable for displaying information about operations on an AV device, an air conditioning device, etc.

[0153] The rear entertainment display 206 is attached to the rear side of the driver's seat 262 and the passenger seat 263, and is used to be viewed by the passengers in the rear seat. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, or entertainment-related information. In particular, since the rear entertainment display 206 is in front of the passengers in the rear seat, information related to the passengers in the rear seat is displayed. The rear entertainment display 206 can display, for example, information about the operation on the AV device or the air conditioning facility, or can display the result of the temperature sensor measuring the body temperature of the passengers in the rear seat, etc.

[0154] The technology according to the above-described embodiments and the like may be applied to the center display 201 , the console display 202 , the head-up display 203 , the digital rearview mirror 204 , the steering wheel display 205 , and the rear entertainment display 206 .

[0155] It should be noted that the effects described in the present disclosure are merely examples and are not limited to the disclosed contents. There may be other effects.

[0156] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the present disclosure. In addition, components of different embodiments and modifications may be appropriately combined.

[0157] It should be noted that the present technology may also have the following configurations.

[0158] (1) A display device comprising:

[0159] A pixel array comprising a plurality of pixels;

[0160] A control unit including a plurality of output terminals for outputting video signals;

[0161] a plurality of selectors disposed between the pixel array and the control unit, each selector electrically connecting or disconnecting a corresponding output terminal of the control unit and a corresponding pixel of the pixel array; and

[0162] A plurality of paths connected to an output terminal corresponding to one end of a corresponding path, wherein

[0163] Multiple paths include:

[0164] a plurality of connection paths connected to selectors corresponding to the other ends of the respective paths; and

[0165] A virtual path that is not connected to the selector corresponding to the other end of the corresponding path.

[0166] (2) The display device according to (1), wherein:

[0167] A virtual path is shorter than a connection path.

[0168] (3) The display device according to (1) or (2), wherein:

[0169] The plurality of paths include a plurality of virtual paths having different lengths from each other.

[0170] (4) The display device according to any one of (1) to (3), wherein:

[0171] The connection path includes a plurality of wirings connected in series between the output terminal and the selector, and

[0172] The virtual path includes a smaller number of wirings than a plurality of wirings of the connection path.

[0173] (5) The display device according to (4), wherein:

[0174] Adjacent wiring vias among the plurality of wirings are connected to each other to extend in different wiring layers.

[0175] (6) The display device according to (4) or (5), wherein:

[0176] The wiring located closest to the selector in the virtual path is shorter than the corresponding wiring of the connection path.

[0177] (7) The display device according to any one of (1) to (6), wherein:

[0178] At least some of the plurality of connection paths include switches connected in series in at least some of the connection paths, and

[0179] At least some of the connection paths are each also virtual paths.

[0180] (8) The display device according to any one of (1) to (7), wherein:

[0181] The virtual path includes switches connected in series in the virtual path.

[0182] (9) The display device according to any one of (1) to (8), wherein:

[0183] The other end of the virtual path is open.

[0184] (10) The display device according to any one of (1) to (9), wherein:

[0185] The other end of the virtual path is grounded via a capacitor.

[0186] (11) An analysis method for a display device,

[0187] The display device comprises:

[0188] A pixel array comprising a plurality of pixels;

[0189] A control unit including a plurality of output terminals for outputting video signals;

[0190] a plurality of selectors disposed between the pixel array and the control unit, each selector electrically connecting or disconnecting a corresponding output terminal of the control unit and a corresponding pixel of the pixel array; and

[0191] a plurality of paths, connected to an output terminal corresponding to one end of a corresponding path,

[0192] Multiple paths include:

[0193] a plurality of connection paths connected to selectors corresponding to the other ends of the respective paths; and

[0194] A virtual path is not connected to the selector corresponding to the other end of the corresponding path.

[0195] Analytical methods include:

[0196] For each of the plurality of paths, assuming that current loads of the corresponding output terminals are equal to each other, outputting a video signal so that a current of a corresponding one output terminal is larger than a current of another output terminal, and measuring a consumption current of the control unit; and

[0197] A defective portion of at least one connection path among the plurality of connection paths is specified based on the result of the measurement.

[0198] (12) The analytical method according to (11), wherein:

[0199] Designations include:

[0200] specifying a connection path with low current consumption based on the measurement result; and

[0201] The disconnected portion of the connection path is specified based on a virtual path having a magnitude of consumption current close to the magnitude of consumption current of the specified connection path.

[0202] Reference Numbers List

[0203] 1 Display device

[0204] 2 Display Panel

[0205] 21 Power Supply

[0206] 3-Pixel Array

[0207] 31 pixels

[0208] 4 Vertical Drivers

[0209] 5 Horizontal drive

[0210] 51 Selector

[0211] 52 Switch

[0212] 6 DDIC (control unit)

[0213] 61 Amplifier

[0214] 62 Output terminals

[0215] P-Path

[0216] CP connection path

[0217] DP Virtual Path

[0218] L Wiring

[0219] SG Pixel signal

[0220] SGL signal cable

[0221] SW switch

[0222] V Via

[0223] WS control signal

[0224] WSL control line.

Claims

1. A display device, comprising: a pixel array comprising a plurality of pixels; A control unit including a plurality of output terminals for outputting video signals; a plurality of selectors disposed between the pixel array and the control unit, each selector electrically connecting or disconnecting a corresponding output terminal of the control unit and a corresponding pixel of the pixel array; as well as A plurality of paths connected to an output terminal corresponding to one end of a corresponding path, wherein The multiple paths include: a plurality of connection paths connected to the selectors corresponding to the other ends of the corresponding paths; and A virtual path is not connected to the selector corresponding to the other end of the corresponding path.

2. The display device according to claim 1, wherein: The virtual path is shorter than the connection path.

3. The display device according to claim 1, wherein: The plurality of paths include a plurality of the virtual paths having different lengths from each other.

4. The display device according to claim 1, wherein: The connection path includes a plurality of wirings connected in series between the output terminal and the selector, and The virtual path includes a smaller number of wirings than the plurality of wirings of the connection path.

5. The display device according to claim 4, wherein: Adjacent wirings among the plurality of wirings are connected to each other via vias to extend in different wiring layers.

6. The display device according to claim 4, wherein: A wiring located closest to the selector in the virtual path is shorter than a corresponding wiring of the connection path.

7. The display device according to claim 1, wherein: At least some of the plurality of connection paths include switches connected in series in the at least some of the connection paths, and The at least some of the connection paths are each also the virtual path.

8. The display device according to claim 1, wherein: The virtual path includes switches connected in series in the virtual path.

9. The display device according to claim 1, wherein: The other end of the virtual path is open.

10. The display device according to claim 1, wherein: The other end of the virtual path is grounded via a capacitor.

11. An analysis method for a display device, The display device comprises: a pixel array comprising a plurality of pixels; A control unit including a plurality of output terminals for outputting video signals; a plurality of selectors disposed between the pixel array and the control unit, each selector electrically connecting or disconnecting a corresponding output terminal of the control unit and a corresponding pixel of the pixel array; as well as a plurality of paths, connected to an output terminal corresponding to one end of a corresponding path, The multiple paths include: a plurality of connection paths connected to selectors corresponding to the other ends of the respective paths; and a virtual path not connected to the selector corresponding to the other end of the corresponding path, The analysis method comprises: For each of the plurality of paths, assuming that current loads of the corresponding output terminals are equal to each other, outputting the video signal so that a current of a corresponding one of the output terminals is larger than a current of another one of the output terminals, and measuring a consumption current of the control unit; and A defective portion of at least one connection path among the plurality of connection paths is specified based on a result of the measurement.

12. The analysis method according to claim 11, wherein Designations include: specifying a connection path with low current consumption based on the measurement result; and The disconnected portion of the connection path is specified based on the virtual path having a magnitude of consumption current close to the magnitude of consumption current of the specified connection path.

Images