Bonding surface verification on dicing tape

Abstract

The disclosed technology relates to a bonding surface for forming and / or verifying an integrated device die mounted on a dicing tape, and a dicing tape therefor. In some embodiments, such methods for forming and validating microelectronic components may include mounting a substrate to a dicing tape; singulating the substrate to form a plurality of dies while the substrate is mounted to a dicing tape; and verifying the bonding surface of at least one die of the plurality of dies while the at least one die is mounted on the dicing tape. In some embodiments, such a dicing tape may include an antistatic adhesive layer disposed on an antistatic base film.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 17 / 744,383, filed on May 13, 2022, the contents of which are incorporated by reference in their entirety. Technical Field

[0003] The following description relates to methods for forming and / or verifying bonding surfaces of integrated device dies mounted on dicing tape, and dicing tapes using the methods. Background Art

[0004] Microelectronic components typically include a thin sheet of semiconductor material (such as silicon or gallium arsenide), commonly referred to as a semiconductor wafer. The wafer can be formed to include multiple integrated chips or dies patterned on the surface of the wafer and / or partially embedded within the wafer. The dies are singulated from the wafer on the dicing tape. In some package designs, the dies are mounted to a substrate or chip carrier, which in turn is mounted on a circuit board (such as a printed circuit board (PCB)). For example, many dies are provided in a package suitable for surface mounting.

[0005] The die or wafers may be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes. This may include stacking one or more layers of die, devices, and / or wafers on a larger base die, device, wafer, substrate, etc., stacking multiple die or wafers in a vertical or horizontal arrangement, and various combinations of the two. The die or wafers may be bonded in a stacked arrangement using a variety of bonding techniques, including direct dielectric bonding, adhesive-free techniques such as ) or hybrid technologies (such as ), both of which can be implemented by Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), an Xperi company (see, for example, U.S. Patent Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entireties). Summary of the invention

[0006] Representative techniques and apparatus are disclosed, including process steps for forming novel microelectronic assemblies. The process includes preparing microelectronic components (such as dies, wafers, substrates, etc.) for bonding. In various implementations, one or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components can be stacked and bonded without adhesive at the prepared bonding surfaces.

[0007] When performing hybrid bonding techniques, the bonding surface prepared for hybrid bonding is usually verified / validated by measuring the grooves of the contact pads (e.g., copper pads). In some embodiments, the verification step may also include comparing the groove measurement results with predetermined or expected measurement results. In other embodiments, the verification step may include measuring and confirming the dielectric roughness and / or dielectric rounding of the bonding surface. A reliable method for measuring pad grooves is atomic force microscopy (AFM). An example sample preparation process for AFM may, for example, involve: 1) coating the relevant substrate with a protective layer, 2) mounting the coated substrate on a dicing tape, wherein the device surface coated with the protective layer faces upward, 3) singulating the coated substrate into tube cores on the dicing tape, 4) when the tube core is mounted on the tape, processing the tube cores to be singulated to remove the protective layer and the unwanted fragments or particles from the singulation step. The tube core processing step may also include preparing the bonding surface of the tube core for direct bonding. Then a plurality of tube cores between the center and the edge of the cleaned singulated substrate can be removed or picked up. Then, the AFM can measure the grooves of the relevant conductive features / pads of the removed / picked-up die to determine that the groove variation between the die from the center of the substrate and the die from the edge of the substrate is within a specific groove range. The removed / picked-up die is usually discarded and not returned to the cutting frame, thereby avoiding the formation of unwanted defects in the remaining prepared die on the frame. Therefore, when the die is in the cutting frame, a field or assembly line method for measuring the grooves of the die is required. Its main advantage is that the die (especially the known good die verified by the AFM measurement results) will not be discarded after determining the grooves of the conductive pads. As used herein, the term "verified die" refers to a die in which the contact pad grooves, dielectric roughness, dielectric rounding and / or other properties of the bonding surface have been measured / confirmed and / or compared with expected values, and the term "verified microelectronic assembly" refers to a microelectronic assembly in which the contact pad grooves, dielectric roughness, dielectric rounding and / or other properties of the bonding surface have been measured / confirmed and / or compared with expected values. As used herein, the terms "verified / known good die," "known good die as verified by AFM measurements," and "verified good die" refer to a die that has been tested / measured and is known or has been verified to function properly (e.g., function within certain expected operating parameters, such as utilizing predetermined or desired contact pad recesses, dielectric roughness, and / or dielectric rounding of the bonding surface).

[0008] In addition, picking up or removing the die from the cut wafer on the dicing tape frame before the die is moved to the AFM stage (i.e., the die ejection process) is full of another challenge. The die ejection process generates electrostatic charge, which can damage the charged (surface with mixed bonding preparation) if it is not correctly dissipated. If a non-conductive dicing tape is used, it may be difficult to remove the electrostatic charge accumulated in the die removal step. Some existing dicing tapes include antistatic / conductive layers, but the antistatic / conductive layers are very thin and may not effectively remove the electrostatic charge for the reasons discussed above. Electrostatic charging / discharging (ESD) may also occur during AFM operation and cause problems (such as making AFM measurements inaccurate). Therefore, it is necessary to develop technologies for dissipating electrostatic charge in the process involving die verification, and these technologies will become more important as chips become smaller and more easily damaged by discharged electrostatic fields.

[0009] In some aspects, a method of forming and verifying a microelectronic assembly is disclosed. The method may include: mounting a substrate to an antistatic dicing tape; singulating the substrate to form a plurality of dies while the substrate is mounted to the antistatic dicing tape; and verifying a bonding surface of at least one of the plurality of dies while the at least one die is mounted to the antistatic dicing tape. In some embodiments, the method may further include: planarizing the substrate before mounting the substrate to the antistatic dicing tape. In some embodiments, the method may further include: preparing the bonding surfaces of the plurality of dies while the plurality of dies are mounted to the antistatic dicing tape, including activating the bonding surfaces of the plurality of dies. In some embodiments, singulating the substrate includes partially cutting through a conductive region of the antistatic dicing tape. In some embodiments, the method may further include: electrically grounding the antistatic dicing tape during verification of the bonding surface of the at least one die. In some embodiments, verifying the bonding surface of the at least one die includes measuring a conductive pad recess of the bonding surface of the at least one die by a metrology device. In some embodiments, the metrology device is an atomic force microscope (AFM) device. In some embodiments, verifying the bonding surface of the at least one die includes measuring a surface roughness of the bonding surface of the at least one die by a metrology device. In some embodiments, the metrology device is an atomic force microscope (AFM) device. In some embodiments, the method may further include: picking up at least one tube core from the antistatic cutting tape, and directly bonding at least one tube core to the component without an intermediate adhesive after verifying at least one tube core. In some embodiments, the method may further include: when picking up at least one tube core from the antistatic cutting tape, electrically grounding the antistatic cutting tape. In some embodiments, directly bonding at least one tube core to the component forms a conductor-to-conductor direct bond and a dielectric-to-dielectric direct bond. In some embodiments, the method may further include: after the substrate has been singulated, removing a protective layer from the bonding surface of multiple tube cores. In some embodiments, the antistatic cutting sheet or cutting tape includes an ultraviolet (UV) sensitive or pressure sensitive adhesive layer. In some embodiments, the substrate includes an active circuit device.

[0010] In some aspects, a dicing tape is disclosed that includes an antistatic adhesive layer disposed on an antistatic base film. In some embodiments, the dicing tape can have an electrostatic discharge of less than 0.1 C / cm. In some embodiments, the dicing tape can have an electrostatic discharge of less than 10 9Ω resistance. In some embodiments, the antistatic base film includes conductive carbon. In some embodiments, the antistatic base film includes a material that does not absorb UV light. In some embodiments, the antistatic adhesive layer is configured for light-activated peeling. In some embodiments, the antistatic adhesive layer includes a photoinitiator that produces an active substance after exposure to UV light. In some embodiments, the antistatic adhesive layer includes a monomer or oligomer that polymerizes in the presence of an active substance to reduce the bonding strength. In some embodiments, the antistatic adhesive layer is pressure sensitive. In some embodiments, the thickness of the antistatic adhesive layer is greater than 10μm. In some embodiments, the antistatic adhesive layer includes conductive carbon or silicon dioxide. In some embodiments, the conductive carbon is less than 30% of the weight of the antistatic adhesive layer.

[0011] In some aspects, a method of forming a microelectronic assembly is disclosed. In some embodiments, the method may include: mounting a substrate to an antistatic dicing tape, the antistatic dicing tape including an antistatic adhesive layer; and singulating through the substrate and partially through the antistatic adhesive layer to form a plurality of dies. In some embodiments, the method may also include: planarizing the substrate before mounting the substrate to the antistatic dicing tape. In some embodiments, the method may also include: preparing the bonding surfaces of the plurality of dies when the plurality of dies are mounted to the antistatic dicing tape, including activating the bonding surfaces of the plurality of dies. In some embodiments, the method may also include: picking up at least one die from the antistatic dicing tape and directly bonding the at least one die to the component without an intermediate adhesive. In some embodiments, the antistatic dicing sheet or dicing tape includes an ultraviolet (UV) sensitive or pressure sensitive adhesive layer.

[0012] In some aspects, a method of forming and verifying a microelectronic assembly is disclosed. In some embodiments, the method may include: mounting a substrate to a dicing tape; singulating the substrate to form a plurality of dies while the substrate is mounted to the dicing tape; and verifying a bonding surface of at least one of the plurality of dies while the at least one die is mounted to the dicing tape. In some embodiments, the method may further include: preparing the bonding surfaces of the plurality of dies while the plurality of dies are mounted to the dicing tape, including activating the bonding surfaces of the plurality of dies. In some embodiments, singulating the substrate includes partially cutting through a conductive region of the dicing tape. In some embodiments, the method may further include: electrically grounding the dicing tape during verification of the bonding surface of the at least one die. In some embodiments, verifying the bonding surface of the at least one die includes measuring a conductive pad recess of the bonding surface of the at least one die by a metrology device. In some embodiments, verifying the bonding surface of the at least one die includes measuring a surface roughness of the bonding surface of the at least one die by a metrology device.

[0013] In some aspects, a dicing tape is disclosed that includes an antistatic adhesive layer disposed on an isolation base film, wherein the thickness of the antistatic adhesive layer is greater than 10 μm. In some embodiments, the thickness of the antistatic adhesive layer is greater than 15, 20, 25, 30, 35, 40, 45, or 50 μm. In some embodiments, the thickness of the antistatic adhesive layer is between 10 and 15, 15 and 20, 20 and 25, 25 and 30, 30 and 35, 35 and 40, 40 and 45, or 45 and 50 μm. In some embodiments, the antistatic adhesive layer has an electrostatic discharge of less than 0.1 C / cm. In some embodiments, the antistatic adhesive layer has an electrostatic discharge of less than 10 9 Ω resistance. In some embodiments, the isolation base film includes polyethylene terephthalate (PET). In some embodiments, the isolation base film includes a material that does not absorb UV light. In some embodiments, the antistatic adhesive layer is configured for light-activated peeling. In some embodiments, the antistatic adhesive layer includes a photoinitiator that produces an active substance after exposure to UV light. In some embodiments, the antistatic adhesive layer includes a monomer or oligomer that polymerizes in the presence of an active substance to reduce the bonding strength. In some embodiments, the antistatic adhesive layer is pressure sensitive. In some embodiments, the antistatic adhesive layer includes conductive carbon or silicon dioxide. In some embodiments, the conductive carbon is less than 30% of the weight of the antistatic adhesive layer.

[0014] In some aspects, a method of forming and verifying a microelectronic assembly is disclosed. In some embodiments, the method may include: applying a protective layer on a bonding surface of a substrate; mounting the substrate to a dicing tape; singulating the substrate to form a plurality of dies while the substrate is mounted to the dicing tape; cleaning the protective layer from surfaces of the singulated dies while the singulated dies are mounted to the dicing tape; and verifying a bonding surface of at least one die of the plurality of dies while at least one die is mounted to the dicing tape. In some embodiments, the method may also include: directly bonding one of the plurality of dies to another substrate.

[0015] In some aspects, a method of verifying and forming a microelectronic assembly is disclosed. In some embodiments, the method may include: mounting a substrate to a dicing tape; singulating the substrate to form a plurality of dies while the substrate is mounted to the dicing tape; verifying a bonding surface of at least one die of the plurality of dies while at least one die is mounted to the dicing tape; and directly bonding a verified good die of the plurality of dies from the dicing tape to a prepared surface of another substrate. In some embodiments, the method may also include: rinsing and drying a dicing frame for holding the dicing tape after the verification step. In some embodiments, the dicing tape includes an antistatic layer. In some embodiments, verification includes using a contact or non-contact metrology device.

[0016] In some aspects, a method of forming a microelectronic assembly is disclosed. In some embodiments, the method may include: verifying a first bonding surface of the first substrate and a second bonding surface of the second substrate while at least one of the first substrate and the second substrate is mounted to a dicing tape, the first bonding surface and the second bonding surface having a conductive portion surrounded by a non-conductive portion; preparing the first bonding surface of the first substrate and the second bonding surface of the second substrate; rinsing and drying the prepared first bonding surface and the second bonding surface; and directly bonding the prepared first bonding surface to the prepared second bonding surface without an intermediate adhesive, wherein preparing the first bonding surface and the second bonding surface includes exposing at least one of the first bonding surface and the second bonding surface to a plasma. In some embodiments, the verification includes using a contact or non-contact metrology device. In some embodiments, the method may also include singulating the directly bonded microelectronic assembly.

[0017] Various implementation methods and arrangements are discussed with reference to electrical and electronic components and different carriers. When referring to specific components (i.e., tube core, wafer, integrated circuit (IC) chip tube core, substrate, etc.), it is not intended to be restrictive, and is used to simplify the discussion and facilitate illustration. The techniques and equipment discussed with reference to wafers, tube cores, substrates, etc. are applicable to any type or number of electrical components, circuits (e.g., integrated circuits (ICs), hybrid circuits, ASICs, memory devices, processors, etc.), component groups, packaged components, structures (e.g., wafers, sheets, boards, PCBs, etc.), etc., which can be coupled to interfaces with each other through external circuits, systems, carriers, etc. Each of these different components, circuits, groups, packages, structures, etc. can be generally referred to as "microelectronic components". For simplicity, unless otherwise specified, a component that is coupled to another component is referred to as a "tube core" herein, and other components to which the tube core is coupled are referred to as "substrates" herein.

[0018] The implementation method will be explained in more detail below using multiple examples.Although various implementation methods and examples are discussed here and below, other implementation methods and examples may be possible by combining features and elements of individual implementation methods and examples. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The detailed description is explained with reference to the accompanying drawings. The same reference numerals are used in different pictures to indicate similar or equivalent items. For this discussion, the devices and systems illustrated in the pictures are shown as having a diversity of components. As discussed herein, various implementations of devices and / or systems may include fewer components and still be within the scope of the present disclosure. Alternatively, other implementations of devices and / or systems may include additional components or various combinations of the components described and still be within the scope of the present disclosure.

[0020] Figure 1 A conventional antistatic ultraviolet (UV) release dicing tape film is illustrated.

[0021] FIG. 2A to FIG. 2B An antistatic cutting sheet according to some embodiments of the presently disclosed technology is illustrated.

[0022] Figure 3-1 to Figure 3-7 A method of using an antistatic cutting blade in hybrid bonding according to some embodiments of the disclosed technology is illustrated.

[0023] Figure 4 A cross-sectional view of a top layer of a hybrid bonded structure is shown.

[0024] FIG. 5A to FIG. 5D Shown is the effect of electrostatic charge on copper pad recess depth measurement.

[0025] FIG. 6A to FIG. 6B The effect of electrostatic charge on dielectric roughness measurement is shown. DETAILED DESCRIPTION

[0026] Overview

[0027] In some embodiments, the die can be prepared for bonding to a component (e.g., a chip or carrier) by a direct bonding method without an intermediate adhesive, such as the hybrid direct bonding process described below and commercially available from Xperi, Inc. of San Jose, Calif. For example, the direct bonding process may include a room temperature, atmospheric pressure direct bonding configuration. and / or Process or for low temperature mixing configuration Ultra process, which is commercially available from Xperi, Inc. of San Jose, California. Direct bonding can be between the dielectric materials of the bonded components and can also include conductive materials (e.g., copper) for direct hybrid bonding at or near the bonding interface. The conductive material at the bonding interface can be a bonding pad and / or a passive electronic component, wherein the bonding pad is formed in or on a redistribution layer (RDL) above the die. In other embodiments, the conductive material can include the contact surface of a TSV (through substrate via or electrode).

[0028] When performing a hybrid bonding method, the surface prepared for hybrid bonding is usually verified before bonding. The surface preparation process may, for example, include: 1) coating the relevant substrate with a protective layer, 2) mounting the coated substrate on a dicing tape with the device surface facing up, 3) singulating the coated substrate on the dicing tape, 4) processing the singulated substrate to remove the protective layer and unwanted fragments or particles from the singulation step when the die is mounted on the dicing tape. In some embodiments, the die surface preparation step may also include exposing the cleaned surface of the singulated die to a plasma environment (e.g., exposed to oxygen plasma or nitrogen plasma or both). The surface after plasma exposure may be cleaned and dried. The cleaning step may include rinsing a frame with a die (e.g., using deionized (DI) water) and drying the cleaned frame and the mounted die by spin drying or other known drying methods. The grooves of the conductive features or the relevant pads may be measured by an atomic force microscope (AFM) to determine that the groove deformation between the die near the center of the substrate and the die near the edge of the substrate is within a specific groove range.

[0029] The pad recess may be the distance from the top of the non-conductive bonding layer to the top of the copper pad. Figure 4 is a cross-sectional view of a hybrid bonding structure, illustrating an example of a pad recess. Figure 4In the hybrid bonding structure 400, a non-conductive bonding layer (e.g., silicon oxide) 410 is provided with a non-conductive bonding layer surface 410A. A metal pad (e.g., copper) 430 is provided with a bonding surface 430A, and a groove 420 is the depth of a step between the non-conductive layer bonding surface 410A and the bonding surface 430A. A non-conductive bonding layer 410 and a metal pad can be formed on a bulk semiconductor portion (e.g., silicon) 450, which is patterned using a circuit device. In some embodiments, one or more back-end process (BEOL) layers or redistribution layers can be formed between the semiconductor portion 450 and the non-conductive bonding layer 410. Other parameters (such as dielectric rounding) can also be measured before direct bonding. In some embodiments, an atomic force microscope (AFM) can be used to measure pad groove depth, dielectric roughness, and / or dielectric rounding. Some existing workflows for confirming copper grooves can include: after a wafer bonded to a dicing tape frame has been singulated into individual dies, the die is manually removed from the dicing tape frame, and then the die is placed on the stage of the AFM. After AFM, it is difficult to place the die in the exact same position and orientation as it was initially on the dicing tape. During the pick-up and placement steps of the die-to-wafer (D2W) combination, the orientation and slight changes in the orientation of the die may cause other problems in the process flow. Because of this challenge, the die used in the AFM is usually not put back on the dicing tape and the die can be used for the remainder of the mixed combination process flow. Therefore, the existing workflow may not be effective and may cause the loss of available die and material. The measured die will usually be discarded and will not return to the cutting frame, thereby avoiding the unwanted shortcomings of the prepared die on the dicing tape.

[0030] The reduction of the number of steps in the workflow can improve efficiency, for example by placing an array of singulated die on an AFM stage together with a dicing tape frame. Then AFM measurements can be performed directly on the die placed on the dicing tape. However, common dicing tapes are non-conductive. If the dicing tape is non-conductive or does not contain metal, static charge may increase on or around the die or dicing tape due to small mechanical vibrations or other interactions between the die and the tape. When the die is on the dicing tape during the AFM measurement, the static charge in the die may affect the interaction between the AFM tip and the die sample, making the AFM measurement inaccurate.

[0031] FIG. 5A to FIG. 5D An example of the effect of electrostatic charge on copper pad recess depth measurement is shown in FIG. Figure 5A A die with a background of non-conductive areas (dark areas) and conductive areas (white areas) measured directly on a non-conductive tape is shown. The results of the measurement are affected by charging effects; Figure 5BThe corresponding measurement results shown in are that the copper pad appears and protrudes above the non-conductive background layer by 13.6 nm. Figure 5C shows the same die measured outside the tape and therefore not affected by charging effects; Figure 5D The corresponding measurement result shown in is a copper pad depression of 7.0 nm, which represents the true value. Figure 5B and Figure 5D Compared to the results shown in , the groove measurement differs by a factor of three due to the effect of electrostatic charge. This measurement error is unacceptable because it leads to the erroneous conclusion that the conductive pad protrudes relative to the surrounding non-conductive layer.

[0032] FIG. 6A to FIG. 6B An example of the effect of electrostatic charge on SiO2 dielectric roughness measurement is shown in FIG. Fig. 6A A die measured directly on a non-conductive tape and subjected to charging effects is shown; the measured root mean square roughness is 0.092 nm. Figure 6B The same die is shown measured outside the tape, which is therefore not affected by charging effects; the measured root mean square roughness is 0.196nm. Fig. 6A and Figure 6B Compared to the results shown in , the dielectric roughness measurement differs by a factor of two due to the effect of electrostatic charge.

[0033] Furthermore, the rapid discharge of the accumulated static charge can damage the die. The smaller the die, the more severe the static charge problem is, since relatively more tape is exposed relative to the size of the die. Furthermore, the tolerance and error margin for the discharge current is smaller for smaller dies. For 1mm x 1mm or 0.25mm x 0.25mm dies, the problem can be severe.

[0034] Various embodiments disclosed herein enable the use of a simplified assembly line process by verifying the bonding surface of one or more dies directly on the dicing tape. In various embodiments, the dicing tape may include at least a conductive portion so that electrostatic charge can be properly dissipated. In some embodiments, the disclosed embodiments relate to die processing and bonding surface verification on an at least partially conductive dicing frame tape. In particular, the disclosed technology relates to the use of at least partially conductive dicing tape during the singulation of dies and the preparation of dies for hybrid direct bonding. The ability of the disclosed technology to perform reliable bonding surface characterization directly on the tape frame can streamline the quality control process. In addition, avoiding ESD events by conductive tape in the disclosed technology can contribute to higher product yields and reduce damage to the dies.

[0035] Sample Cutting Tape

[0036] Standard dicing tape is non-conductive and is typically made of polyvinyl chloride (PVC), polyolefin, or polyethylene with an adhesive to bond the die in place. Standard dicing tape may use a UV or thermal release mechanism. Standard dicing tape may be approximately 100 μm thick.

[0037] Figure 1 A conventional antistatic UV release dicing tape film is illustrated. After UV exposure, the adhesive strength of the acrylic adhesive with light-activated components is reduced by 85-90%, making the removal of the film easier. The dicing tape film includes: a base film 101 including a non-conductive material, an antistatic layer 103, an adhesive layer 105, and a backing film 107. The antistatic layer 103 may include conductive carbon and / or fillers or nanoparticles (such as silicon dioxide). The antistatic layer 103 is very thin (e.g., less than about 5 μm thick). After removing the backing film 107, the wafer can contact the adhesive layer 105 and be bonded to the tape. In order to singulate the die from the wafer, the user will cut through the wafer, the adhesive layer 105, the antistatic layer 103 and partially into the base film 101 by a certain amount to keep the base film 101 partially connected, thereby keeping the die together for processing purposes.

[0038] FIG. 2A to FIG. 2B The antistatic cutting tape or cutting sheet according to various embodiments disclosed herein is illustrated. In the illustrated embodiment, FIG. 2A to FIG. 2B The at least partially conductive dicing tape shown in can be peeled off using UV exposure or applied pressure. FIG. 2A to FIG. 2B In the embodiment shown in , the entire antistatic / conductive area is thicker than the depth that the dicing process cuts into the dicing tape, thereby avoiding electrical isolation.

[0039] Figure 2AA portion of an antistatic tape 200A is illustrated, comprising two antistatic layers, an antistatic light activated (e.g., UV sensitive) adhesive 203A (which may include, for example, a methacrylate polymer), and a base film formed by an antistatic material 201A, which together form an entire antistatic / conductive tape. In some embodiments, conductive carbon and / or silicon dioxide and / or silicon may be added to the base film 201A and / or to the adhesive 203A. In some embodiments, the tape includes a material that is transparent to UV light in the antistatic base film 201A. In some embodiments, the antistatic base film 201A includes a material that does not absorb UV light. In some examples, the adhesive 203A may have a thickness greater than 10 μm. In other examples, the adhesive 203A may have a thickness greater than 15, 20, 25, 30, 35, 40, 45, or 50 μm. In other examples, adhesive 203A may have a thickness between 10 and 15, 15 and 20, 20 and 25, 25 and 30, 30 and 35, 35 and 40, 40 and 45, or 45 and 50 μm. In some examples, base film 201A may have a thickness greater than 20, 30, 40, 50, 60, 70, 80, 90, or 100 μm. In other examples, base film 201A may have a thickness between 20 and 30, 30 and 40, 40 and 50, 50 and 60, 60 and 70, 70 and 80, 80 and 90, or 90 and 100 μm.

[0040] Figure 2B A portion of an antistatic tape 200B is illustrated, comprising a single antistatic layer of an antistatic light activated adhesive 203B (which may comprise, for example, a methacrylate polymer) on an isolating base film 201B. In an embodiment, the isolating base film 201B comprises a polymer such as polyethylene terephthalate (PET). Figure 2BIn some embodiments, the entire antistatic / conductive area includes only the antistatic light-activated adhesive layer 203B. In some embodiments, the tape includes a material that is transparent to UV light in the isolation base film 201B. In some embodiments, the isolation base film 201B includes a material that does not absorb UV light. In some examples, the adhesive 203B may have a thickness greater than 10 μm. In other examples, the adhesive 203B may have a thickness greater than 15, 20, 25, 30, 35, 40, 45, or 50 μm. In other examples, the adhesive 203B may have a thickness between 10 to 15, 15 to 20, 20 to 25, 25 to 30, 30 to 35, 35 to 40, 40 to 45, or 45 to 50 μm. In some embodiments, the base film 201B may have a thickness greater than 20, 30, 40, 50, 60, 70, 80, 90, or 100 μm. In other examples, the base film 201B may have a thickness between 20 to 30, 30 to 40, 40 to 50, 50 to 60, 60 to 70, 70 to 80, 80 to 90, or 90 to 100 μm.

[0041] exist FIG. 2A to FIG. 2B In the embodiment shown in , the adhesive layer 203A or 203B of the tape is greater than 10 μm thick. In other examples, the adhesive layer 203A or 203B can have a thickness greater than 15, 20, 25, 30, 35, 40, 45, or 50 μm. In other examples, the adhesive layer 203A or 203B can have a thickness between 10 to 15, 15 to 20, 20 to 25, 25 to 30, 30 to 35, 35 to 40, 40 to 45, or 45 to 50 μm. In some embodiments, the adhesive layer of the tape can include conductive carbon or silicon dioxide in a pressure sensitive adhesive with a light activated component. In some embodiments, the tape can be conductive enough to discharge static charges, for example, the tape can have an electrostatic discharge of less than 0.1 C / cm or have an electrostatic discharge of less than 10 6 Up to 10 9 In some embodiments, the composition of the conductive carbon used in the antistatic layer is less than 30% by weight, and preferably between 0.1 and 30% by weight. In some embodiments, the tape does not shield against UV light.

[0042] exist FIG. 2A to FIG. 2BIn the embodiment shown in , the adhesive layers 203A, 203B of the tape can allow for light-activated peeling. For example, the adhesive layers 203A, 203B of the tape can include a photoinitiator that absorbs UV light and produces an active substance after exposure to UV light, and a monomer / oligomer that polymerizes in the presence of the active substance to reduce the adhesive strength. In some examples, the photoinitiator can be an azo initiator (such as 2,2'azobis(isobutyronitrile)). In some examples, the monomer can be an acrylic monomer (such as ethyl 2-ethylacrylate, butyl acrylate, or ethyl 2-hydroxyacrylate).

[0043] Additional components of dicing tapes, such as fillers, crosslinking agents, and antistatic agents, can be found in U.S. Pat. No. 10,975,274, which is incorporated herein by reference in its entirety. Other examples of resins and conductive particles that can be used in antistatic layers can be found in U.S. Pat. Nos. 9,484,240; 11,066,577; 5,508,107; 6,224,975, which are incorporated herein by reference in their entirety.

[0044] Example method combining surface verification

[0045] Figure 3-1 to Figure 3-6 A method of using an antistatic dicing sheet in preparation for hybrid bonding according to some embodiments is illustrated. To verify the surface prepared for hybrid bonding, surface characterization (e.g., using AFM) can be performed directly on one or more dies attached to the conductive dicing tape frame, thus streamlining the quality control process.

[0046] This method can be Figure 3-1 Starting at the step shown in , the wafer / substrate 320 is attached to the antistatic dicing tape 310 with the protective layer 330 facing upward. The antistatic dicing tape 310 can be held by a dicing frame (not shown) in various embodiments. In some embodiments, Figure 3-1 to Figure 3-6 The dicing tape 310 shown in FIG. 3 may include Figure 2A Dicing tape 200A or Figure 2B The dicing tape 200B shown in FIG. Figure 3-1 The substrate 320 shown in FIG. 1 may include a planarized bonding surface over a semiconductor device portion, as described herein with respect to FIG. Figure 4 As shown and described. Protective layer 330 may include a polymer (such as photoresist) that protects the bonding surface during dicing.

[0047] The method can then be moved to Figure 3-2, singulates substrate 320 on antistatic dicing tape 310. Substrate 320 may be singulated or diced in any suitable manner (e.g., by sawing, etching, etc.). In some embodiments, the wafer is only partially diced through the conductive areas of the tape (e.g., Figure 2A The entire tape is 200A or Figure 2B As discussed later, when the tape is electrically grounded, because the tape is only partially sheared through the conductive area, the tape can still be electrically connected for discharge.

[0048] The method can then move to Figure 3-3 In the steps shown in , the protective layer 330 is peeled off from the diced wafer 320 on the antistatic dicing tape 310. The protective layer 330 can be removed in any suitable manner, such as by exposing the protective layer 330 to oxygen plasma and cleaning the debris with deionized water and / or other processing liquids.

[0049] The method can then move to Figure 3-4 The steps shown in the figure prepare (e.g., clean and activate) the hybrid bonding surface of the singulated tube die 340 attached to the antistatic dicing tape 310. For example, in some embodiments, the tube die 340 that is singulated can be exposed to a nitrogen-containing plasma to activate the bonding surface. In some embodiments, the tube die surface preparation step can also include exposing the cleaned surface of the tube die that is singulated to a plasma environment (e.g., oxygen plasma or nitrogen plasma or both). The surface after plasma exposure can be cleaned and dried. The cleaning step can include rinsing the structure with the tube die (e.g., using deionized (DI) water), and drying the cleaned frame and the installed tube die by spin drying or other known drying methods. The grooves of the conductive features or related pads can be measured by AFM to determine that the groove changes between the tube die near the center of the substrate and the tube die near the edge of the substrate are within a specific groove range.

[0050] After the hybrid binding surface has been prepared as explained above, the method can move to Figure 3-5 In the steps shown in , the prepared hybrid bonding surface of the singulated die 340 is verified or validated (e.g., using AFM) while the die is placed on the antistatic dicing tape 310. The frame with the antistatic dicing tape 310 is placed over the surface of a flat porous vacuum chuck (not shown). A vacuum is applied to secure the antistatic dicing tape 310 to the surface of the vacuum chuck. In some preferred embodiments, the width or diameter of the holes of the porous chuck can be less than the thickness of the antistatic dicing tape 310. As explained herein, the AFM process can verify the pad groove depth and / or other features of the bonding surface (such as the amount of dielectric roughness and rounding). In Figure 3-5In the steps shown in , the tape can be electrically grounded to provide a discharge path for static charges. Figure 2A Tape 200A or Figure 2B The antistatic adhesive layer 203B) is only partially sheared, so the conductive layers 200A and 203B remain electrically connected, thereby discharging the entire chip. In some cases, the step of removing the protective layer 330 from the cut wafer 320 and other surface preparation steps can change the copper grooves of the tube core. Therefore, if performed after wafer cutting, removing the protective layer and various surface preparation steps, the hybrid bonding surface inspection / verification can be more accurate.

[0051] In some embodiments, after verifying or validating the prepared hybrid bonding surface of the singulated die 340 when the die is placed on the antistatic dicing tape 310, the method can then move to the step of bonding the verified / known good die directly from the dicing tape to the prepared surface of another substrate. Alternatively, the method can move to Figure 3-6 and Figure 3-7 In the steps shown in , the singulated die 347 is picked up from the tape and the prepared hybrid bonding surface of the singulated die 347 is hybrid bonded with the component 349 to form the direct bonding structure 343, while the remaining portion of the singulated die 340 is mounted to the antistatic dicing tape 310. In some embodiments, picking up the die 347 may include: contacting the bonding surface of the die 347 with a pick and place tool formed of or coated with a hydrophobic material. In some embodiments, the hybrid bonding surface inspection / verification step may be performed just before hybrid bonding the die 347 with the component 349, with no intermediate steps in between. In Figure 3-6 In the steps shown in , the tape 310 can be electrically grounded to provide a discharge path for static charges. In some embodiments, a stylus with a preferably low force (e.g., less than 20 mg, less than 10 mg, or less than 5 mg) can be scanned across the surface of the prepared die to characterize the surface of the die. The tip of a mechanical profiler for the die can be configured so that it does not introduce undesirable defects (e.g., scratches or multiple scratches) on the non-conductive and / or conductive portions of the prepared surface of the die or multiple dies. In other embodiments, a non-contact device (e.g., an optical profiler) can be applied to authenticate or verify the surface of the die.

[0052] In some embodiments, the verified die on the cutting frame can be rinsed with a suitable solvent or DI water or both and dried to clean any contaminant particles from the groove verification step. The directly bonded die and substrate are annealed at high temperature to electrically contact and mechanically contact the relative corresponding pads on the bonding surface of the die and substrate. The annealing temperature can range between 150 and 400°C and depending on the width and depth of the conductive features, the annealing time can vary from 15 minutes to more than 6 hours. In practice, the smaller the groove, the shorter the annealing time; the smaller the width of the conductive feature, the higher the bonding temperature.

[0053] From the foregoing, smaller recesses (e.g., less than 12 nm) may be preferred over larger recesses (e.g., greater than 25 nm). The verification step may accordingly be an important tool in process control for confirming good device cleaning and preparation steps and for selecting appropriate annealing conditions for post-bonding the die to the substrate.

[0054] Additional details regarding handling equipment on a cutting frame may be found in US Pat. Nos. 10,727,219 and 11,037,919, the disclosures of which are incorporated herein by reference.

[0055] Electronic components

[0056] A die may refer to any type of integrated device die. For example, an integrated device die may include an electronic component such as an integrated circuit (such as a processor die, a controller die, or a memory die), a microelectromechanical system (MEMS) die, an optical device, or any other suitable type of device die. In some embodiments, the electronic component may include a passive device (such as a capacitor, an inductor, or other surface mounted device). In various embodiments, a circuit device (such as an active component (e.g., a transistor)) may be patterned at or near the active surface of the die. The active surface may be on one side of the die, which is opposite to the back side of the die. The back side may or may not include any active circuit device or passive device.

[0057] The integrated device die may include a bonding surface and a back surface opposite the bonding surface. The bonding surface may have a plurality of conductive bonding pads including a conductive bonding pad and a non-conductive material proximate to the conductive bonding pads. In some embodiments, the conductive bonding pads of the integrated device die may be directly bonded to corresponding conductive pads of a substrate or wafer without an intermediate adhesive, and the non-conductive material of the integrated device die may be directly bonded to a portion of a corresponding non-conductive material of a substrate or wafer without an intermediate adhesive. Direct bonding without an adhesive is described throughout U.S. Patent Application Nos. 7,126,212; 8,153,505; 7,622,324; 7,602,070; 8,163,373; 8,389,378; 7,485,968; 8,735,219; 9,385,024; 9,391,143; 9,431,368; 9,953,941; 9,716,033; 9,852,988; 10,032,068; 10,204,893; 10,434,749; and 10,446,532, the contents of each of which are hereby incorporated by reference in their entirety and for all purposes.

[0058] Examples of direct binding methods and direct binding structures

[0059] Various embodiments disclosed herein relate to direct bonding structures in which two elements can be directly bonded to each other without an intermediate adhesive. Two or more electronic components that may be semiconductor elements (such as integrated device dies, wafers, etc.) may be stacked on one another or bonded to each other to form a bonding structure. A conductive contact pad of one element may be electrically connected to a corresponding conductive contact pad of another element. Any suitable number of elements may be stacked in the bonding structure. The contact pad may include a metal pad formed in a non-conductive bonding region, and the metal pad may be connected to a bottom metallization (such as a redistribution layer (RDL)).

[0060] In some embodiments, an element is directly bonded to another element without an adhesive. In various embodiments, a non-conductive material or dielectric material of a first element can be directly bonded to a corresponding non-conductive or dielectric field of a second element without an adhesive. The non-conductive material can be referred to as a non-conductive bonding area or bonding layer of the first element. In some embodiments, a dielectric-to-dielectric bonding technique can be used to directly bond the non-conductive material of a first element to a corresponding non-conductive material of a second element. For example, a dielectric-to-dielectric bonding technique disclosed at least in U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749 can be used to form a dielectric-to-dielectric bond without an adhesive, wherein the entire contents of each patent are incorporated herein by reference and for all purposes. Suitable dielectric materials for direct bonding include dielectric materials that do not include polymer materials (such as epoxy resins, resins, or molding materials); for example, suitable dielectric materials may include inorganic dielectrics (such as silicon oxide, silicon nitride, or silicon oxynitride) or may include carbon (such as silicon carbide, silicon carbon oxynitride, silicon carbonitride, or diamond-like carbon).

[0061] In various embodiments, because the dielectric bonding surface can be polished to a high smoothness, hybrid direct bonding can be formed without an intermediate adhesive. The bonding surface can be cleaned and exposed to plasma and / or etchant to activate the surface. In some embodiments, the surface can be terminated with a substance after activation or during activation (e.g., during a plasma and / or etching process). Without being limited by theory, in some embodiments, an activation process can be performed to break chemical bonds at the bonding surface, and the termination process can provide additional chemicals at the bonding surface that improve the bonding energy during direct bonding. In some embodiments, activation and termination are provided in the same step (e.g., plasma or wet etchant) to activate and terminate the surface. In other embodiments, the bonding surface can be terminated in a separate process to provide additional substances for direct bonding. In various embodiments, the termination substance can include nitrogen. In addition, in some embodiments, the bonding surface can be exposed to fluorine. For example, one or more fluorine peaks can exist near the layer and / or bonding interface. Therefore, in a direct bonding structure, the bonding interface between two dielectric materials can include a very smooth interface, wherein there is a higher nitrogen content and / or fluorine peak at the bonding interface. Additional examples of activation and / or termination processes may be found in U.S. Patent Application Nos. 9,564,414; 9,391,143; and 10,434,749, each of which is incorporated herein by reference in its entirety and for all purposes.

[0062] In various embodiments, the conductive contact pads of the first element may also be directly bonded to corresponding conductive contact pads of the second element. For example, hybrid direct bonding techniques may be used to provide direct bonding of conductors to conductors along a bonding interface comprising covalently directly bonded dielectric to dielectric surfaces prepared as described above. In various embodiments, direct bonding techniques disclosed in at least U.S. Pat. Nos. 9,716,033 and 9,852,988 may be used to form direct bonding of conductors to conductors (e.g., contact pad to contact pad) and hybrid bonding of dielectrics to dielectrics, each of which is incorporated herein by reference in its entirety and for all purposes.

[0063] For example, as explained above, dielectric bonding surfaces can be prepared and directly bonded to each other without an intermediate adhesive. Conductive contact pads (which can be surrounded by a non-conductive dielectric field region) can also be directly bonded to each other without an intermediate adhesive. In some embodiments, the corresponding contact pads can be recessed below the outer (e.g., upper) surface of the dielectric field or non-conductive bonding area, for example, less than 30nm, less than 20nm, less than 15nm, or less than 10nm, for example, recessed within a range of 2nm to 20nm or within a range of 4nm to 10nm. In some embodiments, the non-conductive bonding areas can be directly bonded to each other at room temperature with the tools described herein without an intermediate adhesive, and the bonded structure can then be annealed. Annealing can be performed in a separate device. After annealing, the contact pads can expand and contact each other to form a metal-to-metal direct bond. Advantageously, hybrid bonding techniques (such as direct bonding interconnects commercially available from Adeia of San Jose, California or ) can enable high density pads to be connected across a direct bonding interface (e.g., a small pitch or fine pitch of a regular array). In some embodiments, the pitch of the bonding pads or the conductive traces embedded in the bonding surface of one of the bonding elements can be less than 40 microns, or less than 10 microns, or even less than 2 microns. For some applications, the ratio of the pitch of the bonding pads to one of the dimensions of the bonding pads is less than 5, or less than 3, and sometimes desirably less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonding elements can be in the range of between 0.3 and 5 microns. In various embodiments, the contact pads and / or traces can include copper, although other metals may be suitable.

[0064] Therefore, in the direct bonding process, the first element can be directly bonded to the second element without an intermediate adhesive. In some arrangements, the first element may include a singulated element (such as a singulated integrated device die). In other arrangements, the first element may include a carrier or substrate (such as a wafer), which includes multiple (such as tens, hundreds or more) device areas, forming multiple integrated device dies when it is singulated. In the embodiments described herein, whether it is a die or a substrate, the first element may be considered as a main substrate and is mounted on a support in a bonding tool to receive a second element from a pick-up and place or a robot end effector. The second element of the illustrated embodiment includes a die. In other arrangements, the second element may include a carrier or a flat plate or a substrate (such as a wafer).

[0065] As explained herein, unlike the deposition process, the first element and the second element can be directly bonded to each other without an adhesive. In one application, the width of the first element in the bonded structure can be similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure can be different from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. The first element and the second element can include non-deposited elements accordingly. In addition, unlike the deposited layer, the direct bonded structure can include defective areas along the bonding interface where nano voids exist. Due to the activation of the bonding surface (e.g., exposure to plasma), nano voids can be formed. As explained above, the bonding interface can include the aggregation of materials from the activation and / or the last chemical treatment process. For example, in an embodiment using nitrogen plasma for activation, a higher concentration of nitrogen can be present at the bonding interface. In an embodiment using oxygen plasma for activation, an oxygen peak can be formed at the bonding interface. In some embodiments, the bonding interface can include silicon oxynitride, silicon oxycarbon nitride, or silicon carbonitride. As explained herein, direct bonding can include covalent bonds, which are stronger than van der Waals bonds. The bonding layer may also include a polished surface that is planarized to a high degree of smoothness. For example, the bonding layer may have a surface roughness of less than 2 nm root mean square (RMS) per micron or less than 1 nm RMS per micron.

[0066] In various embodiments, the metal-to-metal bonding between the contact pads in the direct hybrid bonding structure can be joined so that the conductive feature grains (e.g., copper grains on the conductive features) grow into each other across the bonding interface. In some embodiments, copper may have grains oriented along 111 crystal planes to improve copper diffusion across the bonding interface. The bonding interface may extend substantially completely to at least a portion of the bonding contact pad so that there is substantially no gap between the non-conductive bonding areas at or near the bonding contact pad. In some embodiments, a barrier layer may be provided below the contact pad (e.g., which may include copper). However, in other embodiments, there may be no barrier layer below the contact pad, such as described in US2019 / 0096741, which is incorporated herein in its entirety by reference and for all purposes. In some embodiments, the bonding assembly may also be attached to a cutting sheet and be singulated. The singulated assembly may be cleaned for subsequent operations. Subsequent operations may include testing the assembly, bonding the singulated assembly to another substrate or package, or shaping the singulated assembly.

[0067] Unless the context clearly requires otherwise, throughout the description and claims, the words "comprise", "comprising", "include", "including", etc. should be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to". The word "coupled" as generally used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Similarly, the word "connected" as generally used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Additionally, when used in this application, the words "herein", "above", "below" and words of similar meaning should refer to the entire application, rather than any particular part of the application. In addition, as used herein, when a first element is described as being "on" or "above" a second element, the first element can be directly on or above the second element, so that the first element and the second element are in direct contact, or the first element can be indirectly on or above the second element, so that one or more elements are between the first element and the second element. Where the context permits, the words used in the singular or plural in the above specific embodiments may also include the plural or singular, respectively. The word "or" refers to a list of two or more items and covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0068] Furthermore, unless specifically stated otherwise or otherwise understood to be used within the context, conditional language used herein (such as "can," "could," "might," "may," "eg," "for example," "such as," etc.) is generally intended to convey that certain embodiments include and other embodiments do not include certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that features, elements, and / or states are in any way required for one or more embodiments.

[0069] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein may be implemented in a variety of other forms; in addition, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, when a block is presented in a given arrangement, an alternative embodiment may utilize different components and / or circuit topologies to perform similar functions, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and actions of the various embodiments described above may be combined to provide further embodiments. The attached claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the present disclosure.

Claims

1. A method of forming and verifying a microelectronic assembly, comprising: Mounting the substrate to the antistatic dicing tape; singulating the substrate to form a plurality of dies while the substrate is mounted to the antistatic dicing tape; as well as A bonding surface of at least one die of the plurality of dies is verified while the at least one die is mounted to the antistatic dicing tape.

2. The method according to claim 1, further comprising: The substrate is planarized before mounting the substrate to the antistatic dicing tape.

3. The method according to claim 1, further comprising: Preparing bonding surfaces of the plurality of dies while the plurality of dies are mounted to the antistatic dicing tape includes activating the bonding surfaces of the plurality of dies. 4 . The method of claim 1 , wherein singulating the substrate comprises partially cutting through conductive regions of the antistatic dicing tape.

5. The method according to claim 1, further comprising: The antistatic dicing tape is electrically grounded during verification of the bonding surface of the at least one die. 6 . The method of claim 1 , wherein verifying the bonding surface of the at least one die comprises measuring conductive pad recesses of the bonding surface of the at least one die by a metrology device.

7. The method of claim 6, wherein the metrology device is an atomic force microscope (AFM) device. 8 . The method of claim 1 , wherein verifying the bonding surface of the at least one die comprises measuring a surface roughness of the bonding surface of the at least one die by a metrology device.

9. The method of claim 8, wherein the metrology device is an atomic force microscope (AFM) device.

10. The method according to claim 1, further comprising: The at least one die is picked up from the antistatic dicing tape and directly bonded to a component without an intermediate adhesive after verifying the at least one die.

11. The method according to claim 10, further comprising: The antistatic dicing tape is electrically grounded when the at least one die is picked up from the antistatic dicing tape.

12. The method of claim 10, wherein directly bonding the at least one die to the component forms a conductor-to-conductor direct bond and a dielectric-to-dielectric direct bond.

13. The method according to claim 1, further comprising: After the substrate has been singulated, the protective layer is removed from the bonding surfaces of the plurality of dies.

14. The method of claim 1, wherein the antistatic dicing sheet or dicing tape comprises an ultraviolet (UV) sensitive or pressure sensitive adhesive layer.

15. The method of claim 1, wherein the substrate comprises active circuit devices.

16. A dicing tape comprising an antistatic adhesive layer disposed on an antistatic base film.

17. The dicing tape of claim 16 having an electrostatic discharge of less than 0.1 C / cm.

18. The dicing tape of claim 16, having a thickness of less than 10 9 Ω resistance.

19. The dicing tape of claim 16, wherein the antistatic base film comprises conductive carbon.

20. The dicing tape of claim 16, wherein the antistatic base film comprises a material that does not absorb UV light.

21. The dicing tape of claim 16, wherein the antistatic adhesive layer is configured for light activated release.

22. The dicing tape of claim 21, wherein the antistatic adhesive layer comprises a photoinitiator that generates a reactive species upon exposure to UV light. 23 . The dicing tape of claim 21 , wherein the antistatic adhesive layer comprises a monomer or an oligomer that polymerizes in the presence of the active substance to reduce adhesive strength.

24. The dicing tape of claim 16, wherein the antistatic adhesive layer is pressure sensitive.

25. The dicing tape of claim 16, wherein the thickness of the antistatic adhesive layer is greater than 10 μm.

26. The dicing tape of claim 16, wherein the antistatic adhesive layer comprises conductive carbon or silicon dioxide.

27. The dicing tape of claim 26, wherein the conductive carbon is less than 30% by weight of the antistatic adhesive layer.

28. A method of forming a microelectronic assembly, comprising: mounting a substrate to an antistatic dicing tape, the antistatic dicing tape comprising an antistatic adhesive layer; as well as Singulation is performed through the substrate and partially through the antistatic adhesive layer to form a plurality of dies.

29. The method according to claim 28, further comprising: The substrate is planarized before mounting the substrate to the antistatic dicing tape.

30. The method of claim 28, further comprising: Preparing bonding surfaces of the plurality of dies while the plurality of dies are mounted to the antistatic dicing tape includes activating the bonding surfaces of the plurality of dies.

31. The method of claim 28, further comprising: At least one die is picked up from the antistatic tape and directly bonded to a component without an intermediate adhesive.

32. The method of claim 28, wherein the antistatic dicing sheet or dicing tape comprises an ultraviolet (UV) sensitive or pressure sensitive adhesive layer.

33. A method of forming and verifying a microelectronic assembly, comprising: Mounting the substrate to the dicing tape; singulating the substrate to form a plurality of dies while the substrate is mounted to the dicing tape; as well as A bonding surface of at least one die of the plurality of dies is verified while the at least one die is mounted to the dicing tape.

34. The method of claim 33, further comprising: Preparing bonding surfaces of the plurality of dies while the plurality of dies are mounted to the dicing tape includes activating the bonding surfaces of the plurality of dies.

35. The method of claim 33, wherein singulating the substrate comprises partially cutting through the conductive regions of the dicing tape.

36. The method of claim 33, further comprising: The dicing tape is electrically grounded during verification of the bonding surface of the at least one die.

37. The method of claim 33, wherein verifying the bonding surface of the at least one die comprises measuring conductive pad recesses of the bonding surface of the at least one die by a metrology device.

38. The method of claim 33, wherein verifying the bonding surface of the at least one die comprises measuring a surface roughness of the bonding surface of the at least one die by a metrology device.

39. A dicing tape comprising an antistatic adhesive layer disposed on a release base film, wherein the thickness of the antistatic adhesive layer is greater than 10 μm.

40. The dicing tape of claim 39, wherein the thickness of the antistatic adhesive layer is greater than 15, 20, 25, 30, 35, 40, 45, or 50 μm.

41. The dicing tape of claim 39, wherein the thickness of the antistatic adhesive layer is between 10 to 15, 15 to 20, 20 to 25, 25 to 30, 30 to 35, 35 to 40, 40 to 45, or 45 to 50 μm.

42. The dicing tape of claim 39, wherein the antistatic adhesive layer has an electrostatic discharge of less than 0.1 C / cm.

43. The dicing tape of claim 39, wherein the antistatic adhesive layer has a 9 Ω resistance.

44. The dicing tape of claim 39, wherein the release base film comprises polyethylene terephthalate (PET).

45. The dicing tape of claim 39, wherein the release base film comprises a material that does not absorb UV light.

46. ​​The dicing tape of claim 39, wherein the antistatic adhesive layer is configured for light activated release.

47. The dicing tape of claim 46, wherein the antistatic adhesive layer comprises a photoinitiator that generates a reactive species upon exposure to UV light.

48. The dicing tape of claim 46, wherein the antistatic adhesive layer comprises a monomer or an oligomer that polymerizes in the presence of the active material to reduce adhesive strength.

49. The dicing tape of claim 39, wherein the antistatic adhesive layer is pressure sensitive.

50. The dicing tape of claim 39, wherein the antistatic adhesive layer comprises conductive carbon or silicon dioxide.

51. The dicing tape of claim 39, wherein the conductive carbon is less than 30% by weight of the antistatic adhesive layer.

52. A method for forming and verifying a microelectronic assembly, comprising: coating a protective layer on the bonding surface of the substrate; mounting the substrate to a dicing tape; singulating the substrate to form a plurality of dies while the substrate is mounted to the dicing tape; cleaning the protective layer from the surfaces of the singulated dies while the singulated dies are mounted to the dicing tape; as well as A bonding surface of at least one die of the plurality of dies is verified while the at least one die is mounted to the dicing tape.

53. The method of claim 52, further comprising: One of the plurality of dies is bonded directly to another substrate.

54. A method of verifying and forming a microelectronic assembly, the method comprising: Mounting the substrate to the dicing tape; singulating the substrate to form a plurality of dies while the substrate is mounted to the dicing tape; verifying a bonding surface of at least one die of the plurality of dies while the at least one die is mounted to the dicing tape; as well as Verified good dies of the plurality of dies are bonded directly from the dicing tape to the prepared surface of another substrate.

55. The method of claim 54, further comprising: After the verification step, the cutting frame holding the cutting tape is rinsed and dried.

56. The method of claim 54, wherein the dicing tape comprises an antistatic layer.

57. The method of claim 54, wherein the verifying comprises using a contact or non-contact metering device.

58. A method of forming a microelectronic assembly, comprising: verifying, when at least one of the first substrate and the second substrate is mounted to the dicing tape, that a first bonding surface of the first substrate and a second bonding surface of the second substrate have a conductive portion surrounded by a non-conductive portion; preparing the first bonding surface of the first substrate and the second bonding surface of the second substrate; rinsing and drying the prepared first bonding surface and the prepared second bonding surface; as well as directly bonding the prepared first bonding surface to the prepared second bonding surface without an intermediate adhesive layer, Wherein preparing the first bonding surface and the second bonding surface comprises exposing at least one of the first bonding surface and the second bonding surface to plasma.

59. The method of claim 58, wherein the verifying comprises using a contact or non-contact metering device.

60. The method of claim 58, further comprising singulating the directly bonded microelectronic assemblies.

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