Semiconductor device package with double-sided cooling

Abstract

A device may include a semiconductor die. The device may include a bottom heat sink and a top heat sink, where the bottom heat sink and the top heat sink are disposed on opposite sides of a semiconductor die, where the top heat sink has an area greater than an area of the semiconductor die, where the top heat sink extends beyond the semiconductor die, and where the top heat sink extends beyond the semiconductor die. Wherein an area of the bottom heat sink is greater than an area of the semiconductor die, where the bottom heat sink extends beyond the semiconductor die, and where a total thickness of the top heat sink and the bottom heat sink is at least four times a thickness of the semiconductor die.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 366,451, filed on June 15, 2022, entitled “SEMICONDUCTOR DEVICE PACKAGE WITH DUAL-SIDED COOLING,” the entire contents of which are incorporated herein by reference and form a part of this specification for all purposes as if fully described herein. Technical Field

[0003] The present application relates to semiconductor device packages. In particular, some embodiments relate to cooling integrated circuits and methods for manufacturing integrated circuit assemblies. Background Art

[0004] Semiconductor devices are used in a wide variety of applications. In certain applications, semiconductor devices may experience high electrical loads, which may result in significant heating of the semiconductor devices. There are many problems associated with high electrical loads, such as detrimental heating of semiconductor devices. Current cooling solutions may not be suitable for certain applications. Therefore, there is a need to improve the cooling of semiconductor devices. Summary of the invention

[0005] Each of the innovations described in the claims has several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the claims, some of the prominent features of the disclosure will now be briefly described.

[0006] In certain aspects, the technology described herein relates to a device with double-sided surge power heat dissipation, comprising: a semiconductor die, a bottom heat sink, and a top heat sink, wherein the bottom heat sink and the top heat sink are disposed on opposite sides of the semiconductor die, wherein an area of ​​the top heat sink is greater than an area of ​​the semiconductor die, wherein the top heat sink extends beyond the semiconductor die, wherein an area of ​​the bottom heat sink is greater than an area of ​​the semiconductor die, wherein the bottom heat sink extends beyond the semiconductor die, and wherein a combined thickness of the top heat sink and the bottom heat sink is at least four times a thickness of the semiconductor die.

[0007] In certain aspects, the technology described herein relates to a device in which a bottom heat sink has at least one electrical contact and a top heat sink has at least one electrical contact.

[0008] In certain aspects, the technology described herein relates to a device further comprising a clip, wherein the clip is disposed on the same side of the semiconductor die as the top heat sink and is configured to be in electrical and thermal contact with the semiconductor die, and wherein the clip is located between the semiconductor die and the top heat sink.

[0009] In certain aspects, the technology described herein relates to a device in which the clip comprises a folded or formed metal sheet.

[0010] In certain aspects, the technology described herein is directed to a device that also includes a thermistor or other passive die disposed on the clip.

[0011] In certain aspects, the technology described herein relates to a device in which both a bottom heat sink and a top heat sink are soldered to a semiconductor die.

[0012] In certain aspects, the technology described herein relates to a device in which a top heat sink includes a lead frame.

[0013] In certain aspects, the technology described herein relates to a device in which at least one of a top heat sink and a bottom heat sink comprises copper.

[0014] In certain aspects, the technology described herein relates to a device in which at least one of a top heat sink and a bottom heat sink comprises a metal.

[0015] In certain aspects, the technology described herein relates to a device in which both the top heat sink and the bottom heat sink include copper or other metal.

[0016] In certain aspects, the technology described herein relates to a device in which a semiconductor die is positioned between a top heat sink and a bottom heat sink so as to have a substantially intermediate position for symmetric thermal expansion.

[0017] In certain aspects, the technology described herein relates to a device in which the thickness of the top heat sink is greater than 1 mm and the thickness of the bottom heat sink is greater than 1 mm.

[0018] In certain aspects, the technology described herein relates to a device in which the thickness of the top heat sink is greater than 2 mm and the thickness of the bottom heat sink is greater than 2 mm.

[0019] In certain aspects, the technology described herein relates to a device in which the thickness of the top heat sink is greater than 3 mm and the thickness of the bottom heat sink is greater than 3 mm.

[0020] In certain aspects, the technology described herein relates to a device with double-sided surge power cooling, comprising: a semiconductor die, a bottom heat sink, and a top heat sink, wherein the bottom heat sink and the top heat sink are disposed on opposite sides of the semiconductor die, and wherein the bottom heat sink and the top heat sink together have sufficient thermal mass to maintain the semiconductor die at a temperature below 180 degrees Celsius when subjected to a surge load of up to 100 W for up to 0.5 seconds.

[0021] In certain aspects, the technology described herein relates to a device in which a bottom heat sink has at least one electrical contact and a top heat sink has at least one electrical contact.

[0022] In certain aspects, the technology described herein relates to a device further comprising a clip, wherein the clip is disposed on the same side of the semiconductor die as the top heat sink and is configured to be in electrical and thermal contact with the semiconductor die, and wherein the clip is located between the semiconductor die and the top heat sink.

[0023] In certain aspects, the technology described herein relates to a device in which the clip comprises a folded or formed metal sheet.

[0024] In certain aspects, the technology described herein is directed to a device that also includes a thermistor or other passive die disposed on the clip.

[0025] In certain aspects, the technology described herein relates to a device in which both a bottom heat sink and a top heat sink are soldered to a semiconductor die.

[0026] In certain aspects, the technology described herein relates to a device in which a top heat sink includes a lead frame.

[0027] In certain aspects, the technology described herein relates to a device in which at least one of a top heat sink and a bottom heat sink comprises copper.

[0028] In certain aspects, the technology described herein relates to a device in which at least one of a top heat sink and a bottom heat sink comprises a metal.

[0029] In certain aspects, the technology described herein relates to a device in which both the top heat sink and the bottom heat sink include copper or other metal.

[0030] In certain aspects, the technology described herein relates to a device in which a semiconductor die is positioned between a top heat sink and a bottom heat sink so as to have a substantially intermediate position for symmetric thermal expansion.

[0031] In certain aspects, the technology described herein relates to a device in which the thickness of the top heat sink is greater than 1 mm and the thickness of the bottom heat sink is greater than 1 mm.

[0032] In certain aspects, the technology described herein relates to a device in which the thickness of the top heat sink is greater than 2 mm and the thickness of the bottom heat sink is greater than 2 mm.

[0033] In certain aspects, the technology described herein relates to a device in which the thickness of the top heat sink is greater than 3 mm and the thickness of the bottom heat sink is greater than 3 mm.

[0034] In certain aspects, the technology described herein relates to a semiconductor device assembly comprising: a packaged semiconductor device comprising: a semiconductor die, a bottom heat sink, and a top heat sink, wherein the bottom heat sink and the top heat sink are disposed on opposite sides of an integrated semiconductor die, wherein an area of ​​the top heat sink is greater than an area of ​​the semiconductor die, wherein the top heat sink extends beyond the semiconductor die, wherein an area of ​​the bottom heat sink is greater than an area of ​​the semiconductor die, wherein the bottom heat sink extends beyond the semiconductor die, and wherein a combined thickness of the top heat sink and the bottom heat sink is at least four times a thickness of the semiconductor die; a printed circuit board, the top heat sink being located between the printed circuit board and the packaged semiconductor die; and a cooling member in thermal contact with the bottom heat sink.

[0035] In certain aspects, the technology described herein relates to a semiconductor device assembly in which a bottom heat sink is configured to be electrically and thermally connected to at least one contact pad (also referred to as a "contact pad") of a printed circuit board, and in which a top heat sink is configured to be thermally connected to a heat sink.

[0036] In certain aspects, the technology described herein relates to a device in which a top heat sink is electrically and thermally connected to a contact pad of a printed circuit board that is different from the at least one contact pad.

[0037] In certain aspects, the technology described herein relates to a semiconductor device assembly in which the semiconductor die is a power switching die.

[0038] In certain aspects, the technology described herein relates to a semiconductor device assembly in which the cooling member includes a heat sink.

[0039] In certain aspects, the technology described herein relates to a semiconductor device assembly in which the thickness of the top heat sink is greater than 1 mm and the thickness of the bottom heat sink is greater than 1 mm.

[0040] In some aspects, the technology described herein relates to a method of making any of the embodiments described herein.

[0041] To summarize the present disclosure, certain aspects, advantages, and novel features of the innovations are described herein. It should be understood that not all of these advantages may be realized according to any particular embodiment. Thus, the innovations may be embodied or performed in a manner that realizes or optimizes one advantage or a group of advantages taught herein without necessarily realizing other advantages that may be taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] These and other features, aspects and advantages of the present disclosure are described with reference to the accompanying drawings of certain embodiments, which are intended to illustrate but not limit the present disclosure. It should be understood that the drawings incorporated into and constituting a part of this specification are for the purpose of illustrating the concepts disclosed herein and may not be to scale.

[0043] Figure 1A Plots of die temperature versus time are shown for steady state and surge load conditions.

[0044] Figure 1B A heat map showing the temperature under surge load conditions is shown.

[0045] FIG. 2A to FIG. 2C An example double-sided cooling package according to embodiments herein is illustrated.

[0046] Figure 3 is an example illustration of heat flow from a die to a dual heat sink according to embodiments herein.

[0047] Figure 4 An exploded view of a semiconductor device package according to embodiments herein is illustrated.

[0048] Figure 5 An example semiconductor device package according to embodiments herein is illustrated.

[0049] Figure 6 Another example semiconductor device package according to embodiments herein is illustrated.

[0050] Figure 7 An example semiconductor device package according to embodiments herein is illustrated.

[0051] Figure 8 Examples of heat transfer paths according to embodiments herein are illustrated.

[0052] Fig. 9 Example precursor components and finished components according to embodiments herein are illustrated.

[0053] Fig.10 A frame mounting component according to embodiments herein is illustrated. DETAILED DESCRIPTION

[0054] The following detailed description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein may be embodied in a variety of different ways, such as as defined and covered by the claims. In this specification, reference is made to the accompanying drawings in which the same reference numerals and / or terms may represent identical or functionally similar elements. It will be understood that the elements shown in the figures are not necessarily drawn to scale. In addition, it will be understood that certain embodiments may include more elements and / or a subset of the elements shown in the figures than shown in the figures. In addition, some embodiments may include any suitable combination of features from two or more figures. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims.

[0055] introduction

[0056] Electronic components containing one or more integrated circuit (IC) dies can be deployed in a variety of applications. For example, such components can form part of a power electronic system. In some cases, such power electronic systems can be used to provide power to electric vehicles or as part of a fixed energy storage system, such as a system for storing solar energy. Such systems also have many other applications. In some cases, the components may include a diode switch, a field effect transistor (FET), such as a metal oxide semiconductor field effect transistor (MOSFET) (e.g., a GaN MOSFET), an insulated gate bipolar transistor (IGBT), other bipolar transistors, etc., or any suitable combination thereof. Any of these components can be implemented on any die of the semiconductor device package disclosed herein. In some applications, such switches may be included in an inverter that converts a direct current (DC) voltage to an alternating current (AC) voltage or a rectifier that converts AC to DC. These components may have a large amount of heat output when in operation. In some embodiments, the electronic components may be provided in the form of a packaged semiconductor device.

[0057] Power electronic systems can generate a lot of heat under both steady-state load conditions and surge conditions. This heat can cause serious problems. For example, excessive heat can cause one or more of component damage, shortened life, reduced reliability, performance degradation, etc. For example, excessive thermal stress can weaken solder joints and / or damage semiconductor components. In some applications, surge loads can cause rapid temperature rise. High surge loads can be encountered in various applications, such as when starting portable compressors, heating, ventilation and air conditioning (HVAC) systems, refrigeration systems, motors, power converters, etc.

[0058] Even short surge loads of about half a second to one second can cause significant changes in temperature. Conventional cooling components may have difficulty handling the rapid rise in heat generation. Figure 1AAs shown, when using traditional cooling through a printed circuit board (PCB), a die operating in steady state and consuming 18W of power may operate at a temperature of about 100°C. When a surge load of 100W is applied for half a second, the die temperature may rise by about 50°C or more. After one second, the die temperature may rise to about 220°C or more, depending on the specific cooling element. Figure 1A A graph of die temperature versus time for two dies with different surface areas is included, where example die B has a larger surface area than example die A. In some cases, the die can be directly attached to a lead frame or die pad (which can operate as a heat sink in a molded semiconductor device package). The semiconductor device package can be attached with a heat sink, cold plate, etc. to help dissipate heat. However, increasing the mass of the heat sink (e.g., by adding a base on top of the heat sink or otherwise increasing the mass of the heat sink) and / or adding an external heat sink may not significantly help manage die temperature during surge conditions. The semiconductor device package may lack good thermal contact with the added mass and may not be able to utilize the added thermal capacity in a short period of time. For example, before reaching the heat sink, heat can pass through a thermal interface material (e.g., thermal paste, thermal pad, solder, etc.), which can limit the rate of heat transfer, thereby playing an important role in managing die temperature during surge loads. Figure 1B An example simulation of the temperature gradient of a die package after different time periods under a transient load is shown.

[0059] In many cases, electronic components can be designed to operate under steady-state conditions. For example, the heat transfer material inside the component can be sized to handle the heat from common load conditions. This approach can provide many advantages, such as minimizing size and reducing cost because less material can be used. However, such an approach may not be suitable for certain types of use cases, such as handling large and / or surge loads.

[0060] The semiconductor device package can be cooled from one side, such as bottom cooling through the PCB. However, heat conduction through the PCB may not be suitable for some applications. In some cases, a "coin" including copper or another thermally conductive material can be embedded in the PCB below the electronic component to promote cooling. However, this method may increase the additional cost and complexity of the PCB and may reduce the density of components on the PCB. In addition, the power electronics system may increase the temperature of the PCB assembly to a temperature exceeding 100°C, which may limit the heat from the semiconductor device package via the PCB. Alternatively, in some cases, the PCB can be configured with a hole, exposing the bottom of the semiconductor device package, and a heat sink or other heat transfer device can be in thermal contact with the bottom of the semiconductor device package through the hole. In some cases, top cooling can be used to cool the semiconductor device package, such as described in U.S. Patent No. 10,658,276, entitled "Device with top-side baseplate", the contents of which are incorporated herein by reference for all purposes, as if fully described herein.

[0061] In some cases, the cooling element can be designed to handle large, continuous loads and short surge loads. Therefore, the cooling element can be designed to have not only a large thermal capacity, but also a fast heat transfer capability. The present disclosure describes examples of systems and techniques for providing effective cooling elements that do not further complicate the PCB design or component installation process. Preferably, such cooling elements can be manufactured using established, effective manufacturing methods.

[0062] Double-sided cooling package

[0063] In some embodiments, the heat sink may be in thermal contact with both sides of the die and may act as a heat reservoir for direct and simultaneous heat dissipation above and below the die. In some embodiments, the top heat sink and the bottom heat sink may be in contact and / or thermally connected with the semiconductor die. In order to promote heat dissipation, both the top heat sink and the bottom heat sink may be thicker than the semiconductor die. The total thickness of the top heat sink and the bottom heat sink may be at least 4 times the thickness of the semiconductor die. This may promote the dissipation of power surges in a steady state. The total thickness of the top heat sink and the bottom heat sink may be in the range of 4 times the thickness of the semiconductor die to 10 times the thickness of the semiconductor die. In some embodiments, when the die is subjected to a surge load of up to 100W or up to 160W for 0.5 seconds in a steady state, the top heat sink and the bottom heat sink may have sufficient thermal mass together to keep the die at a temperature below 170°C, below 160°C, or below 150°C. In some embodiments, the top heat sink and the bottom heat sink may together have sufficient thermal mass to maintain the die at a temperature below 200° C., below 190° C., or below 180° C. when the die is subjected to a surge load of up to 100 W or up to 160 W for 1 second in steady state. The top heat sink and the bottom heat sink may both have an area larger than the area of ​​the die. The top heat sink and the bottom heat sink may both extend beyond the die.

[0064] Figure 2A and Figure 2B An example embodiment of a dual heat sink system is shown. Figure 2A and Figure 2B As shown, the top heat sink 201 and the bottom heat sink 202 can be in thermal contact with the die 203 via solder 204 and 205. The die 203 can be an IC die. The die 203 can be a semiconductor switching die. In some embodiments, sintering or epoxy bonding can be used instead of solder 204 and 205. In some embodiments, dual heat sinks (e.g., plates) can be nested, such as Figure 2A In some other embodiments, the dual heat sinks may be stacked one on top of the other, for example Figure 2B shown.

[0065] The top heat sink 201 may include copper. For example, the top heat sink 201 may be mostly or entirely copper. The bottom heat sink 202 may include copper. For example, the bottom heat sink 202 may be mostly or entirely copper. The top heat sink 201 and the bottom heat sink 202 may be thick enough to simultaneously dissipate the heat associated with the power surge. Such thickness may be significantly greater than conventional thicknesses, sufficient to achieve steady-state heat dissipation to obtain a stable maximum die temperature. The top heat sink 201 and the bottom heat sink 202 may suppress the temperature increase of the die 203 when there is a transient power surge. Thus, the dual heat sink system may keep the die and package within power surge specifications.

[0066] The die 203 may be located between the top heat sink 201 and the bottom heat sink 202 to have a substantially intermediate position for symmetrical thermal expansion. This may reduce or eliminate coefficient of thermal expansion (CTE) mismatch stresses.

[0067] Figure 2C Various example embodiments of dual heat sinks are illustrated. In some embodiments, there may be only two components (e.g., a top heat sink 201 and a bottom heat sink 202), while in other embodiments, there may be more than two components, and some of the components may be connected using a conductive bonding material 210 (such as solder, sintering paste, or epoxy). For example, Figure 2C The "LI" and "LII" example embodiments shown in the drawings can have one or more components 202' attached to and in electrical communication with the bottom heat sink portion. In some embodiments, the heat sink components can be connected by other methods, such as, for example, ultrasonic welding, laser welding, diffusion bonding, impact welding, friction welding, or riveting.

[0068] Figure 3 is an example illustration of heat flow from the die to the dual heat sink according to some embodiments. Figure 3 As shown, the die 203 can be disposed between the top heat sink 201 and the bottom heat sink 202. The top heat sink 201 can be in thermal and / or electrical contact with the PCB 206 via an interface material 207. For example, the interface material can be a metal, such as a copper contact pad. In some embodiments, the interface material 207 may not be present. In some embodiments, the PCB 206 can be any other suitable substrate for mounting the packaged electronic device. The bottom heat sink 202 can be thermally connected to the cooling member 208 via a thermal interface material 209 and / or other gap filling materials. In some embodiments, the cooling member 208 can be a heat sink. In some embodiments, the cooling member 208 can include a fin. In some embodiments, the cooling member 208 can be a cold plate or other suitable cooling member.

[0069] In some embodiments, the thickness of the top and bottom heat sinks can be enhanced or optimized using the equation Q = mcΔT, where Q is the energy absorbed, m is the mass, c is the specific heat capacity, and ΔT is the temperature change. Thus, for example, for a dual heat sink arrangement, the total absorbed heat can be calculated by Q = mcΔT. t c t ΔT t +m b c b ΔT b As used herein, the subscript t refers to the top heat sink and the subscript b refers to the bottom heat sink. If the top heat sink and the bottom heat sink are made of the same material, the equation can be simplified because c tand c b In some embodiments, mass, mass ratio (e.g., mass of the top heat sink relative to the bottom heat sink) can be enhanced or optimized by at least partially considering the initial and target maximum temperatures to achieve a specific total energy absorption. In some embodiments, geometric and / or spatial optimization can be performed using simulations (e.g., 3D transient thermal simulations).

[0070] As used herein, top and bottom are used to indicate that the heat sink is primarily located on opposite sides of the die. In some embodiments, the "top" side may be the side closest to the PCB, but in some embodiments, the top side may face away from the PCB. The top heat sink may also be referred to as a lead frame or PCB lead frame. The bottom heat sink may also be referred to as a die pad.

[0071] In some embodiments, the bottom heat sink (e.g., bottom plate) can face outwardly away from the PCB and can be designed to interface with a cold plate or heat sink that can be cooler than the PCB. In some embodiments, at low temperatures, such as during steady-state operation, the bottom heat sink can be the primary heat reservoir. Therefore, the bottom heat sink is proportionally larger than the top heat sink (e.g., top plate), which can be primarily designed to address rapid thermal demands due to surge loads. The proportion of the top heat sink compared to the bottom heat sink can be adjusted to absorb transient thermal loads, enabling higher overall energy absorption within defined parameter limits (e.g., a maximum die temperature limit that can last for a defined period of time). The bottom heat sink and the top heat sink can be additionally or alternatively proportionally or otherwise designed to reduce temperature gradients near the die during high load events.

[0072] As described above, the top heat sink can be provided to address rapid heat absorption when a transient surge load is applied to the die, resulting in heat generation exceeding steady-state operation. The top heat sink can be soldered or sintered to the die and can be much thicker than is typically used to facilitate electrical conduction with the PCB. For example, the top and bottom heat sinks can be about 1 mm, 2 mm, about 3 mm, about 4 mm, or about 5 mm thick, or any thickness between these numbers, or even more if desired.

[0073] Figure 4 Depicted are exploded views of two semiconductor device packages with double-sided cooling according to some embodiments. As described in more detail above, in some embodiments, the semiconductor device packages may be Figure 4The semiconductor device package may include a PCB lead frame 402 (also referred to as a lead frame), solder 404, thermistor 406, solder 408, die clip 410, solder 412, die 414, solder 416, and die pad 418. Figure 4 As shown, solder 416 is used to attach die 414 to die pad 418, which may be, for example, a copper block, an AlN block, or other material having desired electrical and thermal conductivity properties. Die pad 418 may be a bottom heat sink. Die clip 410 may be attached to the side of die 414 opposite to die pad 418 using solder 412. Die clip 410 may be thin. Die clip 410 may reduce drain and source loop inductance and associated losses. Lead frame 402 may be soldered to die clip 410 using solder 404. Lead frame 402 may be a top heat sink. In some embodiments, the semiconductor device package may include (multiple) other active or passive die. For example, passive die 406 may be a thermistor attached to die clip 410 using solder 408.

[0074] Figure 5 4 shows a side view of a semiconductor device package with double-sided cooling according to some embodiments. The semiconductor device package may include a lead frame 402, a passive die 406, a die clip 410, a die 414, and a die pad 418. The components shown may be attached to each other by solder, for example, as shown in FIG. Figure 4 For simplicity, Figure 5 Solder is omitted. The semiconductor device package may include a heat sink 506 in thermal contact with the die pad 418 via a thermal interface material 508. The heat sink may be a cold plate, a heat sink, or any other suitable cooling member. The semiconductor device package may be disposed on a PCB 502, wherein a copper contact pad 504 is disposed. The die pad 418 may operate as a drain contact for the die 414 and may be attached to the contact pad 504 (e.g., a copper contact pad), and the die 414 may be disposed thereon (e.g., by soldering), as shown in FIG. Figure 4As shown. The die clip 410 can be used to provide a source contact for the semiconductor device and can be in electrical and thermal contact with the second copper pad 504 on the top of the PCB 502 and the die 414. The heat sink 506 can be placed in thermal contact with the die clip 410. In some embodiments, a passive die 406 (e.g., a thermistor) can be disposed on the die clip 410 for monitoring the temperature of the semiconductor device. The thermal interface material 508 can be used to place the die pad 418 in thermal contact with the heat sink 506. In some embodiments, the heat sink 506 can be outside the semiconductor device package. In some embodiments, the heat sink 506 can be part of the semiconductor device package. For example, the heat sink 506 can have an outward-facing surface disposed at or near an outer surface of the semiconductor device package.

[0075] exist Figure 5 , arrows are shown to indicate paths that heat can transfer away from the die. For example, heat can flow through the die clip 410, through the contact pad 504, and into the PCB 502. Heat can flow through the lead frame 402, to the contact pad 504, and then to the PCB 502. Heat can flow through the die pad 418 and the thermal contact material 508 to the heat sink 506.

[0076] exist Figure 5 In a system of FIG. 4 , die 414 may be a high power die arranged for operation at 1 kV or higher power (eg, 1200 V operation). The die may include power switches and / or other components.

[0077] Despite Figure 5 In the embodiment of the present invention, a single die is shown as being between the die pad and the heat sink, but in some other applications, two or more die can be included between the die pad and the heat sink. In such applications, the two or more die can be electrically and / or thermally connected to each other.

[0078] will understand, Figure 5 These are merely examples, and other embodiments are possible. For example, in some embodiments, neither the die pad nor the clip may be used to provide electrical contacts, or additional or alternative contacts may be provided. If contacts are provided, they may be designed to improve electrical performance. For example, source and drain connections may be closely nested to reduce parasitic inductance. In some embodiments, the lead frame may implement a heat sink.

[0079] Placing a die between two heat transfer materials (e.g., a thermal mass die pad and a thermal mass heat sink or lead frame) presents several challenges. The metals used for electrical contact and heat transfer can expand significantly when heated. For example, in some applications, copper can expand by about 17ppm / °C. Thermal expansion can create stress on the die. Therefore, in some embodiments, the die can be centered on the pad and / or heat sink (or lead frame) to reduce or minimize stress non-uniformity that can lead to die damage.

[0080] Figure 6 Another example embodiment of a semiconductor device package according to some embodiments herein is illustrated. Figure 6 Examples and Figure 5 The embodiments of are substantially similar. Figure 6 In the embodiment, the bottom heat sink 418' (also called the die pad) may have a Figure 5 The bottom heat sink has different structures. For example, Figure 5 In FIG. 4 , the die pad 418 is directly electrically connected to the contact pad of the PCB. Figure 6 In the embodiment, the bottom heat sink 418' is not directly electrically connected to the contact pads of the PCB. Figure 6 In the embodiment of the present invention, the die is placed on the thermal mass die pad and the top of the die is in contact with the clip. The heat sink is in contact with the clip. Figure 6 As shown, heat can flow from the die to the pads and eventually to the PCB through pads (e.g., copper pads). Heat can also simultaneously flow from the die to the clip, to the heat sink, and eventually to the heat sink by passing through the thermal interface material, which can have a wide range of thermal conductivities. In addition, some of the thermal energy can travel along the clip and eventually reach the PCB through pads (e.g., copper pads) that are in contact with the clip.

[0081] Figure 7 1 illustrates heat transfer paths of semiconductor device components according to some embodiments herein. Figure 7 As shown, two main paths are provided to carry heat away from the die. From the die to the PCB, heat can be transferred from the die through the die attach solder to the die pad, to the pad (e.g., copper pad) on which the device package is mounted, and finally into the PCB. Alternatively or additionally, heat can travel from the die through the clip-die solder, through the die clip, through the lead solder and into the lead frame. Heat can be carried away from the lead frame and transported from the device package to the heat sink via the thermal interface material.

[0082] like Figure 7The arrangement shown allows heat to be taken away from the die in both directions with relatively high efficiency. Advantageously, a large thermal mass block is in contact with the die without the use of a thermal interface material (e.g., thermal paste or thermal pad) because the thermal interface material can be a thermal bottleneck. Thermal interface materials typically have high thermal impedance compared to metals. Die attachment bonding compounds, such as solder, sintering paste, and epoxy resins, can provide significantly higher thermal conductivity and lower interface impedance compared to typical thermal interface materials. For example, solder can have a thermal conductivity of at least about 20W / m·K, 50W / m·K, or 80W / m·K or more, depending on the solder. Typical dielectric, electrically insulating thermal interface materials can have a thermal conductivity of less than about 10W / m·K, although some special materials can achieve slightly higher thermal conductivities.

[0083] Although Figures 4 to 7 The die clip is depicted as a separate component from the heat sink, but in some embodiments, the die clip and the heat sink may be a single integrated component. In some embodiments, the heat sink and the die clip may be separate components. In some embodiments, the heat sink and the clip may be pre-joined. In some embodiments, the die clip may be a sheet metal clip and may be folded so that it acts as a double thickness stepped area for die attachment as well as a heat sink. As described above, in some embodiments, the die clip may have a thermistor that is secured to the die clip (e.g., by soldering). In some embodiments, pre-joining the die clip and the heat sink or forming the die clip and the heat sink as a single component may simplify the manufacturing process of the packaged semiconductor device, such as by reducing some reflow steps in the manufacturing process.

[0084] In some embodiments, contact pads and / or other features on the PCB can be shaped, sized, and arranged to facilitate lateral heat transfer and power conduction across the thermally conductive PCB plane, and heat can be carried away from the device package using a heat spreading effect. In some embodiments, the PCB can include thermal vias that can be used to transfer heat to the underlying PCB plane.

[0085] In some embodiments, the contacts on the exterior of the semiconductor device package can be positioned to reduce or minimize surface creepage. For example, in some high power applications, the device can have source and drain potential drops of about 1 kV or more, which can result in considerable surface creepage distances. Therefore, the source lead 804 and the drain lead 802 can be kept at a considerable distance, such as about 4 mm, 5 mm, or 6 mm or more, as shown in FIG. Figure 8As shown. In some embodiments, the contacts can be kept as far apart as possible without increasing the size of the package beyond acceptable limits. In some embodiments, surface mount device (SMD) epoxy grooves 806 can be used to guide flow paths for forming curvilinear epoxy patterns to provide underside high voltage isolation between component assemblies and features of the PCB.

[0086] Design and manufacture of double-sided heat sinks

[0087] Preferably, semiconductor packages with double-sided cooling can be manufactured using conventional techniques to minimize cost and / or improve yield. Thus, for example, while a heat sink of considerable thickness may be required for cooling, the thickness of the heat sink may be limited, e.g., to about 3 mm or less, so that metal components (such as a lead frame of a semiconductor package) can be manufactured using a roll-to-roll manufacturing process.

[0088] In some embodiments, each of the dual heat sinks can be produced from a single shaped copper strip using stamping, corner bending, cutting, and / or other manufacturing techniques. In some embodiments, the dual heat sinks can be attached to a thin stamping frame to improve manufacturing efficiency and enable other forming processes (such as cold forging or hot forging), and can optionally allow roll-to-roll manufacturing.

[0089] like Fig. 9 As shown, shaped copper 902, 904 (or another suitable material) can be used to prepare the lead frame and the die pad. For example, the shaped copper 902 can have a lead frame profile, and the shaped copper 904 can have a die pad profile. Typical manufacturing processes can add grooves, depressions, etc. that are required for the finished shapes 906, 908 without removing a large amount of material (which may slow down and / or complicate the manufacturing process). For example, the finished shape can include a lead frame 906, a die clip 908, and / or a die pad 910.

[0090] Although Fig. 9 The depicted approach has several advantages, but manufacturing challenges may still exist. For example, after forming, the shapes still need to be cut, sawed, diced, or otherwise singulated into individual parts for making individual semiconductor die packages, and cutting thick copper can significantly slow the manufacturing process, among other disadvantages. Therefore, in some embodiments, thick metal parts can be hot forged and then mounted on a light, thin frame, such as Fig.10 As shown. Fig.10 , the die pad 418 is riveted to the carrier frame 1002 .

[0091] Additional Embodiments

[0092] In the above description, the present disclosure has been described with reference to specific embodiments. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

[0093] In fact, although the present disclosure is in the context of certain embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the present invention and its equivalents. Additionally, although several variations of the embodiments have been shown and described in detail, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art based on the present disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still be within the scope of the present disclosure. It should be understood that the various features and aspects of the disclosed embodiments may be combined or substituted with each other to form different modes of the embodiments disclosed herein. None of the methods disclosed herein need to be performed in the order described. Therefore, it is expected that the scope of the present disclosure should not be limited by the specific embodiments described above.

[0094] It will be appreciated that the systems and methods of the present disclosure each have several innovative aspects, none of which is solely responsible for or requires the desired properties disclosed herein. The various features and processes described above can be used independently of one another or can be combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of the present disclosure.

[0095] Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. Furthermore, although features may be described above as acting in certain combinations, or even initially claimed as such, in some cases one or more features from a claimed combination may be deleted from the combination, and a claimed combination may involve sub-combinations or variations of sub-combinations. No single feature or group of features is essential or indispensable to each and every embodiment.

[0096] It will also be understood that, unless expressly stated otherwise or otherwise understood in the context of use, conditional language used herein, such as "can," "could," "may," "for example," and the like, is generally intended to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Thus, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or steps in any way, or that one or more embodiments must include logic for determining whether such features, elements, and / or steps are included or to be performed in any particular embodiment, with or without author input or prompting. The terms "comprising," "including," "having," and the like are synonymous and are used inclusively in an open-ended manner and do not exclude additional elements, features, actions, operations, and the like. Additionally, the term "or" is used in its inclusive sense (and not in its exclusive sense), and thus, when used, for example, to connect a list of elements, the term "or" means one, some, or all of the elements in the list. Additionally, the articles "one", "an" and "the" used in the present application and the appended claims are interpreted as meaning "one or more" or "at least one", unless otherwise specified. Similarly, although the operations may be depicted in a particular order in the accompanying drawings, it should be appreciated that such operations do not need to be performed in the particular order shown or in sequence, or do not need to perform all the operations shown to obtain the desired results. In addition, the accompanying drawings may schematically depict one or more example processes in the form of a flow chart. However, other operations that are not depicted may be incorporated into the schematically illustrated example methods and processes. For example, one or more additional operations may be performed before, after, at the same time, or between any of the illustrated operations. Additionally, the operations may be rearranged or reordered in other embodiments. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together into a single software product or packaged into multiple software products. Additionally, other embodiments are within the scope of the following claims. In some cases, the actions described in the claims may be performed in different orders and still achieve the desired results.

[0097] In addition, although the methods and devices described herein may be susceptible to various modifications and alternative forms, specific examples thereof have been shown in the drawings and described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms or methods disclosed, but on the contrary, the present disclosure is intended to cover all modifications, equivalents and alternatives within the spirit and scope of the various embodiments described and the appended claims. In addition, any specific features, aspects, methods, properties, characteristics, qualities, attributes, elements, etc. disclosed herein in relation to an embodiment or embodiment can be used for all other embodiments or embodiments described herein. Any method disclosed herein does not need to be performed in the order described. The methods disclosed herein may include certain actions taken by the practitioner; however, the methods may also include any third-party instructions for these actions, whether express or implied. The ranges disclosed herein also include any and all overlaps, sub-ranges, and combinations thereof. Languages ​​such as "up to", "at least", "greater than", "less than", "between", etc. include the numbers described. The numbers preceding terms (such as "about" or "approximately") include the numbers described and should be interpreted as appropriate (e.g., as accurately as possible in these cases, such as ±5%, ±10%, ±15%, etc.). A phrase preceding a term such as "substantially" includes the phrase and should be interpreted as appropriate (e.g., as much as possible under those circumstances). For example, "substantially unchanged" includes "unchanged." Unless otherwise indicated, all measurements are under standard conditions, including temperature and pressure.

[0098] As used herein, a phrase referring to "at least one" of a list of items refers to any combination of those items, including a single component. As an example, "at least one of A, B, or C" is intended to cover: A, B, C, A and B, A and C, B and C, and A, B and C. Unless expressly stated otherwise, conjunction language (such as the phrase "at least one of X, Y, and Z") is understood with the context in which it is normally used to express that an item, item, etc. can be at least one of X, Y, and Z. Therefore, such conjunction language is generally not intended to imply that certain embodiments require that at least one of X, at least one of Y, and at least one of Z each be present. The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the apparatus and methods disclosed herein.

[0099] Thus, the claims are not intended to be limited to the embodiments shown herein, but are to be accorded the widest scope consistent with the disclosure, the principles and the novel features disclosed herein.

[0100] Although the claims presented herein are in a single dependent format, it should be understood that any claim can be dependent on any previous claim of the same type unless it is obviously technically infeasible.

Claims

1. A device with double-sided surge power heat dissipation, comprising Semiconductor die; a bottom heat sink; and Top heat sink, wherein the bottom heat sink and the top heat sink are disposed on opposite sides of the semiconductor die, wherein the top heat sink has an area greater than the area of ​​the semiconductor die, wherein the top heat sink extends beyond the semiconductor die, wherein an area of ​​the bottom heat sink is greater than the area of ​​the semiconductor die, wherein the bottom heat sink extends beyond the semiconductor die, and The combined thickness of the top heat sink and the bottom heat sink is at least 4 times the thickness of the semiconductor die. 2 . The device of claim 1 , wherein the bottom heat sink has at least one electrical contact and the top heat sink has at least one electrical contact.

3. The device of claim 1 , further comprising a clip, wherein the clip is disposed on the same side of the semiconductor die as the top heat sink and is configured to be in electrical and thermal contact with the semiconductor die, and wherein the clip is located between the semiconductor die and the top heat sink.

4. The device of claim 3 further comprising a thermistor or other passive die disposed on the clip. 5 . The device of claim 1 , wherein the bottom heat sink and the top heat sink are both soldered to the semiconductor die. 6 . The device of claim 1 , wherein at least one of the top heat sink and the bottom heat sink comprises copper. 7 . The device of claim 1 , wherein the semiconductor die is located between the top heat sink and the bottom heat sink so as to have a substantially intermediate position for symmetric thermal expansion. 8 . The device of claim 1 , wherein the top heat sink has a thickness greater than 1 mm, and the bottom heat sink has a thickness greater than 1 mm. 9 . The device of claim 1 , wherein the top heat sink has a thickness greater than 3 mm, and the bottom heat sink has a thickness greater than 3 mm.

10. The device of claim 1, wherein the top heat sink and the bottom heat sink are together configured to maintain the semiconductor die at a temperature below 160 degrees Celsius when the semiconductor die is subjected to a surge load of up to 100 W for 0.5 seconds in a steady state.

11. A device with double-sided surge power heat dissipation, comprising Semiconductor die; a bottom heat sink in thermal communication with the semiconductor die; as well as a top heat sink in thermal communication with the semiconductor die; wherein the bottom heat sink and the top heat sink are disposed on opposite sides of the semiconductor die, and wherein the bottom heat sink and the bottom heat sink are together configured to maintain the semiconductor die at a temperature below 160 degrees Celsius when the semiconductor die is subjected to a surge load of up to 100 W for up to 0.5 seconds in a steady state.

12. The device of claim 11, wherein the top heat sink and the bottom heat sink are together configured to maintain the semiconductor die at a temperature below 200 degrees Celsius when the semiconductor die is subjected to a surge load of up to 100 W for 1 second in a steady state.

13. The device of claim 11, wherein the bottom heat sink has at least one electrical contact and the top heat sink has at least one electrical contact.

14. The device of claim 11, further comprising a clip, wherein the clip is disposed on the same side of the semiconductor die as the top heat sink and is configured to be in electrical and thermal contact with the semiconductor die, and wherein the clip is located between the semiconductor die and the top heat sink.

15. The device of claim 14 further comprising a thermistor or other passive die disposed on the clip.

16. The device of claim 11, wherein at least one of the top heat sink and the bottom heat sink comprises copper. 17 . The device of claim 11 , wherein the semiconductor die is located between the top heat sink and the bottom heat sink to have a substantially intermediate position for symmetric thermal expansion.

18. The device of claim 11, wherein the top heat sink has a thickness greater than 2 mm and the bottom heat sink has a thickness greater than 2 mm.

19. A semiconductor device assembly comprising: Packaged semiconductor devices, including: Semiconductor die; bottom heat sink; and Top heat sink, wherein the bottom heat sink and the top heat sink are disposed on opposite sides of the semiconductor die, wherein the top heat sink has an area greater than the area of ​​the semiconductor die, wherein the top heat sink extends beyond the semiconductor die, wherein an area of ​​the bottom heat sink is greater than the area of ​​the semiconductor die, wherein the bottom heat sink extends beyond the semiconductor die, and wherein the combined thickness of the top heat sink and the bottom heat sink is at least 4 times the thickness of the semiconductor die; a printed circuit board, the top heat sink being located between the printed circuit board and the packaged semiconductor die; and A cooling element is in thermal contact with the bottom heat sink.

20. The semiconductor device assembly of claim 19, wherein the bottom heat sink is configured to be electrically and thermally connected to at least one contact pad of a printed circuit board, and wherein the top heat sink is configured to be in thermal communication with a heat sink.

21. The device of claim 20, wherein the top heat sink is electrically and thermally connected to a contact pad of the printed circuit board different from the at least one contact pad.

22. The semiconductor device assembly of claim 19, wherein the cooling member comprises a heat sink.

23. The semiconductor device assembly of claim 19, wherein the top heat sink has a thickness greater than 1 mm and the bottom heat sink has a thickness greater than 1 mm.

24. The semiconductor device assembly of claim 19, wherein the top heat sink and the bottom heat sink are together configured to maintain the semiconductor die at a temperature below 160 degrees Celsius when the semiconductor die is subjected to a surge load of up to 100 W for 0.5 seconds in a steady state.

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