Layout design for custom stacked capacitors to achieve high capacitance

Abstract

A chip includes a first capacitor. The first capacitor includes first electrodes formed of a metal layer M0, where the first electrodes are coupled to each other. The first capacitor further includes second electrodes formed by the metal layer M0, where the second electrodes are coupled to each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application serial number 17 / 888,369 filed in the U.S. Patent Office on August 15, 2023. Technical Field

[0003] Aspects of the present disclosure relate generally to capacitors, and more particularly to the layout of capacitors on a chip. Background Art

[0004] Capacitors can be integrated on a chip (i.e., die). For example, integrated capacitors can be used as decoupling capacitors on supply rails. Integrated capacitors can also be used, for example, in filters, switched capacitor circuits, analog-to-digital converters, digital-to-analog converters, etc. Because silicon die cost is proportional to die area, it is desirable to manufacture high-density capacitors on a die to reduce the die area required for the capacitors. Summary of the invention

[0005] A simplified overview of one or more implementations is presented below in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is neither intended to identify key or important elements of all implementations nor to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to a more detailed description that is presented later.

[0006] The first aspect relates to a chip comprising a first capacitor. The first capacitor comprises a first electrode, the first electrode is formed by a metal layer M0, wherein the first electrodes are coupled to each other. The first capacitor also comprises a second electrode, the second electrode is formed by a metal layer M0, wherein the second electrodes are coupled to each other.

[0007] A second aspect relates to a chip including a capacitor. The capacitor includes first electrodes, wherein the first electrodes are coupled to each other, each of the first electrodes extends in a first direction, a first first electrode among the first electrodes and a second first electrode among the first electrodes are separated by a first gap in the first direction, and a third first electrode among the first electrodes and a fourth first electrode among the first electrodes are separated by a second gap in the first direction. The capacitor also includes second electrodes, wherein the second electrodes are coupled to each other, and each of the second electrodes extends in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A side view of an example of a chip including metal layers and vias according to certain aspects of the present disclosure is shown.

[0009] Figure 2AA side view of an example of a fin field effect transistor (FinFET) according to certain aspects of the present disclosure is shown.

[0010] Figure 2B A perspective view of a FinFET according to certain aspects of the present disclosure is shown.

[0011] Figure 3A A top view of a transistor according to certain aspects of the present disclosure is shown.

[0012] Figure 3B An example of a finger capacitor formed over a transistor in accordance with certain aspects of the present disclosure is shown.

[0013] Figure 3C According to certain aspects of the present disclosure Figure 3B Example of metal wiring coupling electrodes in a finger capacitor.

[0014] Figure 4A A top view of a transistor according to certain aspects of the present disclosure is shown.

[0015] Figure 4B An example of a finger capacitor formed over a transistor in accordance with certain aspects of the present disclosure is shown.

[0016] Figure 4C According to certain aspects of the present disclosure Figure 4B Example of metal wiring coupling electrodes in a finger capacitor.

[0017] Figure 4D shows coupling according to certain aspects of the present disclosure Figure 4C An example of metal wiring in metal wiring.

[0018] Figure 5 According to certain aspects of the present disclosure, Figure 4B An example of a second finger capacitor formed above the finger capacitor in FIG.

[0019] Figure 6 An example of a third finger capacitor formed over a second finger capacitor in accordance with certain aspects of the present disclosure is shown.

[0020] Figure 7 Examples of decoupling capacitors in accordance with certain aspects of the present disclosure are shown. DETAILED DESCRIPTION

[0021] The specific embodiments described below in conjunction with the drawings are intended as descriptions of various configurations and are not intended to represent the only configurations in which the concepts described herein may be practiced. The specific embodiments include specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, in order to avoid confusing these concepts, well-known structures and components are shown in block diagram form.

[0022] Figure 1 1 shows a side view of an example of a chip 100 (ie, a bare die) according to certain aspects. The chip 100 may include many devices (eg, transistors) integrated on the chip 100. In this aspect, Figure 1 An example of a transistor 110 integrated on a chip 100 is shown. Although for simplicity, Figure 1 One transistor 110 is shown in FIG. 1 , but it should be understood that chip 100 may include many transistors. Chip 100 may also include stacked capacitors, as discussed further below.

[0023] exist Figure 1 In the example shown in , transistor 110 includes a gate 115, a first source / drain 120-1, and a second source / drain 120-2. As used herein, the term "source / drain" refers to a source or a drain. Gate 115 is formed over a channel between the first source / drain 120-1 and the second source / drain 120-2. Transistor 110 may also include a thin gate oxide (not shown) between the gate and the channel. Gate 115 may be a polysilicon gate, a metal gate, or another type of gate. Figure 1 In the example shown in FIG. 1 , transistor 110 is depicted as a planar transistor. However, it should be understood that transistor 110 may be implemented using a fin field effect transistor (FinFET), as described below with reference to FIG. Figure 2A and Figure 2B The transistor 110 may be part of the front end of line (FEOL) of the chip 100 .

[0024] The chip 100 may further include a first source / drain contact 130-1 formed on the first source / drain 120-1, and a second source / drain contact 130-2 formed on the second source / drain 120-2. The source / drain contacts 130-1 and 130-2 may be formed by forming a source / drain contact layer (at the top) using, for example, a photolithography process and an etching process. Figure 1 Although Figure 1In the example of FIG. 1 , the source / drain contact layer is marked as “MD”, but it should be understood that the source / drain contact layer may also be marked as “CA” or other marks. The source / drain contact layer may include one or more metals and / or one or more other conductive materials.

[0025] The chip 100 may further include a gate contact 135 formed on the gate 115. The gate contact 135 may be formed by forming a gate contact layer (in the embodiment of FIG. 1 ) using, for example, a photolithography process and an etching process. Figure 1 Marked as "MP" in the Figure 1 In the example of FIG. 1 , the gate contact layer is labeled as “MP”, but it should be understood that the gate contact layer may also be labeled with another label. The gate contact layer may include one or more metals and / or one or more other conductive materials.

[0026] The chip 100 may also include a stack of metal layers 150. The metal layers 150 are patterned (e.g., using photolithography and etching) to provide metal wiring for the transistors 110 and other devices (not shown) on the chip 100. The metal wiring may be used, for example, to interconnect devices on the chip 100, couple the devices to a power source, couple the devices to one or more input / output (I / O) pins, etc. The metal layers 150 may also be used to form stacked capacitors, as discussed further below. The metal layers 150 may also be referred to as metallization layers or another term.

[0027] exist Figure 1 In the example of FIG. 1 , the bottommost metal layer in the metal layer stack 150 may be designated as metal layer M1 (also referred to as metal 1), the metal layer directly above metal layer M1 may be designated as metal layer M2 (also referred to as metal 2), the metal layer directly above metal layer M2 may be designated as metal layer M3 (also referred to as metal 3), and so on. Although for ease of explanation, in Figure 1 Three metal layers are illustrated in FIG. 1 , but it should be understood that chip 100 may include additional metal layers (eg, five or more metal layers, including metal layer M4 , metal layer M5 , etc.).

[0028] Chip 100 also includes vias 160 that provide electrical coupling between metal layers 150. In this example, via V1 provides electrical coupling between metal layer M1 and metal layer M2, and via V2 provides electrical coupling between metal layer M2 and metal layer M3.

[0029] As discussed above, metal layer 150 may also be used to form a stacked capacitor ( Figure 1). For example, metal layer 150 can be used to form a stacked capacitor including a plurality of finger capacitors, wherein each finger capacitor is formed by a corresponding one of the finger capacitors in metal layer 150. In this example, the finger capacitors can be stacked in a vertical direction to provide a high capacitance density within a given die area. Finger capacitors may also be referred to as interdigital capacitors or another term.

[0030] In advanced process nodes, a new metal layer (referred to as metal layer M0) is introduced between metal layer M1 and device structures (e.g., first source / drain 120-1, second source / drain 120-2, and gate 115) on chip 100. Metal layer M0 is used as an intermediate metal layer for coupling the device structure on chip 100 to metal layer M1. In other words, in advanced process nodes, the device structure is coupled to metal layer M1 through metal layer M0, while in existing process nodes, the device structure is coupled to metal layer M1 without metal layer M0. Figure 1 In the example shown in FIG. 1 , source / drain contacts 130 - 1 and 130 - 2 are coupled to metal layer M0 by vias VD, and gate contact 135 is coupled to metal layer M0 by vias VG. Metal layer M0 is coupled to metal layer M1 by vias V0. Unless otherwise specified, “coupled” as used herein refers to electrical coupling.

[0031] Figure 2A A side view of an example of implementing transistor 110 with a FinFET is shown and Figure 2B 1 is a perspective view of an example of implementing transistor 110 with FinFET. In this example, transistor 110 includes fins 210-1 to 210-4 extending vertically relative to gate 115 and source / drain contacts 130-1 and 130-2 (eg, Figure 2B Although Figure 2B In the example of FIG. 1 , four fins 210 - 1 to 210 - 4 are shown, but it should be understood that the transistor 110 may include a different number of fins. In addition, although the fins 210 - 1 to 210 - 4 are shown as having a rectangular cross-section, it should be understood that the fins may have other cross-sectional shapes (e.g., a tapered cross-section). It should be noted that Figure 2B The metal layer 150, the via 160 and the gate contact 135 are not explicitly shown.

[0032] In this example, gate 115 is formed on first portion 215 of fins 210-1 to 210-4. Gate 115 may wrap around three or more sides of each fin (e.g., the top side and two opposing sidewalls of each fin). In this example, transistor 110 may also include a thin dielectric layer (not shown) between fins 210-1 to 210-4 and gate 115. Figure 2AAs shown in , a gate contact 135 may be formed on the gate 115 , and a via VG may electrically couple the gate contact 135 to the metal layer M0 .

[0033] A portion of the fins 210-1 to 210-4 extending from a first side 222-1 of the gate 115 forms a first source / drain 120-1, and a portion of the fins 210-1 to 210-4 extending from a second side 222-2 of the gate 115 forms a second source / drain 120-2, wherein the first side 222-1 and the second side 222-2 are opposite sides of the gate 115. In this example, a first source / drain contact 130-1 is formed over a second portion 220-1 of the fins 210-1 to 210-4 over the first side 222-1 of the gate 115, and a second source / drain contact 130-2 is formed over a third portion 220-2 of the fins 210-1 to 210-4 over the second side 222-2 of the gate 115. Each of the source / drain contacts 130-1 to 130-2 may be made of a conductive material (eg, one or more metals). Figure 2A As shown in , vias VD may electrically couple source / drain contacts 130 - 1 to 130 - 2 to metal layer M0 .

[0034] As discussed above, metal layer M0 serves as an intermediate metal layer that couples device structures (e.g., first source / drain 120-1, second source / drain 120-2, and gate 115) to metal layer M1. In order to increase capacitance density (i.e., capacitance for a given die area), aspects of the present disclosure provide finger capacitors formed by metal layer M0. In a stacked capacitor, aspects of the present disclosure increase the number of finger capacitors in a stacked capacitor by forming additional finger capacitors in the stacked capacitor using additional metal layers (e.g., metal layer M0). The features discussed above and other features of the present disclosure are further discussed below according to various aspects.

[0035] Figure 3A 1 shows an exemplary top view of a transistor 110 according to certain aspects. As discussed further below, a finger capacitor (e.g. Figure 3B ) is formed by the metal layer M0 on the transistor 110. The transistor 110 may include an active region 310, which includes a first source / drain 120-1 and a second source / drain 120-2 (such as Figure 1 , Figure 2A and Figure 2B For an example in which transistor 110 is implemented using a FinFET, active region 310 includes fins 210 - 1 to 210 - 4 extending in lateral direction 322 (eg, Figure 2A and Figure 2BAs used herein, a “lateral direction” is a direction extending parallel to the substrate of the chip 100. The active region 310 may also be referred to as an active diffusion region, an oxide diffusion region, or another term.

[0036] Transistor 110 also includes a first source / drain contact 130-1, a second source / drain contact 130-2, and a gate 115. Gate 115 is located between first source / drain contact 130-1 and second source / drain contact 130-2. As discussed further below, finger capacitors (such as Figure 3B ) can electrically couple the first source / drain 120-1 and the second source / drain 120-2 together to configure the transistor 110 as a metal oxide semiconductor (MOS) capacitor. However, it should be understood that the present disclosure is not limited to this example. Figure 3A In the example of FIG. 1 , the first source / drain contact 130 - 1 , the second source / drain contact 130 - 2 , and the gate 115 are parallel to each other and extend in a lateral direction 324 that is perpendicular to the lateral direction 322 .

[0037] Figure 3A Also shown are first vias 320-1 and 320-2 coupled to gate 115. Figure 1 and Figure 2A 1 and 320-2 are formed on the gate 115, the first vias 320-1 and 320-2 can be coupled to the gate 115 through the gate contact 135. In this example, the first vias 320-1 and 320-2 can be disposed on the gate contact 135. As discussed further below, the first vias 320-1 to 320-2 are used to couple the gate 115 to the metal layer M0.

[0038] Figure 3A Also shown are second vias 325-1 and 325-2 coupled to the first source / drain contact 130-1 and third vias 330-1 and 330-2 coupled to the second source / drain contact 130-2. For example, the second vias 325-1 and 325-2 may be disposed on the first source / drain contact 130-1, and the third vias 330-1 and 330-2 may be exposed on the second source / drain contact 130-2. As discussed further below, the second vias 325-1 and 325-2 are used to couple the first source / drain contact 130-1 to the metal layer M0 and the third vias 330-1 and 330-2 are used to couple the second source / drain contact 130-2 to the metal layer M0.

[0039] Figure 3BAn example of a finger capacitor 335 formed by a metal layer M0 according to certain aspects is shown. In this example, the metal layer M0 is patterned to form first electrodes 340-1, 340-2, and 340-3 and second electrodes 345-1 and 345-2 (e.g., using a photolithography process and an etching process that patterns the metal layer M0 into separate electrodes). The electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 are elongated and extend in a lateral direction 322. Figure 3B In the example shown in , electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 are spaced apart from each other in a lateral direction 324, wherein the lateral direction 324 is perpendicular to the lateral direction 322. However, it should be understood that the present disclosure is not limited to this example. As discussed further below, first electrodes 340-1, 340-2, and 340-3 are coupled to a first terminal of capacitor 335, and second electrodes 345-1 and 345-2 are coupled to a second terminal of capacitor 335. Electrodes may also be referred to as plates, fingers, or another term.

[0040] like Figure 3B As shown in FIG. 1 , first electrodes 340-1, 340-2, and 340-3 are interleaved with second electrodes 345-1 and 345-2. In other words, the arrangement of electrodes in finger capacitor 335 alternates between first electrodes 340-1, 340-2, and 340-3 and second electrodes 345-1 and 345-2. Chip 100 may include dielectric material between electrodes 340-1, 340-2, 340-3, 345-1, and 345-2.

[0041] The first electrodes 340-1 and 340-3 are coupled to the gate electrode 115 through the first via holes 320-1 and 320-2. Figure 3B In the example shown in FIG. 1 , each of the first vias 320-1 and 320-2 is coupled between the gate 115 and a corresponding one of the first electrodes 340-1 and 340-3. It should be noted that the first vias 320-1 and 320-2 are connected to the gate 115 and the first electrodes 340-1 and 340-3. Figure 3B 1 and 3. The first electrodes 340-1 and 340-3 are shown with dots to indicate that the first vias 320-1 and 320-2 are respectively below the first electrodes 340-1 and 340-3. It should also be noted that in this example, the first electrode 340-2 is not coupled to the gate 115 through the via. As discussed further below, the first electrode 340-2 is coupled to the first electrodes 340-1 and 340-3 through the metal layer M1.

[0042] The second electrodes 345-1 and 345-2 are coupled to the first source / drain contact 130-1 through the second vias 325-1 and 325-2. Figure 3BIn the example shown in FIG. 1 , each of the second vias 325-1 and 325 is coupled between the first source / drain contact 130-1 and a corresponding one of the second electrodes 345-1 and 345-2. It should be noted that the second vias 325-1 and 325-2 are Figure 3A 3. Dots are shown in FIG. 3 to indicate that the second via holes 325-1 and 325-2 are respectively below the second electrodes 345-1 and 345-2.

[0043] The second electrodes 345-1 and 345-2 are also coupled to the second source / drain contact 130-2 through the third vias 330-1 and 330-2. Figure 3B In the example shown in FIG. 1 , each of the third vias 330-1 and 330-2 is coupled between the second source / drain contact 130-2 and a corresponding one of the second electrodes 345-1 and 345-2. It should be noted that the third vias 330-1 and 330-2 are Figure 3A 3. Dots are shown in FIG. 3 to indicate that the third via holes 330-1 and 330-2 are respectively below the second electrodes 345-1 and 345-2.

[0044] Thus, in this example, the first source / drain contact 130-1 and the second source / drain contact 130-2 are coupled together through the second electrodes 345-1 and 345-2. This couples the first source / drain 120-1 and the second source / drain 120-2 together, causing the transistor 110 to act as a MOS capacitor coupled in parallel with the finger capacitor 335. However, it should be understood that the present disclosure is not limited to this example. For example, in other implementations, the finger capacitor 335 may be formed on top of another type of capacitor. In some implementations, there may be no device below the finger capacitor 335.

[0045] Figure 3B Also shown are fourth vias 350-1, 350-2, and 350-3 coupled to the first electrodes 340-1, 340-2, and 340-3, respectively. For example, each of the fourth vias 350-1, 350-2, and 350-3 may be disposed on a corresponding one of the first electrodes 340-1, 340-2, and 340-3. Figure 3B Also shown are fifth vias 355-1 and 355-1 coupled to the second electrodes 345-1 and 345-2. For example, each of the fifth vias 355-1 and 355-2 may be disposed on a corresponding one of the second electrodes 345-1 and 345-2.

[0046] Figure 3C1 and 2 are shown as first and second metal wirings 360 and 365 formed from the metal layer M1 (eg, a photolithography process and an etching process for patterning the metal layer M1 into the metal wirings 360 and 365). Figure 3C In the example shown in , each of the first metal wiring 360 and the second metal wiring 365 extends in the lateral direction 324 .

[0047] In this example, each of the fourth vias 350-1, 350-2, and 350-3 is coupled between a corresponding one of the first electrodes 340-1, 340-2, and 340-3 and the first metal wiring 360. Therefore, in this example, the first electrodes 340-1, 340-2, and 340-3 are coupled to each other through the first metal wiring 360. In this example, the first metal wiring 360 can be used as a first terminal of the finger capacitor 335 discussed above. The first metal wiring 360 can also be used as an electrode of another finger capacitor formed by the metal layer M1.

[0048] In this example, each of the fifth vias 355-1 and 355-2 is coupled between a corresponding one of the second electrodes 345-1 and 345-2 and the second metal wiring 365. Therefore, in this example, the second electrodes 345-1 and 345-2 are coupled to each other through the second metal wiring 365. In this example, the second metal wiring 365 can serve as a second terminal of the finger capacitor 335 discussed above. The second metal wiring 365 can also serve as an electrode of another finger capacitor formed by the metal layer M1.

[0049] Finger capacitor 335 may be used in a stacked capacitor that includes a stack of multiple finger capacitors formed from multiple metal layers. Using metal layer M0 to form finger capacitor 335 provides an increased capacitance density (i.e., capacitance for a given die area) for the stacked capacitor by providing an additional metal layer (i.e., metal layer M0) to form an additional finger capacitor (i.e., finger capacitor 335) in the stacked capacitor. In some aspects, other finger capacitors (not shown) in the stacked capacitor may be stacked above finger capacitor 335, where the other finger capacitors may be formed from metal layers M1 to Mx, where x is an integer greater than 1.

[0050] It should be understood that the present disclosure is not limited to FIG. 3A to FIG. 3C For example, it should be understood that the finger capacitor 335 can be formed on multiple devices. For example, in some implementations, the electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 can extend across multiple devices (e.g., transistors) in the lateral direction 322. It should also be understood that in addition to FIG. 3A to FIG. 3CIn addition to the electrodes 340 - 1 , 340 - 2 , 340 - 3 , 345 - 1 , and 345 - 2 shown in FIG. 3 , the finger capacitor 335 may include additional electrodes in the lateral direction 324 .

[0051] exist Figure 3B and Figure 3C In the example of FIG. 3 , each of electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 is shown as a continuous metal line extending in the lateral direction 322. However, it should be understood that electrodes 340-1, 340-2, 340-3, 345-1, and 345-2 are not limited to Figure 3B and 3C , and the electrodes 340 - 1 , 340 - 2 , 340 - 3 , 345 - 1 , and 345 - 2 may have other shapes.

[0052] It should be understood that any reference to an element using names such as "first", "second", etc. herein generally does not limit the number or order of these elements. Instead, these names are used herein as a convenient way to distinguish two or more elements or element instances. For example, the fourth vias 350-1, 350-2, and 350-3 and the fifth vias 355-1 and 355-2 may also be referred to as the first via and the second via, respectively (e.g., for an implementation in which transistor 110 is omitted). In addition, the first vias 320- and 320-2, the second vias 325-1 and 325-2, and the third vias 330-1 and 330-2 may also be referred to as the third via, the fourth via, and the fifth via, respectively.

[0053] Figure 4A An exemplary top view of transistor 110 and second transistor 410 is shown according to certain aspects. In the following discussion, transistor 110 is referred to as first transistor 110 and gate 115 is referred to as first gate.

[0054] The first transistor 110 is discussed above according to various aspects. Therefore, for the sake of brevity, the description of the first transistor 110 is not repeated here. In some aspects, the second transistor 410 can be an independent instance (i.e., a copy) of the transistor 110. However, it should be understood that this is not necessarily the case. As further discussed below, according to certain aspects, the finger capacitor can be formed above the first transistor 110 and the second transistor 410. It should be understood that in some implementations, the first transistor 110 and the second transistor 410 can be combined into a multi-gate transistor (also known as a multi-finger transistor).

[0055] In this example, the second transistor 410 includes an active region 412. For the example of implementing the second transistor 410 with a FinFET, the active region 412 includes a fin extending in the lateral direction 322 (e.g., similar to Figure 2A and Figure 2B For the example in which the first transistor 110 and the second transistor 410 are combined into a multi-gate transistor, the active region 412 may be combined with the active region 310 into one active region.

[0056] The second transistor 410 further includes a third source / drain contact 418-1, a fourth source / drain contact 418-2, and a second gate 415. The third source / drain contact 418-1 may be formed on the first source / drain of the second transistor 410, and the fourth source / drain contact 418-2 may be formed on the second source / drain of the second transistor 410. The second gate 415 is located between the third source / drain contact 418-1 and the fourth source / drain contact 418-2. Figure 4A In the example of FIG. 4 , the third source / drain contact 418 - 1 , the fourth source / drain contact 418 - 2 , and the second gate 415 are parallel to each other and extend in the lateral direction 324 .

[0057] Figure 4A Also shown are fourth vias 420-1 and 420-2 coupled to the second gate 415. For an example where the second gate contact is formed on the second gate 415, the fourth vias 420-1 and 420-2 may be coupled to the second gate 415 through the gate contact. Figure 4A Also shown are fifth vias 425-1 and 425-2 coupled to the third source / drain contact 418-1 and sixth vias 430-1 and 430-2 coupled to the fourth source / drain contact 418-2. For example, the fifth vias 425-1 and 425-2 may be disposed on the third source / drain contact 418-1, and the sixth vias 430-1 and 430-2 may be disposed on the fourth source / drain contact 418-2.

[0058] Figure 4BAn example of a finger capacitor 435 formed by a metal layer M0 according to certain aspects is shown. In this example, the metal layer M0 is patterned to form first electrodes 440-1 to 440-6 and second electrodes 445-1 and 445-2 (e.g., using a photolithography process and an etching process that patterns the metal layer M0 into separate electrodes). The electrodes 440-1 to 440-6, 445-1, and 445-2 are elongated and extend in the lateral direction 322. As discussed further below, the first electrodes 440-1 to 440-6 are coupled to a first terminal of the capacitor 435, and the second electrodes 445-1 and 445-2 are coupled to a second terminal of the capacitor 435.

[0059] In this example, first electrodes 440-1 and 440-2 are aligned in the lateral direction 324 and separated by a first gap 456 (i.e., spacing) in the lateral direction 322, first electrodes 440-3 and 440-4 are aligned in the lateral direction 324 and separated by a second gap 457 in the lateral direction 322, and first electrodes 440-5 and 440-6 are aligned in the lateral direction 324 and separated by a third gap 458 in the lateral direction 322. In other words, gaps 456, 457, and 458 separate first electrodes 440-1, 440-3, and 440-5 from first electrodes 440-2, 440-4, and 440-6 in the lateral direction 322. Gaps 456, 457, and 458 may have substantially the same length in the lateral direction 322. As discussed further below, gaps 456, 457, and 458 may be used to increase capacitance density while complying with design rules for chip layout. It should be understood that the gap between the two electrodes may be filled with a dielectric material (eg, oxide). In other words, a dielectric material may be disposed between the first electrodes 440-1 and 440-2, between the first electrodes 440-3 and 440-4, and between the first electrodes 440-5 and 440-6.

[0060] exist Figure 4B In the example, the second electrode 445-1 extends in the lateral direction 322, wherein a first portion of the second electrode 445-1 is between the first electrodes 440-1 and 440-3, a second portion of the second electrode 445-1 is between the first electrodes 440-2 and 440-4, and a third portion 447-1 of the second electrode 445-1 is between the second electrode 445-1 and the first portion and the second portion.

[0061] The second electrode 445-2 extends in the lateral direction 322, wherein a first portion of the second electrode 445-2 is between the first electrodes 440-3 and 440-5, a second portion of the second electrode 445-2 is between the first electrodes 440-4 and 440-6, and a third portion 447-2 of the second electrode 445-2 is between the first portion and the second portion of the second electrode 445-2.

[0062] exist Figure 4B In the example of , the first electrodes 440-1 and 440-5 are coupled to the first gate 115 through the first vias 320-1 and 320-2, wherein each of the first vias 320-1 and 320-2 is coupled between the first gate 115 and a corresponding one of the first electrodes 440-1 and 440-5. Figure 4B , the vias below the metal layer M0 are shown with dots. The second electrodes 445-1 and 445-2 are coupled to the first source / drain contact 130-1 through the second vias 325-1 and 325-2, wherein each of the second vias 325-1 and 325-2 is coupled between the first source / drain contact 130-1 and a corresponding one of the second electrodes 445-1 and 445-2. The second electrodes 445-1 and 445-2 are coupled to the second source / drain contact 130-2 through the third vias 330-1 and 330-2, wherein each of the third vias 330-1 and 330-2 is coupled between the second source / drain contact 130-2 and a corresponding one of the second electrodes 445-1 and 445-2.

[0063] exist Figure 4B In the example of FIG. 1 , the first electrodes 440-2 and 440-6 are coupled to the second gate 415 through the fourth vias 420-1 and 420-2, wherein each of the fourth vias 420-1 and 420-2 is coupled between the second gate 415 and a corresponding first electrode of the first electrodes 440-2 and 440-6. The second electrodes 445-1 and 445-2 are coupled to the third source / drain contact 418-1 through the fifth vias 425-1 and 425-2, wherein each of the fifth vias 425-1 and 425-2 is coupled between the third source / drain contact 418-1 and a corresponding second electrode of the second electrodes 445-1 and 445-2. The second electrodes 445-1 and 445-2 are coupled to the fourth source / drain contact 418-2 through sixth vias 430-1 and 430-2, wherein each of the sixth vias 430-1 and 430-2 is coupled between the fourth source / drain contact 418-2 and a corresponding one of the second electrodes 445-1 and 445-2.

[0064] Figure 4BAlso shown are examples of seventh vias 450-1 to 450-6, where each of the seventh vias 450-1 to 450-6 is coupled to a corresponding one of the first electrodes 440-1 to 440-6. For example, each of the seventh vias 450-1 to 450-6 may be disposed on a corresponding one of the first electrodes 440-1 to 440-6.

[0065] exist Figure 4B In the example shown in , the seventh vias 450-1, 450-3 and 450-5 are aligned in the lateral direction 322, and the seventh vias 450-2, 450-4 and 450-6 are aligned in the lateral direction 322. Each of the seventh vias 450-1, 450-3 and 450-5 is disposed on a portion of the corresponding first electrode 440-1, 450-3 and 450-5 extending beyond the boundary of the active area 310 of the first transistor 110. In addition, each of the seventh vias 450-2, 450-4 and 450-6 is disposed on a portion of the corresponding first electrode 440-2, 440-4 and 440-6 extending beyond the boundary of the active area 412 of the second transistor 410. However, it should be understood that the present disclosure is not limited to this example.

[0066] Figure 4B An example of the eighth vias 455-1 to 455-4 is also shown, where the eighth vias 455-1 and 455-2 are coupled to the second electrode 445-1 and the eighth vias 455-3 and 455-4 are coupled to the second electrode 445-2. In this example, the eighth vias 455-1 and 455-2 are disposed on the third portion 447-1 of the second electrode 445-1. In addition, the eighth vias 455-3 and 455-4 are disposed on the third portion 447-2 of the second electrode 445-2.

[0067] like Figure 4B As shown in FIG. 3 , the interval between the first electrodes 440-1 to 440-6 and the second electrodes 445-1 and 445-2 is s1 in the lateral direction 324. However, due to the gaps 456, 457, and 458 separating the first electrodes 440-1, 440-3, and 440-5 from the first electrodes 440-2, 440-4, and 440-6, the interval between the eighth via holes 455-1 to 455-4 and the first electrodes 440-1 to 440-6 may be s2, where s2 is greater than s1 (i.e., s2>s1), as shown in FIG. Figure 4B456, 457, and 458. Thus, the gaps 456, 457, and 458 increase the spacing (i.e., distance) between the eighth vias 455-1 to 455-4 and the first electrodes 440-1 to 440-6. Without the gaps 456, 457, and 458, the spacing between the eighth vias 455-1 to 455-4 and the first electrodes 440-1 to 440-6 would be s1. The increased spacing between the eighth vias 455-1 to 455-4 and the first electrodes 440-1 to 440-6 allows the first electrodes 440-1 to 440-6 and the second electrodes 445-1 and 445-2 to be spaced closer to obtain a higher capacitance density while still complying with design rules, as discussed further below.

[0068] In some aspects, the layout of the chip can be managed by the design rules provided by the foundry or another entity. The design rules can be specific to the manufacturing process used to manufacture the chip 100. For example, the design rules can define the minimum spacing between the vias (e.g., the eighth vias 455-1 to 455-4) on the second electrodes 445-1 and 445-2 and the first electrodes 440-1 to 440-6. For example, the minimum spacing can be defined to prevent the vias from accidentally shorting the second electrodes 445-1 and 445-2 to the first electrodes 440-1 to 440-6 due to process variations. In this example, the design rules can allow the spacing between the eighth vias 455-1 to 455-4 and the first electrodes 440-1 to 440-6 to be equal to or greater than the minimum spacing but not less than the minimum spacing. During chip layout, the placement of the eighth vias 455-1 to 455-4 relative to the first electrodes 440-1 to 440-6 can be checked during a period called design rule checking (DRC) to see if it complies with the design rules. DRC helps ensure that chip layout complies with design rules.

[0069] In this example, the interval s2 between the eighth vias 455-1 to 455-4 and the first electrodes 440-1 to 440-6 can be approximately equal to the minimum interval defined by the design rule to comply with the design rule. Since the interval s1 between the first electrodes 440-1 to 440-6 and the second electrodes 445-1 and 445-2 is less than the interval s2, the interval s1 between the first electrodes 440-1 to 440-6 and the second electrodes 445-1 and 445-2 can be less than the minimum interval defined by the design rule while still complying with the design rule. The smaller (i.e., closer) interval between the first electrodes 440-1 to 440-6 and the second electrodes 445-1 and 445-2 increases the capacitance density of the finger capacitor 435. Therefore, the gaps 456, 457 and 458 allow the first electrodes 440-1 to 440-6 and the second electrodes 445-1 and 445-2 to be spaced closer to obtain a higher capacitance density.

[0070] Figure 4CA first metal wiring 460, a second metal wiring 462, a third metal wiring 464, and a fourth metal wiring 466 formed from a metal layer M1 are shown (eg, a photolithography process and an etching process are used to pattern the metal layer M1 into metal wirings). Figure 3C In the example shown in , each of metal wirings 460, 462, 464, and 466 is elongated and extends in lateral direction 324. It should be understood that metal wirings 460, 462, 464, and 466 may also be used as electrodes for capacitors formed above finger capacitors 435.

[0071] In this example, each of the seventh vias 450-1, 450-3, and 450-5 is coupled between a corresponding one of the first electrodes 440-1, 440-3, and 440-5 and the first metal wiring 460. Therefore, in this example, the first electrodes 440-1, 440-3, and 440-5 are coupled together through the first metal wiring 460. Each of the seventh vias 450-2, 450-4, and 450-6 is coupled between a corresponding one of the first electrodes 440-2, 440-4, and 440-6 and the second metal wiring 462. Therefore, in this example, the first electrodes 440-2, 440-4, and 440-6 are coupled together through the second metal wiring 462.

[0072] Each of the eighth vias 455-1 and 455-3 is coupled between a corresponding one of the second electrodes 445-1 and 445-2 and the third metal wiring 464, and each of the eighth vias 455-2 and 455-4 is coupled between a corresponding one of the second electrodes 445-1 and 445-2 and the fourth metal wiring 466. Therefore, the second electrodes 445-1 and 445-2 are coupled together through the third metal wiring 464 and the fourth metal wiring 466. In this example, the third metal wiring 464 and the fourth metal wiring 466 extend across the gaps 456, 457, and 458 in the lateral direction 324.

[0073] Figure 4D A fifth metal wiring 480 and a sixth metal wiring 485 formed from the metal layer M2 are shown (eg, a photolithography process and an etching process to pattern the metal layer M2 into the metal wiring). Figure 3C In the example shown in , each of metal wirings 480 and 485 is elongated and extends in lateral direction 322. It should be understood that metal wirings 480 and 485 may also serve as electrodes of capacitors formed over finger capacitors 435.

[0074] In this example, the fifth metal wiring 480 extends from the first metal wiring 460 to the second metal wiring 462. The fifth metal wiring 480 is coupled to the first metal wiring 460 through a via 472, which is coupled between the first metal wiring 460 and the fifth metal wiring 480. The fifth metal wiring 480 is also coupled to the second metal wiring 462 through a via 474, which is coupled between the second metal wiring 462 and the fifth metal wiring 480. Therefore, in this example, the first metal wiring 460 is coupled to the second metal wiring 462 through the fifth metal wiring 480. Therefore, the first electrodes 440-1 to 440-6 are coupled together through the first metal wiring 460, the second metal wiring 462, and the fifth metal wiring 480. In this regard, in this example, the first metal wiring 460, the second metal wiring 462, and / or the fifth metal wiring 480 can be considered as the first terminal of the finger capacitor 435. However, it should be understood that the present disclosure is not limited to this example.

[0075] The sixth metal wiring 485 is coupled to the third metal wiring 464 through a via 476, which is coupled between the third metal wiring 464 and the sixth metal wiring 485. The sixth metal wiring 485 is also coupled to the fourth metal wiring 466 through a via 478, which is coupled between the fourth metal wiring 466 and the sixth metal wiring 485. Therefore, in this example, the third metal wiring 464 is coupled to the fourth metal wiring 466 through the sixth metal wiring 485. Therefore, the second electrodes 445-1 and 445-2 are coupled together through the third metal wiring 464, the fourth metal wiring 466, and the sixth metal wiring 485. In this regard, the third metal wiring 464, the fourth metal wiring 466, and / or the sixth metal wiring 485 can be considered as the second terminal of the finger capacitor 435. However, it should be understood that the present disclosure is not limited to this example.

[0076] Figure 5 An example of a finger capacitor 535 formed by metal layer M1 according to certain aspects is shown. Finger capacitor 535 can be formed above finger capacitor 435 and can be coupled in parallel with finger capacitor 435. It should be noted that for ease of illustration, Figure 5 Finger capacitor 435 is not shown in the figure.

[0077] In this example, the finger capacitor 535 includes third electrodes 510-1 to 510-8 and fourth electrodes 530-1 to 530-10. For example, the electrodes 510-1 to 510-8 and 530-1 to 530-10 may be formed using a photolithography process and an etching process for patterning the metal layer M1 into respective electrodes. Figure 5In the example shown in FIG. 3 , the electrodes 510-1 to 510-8 and 530-1 to 530-10 are elongated and extend in the lateral direction 324. The third electrodes 510-1 to 510-8 may be interleaved with the fourth electrodes 530-1 to 530-10.

[0078] In some aspects, the third electrodes 510-1 and 510-8 may correspond to the first metal wiring 460 and the second metal wiring 462, respectively. Figure 5 Similarly, Figure 5 As shown, the fourth electrodes 530-5 and 530-6 may correspond to the third metal wiring 464 and the fourth metal wiring 466. However, it should be understood that the present disclosure is not limited to this example.

[0079] Figure 5 Ninth vias 520-1 to 520-8 are shown, wherein each of the ninth vias 520-1 to 520-8 is coupled between a corresponding one of the third electrodes 510-1 to 510-8 and the fifth metal wiring 480. Thus, in this example, the third electrodes 510-1 to 510-8 are coupled together through the fifth metal wiring 480. In this aspect, the fifth metal wiring 480 can be considered as a first terminal of the finger capacitor 535.

[0080] Figure 5 Tenth vias 540-1 to 540-10 are also shown, wherein each of the tenth vias 540-1 to 540-10 is coupled between a corresponding one of the fourth electrodes 530-1 to 510-10 and the sixth metal wiring 485. Thus, in this example, the fourth electrodes 530-1 to 530-10 are coupled together through the sixth metal wiring 485. In this aspect, the sixth metal wiring 485 can be considered as a second terminal of the finger capacitor 535.

[0081] Figure 6 An example of a finger capacitor 635 formed by a metal layer M2 according to certain aspects is shown. In this example, the metal layer M2 is patterned to form fifth electrodes 640-1 to 640-6 and sixth electrodes 645-1 and 645-2 (e.g., using a photolithography process and an etching process that patterns the metal layer M2 into separate electrodes). The electrodes 640-1 to 640-6, 645-1, and 645-2 are elongated and extend in the lateral direction 322.

[0082] In this example, fifth electrodes 640-1 and 640-2 are aligned in the lateral direction 324 and separated by a first gap 656 (i.e., spacing) in the lateral direction 322, fifth electrodes 640-3 and 640-4 are aligned in the lateral direction 324 and separated by a second gap 657 in the lateral direction 322, and fifth electrodes 640-5 and 640-6 are aligned in the lateral direction 324 and separated by a third gap 658 in the lateral direction 322. Gaps 656, 657, and 658 may have substantially the same length in the lateral direction 322.

[0083] exist Figure 6 In the example, the sixth electrode 645-1 extends in the lateral direction 322, wherein a first portion of the sixth electrode 645-1 is between the fifth electrodes 640-1 and 640-3, a second portion of the sixth electrode 645-1 is between the fifth electrodes 640-2 and 640-4, and a third portion of the sixth electrode 645-1 is between the first portion and the second portion.

[0084] The sixth electrode 645-2 extends in the lateral direction 322, wherein a first portion of the sixth electrode 645-2 is between the fifth electrodes 640-3 and 640-5, a second portion of the sixth electrode 645-2 is between the fifth electrodes 640-4 and 640-6, and a third portion of the sixth electrode 645-2 is between the first portion and the second portion.

[0085] exist Figure 6 In the example of FIG. 1 , the fifth electrodes 640-1, 640-3, and 640-5 are coupled to the first metal wiring 460 through the vias 650-1, 650-3, and 650-5, respectively, wherein each of the vias 650-1, 650-3, and 650-5 is coupled between a corresponding one of the fifth electrodes 640-1, 640-3, and 640-5 and the first metal wiring 460. The fifth electrodes 640-2, 640-4, and 640-6 are coupled to the second metal wiring 462 through the vias 650-2, 650-4, and 650-6, respectively, wherein each of the vias 650-2, 650-4, and 650-6 is coupled between a corresponding one of the fifth electrodes 640-2, 640-4, and 640-6 and the second metal wiring 462. In this example, the first metal wiring 460 and the second metal wiring 462 are coupled through the fifth metal wiring 480. Therefore, in this example, the fifth electrodes 640-1 to 640-6 are coupled together through the first metal wiring 460, the second metal wiring 462, and the fifth metal wiring 480.

[0086] The sixth electrode 645-1 is coupled to the third metal wiring 464 and the fourth metal wiring 466 through vias 655-1 and 655-2, respectively, wherein the via 655-1 is coupled between the sixth electrode 645-1 and the third metal wiring 464, and the via 655-2 is coupled between the sixth electrode 645-1 and the fourth metal wiring 466. The sixth electrode 645-2 is coupled to the third metal wiring 464 and the fourth metal wiring 466 through vias 655-3 and 655-4, respectively, wherein the via 655-3 is coupled between the sixth electrode 645-2 and the third metal wiring 464, and the via 655-4 is coupled between the sixth electrode 645-2 and the fourth metal wiring 466. The third metal wiring 464 and the fourth metal wiring 466 are coupled through the sixth metal wiring 485. Thus, in this example, the sixth electrodes 645 - 1 and 645 - 2 are coupled together through the third metal wiring 464 , the fourth metal wiring 466 , and the sixth metal wiring 485 .

[0087] As discussed above, capacitors can be used as decoupling capacitors. In this regard, Figure 7 A circuit diagram of a decoupling capacitor 735 that can be implemented with any of the capacitors 335, 435, 535, and / or 635 is shown. One terminal 740 of the capacitor 735 is coupled to a voltage supply rail 720 (also referred to as a power rail) that supplies a power supply voltage Vdd, and the other terminal 745 of the capacitor 735 is coupled to a lower rail 730 that is lower in potential than the supply rail 720. For example, the lower rail 730 can be coupled to ground. When the capacitor 735 is implemented with any of the capacitors 335, 435, 535, and / or 635, the terminal 740 coupled to the supply rail 720 can correspond to the first terminal discussed above, and the terminal 745 coupled to the ground rail 730 can correspond to the second terminal discussed above, or vice versa. However, it should be understood that the present disclosure is not limited to this example, and the capacitors discussed above according to various aspects can be used in other applications.

[0088] Examples of implementations are described in the following numbered clauses:

[0089] 1. A chip, comprising:

[0090] A first capacitor comprising:

[0091] first electrodes formed of the metal layer M0, wherein the first electrodes are coupled to each other; and

[0092] The second electrodes are formed by the metal layer M0, wherein the second electrodes are coupled to each other.

[0093] 2. The chip according to clause 1, wherein the first electrode and the second electrode are staggered.

[0094] 3. A chip according to clause 1 or 2, wherein the first capacitor is above one or more transistors.

[0095] 4. A chip according to clause 3, wherein:

[0096] The first electrode is coupled to one or more gates of one or more transistors; and

[0097] The second electrode is coupled to one or more source / drain contacts of the one or more transistors.

[0098] 5. A chip according to any one of clauses 1 to 4, further comprising:

[0099] a first metal wiring formed of the metal layer M1, wherein the first electrodes are coupled to each other through the first metal wiring; and

[0100] A second metal wiring is formed of the metal layer M1, wherein the second electrodes are coupled to each other through the second metal wiring.

[0101] 6. A chip according to any of clauses 1 to 5, wherein each of the first electrodes and each of the second electrodes comprises a respective metal wire.

[0102] 7. The chip according to any of clauses 1 to 6, further comprising a second capacitor formed by metal layer M1, wherein the second capacitor is coupled in parallel with the first capacitor.

[0103] 8. A chip according to any one of clauses 1 to 7, wherein:

[0104] Each of the first electrodes and each of the second electrodes extends in a first direction;

[0105] A first one of the first electrodes and a second one of the first electrodes are separated in a first direction by a first gap; and

[0106] A third one of the first electrodes and a fourth one of the first electrodes are separated in the first direction by a second gap.

[0107] 9. A chip according to clause 8, wherein:

[0108] a first portion of one of the second electrodes is between a first one of the first electrodes and a third one of the first electrodes; and

[0109] The second portion of one of the second electrodes is between a second one of the first electrodes and a fourth one of the first electrodes.

[0110] 10. The chip of clause 9, wherein each of the first electrodes and each of the second electrodes comprises a respective metal line.

[0111] 11. The chip according to clause 9 or 10 further includes one or more vias, which are arranged on the third part of one of the second electrodes, wherein the third part of one of the second electrodes is between the first part of one of the second electrodes and the second part of one of the second electrodes.

[0112] 12. The chip according to clause 11, further comprising:

[0113] A first metal wiring formed of a metal layer M1, wherein the first metal wiring is coupled to a first first electrode among the first electrodes and a third first electrode among the first electrodes;

[0114] a second metal wiring formed of the metal layer M1, wherein the second metal wiring is coupled to a second one of the first electrodes and a fourth one of the first electrodes; and

[0115] A third metal wiring is formed by the metal layer M1, wherein the one or more vias are coupled between one of the second electrodes and the third metal wiring.

[0116] 13. The chip according to clause 12, wherein each of the first metal wiring, the second metal wiring, and the third metal wiring extends in a second direction, and the second direction is perpendicular to the first direction.

[0117] 14. The chip according to clause 12 or 13, further comprising a fourth metal wiring formed by the metal layer M2, wherein the fourth metal wiring is coupled to the first metal wiring and the second metal wiring.

[0118] 15. A chip according to any one of clauses 12 to 14, wherein:

[0119] The first metal wiring and the third metal wiring are located on opposite sides of the first gate; and

[0120] The third metal wiring and the second metal wiring are located on opposite sides of the second gate.

[0121] 16. The chip according to clause 15, wherein each of the first metal wiring, the second metal wiring, the third metal wiring, the first gate, and the second gate extends in a second direction, and the second direction is perpendicular to the first direction.

[0122] 17. A chip, comprising:

[0123] Capacitors, including:

[0124] first electrodes, wherein the first electrodes are coupled to each other, each of the first electrodes extends in a first direction, a first one of the first electrodes and a second one of the first electrodes are separated by a first gap in the first direction, and a third one of the first electrodes and a fourth one of the first electrodes are separated by a second gap in the first direction; and

[0125] The second electrodes are coupled to each other and each of the second electrodes extends in the first direction.

[0126] 18. A chip according to clause 17, wherein:

[0127] a first portion of one of the second electrodes is between a first one of the first electrodes and a third one of the first electrodes; and

[0128] The second portion of one of the second electrodes is between a second one of the first electrodes and a fourth one of the first electrodes.

[0129] 19. The chip of clause 18, wherein each of the first electrodes and each of the second electrodes comprises a respective metal line.

[0130] 20. The chip according to clause 18 or 19 further includes one or more vias, which are arranged on the third portion of one of the second electrodes, wherein the third portion of one of the second electrodes is between the first portion of one of the second electrodes and the second portion of one of the second electrodes.

[0131] 21. The chip according to clause 20, further comprising:

[0132] a first metal wiring coupled to a first one of the first electrodes and a third one of the first electrodes;

[0133] a second metal wiring coupled to a second one of the first electrodes and a fourth one of the first electrodes; and

[0134] A third metal, wherein one or more vias are coupled between one of the second electrodes and the third metal wiring.

[0135] 22. The chip of clause 21, wherein each of the first metal wiring, the second metal wiring, and the third metal wiring extends in a second direction, and the second direction is perpendicular to the first direction.

[0136] 23. The chip according to clause 21 or 22, further comprising a fourth metal wiring, wherein the fourth metal wiring is coupled to the first metal wiring and the second metal wiring.

[0137] 24. A chip according to any of clauses 21 to 23, wherein:

[0138] The first metal wiring and the third metal wiring are located on opposite sides of the first gate; and

[0139] The third metal wiring and the second metal wiring are located on opposite sides of the second gate.

[0140] 25. The chip of clause 24, wherein each of the first metal wiring, the second metal wiring, the third metal wiring, the first gate, and the second gate extends in a second direction, and the second direction is perpendicular to the first direction.

[0141] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled," as used herein, refers to a direct or indirect electrical coupling between two structures.

[0142] The foregoing description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip, comprising: A first capacitor comprising: first electrodes formed of the metal layer M0, wherein the first electrodes are coupled to each other; and The second electrodes are formed by the metal layer M0, wherein the second electrodes are coupled to each other. 2 . The chip according to claim 1 , wherein the first electrode and the second electrode are staggered. The chip according to claim 1 , wherein the first capacitor is above one or more transistors.

4. The chip according to claim 3, wherein: The first electrode is coupled to one or more gates of the one or more transistors; and The second electrode is coupled to one or more source / drain contacts of the one or more transistors.

5. The chip according to claim 1, further comprising: a first metal wiring formed of a metal layer M1, wherein the first electrodes are coupled to each other through the first metal wiring; as well as A second metal wiring is formed by the metal layer M1, wherein the second electrodes are coupled to each other through the second metal wiring. 6 . The chip according to claim 1 , wherein each of the first electrodes and each of the second electrodes comprises a corresponding metal wire. 7 . The chip of claim 1 , further comprising a second capacitor formed by metal layer M1 , wherein the second capacitor is coupled in parallel with the first capacitor.

8. The chip according to claim 1, wherein: Each of the first electrodes and each of the second electrodes extends in a first direction; A first first electrode among the first electrodes and a second first electrode among the first electrodes are separated by a first gap in the first direction; and A third one of the first electrodes and a fourth one of the first electrodes are separated by a second gap in the first direction.

9. The chip according to claim 8, wherein: A first portion of one of the second electrodes is between the first one of the first electrodes and the third one of the first electrodes; and The second portion of the one of the second electrodes is between the second one of the first electrodes and the fourth one of the first electrodes. 10 . The chip according to claim 9 , wherein each of the first electrodes and each of the second electrodes comprises a corresponding metal wire.

11. The chip according to claim 9 further includes one or more vias, wherein the one or more vias are arranged on the third portion of the one of the second electrodes, wherein the third portion of the one of the second electrodes is between the first portion of the one of the second electrodes and the second portion of the one of the second electrodes.

12. The chip according to claim 11, further comprising: a first metal wiring formed of a metal layer M1, wherein the first metal wiring is coupled to the first one of the first electrodes and the third one of the first electrodes; a second metal wiring formed by the metal layer M1, wherein the second metal wiring is coupled to the second first electrode among the first electrodes and the fourth first electrode among the first electrodes; as well as A third metal wiring is formed by the metal layer M1, wherein the one or more vias are coupled between the one of the second electrodes and the third metal wiring. 13 . The chip according to claim 12 , wherein each of the first metal wiring, the second metal wiring, and the third metal wiring extends in a second direction, and the second direction is perpendicular to the first direction. 14 . The chip according to claim 12 , further comprising a fourth metal wiring formed of a metal layer M2 , wherein the fourth metal wiring is coupled to the first metal wiring and the second metal wiring.

15. The chip according to claim 12, wherein: The first metal wiring and the third metal wiring are located on opposite sides of the first gate; and The third metal wiring and the second metal wiring are located on opposite sides of the second gate. 16 . The chip according to claim 15 , wherein each of the first metal wiring, the second metal wiring, the third metal wiring, the first gate, and the second gate extends in a second direction, and the second direction is perpendicular to the first direction.

17. A chip, comprising: Capacitors, including: first electrodes, wherein the first electrodes are coupled to each other, each of the first electrodes extends in a first direction, a first first electrode of the first electrodes and a second first electrode of the first electrodes are separated by a first gap in the first direction, and a third first electrode of the first electrodes and a fourth first electrode of the first electrodes are separated by a second gap in the first direction; and second electrodes, wherein the second electrodes are coupled to each other and each of the second electrodes extends in the first direction.

18. The chip according to claim 17, wherein: A first portion of one of the second electrodes is between the first one of the first electrodes and the third one of the first electrodes; and The second portion of the one of the second electrodes is between the second of the first electrodes and the fourth of the first electrodes. 19 . The chip according to claim 18 , wherein each of the first electrodes and each of the second electrodes comprises a corresponding metal wire.

20. The chip according to claim 18 further includes one or more vias, wherein the one or more vias are arranged on the third portion of the one of the second electrodes, wherein the third portion of the one of the second electrodes is between the first portion of the one of the second electrodes and the second portion of the one of the second electrodes.

21. The chip according to claim 20, further comprising: a first metal wiring coupled to the first one of the first electrodes and the third one of the first electrodes; a second metal wiring coupled to the second of the first electrodes and the fourth of the first electrodes; as well as a third metal, wherein the one or more vias are coupled between the one of the second electrodes and the third metal wiring. 22 . The chip according to claim 21 , wherein each of the first metal wiring, the second metal wiring, and the third metal wiring extends in a second direction, and the second direction is perpendicular to the first direction. 23 . The chip of claim 21 , further comprising a fourth metal wiring, wherein the fourth metal wiring is coupled to the first metal wiring and the second metal wiring.

24. The chip according to claim 21, wherein: The first metal wiring and the third metal wiring are located on opposite sides of the first gate; and The third metal wiring and the second metal wiring are located on opposite sides of the second gate. 25 . The chip according to claim 24 , wherein each of the first metal wiring, the second metal wiring, the third metal wiring, the first gate, and the second gate extends in a second direction, and the second direction is perpendicular to the first direction.

Images