Dynamic amplifier with reduced sensitivity

Abstract

Techniques and apparatus for reducing sensitivity (e.g., smaller gain variations due to parasitic capacitance) in dynamic amplifiers. One example dynamic amplifier generally includes: a pair of differential input transistors; a pair of cross-coupled switches coupled between the pair of differential input transistors and a pair of differential output nodes of the dynamic amplifier; a first switch pair coupled between the differential input transistor pair and the differential output node pair; and a second switch pair coupled between the differential input transistor pair and the differential output node pair.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial number 17 / 821,115 filed on August 19, 2022, which is incorporated herein by reference. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic components and, more particularly, to dynamic amplifiers. Background Art

[0004] Electronic devices include computing devices such as desktop computers, notebook computers, tablet computers, smart phones, wearable devices (such as smart watches), Internet servers, etc. These different electronic devices provide information, entertainment, social, security, productivity, transportation, manufacturing and other services to human users. Many functions of these different electronic devices rely on wireless communications. Wireless communication systems and devices are widely deployed to provide various types of communication content, such as voice, video, packet data, messaging, broadcasting, etc. These systems may be able to support communication with multiple users by sharing available system resources (e.g., time, frequency and power). Examples of such systems include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, and orthogonal frequency division multiple access (OFDMA) systems (e.g., long term evolution (LTE) systems or new radio (NR) systems).

[0005] For example, wireless devices in these and other communication systems may include one or more analog-to-digital converters (ADCs) for converting received, amplified, filtered, and down-converted analog signals into digital signals for additional signal processing in the digital domain. There are a variety of types of ADCs to choose from, some of which are better suited to specific applications than others. For example, a successive approximation register (SAR) ADC provides an area and power efficient architecture for low to medium precision analog-to-digital conversion applications. A SAR ADC can use a digital-to-analog converter (DAC) and a comparator to approximate a digital value corresponding to an analog input. Another type of ADC called a flash ADC can provide faster conversion speeds than a SAR ADC, but at the expense of exponentially increased power and area consumption. Another type of ADC is called a pipeline ADC, which has a faster sampling rate than a SAR ADC but consumes less power and area than a flash ADC. Summary of the invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no one of which is solely responsible for its desired attributes. Without limiting the scope of the present disclosure as expressed by the appended claims, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description of the Invention," one should understand how the features of the present disclosure provide the advantages described herein.

[0007] Certain aspects of the present disclosure generally relate to dynamic amplifiers having reduced sensitivity to circuit non-idealities (eg, reduced gain variations due to parasitic capacitance), and to analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers.

[0008] Certain aspects of the present disclosure provide a dynamic amplifier. The dynamic amplifier generally includes: a differential input node pair, including a first input node and a second input node; a differential output node pair, including a first output node and a second output node; a first differential input transistor, having a gate coupled to the first input node and having a drain coupled to the first intermediate node; and a second differential input transistor, having a gate coupled to the second input node and having a drain coupled to the second intermediate node. The dynamic amplifier generally also includes: a first switch coupled between the first intermediate node and the first output node; a second switch coupled between the second intermediate node and the second output node; a third switch coupled between the first intermediate node and the second output node; a fourth switch coupled between the second intermediate node and the first output node; a fifth switch coupled between the first intermediate node and the second output node; and a sixth switch coupled between the second intermediate node and the first output node.

[0009] Certain aspects of the present disclosure provide a method for amplification using a dynamic amplifier. The dynamic amplifier generally includes: a differential input node pair, including a first input node and a second input node; a differential output node pair, including a first output node and a second output node; a first differential input transistor, having a gate coupled to the first input node and having a drain coupled to the first intermediate node; a second differential input transistor, having a gate coupled to the second input node and having a drain coupled to the second intermediate node; a first switch, coupled between the first intermediate node and the first output node; a second switch, coupled between the second intermediate node and the second output node; a third switch, coupled between the first intermediate node and the second output node; a fourth switch, coupled between the second intermediate node and the first output node; a fifth switch, coupled between the first intermediate node and the second output node; and a sixth switch, coupled between the second intermediate node and the first output node. The method generally includes charging a common source node of a first differential input transistor and a second differential input transistor during a first phase, the charging including closing a first switch, a second switch, a third switch, and a fourth switch, wherein a fifth switch and a sixth switch are opened; and amplifying a voltage difference between a first input signal at the first input node and a second input signal at the second input node during a second phase following the first phase, the amplifying including opening the first switch and the second switch and closing the fifth switch and the sixth switch, wherein the third switch and the fourth switch are closed during the second phase.

[0010] Certain aspects of the present disclosure provide a dynamic amplifier. The dynamic amplifier generally includes: a differential input transistor pair; a cross-coupled switch pair coupled between the differential input transistor pair and a differential output node pair of the dynamic amplifier; a first switch pair coupled between the differential input transistor pair and the differential output node pair; and a second switch pair coupled between the differential input transistor pair and the differential output node pair.

[0011] Certain aspects of the present disclosure provide an ADC. The ADC generally includes a dynamic amplifier as described herein and a conversion stage configured to generate a digital output and a residual voltage, wherein the dynamic amplifier is coupled to the conversion stage and configured to amplify the residual voltage.

[0012] To achieve the foregoing and related ends, one or more aspects include features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative features of one or more aspects. However, these features are only indicative of a few of the various ways in which the principles of the various aspects can be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to be able to understand in detail the manner of the above-mentioned features of the present disclosure, the more specific description of the above invention content can refer to the multiple aspects of some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate certain aspects of the present disclosure and therefore should not be considered as limiting its scope, because this description may admit to other equally effective aspects.

[0014] Figure 1 is a block diagram of an example pipeline analog-to-digital converter (ADC) in which various aspects of the present disclosure may be practiced.

[0015] Figure 2A is a circuit diagram of an example dynamic amplifier in which various aspects of the present disclosure may be practiced.

[0016] Figure 2B yes Figure 2A Timing diagram of the dynamic amplifier.

[0017] Figure 3A is a circuit diagram of an example dynamic amplifier having a plurality of parallel switches including the cross-coupled switch pair according to certain aspects of the present disclosure.

[0018] Figure 3B yes Figure 3A Timing diagram of the dynamic amplifier.

[0019] Figure 4 is a flow chart depicting example operations for amplifying with a dynamic amplifier in accordance with certain aspects of the present disclosure.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0021] Certain aspects of the present disclosure generally relate to dynamic amplifiers with reduced sensitivity to circuit non-idealities, and to analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. For example, certain aspects provide a dynamic amplifier with reduced gain variation due to parasitic capacitance.

[0022] During amplification of some dynamic amplifiers, such parasitic capacitance may take charge from the output load capacitance, thereby changing the gain of the dynamic amplifier (and reducing linearity). By introducing multiple parallel cascode switches (one differential pair with a cross-coupled configuration) into the dynamic amplifier and charging the parasitic capacitance for a short time before amplification, the parasitic capacitance can be effectively pre-charged and does not take charge (or at least takes less charge) from the output load capacitance during amplification. Therefore, such a dynamic amplifier can reduce sensitivity to parasitic capacitance and thus provide reduced gain variation, which can enhance the performance of ADCs and other circuits that employ such dynamic amplifiers. With a cross-coupled configuration, this solution has no significant impact on the differential output of the dynamic amplifier.

[0023] Example Pipeline Analog-to-Digital Converter with Dynamic Amplifier

[0024] The pipeline ADC can be used for high-performance analog-to-digital conversion in a device, such as in the receive chain of a transceiver in a fifth generation (5G) (or other radio access technology) wireless device. For example, the pipeline ADC can be used at sampling rates of several megasamples per second (Msps) to 1000Msps+.

[0025] Figure 1 An example pipeline ADC 100 is illustrated in which various aspects of the present disclosure may be practiced. The pipeline ADC 100 includes at least an ADC 102 (e.g., a first ADC), a digital-to-analog converter (DAC) 104, an analog combiner 106, a residue amplifier 108, and an ADC 110 (e.g., a second ADC). Although the pipeline ADC 100 includes separate stages for generating a digital output and a digital residue, the reader should understand that the pipeline ADC may include more than one stage, where the analog residue from one stage is input as an analog input to the next stage. In this case, the residue amplifier 108 may also be referred to as an "inter-stage amplifier." The pipeline ADC 100 may also include a digital combiner 120 for combining the output of one or more stages and the digital residue from the ADC 110 and generating a digital output (labeled "D 输出 ”). Although illustrated as a differential pipeline ADC, ADC 100 may alternatively be implemented as a single-ended pipeline ADC.

[0026] ADC 102 and DAC 104 may constitute a conversion stage of pipeline ADC 100 configured to generate a digital output and a residual voltage. ADC 102 has an input coupled to a differential input pair (e.g., an input node) and receives an analog input (e.g., a differential input voltage signal). ADC 102 may be a relatively low-resolution ADC and may be implemented by a flash ADC or any other suitable type of ADC. ADC 102 generates a digital output (e.g., a single-ended stage 1 output) based on the analog input. DAC 104 has an input coupled to the output of ADC 102, which receives the digital output of ADC 102 as an input. DAC 104 regenerates the digital input received from ADC 102 as an analog voltage (differential voltage) on another differential pair.

[0027] Analog combiner 106 has a first input coupled to the differential input pair and the differential output of DAC 104. Analog combiner 106 outputs a residual voltage (also referred to as “residual”) based on the difference between the analog input and the analog voltage from DAC 104.

[0028] As shown, the residual amplifier 108 has an input coupled to the conversion stage via the output of the analog combiner 106, and is configured to receive the residual voltage as an input from the analog combiner 106. For some aspects, the residual amplifier 108 can be implemented as a dynamic amplifier circuit (with a dynamic amplifier), as described below. The residual amplifier 108 amplifies the residual voltage according to the gain of the residual amplifier. The ADC 110 has an input coupled to the output of the residual amplifier 108, and receives the output voltage from the residual amplifier 108 as an input. The ADC 110 can be implemented as a successive approximation register (SAR) ADC, a flash ADC, or any other suitable type of ADC. The ADC 110 generates a digital output (e.g., a digitized residual, but here marked as the second stage output) based on the output voltage received from the residual amplifier 108.

[0029] Although the residue amplifier 108 is important to the performance of the pipeline ADC, some implementations of the residue amplifier 108 may use a large amount of power to amplify the residue voltage. Dynamic amplifiers are relatively power efficient and, therefore, can be used as the residue amplifier 108 in the pipeline ADC 100.

[0030] although Figure 1A pipeline ADC in which certain aspects of the present disclosure may be implemented is provided as an example application for ease of understanding, but certain aspects described herein may be used for amplification and / or analog-to-digital conversion in any of a variety of other suitable systems. For example, the dynamic amplifiers described herein may be used in any circuit involving analog multiplication where the output is a capacitor (e.g., having a capacitive component), such as a switched capacitor filter, a class H audio amplifier, a delta-sigma converter, or a mixer (e.g., an RF mixer).

[0031] Example Dynamic Amplifier

[0032] Figure 2A is a circuit diagram of an example dynamic amplifier 200A in which various aspects of the present disclosure may be practiced. For example, the dynamic amplifier 200A may be used as a pipeline analog-to-digital converter (ADC) (e.g., Figure 1 A residual amplifier (e.g., residual amplifier 108) in the pipeline ADC 100).

[0033] As shown, the dynamic amplifier 200A has a differential input node pair 202a and 202b (collectively referred to herein as “differential input nodes 202”) coupled to the gates of a first differential input transistor 204a and a second differential input transistor 204b (collectively referred to herein as “differential input transistor 204”). A differential input voltage at the differential input node 202 (labeled “Vip” and “Vim” for positive and negative input voltages) may be input to the differential input transistor 204. The first differential input transistor 204a may have a gate coupled to a first intermediate node 220 (labeled “V x ”) and the second differential input transistor 204b may have a drain coupled to the second intermediate node 222 (with a voltage labeled “V y ” voltage). The sources of the differential input transistors 204 can be coupled together at a common source node 224.

[0034] The dynamic amplifier 200A also has a differential output node pair, including a first differential output node 206a and a second differential output node 206b (collectively referred to herein as “differential output nodes 206”), at which the dynamic amplifier generates differential output voltages (labeled “Vop” and “Vom” for positive and negative output voltages, respectively). The first capacitive element (e.g., labeled “C L1 ” load capacitor) can be coupled between the first differential output node 206a and a reference potential node (eg, electrical ground) of the dynamic amplifier 200A. Similarly, a second capacitive element (eg, labeled “C L2" " load capacitor) can be coupled between the second differential output node 206b and the reference potential node. Although the capacitive element can be referred to as a capacitor C L1 and C L2 , but C L1 and C L2 May also refer to the corresponding capacitance of a capacitive element.

[0035] The dynamic amplifier 200A may also include a first pre-charge switch 208a and a second pre-charge switch 208b (collectively referred to herein as "pre-charge switch 208"). As shown in the figure, the first pre-charge switch 208a can be coupled between a power rail (labeled "VDD") and a second differential output node 206b, and the second pre-charge switch 208b can be coupled between the power rail and the first differential output node 206a. As shown in the figure, the pre-charge switch 208 can be implemented by a transistor (e.g., a p-type field effect transistor (PFET)). The pre-charge switch 208 can have control inputs (e.g., gates of transistors implementing the pre-charge switch 208) coupled together at a control node 210 having a control voltage labeled "pre_chrg".

[0036] The dynamic amplifier 200A may also include a first amplifying switch 212a and a second amplifying switch 212b (collectively referred to herein as "amplifying switches 212"). As shown in the figure, the first amplifying switch 212a may be coupled between the second differential output node 206b and the first intermediate node 220, and the second amplifying switch 212b may be coupled between the first differential output node 206a and the second intermediate node 222. Since the amplifying switch 212 is cascode coupled with the input transistor 204, the amplifying switch 212 may be referred to as a "cascode device". The amplifying switch 212 may be implemented by a transistor (e.g., an n-type field effect transistor (NFET) as shown in the figure), wherein the drain of the transistor is coupled to the corresponding output node, and wherein the source of the transistor is coupled to the corresponding intermediate node. The amplifying switch 212 may have control inputs (e.g., gates of transistors implementing the amplifying switch 212) coupled together at a control node 214 having a control voltage labeled "amp".

[0037] The dynamic amplifier 200A may also include a bias device 216 (which may be a current sink implemented by a transistor (e.g., NFET), as shown in the figure) coupled between the source of the differential input transistor 204 and a reference potential node (e.g., electrical ground) of the dynamic amplifier. The bias device 216 may have a capacitor labeled “V 偏置” A control input 218 (e.g., a gate of a transistor implementing bias device 216) of an input voltage (e.g., a bias voltage) is provided. Bias device 216 can be configured to act as a voltage-controlled current sink based on the voltage at control input 218 to sink a certain amount of current from the source of differential input transistor 204.

[0038] Figure 2B is used for Figure 2A FIG. 2 is an example timing diagram 200B of a dynamic amplifier 200A. As shown, at time 250, the control signal pre_chrg at the control node 210 transitions from logic high to logic low, so that the precharge switch 208 can be closed to start the precharge period. By closing the precharge switch 208 at time 250, the load capacitor C L1 and C L2 Charging begins, and the output voltage (eg, Vop, Vom) at the differential output node 206 begins to increase, ideally until the output voltage equals the voltage of the power rail (eg, VDD), as shown in timing diagram 200B.

[0039] At time 255, the pre_chrg signal at the control node 210 transitions from logic low to logic high (to end the precharge period), and the control signal "amp" at the control node 214 transitions from logic low to logic high (to start the amplification period). That is, at time 255, the precharge switch 208 is opened, and the amplification switch 212 is closed. As shown, between time 255 and time 260, the output voltages Vop and Vom begin to decrease at different rates (e.g., according to the different transconductances of the input transistor 204 and the different load capacitances). Therefore, as the output voltages decrease, the difference between the output voltages (e.g., Vop-Vom) increases over time.

[0040] At time 260, the amp signal at control node 214 transitions from logic high to logic low, thereby turning off amplification switch 212 and ending the amplification period of dynamic amplifier 200A. According to the differential gain of the dynamic amplifier, the difference between the output voltages is an amplified version of the difference between input voltages Vip and Vim. The differential gain is the product of the input transistor transconductance, the amplification period t amp (the time between time 255 and 260) and a function of the load capacitance.

[0041] Between time 260 and time 265, the output voltages Vop and Vom are maintained by the load capacitors, and the difference between the output voltages remains constant (or at least relatively constant). At time 265, the pre_chrg signal at the control node 210 transitions from a logic high to a logic low, thereby closing the precharge switch 208 and starting another precharge period. Therefore, between time 265 and time 270, the output voltage increases again, ideally until the output voltage is equal to the voltage VDD of the power rail, thereby effectively resetting the output voltage before another amplification period. At reset, the difference between the output voltages is zero.

[0042] At time 270, the pre_chrg signal at the control node 210 changes from logic low to logic high, thereby ending the precharge period, and the amp signal at the control node 214 changes from logic low to logic high, thereby starting another amplification period. That is, the precharge switch 208 is disconnected (e.g., the precharge transistor is turned off), and the amplification switch 212 is closed (e.g., the common source and common gate transistor is turned on). As shown, between time 270 and time 275 (when the amp signal at the control node 214 changes from logic high to logic low), the output voltages Vop and Vom begin to decrease at different rates, again generating a difference between the output voltages at time 275. The difference between the output voltages can be negative (e.g., Vom can be greater than Vop), as shown at time 275.

[0043] Dynamic amplifiers, such as dynamic amplifier 200A, generally have lower power consumption than some other amplifier architectures (e.g., Class A amplifiers) because the dynamic amplifier is active only during a portion of each switching interval. However, dynamic amplifiers may be sensitive to variations in process, voltage, and temperature (PVT) and may be affected by nonlinearity.

[0044] For example, the differential gain of the dynamic amplifier 200A may be susceptible to parasitic capacitance, where the parasitic capacitance at the common source node 224 (denoted by the reference numeral “C p "The capacitor, its capacitance can also be called C p ) may have the most significant effect on the differential gain. Prior to amplification (e.g., before time 255), the voltage at the common source node 224 (labeled “V CS ”) can be approximately equal to zero, but during amplification, the voltage V CS is approximately equal to the common-mode input voltage of dynamic amplifier 200A minus the gate-source voltage (V GS ). Therefore, the capacitor C p Usually it is necessary to charge at the beginning of the amplification period. Therefore, during the amplification period, the load capacitor C LSome of the discharge current is taken up by capacitor C p As mentioned above, the differential output is proportional to the differential input through the differential gain. However, by capacitor C p The absorbed charge causes an error in this scale factor, resulting in a gain error in the dynamic amplifier 200 A. In certain applications (such as dynamic amplifiers in ADCs), gain error is generally undesirable.

[0045] Therefore, certain aspects of the present disclosure provide a dynamic amplifier with reduced sensitivity to parasitic capacitance and reduced gain variation. The dynamic amplifier can be configured to charge the parasitic capacitance at the common source node before amplification without any significant effect on the differential output.

[0046] Figure 3A is a circuit diagram of an example dynamic amplifier 300A according to certain aspects of the present disclosure. The dynamic amplifier 300A may be similar to the dynamic amplifier 200A, but with an additional amplification switch coupled in parallel between the differential output node 206 and the intermediate nodes 220 and 222. The additional amplification switch may allow the dynamic amplifier 300A to introduce a pre-amplification period for charging the parasitic capacitance at the common source node 224 prior to the amplification period, resulting in reduced gain variation compared to the dynamic amplifier 200A, as discussed in more detail below.

[0047] The dynamic amplifier 300A generally includes a first switch 302 coupled between the first intermediate node 220 and the first differential output node 206a, and a second switch 304 coupled between the second intermediate node 222 and the second differential output node 206b. As shown, the first switch 302 and the second switch 304 may be a cross-coupled switch pair coupled between the differential input transistor pair 204 and the differential output node pair 206 of the dynamic amplifier 300A. The first switch 302 and the second switch 304 may have control inputs (e.g., gates of transistors implementing the first switch 302 and the second switch 304) coupled together at a control node 314 having a control voltage labeled “amp1”.

[0048] The dynamic amplifier 300A further includes a third switch 306 coupled between the first intermediate node 220 and the second differential output node 206b, a fourth switch 308 coupled between the second intermediate node 222 and the first differential output node 206a, a fifth switch 310 coupled between the first intermediate node 220 and the second differential output node 206b, and a sixth switch 312 coupled between the second intermediate node 222 and the first differential output node 206a. In other words, the third switch 306 and the fourth switch 308 may constitute a first switch pair coupled between the differential input transistor pair 204 and the differential output node pair 206, and the fifth switch 310 and the sixth switch 312 may constitute a second switch pair. The third switch 306 and the fourth switch 308 may have control inputs (e.g., gates of transistors implementing the third switch 306 and the fourth switch 308) coupled together at a control node 316 having a control voltage labeled “amp2”. The fifth switch 310 and the sixth switch 312 may have control inputs (eg, gates of transistors implementing the fifth switch 310 and the sixth switch 312 ) coupled together at a control node 318 having a control voltage labeled “ amp3 ”.

[0049] Figure 3B 3 is a timing diagram 300B for the dynamic amplifier 300A. As shown, at time 350, the pre_chrg signal at the control node 210 transitions from a logic high to a logic low, thereby closing the precharge switch 208 as described above. Although not shown, at time 350, the output voltage (e.g., Vop, Vom) at the differential output node 206 begins to increase until the output voltage is equal to the voltage of the power supply rail.

[0050] At time 355, while the pre_chrg signal at control node 210 is still low, the amp1 signal at control node 314 transitions from logic low to logic high, thereby closing first switch 302 and second switch 304 (i.e., the pair of cross-coupled switches). Additionally, at time 355, the amp2 signal at control node 316 may also transition from logic low to logic high, thereby closing third switch 306 and fourth switch 308. Between time 355 and time 360 ​​(labeled “t ov ”), the current passing through the first switch 302, the second switch 304, the third switch 306 and the fourth switch 308 can affect the parasitic capacitance at the common source node 224 (composed of the capacitor C p In some aspects, for example, the time t ov Can be equal to the delay of the inverter.

[0051] The time period t between time 355 and time 360 ovThis may be referred to herein as the “first phase” and may be considered a pre-amplification period. According to certain aspects, during the first phase, the cross-coupled switch pairs (e.g., the first switch 302 and the second switch 304) and the first switch pairs (e.g., the third switch 306 and the fourth switch 308) may be configured to be closed, and the second switch pairs (e.g., the fifth switch 310 and the sixth switch 312) may be configured to be open. For certain aspects, the sources of the differential input transistor pair 204 may be coupled together at a common source node 224, and the voltage (V CS ) is configured to rise during the first phase. The cross-coupling of the cross-coupled switch pair can be configured to allow the voltage of the common source node to rise during the first phase while the differential output voltage across the differential output node pair does not change.

[0052] According to certain aspects, the first switch 302 and the third switch 306 can each have a transistor width equal to half the transistor width of the amplifying switch 212a, and the second switch 304 and the fourth switch 308 can each have a transistor width equal to half the transistor width of the amplifying switch 212b. By sizing the switches in this manner, when the first switch 302, the second switch 304, the third switch 306, and the fourth switch 308 are turned on (e.g., between time 355 and time 360), substantially equal amounts of current will flow through each switch. The cross-coupling of the first switch 302 and the second switch 304 ensures that when the capacitor C p When charged, no differential voltage is generated at the differential output node 206 .

[0053] At time 360, the pre_chrg signal at the control node 210 transitions from logic low to logic high, thereby opening the precharge switch 208. Additionally, at time 360, the amp1 signal at the control node 314 transitions from logic high to logic low, thereby opening the first switch 302 and the second switch 304 (e.g., a cross-coupled pair), and the amp3 signal at the control node 318 transitions from logic low to logic high, thereby closing the fifth switch 310 and the sixth switch 312. At time 360, the third switch 306 and the fourth switch 308 remain closed. Time 360 ​​may be considered the time when amplification begins.

[0054] Between time 360 ​​and time 365 (labeled as “t amp”, and is considered to be an amplification period), although not shown, the output voltages begin to decrease at different rates. Therefore, as the output voltage decreases, the difference between the output voltages (e.g., Vop−Vom) increases. At time 365, the amp2 and amp3 signals at the control nodes 316 and 318 transition from logic high to logic low, respectively, thereby disconnecting the third switch 306, the fourth switch 308, the fifth switch 310, and the sixth switch 312. Therefore, after time 365, the load capacitor can maintain the output voltage, and the difference between the output voltages can remain constant (or at least relatively constant).

[0055] The time period between time 360 ​​and time 365 can be referred to as a "second phase" and can be considered an amplification period. For some aspects, during the second phase, the cross-coupled switch pair can be configured to be open, and the first switch pair and the second switch pair can be configured to be closed. In some aspects, amplification of the differential input signal input to the differential input transistor pair 204 is configured to occur during the second phase.

[0056] According to certain aspects, third switch 306 and fifth switch 310 can each have a transistor width equal to half the transistor width of amplifying switch 212a, and fourth switch 308 and sixth switch 312 can each have a transistor width equal to half the transistor width of amplifying switch 212b. By sizing the switches in this manner, dynamic amplifier 300A can function similarly to dynamic amplifier 200A when third switch 306, fourth switch 308, fifth switch 310, and sixth switch 312 are all closed (e.g., during amplification between time 360 ​​and time 365).

[0057] The time period after time 365 may be referred to as a "third phase." During the third phase, the cross-coupled switch pair, the first switch pair, and the second switch pair may be configured to be disconnected. After the third phase, the dynamic amplifier 300A may enter a fourth phase, which may be another precharge period (similar to the period between time 350 and time 355).

[0058] The introduction of multiple cascode devices (switches 302, 304, 306, 308, 310, and 312) in parallel and the pre-amplification period provides a switching scheme for the dynamic amplifier that allows the parasitic capacitance at the common source node 224 to be pre-charged prior to amplification, so that the load capacitor C L The amount of differential charge acquired is significantly reduced, thereby reducing sensitivity to this parasitic capacitance and, therefore, reducing the gain error of the dynamic amplifier.The pair of cross-coupled switches prevents the pre-amplification period from affecting the differential output.

[0059] Example zoom operation

[0060] Figure 4 1 is a flow chart depicting example operations 400 for amplification using a dynamic amplifier (e.g., dynamic amplifier 300A) in accordance with various aspects of the present disclosure. The dynamic amplifier may include a differential input node pair including a first input node (e.g., node 202a) and a second input node (e.g., node 202b); a differential output node pair including a first output node (e.g., node 206a) and a second output node (e.g., node 206b); a first differential input transistor (e.g., transistor 204a) having a gate coupled to the first input node and having a drain coupled to a first intermediate node (e.g., node 220); a second differential input transistor (e.g., transistor 204b) having a gate coupled to the second input node and having a drain coupled to the second intermediate node (e.g., node 222); a first switch (e.g., switch 302) coupled between the first intermediate node and the first output node; a second switch (e.g., switch 304) coupled between the second intermediate node and the second output node; a third switch (e.g., switch 306) coupled between the first intermediate node and the second output node; a fourth switch (e.g., switch 308) coupled between the second intermediate node and the first output node; a fifth switch (e.g., switch 310) coupled between the first intermediate node and the second output node; and a sixth switch (e.g., switch 312) coupled between the second intermediate node and the first output node.

[0061] Operations 400 may begin at block 402 by charging a common source node (e.g., node 320) of a first differential input transistor and a second differential input transistor during a first phase (e.g., a pre-amplification period t0v between time 355 and time 360) (or more accurately, allowing the common source node to be charged during the first phase). Allowing the common source node to be charged at block 402 may include closing a first switch, a second switch, a third switch, and a fourth switch, with a fifth switch and a sixth switch open.

[0062] At block 404, during a second phase following the first phase (eg, an amplification period t between time 360 ​​and time 365), amp ), the dynamic amplifier may amplify a voltage difference between a first input signal (e.g., Vip signal) at a first input node and a second input signal (e.g., Vim signal) at a second input node. The amplification at block 404 may include opening the first switch and the second switch, and closing the fifth switch and the sixth switch. The third switch and the fourth switch may be closed during the second phase.

[0063] According to certain aspects, operation 400 may also include resetting the dynamic amplifier during a third phase after the second phase (e.g., after time 365). Resetting may include opening the third switch, the fourth switch, the fifth switch, and the sixth switch. The first switch and the second switch may be opened during the third phase.

[0064] According to certain aspects, the common source node (eg, V CS ) can rise during the first phase without changing the differential output voltage (e.g., Vop-Vom) across the differential output node pair.

[0065] Example aspects

[0066] Examples of implementations are described in the following numbered aspects:

[0067] Aspect 1: A dynamic amplifier comprises: a differential input node pair, including a first input node and a second input node; a differential output node pair, including a first output node and a second output node; a first differential input transistor, having a gate coupled to the first input node and having a drain coupled to the first intermediate node; a second differential input transistor, having a gate coupled to the second input node and having a drain coupled to the second intermediate node; a first switch, coupled between the first intermediate node and the first output node; a second switch, coupled between the second intermediate node and the second output node; a third switch, coupled between the first intermediate node and the second output node; a fourth switch, coupled between the second intermediate node and the first output node; a fifth switch, coupled between the first intermediate node and the second output node; and a sixth switch, coupled between the second intermediate node and the first output node.

[0068] Aspect 2: A dynamic amplifier according to Aspect 1, wherein: the control input of the first switch is coupled to the control input of the second switch, the control input of the third switch is coupled to the control input of the fourth switch, and the control input of the fifth switch is coupled to the control input of the sixth switch.

[0069] Aspect 3: A dynamic amplifier according to Aspect 1 or 2, wherein: for a first stage, the first switch, the second switch, the third switch and the fourth switch are configured to be closed, and the fifth switch and the sixth switch are configured to be open; and for a second stage after the first stage, the first switch and the second switch are configured to be open, and the third switch, the fourth switch, the fifth switch and the sixth switch are configured to be closed.

[0070] Aspect 4: The dynamic amplifier according to aspect 3, wherein: the source of the first differential input transistor is coupled to the source of the second differential input transistor at a common source node; and the voltage of the common source node is configured to rise during the first stage.

[0071] Aspect 5: A dynamic amplifier according to Aspect 4, wherein: compared to the third switch and the fourth switch, the cross-coupling of the first switch and the second switch is configured to allow the voltage of the common source node to rise during the first stage while the differential output voltage across the differential output node pair does not change; and the amplification of the differential input signal across the differential input node pair is configured to occur during the second stage.

[0072] Aspect 6: The dynamic amplifier according to any one of aspects 3 to 5, wherein for a third stage after the second stage, the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are configured to be opened.

[0073] Aspect 7: A dynamic amplifier according to any one of the preceding aspects, wherein: the first switch and the second switch are implemented by a first transistor pair, the third switch and the fourth switch are implemented by a second transistor pair, and the first transistor pair has the same transistor size as the second transistor pair.

[0074] Aspect 8: The dynamic amplifier according to any of the preceding aspects further includes: a seventh switch coupled between the second output node and the power supply rail; an eighth switch coupled between the first output node and the power supply rail, wherein the control input of the seventh switch is coupled to the control input of the eighth switch; and a current sink coupled between the source of the first differential input transistor and the reference potential node, wherein the source of the first differential input transistor is coupled to the source of the second differential input transistor.

[0075] Aspect 9: A dynamic amplifier according to Aspect 8, wherein: for a first stage, the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are configured to be open; for a second stage after the first stage, the first switch, the second switch, the third switch and the fourth switch are configured to be closed, and the fifth switch and the sixth switch are configured to be open; and for a third stage after the second stage, the first switch and the second switch are configured to be open, and the third switch, the fourth switch, the fifth switch and the sixth switch are configured to be closed.

[0076] Aspect 10: A dynamic amplifier according to Aspect 9, wherein: for the first stage, the seventh switch and the eighth switch are configured to be closed; for the second stage, the seventh switch and the eighth switch are configured to be closed; and for the third stage, the seventh switch and the eighth switch are configured to be open.

[0077] Aspect 11: An analog-to-digital converter (ADC), comprising the dynamic amplifier described in any of the preceding aspects, the ADC also comprising a conversion stage configured to generate a digital output and a residual voltage, wherein the dynamic amplifier is coupled to the conversion stage and configured to amplify the residual voltage.

[0078] Aspect 12: A method for amplifying using a dynamic amplifier, comprising: a differential input node pair, including a first input node and a second input node; a differential output node pair, including a first output node and a second output node; a first differential input transistor, having a gate coupled to the first input node and having a drain coupled to the first intermediate node; a second differential input transistor, having a gate coupled to the second input node and having a drain coupled to the second intermediate node; a first switch, coupled between the first intermediate node and the first output node; a second switch, coupled between the second intermediate node and the second output node; a third switch, coupled between the first intermediate node and the second output node; and a fourth switch, coupled between the second intermediate node and the first output node. a fifth switch coupled between the first intermediate node and the second output node; and a sixth switch coupled between the second intermediate node and the first output node, the method comprising: charging the common source node of the first differential input transistor and the second differential input transistor during a first stage, the charging comprising closing the first switch, the second switch, the third switch and the fourth switch, wherein the fifth switch and the sixth switch are opened; and amplifying a voltage difference between a first input signal at the first input node and a second input signal at the second input node during a second stage after the first stage, the amplification comprising opening the first switch and the second switch and closing the fifth switch and the sixth switch, wherein the third switch and the fourth switch are closed during the second stage.

[0079] Aspect 13: The method according to aspect 12 further includes resetting the dynamic amplifier during a third phase after the second phase, the resetting including opening the third switch, the fourth switch, the fifth switch and the sixth switch, wherein the first switch and the second switch are opened during the third phase.

[0080] Aspect 14: The method according to aspect 12 or 13, wherein the voltage of the common source node rises during the first phase due to cross-coupling of the first switch and the second switch compared to the third switch and the fourth switch, while the differential output voltage across the differential output node pair does not change.

[0081] Aspect 15: A dynamic amplifier comprising: a differential input transistor pair; a cross-coupled switch pair coupled between the differential input transistor pair and a differential output node pair of the dynamic amplifier; a first switch pair coupled between the differential input transistor pair and the differential output node pair; and a second switch pair coupled between the differential input transistor pair and the differential output node pair.

[0082] Aspect 16: A dynamic amplifier according to Aspect 15, wherein: for a first stage, the cross-coupled switch pair and the first switch pair are configured to be closed, and the second switch pair is configured to be open; and for a second stage after the first stage, the cross-coupled switch pair is configured to be open, and the first switch pair and the second switch pair are configured to be closed.

[0083] Aspect 17: The dynamic amplifier of aspect 16, wherein: sources of the differential input transistor pair are coupled together at a common source node; and a voltage of the common source node is configured to rise during the first phase.

[0084] Aspect 18: A dynamic amplifier according to Aspect 16 or 17, wherein: the cross-coupling of the cross-coupled switch pair is configured to allow the voltage of the common source node to rise during the first phase while the differential output voltage across the differential output node pair does not change; and the amplification of the differential input signal input to the differential input transistor pair is configured to occur during the second phase.

[0085] Aspect 19: The dynamic amplifier according to any one of aspects 16 to 18, wherein for a third stage after the second stage, the cross-coupled switch pair, the first switch pair, and the second switch pair are configured to be open.

[0086] Aspect 20: An analog-to-digital converter (ADC), comprising the dynamic amplifier of any one of Aspects 15 to 20, the ADC further comprising a conversion stage configured to generate a digital output and a residual voltage, wherein the dynamic amplifier is coupled to the conversion stage and configured to amplify the residual voltage.

[0087] Other considerations

[0088] In this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as being preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the features, advantages, or modes of operation discussed. The term "coupling" as used herein refers to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered to be coupled to each other—even if objects A and C are not in direct physical contact with each other. For example, a first object can be coupled to a second object even if the first object has never been in direct physical contact with the second object. The terms "circuit" and "circuitry" are used broadly and are intended to include both hardware implementations of electrical devices and conductors that, when connected and configured, enable the functions described in this disclosure to be performed, without limiting the type of electronic circuitry.

[0089] The apparatuses and methods described in the detailed description are illustrated in the drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"), which may be implemented using hardware, for example.

[0090] One or more components, steps, features and / or functions shown herein may be rearranged and / or combined into a single component, step, feature or function, or implemented in several components, steps or features. Additional elements, components, steps and / or features may also be added without departing from the features disclosed herein. The devices, equipment and / or components shown herein may be configured to perform one or more of the methods, features or steps described herein.

[0091] It is understood that the specific order or hierarchy of steps in the disclosed methods is an illustration of an exemplary process. Based on design preferences, it is understood that the specific order or hierarchy of steps in the methods may be rearranged. The accompanying method claims present elements of the various steps in an example order, and are not meant to be limited to the specific order or hierarchy presented unless specifically recited therein.

[0092] The previous description is provided to enable those skilled in the art to practice the various aspects described herein. Those skilled in the art will readily understand the various modifications to these aspects, and the general principles defined herein are applicable to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but to conform to the full range consistent with the language of the claims, wherein unless otherwise stated, the elements in the singular form are not intended to represent "one and only one", but to represent "one or more". Unless otherwise clearly stated, the term "some" refers to one or more. The phrase "at least one of" referring to a series of items refers to any combination of these items, including a single member. As an example, "at least one of a, b or c" is intended to at least cover a, b, c, ab, ac, bc and abc and any combination (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbb, bbb, cc and cccc or any other order of a, b and c) with multiple identical elements. All structural and functional equivalents of the elements of the various aspects described in this disclosure known to those of ordinary skill in the art or to be known later are expressly incorporated herein by reference, and are intended to be included by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is expressly recited in a claim. Under 35 U.S.C. 112(f), no claim element shall be construed unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”

[0093] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A dynamic amplifier, comprising: a differential input node pair, comprising a first input node and a second input node; a differential output node pair, comprising a first output node and a second output node; a first differential input transistor having a gate coupled to the first input node and having a drain coupled to a first intermediate node; a second differential input transistor having a gate coupled to the second input node and having a drain coupled to a second intermediate node; A first switch coupled between the first intermediate node and the first output node; a second switch coupled between the second intermediate node and the second output node; a third switch coupled between the first intermediate node and the second output node; a fourth switch coupled between the second intermediate node and the first output node; a fifth switch coupled between the first intermediate node and the second output node; as well as A sixth switch is coupled between the second intermediate node and the first output node.

2. The dynamic amplifier according to claim 1, wherein: The control input of the first switch is coupled to the control input of the second switch; The control input of the third switch is coupled to the control input of the fourth switch; as well as The control input of the fifth switch is coupled to the control input of the sixth switch.

3. The dynamic amplifier according to claim 1, wherein: For the first stage, the first switch, the second switch, the third switch and the fourth switch are configured to be closed, and the fifth switch and the sixth switch are configured to be open; as well as For a second phase after the first phase, the first switch and the second switch are configured to be open, and the third switch, the fourth switch, the fifth switch, and the sixth switch are configured to be closed.

4. The dynamic amplifier according to claim 3, wherein: a source of the first differential input transistor coupled to a source of the second differential input transistor at a common source node; as well as The voltage of the common source node is configured to rise during the first phase.

5. The dynamic amplifier according to claim 4, wherein: The cross-coupling of the first switch and the second switch is configured, compared to the third switch and the fourth switch, to: allow the voltage of the common source node to rise during the first phase without changing the differential output voltage across the differential output node pair; as well as Amplification of the differential input signal across the pair of differential input nodes is configured to occur during the second phase. 6 . The dynamic amplifier of claim 3 , wherein for a third stage after the second stage, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are configured to be turned off.

7. The dynamic amplifier according to claim 1, wherein: The first switch and the second switch are implemented by a first transistor pair; The third switch and the fourth switch are implemented by a second transistor pair; and The first transistor pair has the same transistor size as the second transistor pair.

8. The dynamic amplifier according to claim 1, further comprising: a seventh switch coupled between the second output node and the power rail; an eighth switch coupled between the first output node and the power rail, wherein a control input of the seventh switch is coupled to a control input of the eighth switch; as well as A current sink is coupled between a source of the first differential input transistor and a reference potential node, wherein the source of the first differential input transistor is coupled to a source of the second differential input transistor.

9. The dynamic amplifier according to claim 8, wherein: For the first stage, the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are configured to be open; For a second stage after the first stage, the first switch, the second switch, the third switch, and the fourth switch are configured to be closed, and the fifth switch and the sixth switch are configured to be open; as well as For a third phase after the second phase, the first switch and the second switch are configured to be open, and the third switch, the fourth switch, the fifth switch, and the sixth switch are configured to be closed.

10. The dynamic amplifier according to claim 9, wherein: For the first stage, the seventh switch and the eighth switch are configured to be closed; For the second stage, the seventh switch and the eighth switch are configured to be closed; as well as For the third phase, the seventh switch and the eighth switch are configured to be open.

11. An analog-to-digital converter (ADC), comprising the dynamic amplifier of claim 1, the ADC further comprising a conversion stage configured to generate a digital output and a residual voltage, wherein the dynamic amplifier is coupled to the conversion stage and configured to amplify the residual voltage.

12. A method for amplifying using a dynamic amplifier, the dynamic amplifier comprising: a differential input node pair, comprising a first input node and a second input node; a differential output node pair, comprising a first output node and a second output node; a first differential input transistor having a gate coupled to the first input node and having a drain coupled to a first intermediate node; a second differential input transistor having a gate coupled to the second input node and having a drain coupled to the second intermediate node; A first switch coupled between the first intermediate node and the first output node; a second switch coupled between the second intermediate node and the second output node; a third switch coupled between the first intermediate node and the second output node; a fourth switch coupled between the second intermediate node and the first output node; a fifth switch coupled between the first intermediate node and the second output node; as well as A sixth switch is coupled between the second intermediate node and the first output node, and the method includes: During a first phase, charging a common source node of the first differential input transistor and the second differential input transistor, the charging comprising closing the first switch, the second switch, the third switch, and the fourth switch, wherein the fifth switch and the sixth switch are open; as well as During a second phase following the first phase, a voltage difference between a first input signal at the first input node and a second input signal at the second input node is amplified, the amplification comprising opening the first switch and the second switch and closing the fifth switch and the sixth switch, wherein the third switch and the fourth switch are closed during the second phase.

13. The method of claim 12, further comprising resetting the dynamic amplifier during a third phase after the second phase, the resetting comprising opening the third switch, the fourth switch, the fifth switch, and the sixth switch, wherein the first switch and the second switch are opened during the third phase.

14. The method of claim 12, wherein the voltage of the common source node rises during the first phase while the differential output voltage across the differential output node pair does not change due to cross-coupling of the first switch and the second switch compared to the third switch and the fourth switch.

15. A dynamic amplifier, comprising: Differential input transistor pair; a pair of cross-coupled switches coupled between the pair of differential input transistors and a pair of differential output nodes for the dynamic amplifier; a first switch pair coupled between the differential input transistor pair and the differential output node pair; as well as A second switch pair is coupled between the differential input transistor pair and the differential output node pair.

16. The dynamic amplifier of claim 15, wherein: For a first phase, the cross-coupled switch pair and the first switch pair are configured to be closed, and the second switch pair is configured to be open; as well as For a second phase following the first phase, the cross-coupled switch pair is configured to be open, and the first switch pair and the second switch pair are configured to be closed.

17. The dynamic amplifier of claim 16, wherein: The sources of the differential input transistor pair are coupled together at a common source node; and The voltage of the common source node is configured to rise during the first phase.

18. The dynamic amplifier of claim 17, wherein: The cross-coupling of the cross-coupled switch pair is configured to: allow the voltage of the common source node to rise during the first phase without changing the differential output voltage across the differential output node pair; as well as Amplification of the differential input signal input to the differential input transistor pair is configured to occur during the second phase. 19 . The dynamic amplifier of claim 16 , wherein for a third stage after the second stage, the cross-coupled switch pair, the first switch pair, and the second switch pair are configured to be open.

20. An analog-to-digital converter (ADC) comprising the dynamic amplifier of claim 15, the ADC further comprising a conversion stage configured to generate a digital output and a residual voltage, wherein the dynamic amplifier is coupled to the conversion stage and configured to amplify the residual voltage.

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