A low-power power-on reset circuit for automotive chips

Abstract

The present invention discloses a low-power power-on reset circuit applied to automotive-grade chips, including: a bias circuit, a startup circuit, and a power-on reset circuit. When power is applied, the startup circuit starts to work, and the startup signal forces the output of the fourth node in the power-on reset circuit to be high level, and the power-on reset circuit outputs a reset signal; after the bias circuit completes startup, it controls the first current source and the second current source in the power-on reset circuit to start working, and the third node in the power-on reset circuit starts to charge. After the third node is charged above the conduction voltage, the power-on reset circuit starts to execute the reset judgment logic.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a low-power power-on reset circuit applied to automotive-grade chips. Background Art

[0002] During the chip startup process, the power supply voltage gradually rises from 0 to the rated value. During this process, the internal circuits of the chip may enter an indeterminate state, causing the chip to operate in an incorrect state and even damaging the internal circuits of the chip. Therefore, the chip must generate a reset signal during power-on to reset the key circuits when the power supply has not reached the operating threshold, enabling the chip to operate stably.

[0003] In automotive applications, the power supply conditions are more complex, and the requirements for automotive-grade chips are second only to those of military-grade chips, posing extremely high requirements for safety and stability. In the face of possible large fluctuations in the power supply, the chip must ensure high reliability and actively reset the circuit when the power supply voltage is too low to prevent the chip from entering an uncontrollable incorrect state. Usually, this circuit must always remain operational to ensure the functional safety of the chip. Therefore, low power consumption is also one of the important design indicators.

[0004] Figure 1 Fig. shows a power-on reset circuit in the prior art, which consists of a resistor, a MOS transistor, a comparator, and a bias circuit. When the power supply voltage is low, due to the threshold voltage of the MOS transistor, the voltage at point B will be lower than the voltage at point A, and the comparator outputs a high level, causing the circuit to enter the reset state. However, in addition to the bias circuit operating at low voltage, this power-on reset circuit also includes a comparator operating at low voltage. Usually, the anti-interference ability of the comparator is weak, and its calculation accuracy is easily affected by factors such as temperature, resulting in poor stability. In addition, the resistance network and the circuit area of the comparator in this power-on reset circuit are relatively large, affecting the miniaturization design of the chip, and the cost of the comparator is relatively high. Moreover, the conduction current in the circuit composed of the resistor and the MOS transistor and the power consumption of the comparator always exist, resulting in relatively high power consumption. Therefore, when designing the chip, it is necessary to consider the power consumption and the circuit area, which limits the chip performance. Summary of the Invention

[0005] To solve the above-mentioned defects in the prior art, the present invention proposes a low-power power-on reset circuit applied to automotive-grade chips, which features low power consumption, low cost, and high stability.

[0006] The technical solution of the present invention is as follows:

[0007] The present invention proposes a low-power power-on reset circuit applied to automotive-grade chips, including: a bias circuit, a startup circuit, and a power-on reset circuit.

[0008] When powered on, the startup circuit starts to work. The startup circuit outputs a startup signal, forcing the output of the fourth node in the power-on reset circuit to be high level, with the logic output being high, and the power-on reset circuit outputs a reset signal.

[0009] After the bias circuit completes startup, it controls the first current source and the second current source in the power-on reset circuit to start working. The third node in the power-on reset circuit starts to charge. After the third node is charged above the conduction voltage, the power-on reset circuit starts to execute the reset judgment logic.

[0010] The reset judgment logic includes:

[0011] When the voltage of the third node in the power-on reset circuit is less than the predetermined voltage, the fourth node outputs a high level, the logic output is high, and the power-on reset circuit outputs a reset signal.

[0012] When the voltage of the third node is higher than the predetermined voltage, the fourth node outputs a low level, the logic output is low, representing the end of reset.

[0013] When the startup circuit is working, it determines whether to pull down the voltage in the bias circuit according to the voltage of the first node in the startup circuit.

[0014] When the voltage of the first node is 0, the pull-down branch in the startup circuit pulls down the voltage in the bias circuit, forcing current to flow into the bias circuit.

[0015] When there is current in the bias circuit and the voltage of the first node is charged to the predetermined startup level, it represents that the bias circuit has completed startup and the startup circuit is turned off.

[0016] The bias circuit includes PMOS transistors PM5, PM6, NMOS transistors NM5, NM6, and the first resistor R1.

[0017] The sources of PM5 and PM6 are connected to the power supply voltage Vdda. The gates of PM5 and PM6 are connected to the drain of PM5. The drains of PM5 and PM6 are respectively connected to the drains of NM5 and NM6. The gates of NM5 and NM6 are connected to the drain of NM6. The source of NM5 is grounded through the first resistor R1, and the source of NM6 is grounded.

[0018] PM5 and PM6 form a P-type current mirror.

[0019] The startup circuit includes PMOS transistors PM7, PM8, NMOS transistors NM7, NM8, NM9, the second resistor R2, the first capacitor C1, and the first Schmitt trigger.

[0020] The sources of PM7 and PM8 are connected to the power supply voltage Vdda. The gates of PM7 and PM8 are connected to the drain of PM7. The drains of PM7 and PM8 are respectively connected to the drains of NM7 and NM8. The gate of NM7 is connected to the drain of NM6. The gate of NM8 is grounded. The sources of NM7 and NM8 are grounded. The drain of NM8 is also connected to the input terminal of the first Schmitt trigger, forming a first node. The output terminal of the first Schmitt trigger is connected to the gate of NM9. The drain of NM9 is connected to the drain of PM5. The source of NM9 is grounded through the second resistor R2. The drain of NM8 is also grounded through the first capacitor C1.

[0021] PM7 and PM8 form a P-type current mirror, and NM6 and NM7 form an N-type current mirror.

[0022] The power-on reset circuit includes PMOS transistors PM1, PM2, PM3, PM4, PM9, NMOS transistors NM1, NM2, NM3, NM4, the second capacitor C2, the first NOT gate NOT1, the second Schmitt trigger, the second NOT gate NOT2, and the third NOT gate NOT3.

[0023] The source of PM9 is connected to the power supply voltage Vdda. The gate of PM9 is connected to the drain of PM7. The drain of PM9 is connected to the source of PM3. The gate of PM3 is connected to the drain of NM8, the input terminal of the first NOT gate NOT1, and the gate of NM3. The drain of PM3 is connected to the drain of NM3, forming a second node. The source of NM3 is grounded. The drain of NM3 is also grounded through the second capacitor C2. The sources of PM1, PM2, and PM4 are connected to the power supply voltage Vdda. The gates of PM1 and PM2 are connected to the drain of PM2 and the gate of NM1, forming a third node. The drain of PM2 is connected to the drain of NM4. The gate of NM4 is connected to the gate of NM6. The source of NM4 is grounded. The drain of PM1 is connected to the drains of NM1, PM4, and the input terminal of the second Schmitt trigger, forming a fourth node. The source of NM1 is connected to the drain of NM2. The gate of NM2 is connected to the drain of NM3. The source of NM2 is grounded. The gate of PM4 is connected to the output terminal of the first NOT gate NOT1. The output terminal of the second Schmitt trigger is connected to the input terminal of the second NOT gate NOT2. The output terminal of the second NOT gate NOT2 is connected to the input terminal of the third NOT gate NOT3. The output terminal of the third NOT gate NOT3 outputs the reset signal por.

[0024] NM6 and NM4 form an N-type current mirror, and NM4 forms the first current source I1, while PM9 forms the second current source I2.

[0025] The sizes of PMOS transistors PM1, PM2, PM5, PM6, PM7, PM8, and PM9 are in proportion, and the sizes of NMOS transistors NM1, NM4, NM5, NM6, and NM7 are in proportion.

[0026] Compared with the traditional power-on reset circuit, on the basis of achieving the same performance, the present invention reduces the use of large resistors, eliminates the comparator, greatly reduces the power consumption while reducing the circuit area, and reduces the cost.

[0027] The features and advantages of the present invention will become clear by referring to the following drawings and the detailed description of the specific embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shows the circuit diagram of a traditional power-on reset circuit.

[0029] Figure 2 Shows the specific circuit diagram of the power-on reset circuit of the present invention.

[0030] Figure 3 Shows the schematic diagram of the power-on reset circuit of the present invention.

[0031] Figure 4 Shows the simulation waveform diagram of the power-on reset circuit of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] In order to make the technical solutions of the present invention clearer and more understandable, the following will be further described in detail with reference to the drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The following refers to Figures 2 to 4 for a detailed description of the present invention.

[0033] Figure 2 Shows the specific circuit diagram of the power-on reset circuit of the present invention. The power-on reset circuit of the present invention includes a bias circuit, a startup circuit, and a power-on reset circuit.

[0034] The bias circuit includes PMOS transistors PM5, PM6, NMOS transistors NM5, NM6, and a first resistor R1. The sources of PM5 and PM6 are connected to the power supply voltage Vdda. The gates of PM5 and PM6 are connected to the drain of PM5. The drains of PM5 and PM6 are respectively connected to the drains of NM5 and NM6. The gates of NM5 and NM6 are connected to the drain of NM6. The source of NM5 is grounded through the first resistor R1, and the source of NM6 is grounded. PM5 and PM6 form a P-type current mirror.

[0035] The startup circuit includes PMOS transistors PM7, PM8, NMOS transistors NM7, NM8, NM9, a second resistor R2, a first capacitor C1, and a first Schmitt trigger. The sources of PM7 and PM8 are connected to the power supply voltage Vdda. The gates of PM7 and PM8 are connected to the drain of PM7. The drains of PM7 and PM8 are respectively connected to the drains of NM7 and NM8. The gate of NM7 is connected to the drain of NM6. The gate of NM8 is grounded. The sources of NM7 and NM8 are grounded. The drain of NM8 is also connected to the input terminal of the first Schmitt trigger to form a first node D. The output terminal of the first Schmitt trigger is connected to the gate of NM9. The drain of NM9 is connected to the drain of PM5. The source of NM9 is grounded through the second resistor R2. The drain of NM8 is also grounded through the first capacitor C1. PM7 and PM8 form a P-type current mirror, and NM6 and NM7 form an N-type current mirror.

[0036] The power-on reset circuit includes PMOS transistors PM1, PM2, PM3, PM4, PM9, NMOS transistors NM1, NM2, NM3, NM4, a second capacitor C2, a first NOT gate NOT1, a second Schmitt trigger, a second NOT gate NOT2, and a third NOT gate NOT3. The source of PM9 is connected to the power supply voltage Vdda. The gate of PM9 is connected to the drain of PM7. The drain of PM9 is connected to the source of PM3. PM9 forms a second current source I2. The gate of PM3 is connected to the drain of NM8, the input terminal of the first NOT gate NOT1, and the gate of NM3. The drain of PM3 is connected to the drain of NM3 to form a second node A. The source of NM3 is grounded. The drain of NM3 is also grounded through the second capacitor C2. The sources of PM1, PM2, and PM4 are connected to the power supply voltage Vdda. The gates of PM1 and PM2 are connected to the drain of PM2 and the gate of NM1 to form a third node B. The drain of PM2 is connected to the drain of NM4. The gate of NM4 is connected to the gate of NM6. The source of NM4 is grounded. NM6 and NM4 form an N-type current mirror, and NM4 forms a first current source I1. The drain of PM1 is connected to NM1, the drain of PM4, and the input terminal of the second Schmitt trigger to form a fourth node C. The source of NM1 is connected to the drain of NM2. The gate of NM2 is connected to the drain of NM3. The source of NM2 is grounded. The gate of PM4 is connected to the output terminal of the first NOT gate NOT1. The output terminal of the second Schmitt trigger is connected to the input terminal of the second NOT gate NOT2. The output terminal of the second NOT gate NOT2 is connected to the input terminal of the third NOT gate NOT3. The output terminal of the third NOT gate NOT3 outputs a reset signal por. The output terminal of the second NOT gate NOT2 also outputs a signal porb that is inverted with respect to the reset signal and can be provided to an external circuit for use when needed.

[0037] In the figure, the sizes of PMOS transistors PM1, PM2, PM5, PM6, PM7, PM8, and PM9 are proportional, and the sizes of NMOS transistors NM1, NM4, NM5, NM6, and NM7 are proportional.

[0038] In the bias circuit of the present invention, MOS transistor NM6 and MOS transistor NM7 in the startup circuit form a bandgap reference mirror. NM7 is the mirrored current source. PM7 and PM8 form a current mirror. When the startup circuit works, it charges the first capacitor C1, and determines whether to pull down the voltage of the gate / drain of PM5 in the bias circuit according to the voltage at point D. The bandgap reference mirror outputs a path of current to the startup circuit. When powered on, the output current of the bandgap reference mirror is 0 and cannot charge the first capacitor C1, and the voltage at point D is 0. At this time, for startup, the pull-down branch composed of NM9 and the second resistor R2 in the startup circuit pulls down the gate / drain of PM5 to force current into the bias circuit. When there is current in the bias circuit, the bandgap reference mirror outputs current, and the first capacitor C1 is slowly charged to a predetermined startup level. The voltage at point D follows the power supply voltage, indicating that the bias circuit has completed startup and the startup circuit is turned off. After the startup circuit is turned off, the power-on reset circuit starts to work, and the specific principle will be described below.

[0039] In addition, NM8 is a device with relatively large leakage. Its function is to pull down the voltage at point D when the bias circuit falls into a zero-current state due to abnormal interference, restart the circuit, and improve the reliability of the circuit.

[0040] Figure 3 The schematic diagram of the power-on reset circuit of the present invention is shown. The working principle of the power-on reset circuit of the present invention is explained below.

[0041] When powered on, the startup circuit of the bias circuit starts to work. The startup signal is output at node D in the startup circuit, and the output at point C is forced to be high level through MOS transistors PM3, PM4, and NM3, and the logic output is high, and the reset signal is output. After the bias circuit completes startup, the N-type current source I1 and the P-type current source I2 that provide the same current start to work, and node A starts to be charged. After node A is charged above the conduction voltage Vth, NM2 conducts, and the power-on reset circuit starts to execute the reset judgment logic.

[0042] PM2 is connected in the form of a diode, that is, the gate is connected to the drain. Then the voltage at point B is (Vdda - Vgsp), where Vgsp is the gate-source voltage of the P-type current mirror. When the power supply voltage is low, the voltage at point B is less than Vgsn, where Vgsn is the gate-source voltage of the N-type current mirror. Then the current flowing through PM1 is greater than the current flowing through NM1, the output at point C is high level, the logic output is high, and a reset signal is output. When the power supply voltage gradually rises to the voltage at point B equal to Vgsn, the output at point C is in an intermediate state. Due to the characteristics of the Schmitt trigger, the logic output still remains high. When the power supply voltage rises to be large enough, the voltage at point B is higher than Vgsn. At this time, the output at point C is low level, the logic output is low, indicating the end of reset. At this time, the power supply voltage is already sufficient to ensure the correct operation of the circuit logic.

[0043] In addition, when the power supply voltage suddenly drops, there are two possible situations.

[0044] The first situation is that the power supply voltage drops to a voltage at which the logic circuit and the bias circuit can still work, such as about 1V. At this time, the voltage at point B drops below Vgsn, and the output at point C is pulled high from low level, and a reset signal is output. When the power supply voltage rises to be large enough, the voltage at point B is higher than Vgsn, and the output at point C is low level, and the reset ends.

[0045] The second situation is that the power supply voltage drops to a voltage at which the logic circuit and the bias circuit cannot work, such as about 500mV. At this time, all points may be in an indeterminate state. However, when the power supply voltage rises again, the above-mentioned power-on reset process is repeated. First, the startup circuit in the bias circuit starts to work, and the output at point C is forced to be high level, and a reset signal is output. After the bias circuit completes startup, the voltage at point B gradually rises from less than Vgsn to higher than Vgsn, and the output at point C changes from high level to low level, and the reset ends.

[0046] In the present invention, the sizes (channel width-to-length ratios) of PM1 and PM2 are proportional to those of the P-type current mirror in the bias circuit, and the size of NM1 is proportional to that of the N-type current mirror. Thus, the power supply voltage that meets the working conditions can be controlled within a certain range, further reducing power consumption.

[0047] When the power supply voltage is stable, since both MOS transistors PM1 and PM2 are proportional to the sizes of the P-type current mirror in the bias circuit, the static currents of these two paths are stable and controllable, depending on the bias current of the bias circuit. Thus, the static current can be controlled within a small range, thereby reducing power consumption.

[0048] Compared with the resistors used in the power-on reset circuit in the prior art, the resistances of the resistors R1 and R2 in the present invention are smaller, further reducing power consumption.

[0049] Figure 4The simulation waveform diagram of the power-on reset circuit of the present invention is shown. The simulation experiment results prove that when the power supply voltage suddenly drops, the power-on reset effect is stable. Moreover, the present invention reduces the circuit area by 40% compared with the traditional power-on reset circuit, and the static current is less than 200 nA under standard conditions, significantly reducing the power consumption.

[0050] The power-on reset circuit of the present invention can be applied to automotive-grade chips, having the advantages of low power consumption, low cost, and high stability, thereby effectively ensuring the safety and reliability of automotive-grade chips from power-on to smoothly entering the normal working state and during subsequent working processes, and can meet the relevant requirements of automotive-grade chips.

[0051] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural transformation made under the concept of the present invention by using the content of the specification and drawings of the present invention, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A low-power power-on reset circuit for automotive chips, comprising: Bias circuit, startup circuit and power-on reset circuit, When powered on, the startup circuit starts working, the startup circuit outputs a startup signal, the output of the fourth node in the power-on reset circuit is forced to be high, the logic output is high, and the power-on reset circuit outputs a reset signal; When the bias circuit is started, the first current source and the second current source in the power-on reset circuit are controlled to start working, and the third node in the power-on reset circuit starts to charge. After the third node is charged to a voltage above the conduction voltage, the power-on reset circuit starts to execute the reset judgment logic, wherein: The power-on reset circuit includes PMOS tubes PM1, PM2, PM3, PM4, PM9, NMOS tubes NM1, NM2, NM3, NM4, a second capacitor C2, a first NOT gate NOT1, The source of PM9 is connected to the power supply voltage Vdda, the gate of PM9 is connected to the startup circuit, the drain of PM9 is connected to the source of PM3, the gate of PM3 is connected to the startup circuit, the input terminal of the first NOT gate NOT1 and the gate of NM3, the drain of PM3 is connected to the drain of NM3 to form a second node, the source of NM3 is grounded, and the drain of NM3 is also grounded through the second capacitor C2, the sources of PM1, PM2 and PM4 are connected to the power supply voltage Vdda, the gates of PM1 and PM2 are connected to the drain of PM2 and the gate of NM1 to form a third node, the drain of PM2 is connected to the drain of NM4, the gate of NM4 is connected to the bias circuit, the source of NM4 is grounded, the drain of PM1 is connected to the drains of NM1 and PM4 to form a fourth node, the source of NM1 is connected to the drain of NM2, the gate of NM2 is connected to the drain of NM3, the source of NM2 is grounded, and the gate of PM4 is connected to the output terminal of the first NOT gate NOT1. The channel length-to-width ratios of the PMOS tubes PM1, PM2, PM5, PM6, PM7, PM8, and PM9 are proportional, and the channel length-to-width ratios of the NMOS tubes NM1, NM4, NM5, NM6, and NM7 are proportional.

2. The power-on reset circuit according to claim 1, wherein: The power-on reset circuit also includes a second Schmitt trigger, a second NOT gate NOT2, and a third NOT gate NOT3. The drain of PM1 is connected to the input of the second Schmitt trigger, the output of the second Schmitt trigger is connected to the input of the second NOT gate NOT2, the output of the second NOT gate NOT2 is connected to the input of the third NOT gate NOT3, and the output of the third NOT gate NOT3 outputs a reset signal por.

3. The power-on reset circuit according to claim 2, wherein: NM6 and NM4 form an N-type current mirror, NM4 forms a first current source I1, and PM9 forms a second current source I2.

4. The power-on reset circuit according to claim 1, wherein: The reset judgment logic includes: When the voltage of the third node in the power-on reset circuit is less than the predetermined voltage, the fourth node outputs a high level, the logic output is high, and the power-on reset circuit outputs a reset signal; When the voltage of the third node is higher than the predetermined voltage, the fourth node outputs a low level, and the logic output is low, indicating that the reset is completed.

5. The power-on reset circuit according to claim 1, wherein: When the startup circuit is working, it is determined whether to lower the voltage in the bias circuit according to the voltage of the first node in the startup circuit. When the voltage on the first node is 0, the pull-down branch in the startup circuit pulls down the voltage in the bias circuit, forcing current to flow into the bias circuit. When there is current in the bias circuit, when the voltage of the first node is charged to a predetermined startup level, it means that the bias circuit has completed startup and the startup circuit is turned off.

6. The power-on reset circuit according to claim 1, 4 or 5, wherein: The bias circuit includes PMOS tubes PM5, PM6, NMOS tubes NM5, NM6, and a first resistor R1; The sources of PM5 and PM6 are connected to the power supply voltage Vdda, the gates of PM5 and PM6 are connected to the drain of PM5, the drains of PM5 and PM6 are connected to the drains of NM5 and NM6 respectively, the gates of NM5 and NM6 are connected to the drain of NM6 and the gate of NM4, the source of NM5 is grounded through the first resistor R1, and the source of NM6 is grounded.

7. The power-on reset circuit according to claim 6, wherein: PM5 and PM6 form a P-type current mirror.

8. The power-on reset circuit according to claim 7, wherein: The startup circuit includes PMOS tubes PM7, PM8, NMOS tubes NM7, NM8, NM9, a second resistor R2, a first capacitor C1, and a first Schmitt trigger. The sources of PM7 and PM8 are connected to the power supply voltage Vdda, the gates of PM7 and PM8 are connected to the drain of PM7 and the gate of PM9, the drains of PM7 and PM8 are connected to the drains of NM7 and NM8 respectively, the gate of NM7 is connected to the drain of NM6, the gate of NM8 is grounded, the sources of NM7 and NM8 are grounded, the drain of NM8 is also connected to the gate of PM3 and the input of the first Schmitt trigger to form a first node, the output of the first Schmitt trigger is connected to the gate of NM9, the drain of NM9 is connected to the drain of PM5, the source of NM9 is grounded through the second resistor R2, and the drain of NM8 is also grounded through the first capacitor C1.

9. The power-on reset circuit according to claim 8, wherein: PM7 and PM8 form a P-type current mirror, and NM6 and NM7 form an N-type current mirror.

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