Command completion message transmission method, transmission system and transmission device

Abstract

The embodiment of the present application provides a method, system and device for transmitting a command completion message, wherein the method includes: obtaining the total number of cores of the processor core and the queue depth of the target completion queue when determining that the processor core has completed the command processing task; determining the sending mode of sending the command completion message to the target completion queue according to the total number of cores and the queue depth; allocating the remaining credit value of the target completion queue according to the sending mode to obtain the available credit value of each processor core; when the available credit value is greater than the preset credit threshold, controlling the processor core to transmit the command completion message to the target completion queue according to the sending mode. Through the present application, the problem in the related art that the message volume of a certain completion queue exceeds the host processing capacity, resulting in the queue being full and blocked, affecting the message transmission efficiency, is solved, thereby achieving the effect of improving the transmission efficiency of the command completion message.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and more specifically, to a method, a system, a device, a computer-readable storage medium, and an electronic device for transmitting a command completion message. Background Art

[0002] With the continuous development of storage systems, NVMe SSDs are constantly replacing traditional hard disks. Under the current NVMe technology, NVMe SSDs interact with hosts through multiple pairs of submission / completion queues to submit and complete IO commands. When the host submits a command, it is distributed to each CPU in the SSD device according to the round-robin command. However, when processing concurrent commands, multiple CPUs simultaneously process messages in a completion queue, which may cause a queue to be full and blocked for a period of time, which is greater than the host's processing capacity for completing commands in this queue. In related technologies, the sending of completion messages of multiple queues according to separate bursts will cause the completion messages sent by a queue to exceed the corresponding carrying capacity of the host, affecting the IO latency and QoS service quality, and under different kernel working ecosystems, there will be different completion queue depths.

[0003] In addition, in the current NVMe technology, the protocol stipulates that the host and SSD use multiple pairs of queues (submission queues and completion queues) for IO command interaction. In the processing of the completion command, the master writes the command completion message to the CQ (Completion Queue) completion queue and modifies the CQ's Tail Door Bell tail doorbell register. After the host processes the completion message in the completion queue CQ, it notifies the SSD's corresponding CQ completion queue Head Door Bell head doorbell register. The update of the Head register is determined by the processing speed of the storage host. At the same time, the number of completion message entries available to the controller can be determined by the Head, Tail and queue depth qSize (when Head < Tail, the number of available completion message entries is qSize - (cq_tail - cq_head); when Head = Tail, the number of available completion messages is qSize; when Head > Tail, the number of available completion messages is cq_head - cq_tail). The Head DoorBell register and Tail Door Bell register of CQ inside the SSD are maintained by the internal hardware module. The real-time acquisition of this register by the multi-core CPU inside the SSD requires the computing power of the corresponding CPU. Summary of the invention

[0004] The embodiments of the present application provide a method, system, device, computer-readable storage medium and electronic device for transmitting a command completion message, so as to at least solve the problem in the related art that the message volume in a completion queue exceeds the host processing capacity, causing the queue to be full and blocked, thereby affecting the message transmission efficiency.

[0005] According to an embodiment of the present application, a method for transmitting a command completion message is provided, comprising: when it is determined that a processor core has completed a command processing task, obtaining the total number of cores of the processor core and the queue depth of a target completion queue, wherein the command processing task refers to a task for processing a pending command sent by a host, and the total number of cores refers to the total number of all the processor cores; determining a sending mode for sending a command completion message to the target completion queue according to the total number of cores and the queue depth, wherein the command completion message refers to a message generated when the processor core completes the command processing task; allocating a remaining credit value of the target completion queue according to the sending mode to obtain an available credit value of each processor core, wherein the remaining credit value is proportional to the current remaining storage space of the target completion queue, and the remaining storage space refers to the space in the target completion queue where the command completion message is not stored; when the available credit value is greater than a preset credit threshold, controlling the processor core to transmit the command completion message to the target completion queue according to the sending mode.

[0006] In an exemplary embodiment, before obtaining the queue depth of the target completion queue, the method also includes: determining that a submission queue that sends the pending commands to the processor core is a target submission queue, wherein the submission queue is a cache queue of the pending commands; and determining that a completion queue that has a preset corresponding relationship with the target submission queue is the target completion queue, wherein the preset corresponding relationship is a corresponding relationship established when the submission queue and the completion queue are created.

[0007] In an exemplary embodiment, determining that a completion queue that has a preset correspondence with the target submission queue is the target completion queue includes: obtaining a first queue identifier of the target submission queue; determining that a queue identifier that matches the first queue identifier is a second queue identifier based on the first queue identifier and an identifier mapping table, wherein the identifier mapping table is used to store multiple groups of the preset correspondences between the submission queues and the completion queues; and determining that the completion queue whose queue identifier is the second queue identifier is the target completion queue.

[0008] In an exemplary embodiment, obtaining the queue depth of a target completion queue includes: obtaining an initial storage space of the target completion queue, wherein the initial storage space is a storage space preset when the target completion queue is created; and determining the total number of message storage locations in the initial storage space as the queue depth, wherein the message storage location refers to a location in the target completion queue for storing the command completion message.

[0009] In an exemplary embodiment, a sending mode for sending a command completion message to the target completion queue is determined based on the total number of cores and the queue depth, including: comparing the total number of cores with the queue depth to obtain a first comparison result; when the first comparison result indicates that the queue depth is less than the total number of cores, determining the sending mode to be a shared credit mode, wherein the shared credit mode is a mode in which all the processor cores share the remaining credit value to send the command completion message to the target completion queue; when the comparison result indicates that the queue depth is greater than the total number of cores, determining the sending mode to be a non-shared credit mode, wherein the non-shared credit mode is a mode in which the remaining credit value is evenly distributed to each of the processor cores to send the command completion message to the target completion queue.

[0010] In an exemplary embodiment, before allocating the remaining credit value of the target completion queue according to the sending mode to obtain the available credit value of each processor core, the method further includes: acquiring a current queue state of the target completion queue; in a case where it is determined according to the current queue state that the target completion queue is in an initial queue state, determining the queue depth of the target completion queue to be the remaining credit value, wherein the initial queue state refers to a state in which the target completion queue has not started to receive the command completion message; in a case where it is determined according to the current queue state that the target completion queue is in a message transmission state, calculating the remaining credit value of the target completion queue according to the positions of a head position number and a tail position number in the target completion queue, wherein the message transmission state refers to a state in which the target completion queue starts to receive the command completion message sent by the processor core, the head position number refers to the number of the next message storage position in the target completion queue where the command completion message needs to be sent, and the tail position number refers to the number of the next message storage position in the target completion queue where the command completion message needs to be received.

[0011] In an exemplary embodiment, the remaining credit value of the target completion queue is calculated according to the positions of the head position number and the tail position number in the target completion queue, including: comparing the head position number with the tail position number to obtain a second comparison result; when the second comparison result indicates that the head position number is equal to the tail position number, determining the queue depth of the target completion queue to be the remaining credit value; when the second comparison result indicates that the head position number is greater than the tail position number, calculating the remaining credit value according to the head position number and the tail position number using a first formula, wherein the first formula is: , represents the remaining credit value, represents the head position number, represents the tail position number; when the second comparison result indicates that the head position number is less than the tail position number, the remaining credit value is calculated using a second formula according to the head position number and the tail position number, wherein the second formula is: , Indicates the queue depth.

[0012] In an exemplary embodiment, the remaining credit value of the target completion queue is allocated according to the sending mode to obtain the available credit value of each of the processor cores, including: when the sending mode is a shared credit mode, determining that the available credit value of each of the processor cores is the remaining credit value; when the sending mode is a non-shared credit mode, evenly allocating the remaining credit value according to the total number of cores to obtain an intermediate available credit value; when the intermediate available credit value is an integer, determining that the available credit value of each of the processor cores is the intermediate available credit value; when the intermediate available credit value is not an integer, determining that the available credit value of each of the processor cores is a target available credit value, wherein the target available credit value is a maximum integer not greater than the intermediate available credit value.

[0013] In an exemplary embodiment, after determining that the available credit value of each of the processor cores is the target available credit value, the method further includes: allocating the idle credit value of the target completion queue to the processor core according to a predetermined allocation method, wherein the idle credit value refers to the credit value of the remaining credit value that is not allocated to the processor core.

[0014] In an exemplary embodiment, the idle credit values ​​of the target completion queue are allocated to the processor cores according to a predetermined allocation method, including at least one of the following: allocating all the idle credit values ​​to any one of the processor cores; allocating the idle credit values ​​one by one to a plurality of processor cores of the same number according to the number of the idle credit values; allocating the idle credit values ​​to the processor cores whose credit demand is higher than a demand threshold, wherein the credit demand is used to reflect the degree of demand of the processor core for the remaining credit value; placing the idle credit values ​​in a shared credit pool to apply for the idle credit values ​​from the shared credit pool when the available credit value of the processor core is not greater than the preset credit threshold and the command completion message needs to be sent.

[0015] In an exemplary embodiment, when the available credit value is greater than a preset credit threshold, the processor core is controlled to transmit the command completion message to the target completion queue according to the sending mode, including: if the sending mode is a shared credit mode, the processor core is controlled to transmit the command completion message to the target completion queue after performing a locking operation on the available credit value; if the sending mode is a non-shared credit mode, the processor core is controlled to transmit the command completion message to the target completion queue.

[0016] In an exemplary embodiment, if the sending mode is a shared credit mode, the processor core is controlled to transmit the command completion message to the target completion queue after performing a locking operation on the available credit value, including: when the sending mode is the shared credit mode, determining that the processor core that currently needs to send the command completion message is the target processor core; controlling the target processor core to perform the locking operation on the available credit value; in the process of locking the available credit value based on the locking operation, controlling the target processor core to transmit the command completion message to the target completion queue, wherein the locking indicates that the processor cores other than the target processor core cannot apply for the available credit value to transmit the command completion message to the target completion queue.

[0017] In an exemplary embodiment, after controlling the processor core to transmit the command completion message to the target completion queue after performing a lock operation on the available credit value, the method further includes: controlling the processor core to perform an unlock operation on the available credit value to unlock the available credit value.

[0018] In an exemplary embodiment, the method further includes: after each time the processor core sends a command completion message to the target completion queue, updating the available credit value of the processor core to a first value reduced by 1, wherein the first value is not less than the value of the preset credit threshold; after each time the target completion queue receives a command completion message, updating the remaining credit value of the target completion queue to a second value reduced by 1, wherein the second value is not less than the preset credit threshold.

[0019] In an exemplary embodiment, the method further includes: during the process of updating the remaining credit value, if the remaining credit value is the same as the preset credit threshold, obtaining the current head position number and the current tail position number of the target completion queue; calculating the current remaining credit value of the target completion queue according to the current head position number and the current tail position number; and reallocating the current remaining credit value according to the sending mode to obtain the current available credit value of each processor core.

[0020] In an exemplary embodiment, the method also includes: when the available credit value is equal to the preset credit threshold, if the processor core needs to send the command completion message to the target completion queue, performing a suspend operation on the command completion message that currently needs to be sent; based on the suspend operation, storing the command completion message in the suspend linked list of the target completion queue; and when the current remaining credit value of the target completion queue is greater than the preset credit threshold, transferring the command completion message stored in the suspend linked list to the target completion queue.

[0021] In an exemplary embodiment, when the current remaining credit value of the target completion queue is greater than the preset credit threshold, the command completion message stored in the suspension linked list is transferred to the target completion queue, including: obtaining the total number of command completion messages in the suspension linked list; when the total number of messages is less than or equal to the current remaining credit value, transferring all the command completion messages stored in the suspension linked list to the target completion queue; when the total number of messages is greater than the current remaining credit value, obtaining the suspension timestamp of each command completion message in the suspension linked list, wherein the suspension timestamp refers to the time when the command completion message is stored in the suspension linked list; sorting all the command completion messages in the suspension linked list in ascending order according to the suspension timestamp to obtain a sorting result; and transferring the command completion messages to the target completion queue in sequence according to the sorting result until the current remaining credit value is the same as the preset credit threshold.

[0022] According to another embodiment of the present application, a command completion message transmission system is provided, including: a host, the host is used to issue commands to be processed; a hard disk, the hard disk includes a processor core, the hard disk is used to determine a sending mode for sending the command completion message to the target completion queue according to the total number of cores of all the processor cores and the queue depth of the target completion queue, and allocate the remaining credit value of the target completion queue to the processor core according to the sending mode to obtain an available credit value of each processor core, the processor core is used to process the commands to be processed to generate a command completion message, and the processor core is also used to transmit the command completion message to the target completion queue when the available credit value is greater than a preset credit threshold.

[0023] According to another embodiment of the present application, a method for transmitting a command completion message is also provided, including: controlling a processor core to process a pending command issued by a host to obtain a command completion message; determining a sending mode for sending the command completion message to the target completion queue according to the total number of cores of all the processor cores and the queue depth of the target completion queue; allocating the remaining credit value of the target completion queue to the processor core according to the sending mode to obtain an available credit value of each processor core; when the available credit value is greater than a preset credit threshold, controlling the processor to send the command completion message to the target completion queue according to the sending mode, so as to transmit the command completion message to the host through the target completion queue.

[0024] According to another embodiment of the present application, a transmission device for a command completion message is also provided, comprising: a first acquisition module, for obtaining the total number of cores of the processor cores in the target hard disk and the queue depth of the target completion queue when determining that the processor core completes the command processing task, wherein the command processing task refers to a task for processing a pending command sent by the host, the target hard disk refers to a hard disk to which command transmission is required, and the total number of cores refers to the total number of all the processor cores; a first determination module, for determining a sending mode for sending a command completion message to the target completion queue according to the total number of cores and the queue depth, wherein the command completion message refers to a message generated when the processor core completes the command processing task; an allocation module, for allocating the remaining credit value of the target completion queue according to the sending mode to obtain the available credit value of each processor core, wherein the remaining credit value is proportional to the current remaining storage space of the target completion queue, and the remaining storage space refers to the space in the target completion queue where the command completion message is not stored; a transmission module, for controlling the processor core to transmit the command completion message to the target completion queue according to the sending mode when the available credit value is greater than a preset credit threshold.

[0025] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0026] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0027] Through this application, the sending mode of controlling the processor core to send command completion messages to the target completion queue is determined by comparing the size relationship between the total number of processor cores in the hard disk and the queue depth of the target completion queue, and the remaining credit value that can quantify the current amount of messages that the queue can carry is introduced in combination with the analysis of the remaining storage space in the target completion queue, and the remaining credit value is allocated according to the sending mode, so that the processor core can adaptively adjust the sending of command completion messages without exceeding its own available credit value and the remaining credit value of the target completion queue, so as to avoid overloading the amount of messages received by a certain completion queue. Therefore, the problem in the related art that the amount of messages in a certain completion queue exceeds the host processing capacity, resulting in a full and blocked queue, which affects the message transmission efficiency, can be solved, thereby achieving the purpose of improving the transmission efficiency of command completion messages. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a hardware structure block diagram of a terminal device of a method for transmitting a command completion message according to an embodiment of the present application;

[0029] Figure 2 is a flowchart of a method for transmitting a command completion message according to an embodiment of the present application;

[0030] Figure 3 It is a schematic diagram of a command sending design under multi-core and multi-queue according to an embodiment of the present application;

[0031] Figure 4 is a structural block diagram of a transmission system of a command completion message according to an embodiment of the present application;

[0032] Figure 5 is a flowchart of an optional command completion message transmission method according to an embodiment of the present application;

[0033] Figure 6 It is a structural block diagram of a transmission device for a command completion message according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0036] The method embodiments provided in the embodiments of the present application can be executed in a terminal device or a similar computing device. Taking running on a terminal device as an example, Figure 1 1 is a hardware structure block diagram of a terminal device of a method for transmitting a command completion message according to an embodiment of the present application. Figure 1 As shown, the terminal device may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above terminal device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is for illustration only and does not limit the structure of the above terminal device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0037] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for transmitting the command completion message in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the terminal device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0038] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the terminal device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0039] In this embodiment, a method for transmitting a command completion message is provided. Figure 2 is a flowchart of a method for transmitting a command completion message according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0040] Step S202, when it is determined that the processor core completes the command processing task, the total number of processor cores and the queue depth of the target completion queue are obtained, wherein the command processing task refers to the task of processing the pending command sent by the host, and the total number of cores refers to the total number of all processor cores;

[0041] Step S204, determining a sending mode for sending a command completion message to a target completion queue according to the total number of cores and the queue depth, wherein the command completion message refers to a message generated when a processor core completes a command processing task;

[0042] Step S206, allocating the remaining credit value of the target completion queue according to the sending mode to obtain the available credit value of each processor core, wherein the remaining credit value is proportional to the current remaining storage space of the target completion queue, and the remaining storage space refers to the space in the target completion queue that does not store the command completion message;

[0043] Step S208: When the available credit value is greater than the preset credit threshold, the processor core is controlled to transmit the command completion message to the target completion queue according to the sending mode.

[0044] Through the above steps, in the process of controlling the processor core to send a command completion message to the target completion queue, the sending mode of controlling the processor core to send the command completion message to the target completion queue is determined by comparing the size relationship between the total number of processor cores in the hard disk and the queue depth of the target completion queue, and combined with the analysis of the remaining storage space in the target completion queue, a remaining credit value that can quantify the current message capacity of the queue is introduced, and the remaining credit value is allocated according to the sending mode, so that the processor core can adaptively adjust the sending of the command completion message without exceeding its own available credit value and the remaining credit value of the target completion queue, so as to avoid overloading the message volume received by a certain completion queue, thereby improving the transmission efficiency of the command completion message.

[0045] The execution subject of the above steps may be a storage device (such as a hard disk), a terminal device, etc., but is not limited thereto.

[0046] The exemplary embodiments of the transmission method of the command completion message provided by the present application will be described in more detail below. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concept of these exemplary embodiments to those of ordinary skill in the art.

[0047] In an exemplary embodiment, before performing the above-mentioned step S202, that is, before obtaining the queue depth of the target completion queue, the method also includes: determining that a submission queue that sends pending commands to the processor core is a target submission queue, wherein the submission queue is a cache queue of pending commands; and determining that a completion queue that has a preset corresponding relationship with the target submission queue is a target completion queue, wherein the preset corresponding relationship is a corresponding relationship established when the submission queue and the completion queue are created.

[0048] Specifically, under the NVMe (Non-Volatile Memory Express) protocol framework, the communication between the host and the solid-state disk (SSD) is carried out through the submission queue (SQ) and the completion queue (SQ). Queue, referred to as CQ); in the initialization stage of the NVMe device, the host (such as a server or PC) creates a series of submission queues (SQs), each SQ is used to receive I / O commands (such as read and write operations, i.e., pending commands in the embodiments of the present application) sent by the host to the SSD, and at the same time, the host creates a corresponding completion queue (CQ) for each SQ, and there is a one-to-one correspondence between SQ and CQ; therefore, when the SSD or its processor core receives a pending command sent by the host, the SSD can first determine through which submission queue the pending command is sent, and determine it as the target submission queue; then, the completion queue corresponding to the target submission queue can be determined as the target completion queue according to the corresponding relationship established when the submission queue and the completion queue were created, so that the processor core of the SSD can transmit the processed command completion message to the host through the corresponding target completion queue for the pending command received through the target submission queue, thereby ensuring the accuracy of the transmission.

[0049] In the above embodiment, determining that a completion queue that has a preset correspondence with a target submission queue is a target completion queue includes: obtaining a first queue identifier of the target submission queue; determining a queue identifier that matches the first queue identifier as a second queue identifier based on the first queue identifier and an identifier mapping table, wherein the identifier mapping table is used to store preset correspondences between multiple groups of submission queues and completion queues; and determining that a completion queue whose queue identifier is the second queue identifier is the target completion queue.

[0050] Specifically, when the host initializes the NVMe device, it creates multiple groups of queue pairs. Each queue pair consists of a submission queue and a completion queue with a corresponding relationship. Each queue pair has an independent identifier. The correspondence between these identifiers can be stored in an identifier mapping table, so as to facilitate search and matching in the identifier mapping table according to the identifier of the target submission queue to obtain the target completion queue that has a corresponding relationship with the target submission queue.

[0051] In an exemplary embodiment, in the above step S202, the queue depth of the target completion queue is obtained, including: obtaining the initial storage space of the target completion queue, wherein the initial storage space is the storage space preset when the target completion queue is created; determining the total number of message storage locations in the initial storage space as the queue depth, wherein the message storage location refers to the location in the target completion queue for storing command completion messages.

[0052] Combine the following Figure 3 The above embodiments of the present application are described in detail. Figure 3 It is a schematic diagram of the command sending design under multi-core and multi-queue according to an embodiment of the present application.

[0053] like Figure 3 As shown in the figure, the whole design system is mainly divided into: a two-dimensional completion command sending memory space module, a completion command sending module, a queue credit Credit update and distribution module, and a multi-queue completion command sending suspension module; when constructing the sending memory space module, the two-dimensional completion command sending memory space module can be constructed according to the maximum number of CPU cores (the total number of processor cores) MAX_CORES (CPU0, CPU1, CPU2...CPU_N) supported by the SSD and the maximum number of queues MAX_CPL_QUEUES (cq0, cq1, cq2...cq_N). The memory space module of each CPU contains the shared and non-shared Credit mode types of each queue, the remaining Credit value of the queue, the queue sending completion command suspension list, the consumed queue Credit Credit feedback value, etc.; in addition, when initializing the sending memory space module, the corresponding memory space can be cleared and initialized when the SSD is powered on or reset, and when the kernel of the storage host is initialized, the Credit initial value and queue processing mode in the two-dimensional sending memory space module are completed.

[0054] Specifically, the queue capacity (i.e., the initial storage space in the embodiment of the present application) of the target completion queue can be determined based on the configuration parameters recorded when the target completion queue is created. The number of command completion messages that the target completion queue can accommodate can be obtained based on the queue capacity. It can also be considered as the number of message storage locations set in the target completion queue for storing command completion messages, thereby determining the queue depth of the target completion queue. This allows the processor core to send command completion messages to the target completion queue while taking into account the target completion queue's carrying capacity for command completion messages, thereby avoiding queue fullness or queue blocking.

[0055] In an exemplary embodiment, in the above step S204, the sending mode of sending the command completion message to the target completion queue is determined according to the total number of cores and the queue depth, including: comparing the total number of cores with the queue depth to obtain a first comparison result; when the first comparison result indicates that the queue depth is less than the total number of cores, determining the sending mode to be a shared credit mode, wherein the shared credit mode is a mode in which all processor cores share the remaining credit value to send the command completion message to the target completion queue; when the comparison result indicates that the queue depth is greater than the total number of cores, determining the sending mode to be a non-shared credit mode, wherein the non-shared credit mode is a mode in which the remaining credit value is evenly distributed to each processor core to send the command completion message to the target completion queue.

[0056] In order to avoid multiple CPUs processing messages in a completion queue at the same time, resulting in a problem of full blocking of a certain queue due to the fact that the processing capacity of the host to complete commands in this queue is greater than that of the host for a period of time, the initialization configuration of the command sending memory space module can be completed when the host storage initializes the completion queue, and the credit Credit working mode of each queue (that is, the sending mode in the embodiment of the present application, including shared credit mode and non-shared credit mode) is determined. That is, shared credit and non-shared credit sending modes can be introduced according to the total number of processor cores in the SSD and the queue depth of the target completion queue, and the process of sending command completion messages to the target completion queue is realized by comprehensively considering the remaining capacity of the target completion queue (that is, the remaining credit value) and the credit value available to each processor core itself.

[0057] Specifically, if the depth of a queue CQ_M is less than the sum of the number of ∑CPUs (i.e., the total number of cores), in order to avoid the performance bottleneck caused by multiple CPUs concurrently accessing the same queue under low queue depth, the shared credit mode can be used when sending a command completion message to the queue CQ_M; if the depth of queue CQ_M is greater than the sum of the number of ∑CPUs, in order to avoid waiting for other processor cores to release locks or resources, maximize the concurrent processing capabilities of multi-core processors, and improve the overall performance and efficiency of the system, the non-shared credit mode can be used when sending a command completion message to the queue CQ_M.

[0058] It should be noted that the host may send pending commands to the SSD through multiple submission queues. The command completion message obtained by each processor core of the SSD after processing the pending commands needs to be sent to the completion queue corresponding to each submission queue. Therefore, it is necessary to determine the sending mode of each processor core sending command completion messages to each completion queue based on the queue depth of each completion queue and the total number of processor cores in the SSD.

[0059] In an exemplary embodiment, before performing the above-mentioned step S206, that is, before allocating the remaining credit value of the target completion queue according to the sending mode to obtain the available credit value of each processor core, the method also includes: obtaining the current queue state of the target completion queue; when it is determined according to the current queue state that the target completion queue is in the initial queue state, determining the queue depth of the target completion queue as the remaining credit value, wherein the initial queue state refers to the state in which the target completion queue has not started to receive command completion messages; when it is determined according to the current queue state that the target completion queue is in the message transmission state, calculating the remaining credit value of the target completion queue according to the positions of the head position label and the tail position label in the target completion queue, wherein the message transmission state refers to the state in which the target completion queue starts to receive the command completion message sent by the processor core, the head position label refers to the label of the next message storage position in the target completion queue where the command completion message needs to be sent, and the tail position label refers to the label of the next message storage position in the target completion queue where the command completion message needs to be received.

[0060] Specifically, Figure 3 As shown, when configuring the sending memory space module, the remaining credit value of the target completion queue can be allocated according to the sending mode. Before obtaining the available credit value of each processor core, the current remaining credit value of the target completion queue must be obtained first. The remaining available resources of the target completion queue, that is, the remaining credit value, can be determined according to the current transmission status; if the current host has just started to send pending commands to the SSD, it can be considered that the current target completion queue has not yet started to receive command completion messages, that is, the available resources of the queue have not yet been consumed, and the current remaining credit value of the target completion queue can be considered to be the queue depth of the queue; if the current SSD has already sent a command completion message to the target completion queue, it means that a part of the available resources of the current target completion queue may have been occupied, and the value of the Head register (corresponding to the head position number in the embodiment of the present application) and the value of the Tail register (corresponding to the tail position number in the embodiment of the present application) can be used to calculate the current remaining available resources in the target completion queue, so as to facilitate the process of the processor core sending the command completion message to the target completion queue without exceeding the carrying capacity of the target completion queue for the command completion message, thereby avoiding the phenomenon of queue fullness or queue blocking.

[0061] Of course, the remaining credit value in the target completion queue at the beginning of the command transmission process can be considered as the queue depth of the queue. During the command transmission process, the target completion queue will receive the command completion message sent by each processor core of the SSD, and will also send it to the host, so the available resources of the target completion queue are changing at any time. In this process, it can be updated according to the above method of calculating the remaining available value of the target completion queue according to the values ​​of the Head and Tail registers. In the credit mechanism (that is, the mechanism for sending command completion messages to the target completion queue in a shared credit mode or a non-shared credit mode), the values ​​of the Head and Tail pointers are also an important basis for updating the remaining credit value. By reading these two pointers regularly or under specific conditions, the SSD can dynamically adjust the remaining credit value of the target completion queue to avoid queue overload or idleness, and improve the performance and stability of the entire system. The specific update timing is described in detail below and will not be repeated here.

[0062] In the above embodiment, the remaining credit value of the target completion queue is calculated according to the positions of the head position number and the tail position number in the target completion queue, including: comparing the head position number with the tail position number to obtain a second comparison result; when the second comparison result indicates that the head position number is equal to the tail position number, determining the queue depth of the target completion queue as the remaining credit value; when the second comparison result indicates that the head position number is greater than the tail position number, calculating the remaining credit value according to the head position number and the tail position number using a first formula, wherein the first formula is: , Indicates the remaining credit value, Indicates the head position number, represents the tail position number; when the second comparison result indicates that the head position number is less than the tail position number, the remaining credit value is calculated using the second formula according to the head position number and the tail position number, wherein the second formula is: , Indicates the queue depth.

[0063] Specifically, the values ​​of the Head and Tail registers reflect the interaction status between the host and the SSD controller on the CQ. In the NVMe completion queue CQ, the Head pointer indicates the location of the next command completion message to be read by the host, and the Tail pointer indicates the location of the next command completion message to be written by the SSD, such as Figure 3As shown, the Credit update and distribution module can determine the remaining available value of the target completion queue according to the values of the Head and Tail registers. The specific determination method is as follows: ① When Head = Tail, the remaining credit value Credi is the queue depth qSize of the target completion queue; ② When Head > Tail, the remaining credit value Credi is ; ③ When Head < Tail, the remaining credit value Credi is , so as to accurately obtain the remaining credit value of the target completion queue and avoid excessive command completion messages received by the queue, resulting in queue full or blocking.

[0064] In an exemplary embodiment, in step S206 above, the remaining credit value of the target completion queue is allocated according to the sending mode to obtain the available credit value of each processor core, including: in the case where the sending mode is the shared credit mode, it is determined that the available credit value of each processor core is the remaining credit value; in the case where the sending mode is the non-shared credit mode, the remaining credit value is evenly distributed according to the total number of cores to obtain the intermediate available credit value; in the case where the intermediate available credit value is an integer, it is determined that the available credit value of each processor core is the intermediate available credit value; in the case where the intermediate available credit value is not an integer, it is determined that the available credit value of each processor core is the target available credit value, where the target available credit value is the largest integer not greater than the intermediate available credit value.

[0065] Specifically, the remaining credit value of the target completion queue can be allocated according to the sending mode determined in step S204 before to obtain the available credit value of each processor core in the SSD, that is, the number of command completion messages that each processor core can send to the target completion queue; in the case where the sending mode is the shared credit mode, all CPU cores in the SSD (i.e., the processor cores in the embodiments of the present application) share the remaining credit value of the target completion queue. In the case of sharing, it can be considered that the available credit value of each CPU core is the remaining credit value. However, after a certain amount of credit value is consumed by one CPU core, the value of the remaining credit value will be updated, and the available credit value of each CPU core will also be updated accordingly; in the case where the sending mode is the non-shared credit mode, the remaining credit value is evenly distributed to each CPU core, and the credit value allocated to each CPU core is its own available credit value, so as to ensure that each CPU core can send command completion messages according to its own available credit value and avoid sending too many messages to the target completion queue at the same time, exceeding the carrying capacity of the queue and the processing capacity of the host.

[0066] In an exemplary embodiment, in a non-shared credit mode, if the remaining credit value cannot be evenly distributed to each CPU core, then after determining that the available credit value of each processor core is the target available credit value, the method further includes: allocating the idle credit value of the target completion queue to the processor core according to a predetermined allocation method, wherein the idle credit value refers to the credit value of the remaining credit value that is not allocated to the processor core.

[0067] Specifically, if the quotient of the remaining credit value divided by the total number of CPU cores is not an integer, a certain strategy may be used to process the remaining unallocated credit value to maximize the use of the available space of the target completion queue.

[0068] In the above embodiment, the idle credit values ​​of the target completion queue are allocated to the processor cores according to a predetermined allocation method, including at least one of the following: allocating all the idle credit values ​​to any one processor core; allocating the idle credit values ​​one by one to multiple processor cores of the same number according to the number of idle credit values; allocating the idle credit values ​​to processor cores whose credit demand is higher than the demand threshold, wherein the credit demand is used to reflect the degree of demand of the processor core for the remaining credit value; placing the idle credit values ​​in a shared credit pool to apply for idle credit values ​​from the shared credit pool when the available credit value of the processor core is not greater than the preset credit threshold and a command completion message needs to be sent.

[0069] Specifically, the following strategies can be used to handle the remaining unallocated credits: ① Round up allocation: First calculate the integer part of the credits that should be allocated to each core, and then allocate the "remaining" credits (i.e., the part that cannot be divided) to some or all of the CPU cores, which usually means that some cores will get slightly more credits than other cores; for example, if the remaining credits are 100 and the total number of cores is 7, each core should get close to 14.29 credits; 14 credits can be allocated to each core first, and then the remaining 2 credits (100-14×7) can be allocated to a certain CPU core, or to two randomly selected CPU cores; ② Round down allocation + shared credit pool: First calculate the integer part of the credits that should be allocated to each core, and then allocate the "remaining" credits (i.e., the part that cannot be divided) to some or all of the CPU cores, which usually means that some cores will get slightly more credits than other cores; for example, if the remaining credits are 100 and the total number of cores is 7, each core should get close to 14.29 credits; then allocate 14 credits to each core, and then allocate the remaining 2 credits (100-14×7) to one CPU core, or to two randomly selected CPU cores; Calculate the integer part of the credit value that should be allocated to each core, and then store the remaining credit value in an additional credit pool for all cores to "borrow" when needed; for example, in the case of 100 credit values ​​and 7 cores mentioned above, 14 credit values ​​can be allocated to each core, and the remaining 2 credit values ​​can be put into a common credit pool. When the credit value of a core is exhausted, additional credit values ​​can be obtained from this pool to continue sending commands; ③ Allocate the remaining credit values ​​in turn or in proportion: The remaining credit values ​​can be allocated to different cores in a rotating manner, or the remaining credit values ​​can be allocated in proportion according to the core load, priority, etc. A more reasonable allocation method can be selected based on the actual situation to maximize the use of the available space in the target completion queue.

[0070] In an exemplary embodiment, in the above step S208, when the available credit value is greater than the preset credit threshold, the processor core is controlled to transmit the command completion message to the target completion queue according to the sending mode, including: if the sending mode is a shared credit mode, the processor core is controlled to transmit the command completion message to the target completion queue after performing a locking operation on the available credit value; if the sending mode is a non-shared credit mode, the processor core is controlled to transmit the command completion message to the target completion queue.

[0071] It should be noted that the above-mentioned preset credit threshold can be zero in the embodiment of the present application to ensure that each CPU core sends a command completion message to the target completion queue when the available credit value is greater than zero, and also to ensure that each target completion queue receives the command completion message only when its own remaining credit value is greater than zero.

[0072] Specifically, Figure 3 As shown, when the command sending module is completed, in the process of controlling the CPU core to send the command completion message to the target completion queue, it is necessary to make an adaptive selection according to the credit Credit working mode of each queue (cq0, cq1, cq2...cq_N) (that is, the sending mode of the CPU core sending the command completion message to the queue); for example, when cq_M is a shared credit mode, in order to ensure the consistency and integrity of the remaining credit value of the target completion queue and avoid data inconsistency or conflict problems caused by simultaneous modifications, the CPU core can be controlled to send the command completion message to the target completion queue in a locked manner; when cq_M is a non-shared credit mode, a high-concurrency processing mode can be adopted, that is, each CPU core independently sends the command completion message obtained by each to the cq_M completion queue and the corresponding queue sending suspension list in parallel according to its own available credit value.

[0073] For example, in the shared credit mode, assuming that CPU0 completes the increase and consumption of credit resources, a CPU core needs to apply for a lock when sending a command completion message with a queue identifier of CQ_M. The completion command can be sent successfully only after the lock application is successful and the credit resources (i.e., available credit value) of the corresponding completion queue maintained by CPU0 have remaining credits; in the non-shared credit mode, each CPU core completes the increase and consumption of the credit resources of each queue respectively, and there is no need for a unified locking method. Each CPU core maintains its own independent queue command sending list. Assuming that a CPU_x applies for the credit resources of the queue CQ_M allocated to this CPU_x when sending a command completion message with a queue identifier of CQ_M, the completion command of CQ_M can be sent successfully only after the credit resources are successfully applied for.

[0074] In the above embodiment, if the sending mode is a shared credit mode, the control processor core transmits the command completion message to the target completion queue after performing a locking operation on the available credit value, including: when the sending mode is a shared credit mode, determining that the processor core that currently needs to send the command completion message is the target processor core; controlling the target processor core to perform a locking operation on the available credit value; in the process of locking the available credit value based on the locking operation, controlling the target processor core to transmit the command completion message to the target completion queue, wherein locking means that processor cores other than the target processor core cannot apply for the available credit value to transmit the command completion message to the target completion queue.

[0075] Specifically, when a CPU core wants to send a command completion message to a target completion queue, it needs to first apply for a lock on the remaining credit value of the target completion queue. And because the remaining credit value will decrease accordingly with the number of command completion messages sent by each CPU core, it is necessary to verify again whether the current remaining available credit value is greater than zero after applying for the lock. That is, if there is still remaining available credit value, the command completion message is sent to the target completion queue while locking the remaining credit value based on the locking operation. During this period, other CPU cores cannot send command completion messages to the target completion queue based on the remaining credit value, so as to avoid problems such as calculation errors caused by multiple CPU cores applying for credit values ​​at the same time in the shared credit mode.

[0076] It should be noted that when multiple CPU cores try to access and modify the remaining credit value of the same target completion queue at the same time, in addition to the CPU core that processes the first successful lock, other CPU cores still need to wait until the lock is released.

[0077] In the above embodiment, after the control processor core transmits the command completion message to the target completion queue after performing a lock operation on the available credit value, the method further includes: controlling the processor core to perform an unlock operation on the available credit value to unlock the available credit value.

[0078] On the other hand, after a CPU core sends the command completion message that needs to be sent to the target completion queue based on the locking process, it is necessary to perform an unlocking operation to release the locked remaining credit value, so that other CPU cores can apply for the remaining credit value to send the command completion message.

[0079] In an exemplary embodiment, the method further includes: after each time the processor core sends a command completion message to the target completion queue, updating the available credit value of the processor core to a first value reduced by 1, wherein the first value is not less than a value of a preset credit threshold; after each time the target completion queue receives a command completion message, updating the remaining credit value of the target completion queue to a second value reduced by 1, wherein the second value is not less than the preset credit threshold.

[0080] Specifically, each time the CPU core sends a command completion message to the target completion queue, the available credit value of the CPU core for sending command completion messages to the target completion queue will be reduced by 1; similarly, each time the target completion queue receives a command completion message, its remaining credit value will be reduced by 1; these two processes are synchronized. When the CPU core sends a command completion message to a target completion queue, the available credit value of the processor core and the remaining credit value of the target completion queue that receives the command completion message will be reduced synchronously; such real-time updates can allow the target completion queue to receive command completion messages when there are sufficient storage space resources, so as to avoid queue fullness and blocking.

[0081] In an exemplary embodiment, the method also includes: during the process of updating the remaining credit value, if the remaining credit value is the same as the preset credit threshold, obtaining the current head position label and the current tail position label of the target completion queue; calculating the current remaining credit value of the target completion queue according to the current head position label and the current tail position label; and reallocating the current remaining credit value according to the sending mode to obtain the current available credit value of each processor core.

[0082] Specifically, in order to more efficiently update the remaining credit values ​​of all completion queues on each CPU core, the processing logic of the credit update method of queue CQ_M is as follows: the timing of credit update is triggered by updating before the command completion message is sent, and is updated according to the remaining credit value of the current queue and the feedback mechanism of the current queue sending credit. The specific methods are as follows: ① When the remaining credit value of a completion queue decreases from the initial allocation value to 0, read the corresponding queue Head and Tail values ​​to update the remaining credit value; ② When the sent consumed Credit value of a queue is 0 (when the CPU sends the command completion message of this queue, it is incremented when the credit value is sent, and decremented when the host confirms that the sending is successful), read the Head and Tail values ​​of the queue to update the remaining credit value; ③ The remaining credit values ​​calculated by the Head and Tail of a and b are calculated according to the shared credit SharedCredit and non-shared credit Non-SharedCredit. Credit mode (determined in step S204) is used to update the remaining credit value on each CPU. If it is a shared credit SharedCredit mode, the calculated remaining credit value is used as the shared credit Credit of all CPU cores, that is, it can be considered that the available credit values ​​of all CPU cores sending command completion messages to the completion queue are the remaining credit values ​​of the queue, and it can be updated to the remaining credit value of CPU0; if it is a non-shared Non-Sharrd Credit mode, the calculated remaining credit value needs to be evenly distributed to each CPU core according to the number of CPUs as an independent remaining credit Credit value used on each CPU core, and as the available credit value for each CPU core to send a command completion message to the completion queue.

[0083] Simply put, each CPU core needs to read the Head and Tail values ​​of each completion queue (hereinafter referred to as Credit register reading). In order to reduce the CPU computing power loss introduced by reading the Credit register of the hardware unit, the Credit reading timing is chosen to be triggered before the completion command is sent, and it is necessary to decide whether to read the Credit based on the remaining Credit value of the current queue and the sent Credit feedback value: the Credit register is read only when the remaining Credit value of the queue is 0 and the sent Credit feedback value is non-0, so as to update the remaining credit value of the completion queue.

[0084] In an exemplary embodiment, the method also includes: when the available credit value is equal to a preset credit threshold, if the processor core needs to send a command completion message to the target completion queue, a suspend operation is performed on the command completion message that currently needs to be sent; based on the suspend operation, the command completion message is stored in the suspend linked list of the target completion queue; when the current remaining credit value of the target completion queue is greater than the preset credit threshold, the command completion message stored in the suspend linked list is transferred to the target completion queue.

[0085] Specifically, if the available credit value of a CPU core to a completion queue has dropped to zero, and / or the remaining credit value of the completion queue has dropped to zero, then if the CPU core still needs to send a command completion message to the completion queue, it can be suspended first, that is, hung on the suspension linked list of the completion queue, until the remaining credit value of the completion queue is updated and the updated value is not zero, and then the command completion message in the suspension linked list is transferred to the queue. In this way, even when the system is busy or the remaining credit value of the queue is tight, it can be ensured that all command completion messages can eventually be sent and processed correctly, and will not be permanently lost due to insufficient credit value.

[0086] In the above embodiment, when the current remaining credit value of the target completion queue is greater than the preset credit threshold, the command completion message stored in the suspension list is transferred to the target completion queue, including: obtaining the total number of command completion messages in the suspension list; when the total number of messages is less than or equal to the current remaining credit value, all command completion messages stored in the suspension list are transferred to the target completion queue; when the total number of messages is greater than the current remaining credit value, obtaining the suspension timestamp of each command completion message in the suspension list, wherein the suspension timestamp refers to the time when the command completion message is stored in the suspension list; sorting all command completion messages in the suspension list in ascending order according to the suspension timestamp to obtain the sorting result; and transferring the command completion messages to the target completion queue in sequence according to the sorting result until the current remaining credit value is the same as the preset credit threshold.

[0087] Specifically, Figure 3As shown, in the multi-queue completion command sending suspension module, each CPU core processes the sending completion command suspension list by adopting a round-robin traversal method to complete the sending of the context of the suspended command. After the credit value of the target completion queue is updated, it is necessary to compare it with the total number of command completion messages stored in the suspension list. If the total number of messages is less than or equal to the updated remaining credit value, all command completion messages in the suspension list can be transferred to the target completion queue at one time. If the total number of messages is greater than the updated remaining credit value, some command completion messages that meet the number of remaining credit values ​​can be transferred to the target completion queue in sequence according to the time when each command completion message is suspended in the suspension list, so as to avoid some command completion messages being suspended in the suspension list for too long, affecting the transmission efficiency.

[0088] It should be noted that in the above embodiments provided in the present application, each CPU core may send command completion messages to multiple completion queues. The specific sending method can be determined according to the queue depth of each completion queue according to the method provided in the above embodiments of the present application, and the completion queues do not affect each other; in addition, the remaining credit value of each completion queue and the available credit value of each CPU core to send a command completion message to a certain completion queue may be updated multiple times during the entire transmission process, but the method of each update is the same as the update method proposed in the above embodiments of the present application.

[0089] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0090] The embodiment of the present application also provides a system for transmitting a command completion message, such as Figure 4As shown, it includes: a host, the host is used to send commands to be processed; a hard disk, the hard disk includes a processor core, the hard disk is used to determine the sending mode of sending a command completion message to the target completion queue according to the total number of cores of all processor cores and the queue depth of the target completion queue, and allocate the remaining credit value of the target completion queue to the processor core according to the sending mode to obtain the available credit value of each processor core, the processor core is used to process the commands to be processed to generate a command completion message, and the processor core is also used to transmit the command completion message to the target completion queue when the available credit value is greater than a preset credit threshold.

[0091] Specifically, the transmission system can control the hard disk (SSD) to distribute the pending commands sent by the host to each processor core (CPU core) for processing. The processor core generates a corresponding command completion message after processing the pending commands. In the process of controlling the processor core to send the command completion message to the target completion queue, the sending mode of controlling the processor core to send the command completion message to the target completion queue can be determined by comparing the size relationship between the total number of processor cores in the hard disk and the queue depth of the target completion queue. In combination with the analysis of the remaining storage space in the target completion queue, a remaining credit value that can quantify the current message capacity of the queue is introduced, and the remaining credit value is allocated according to the sending mode, so that the processor core can adaptively adjust the sending of the command completion message without exceeding its own available credit value and the remaining credit value of the target completion queue, so as to avoid overloading the message volume received by a certain completion queue, thereby improving the transmission efficiency of the command completion message.

[0092] The embodiment of the present application further provides a method for transmitting a command completion message. Figure 5 is a flowchart of an optional command completion message transmission method according to an embodiment of the present application, such as Figure 4 As shown, the process includes the following steps:

[0093] Step S502, controlling the processor core to process the pending command sent by the host and obtaining a command completion message;

[0094] Step S504, determining a sending mode for sending a command completion message to the target completion queue according to the total number of cores of all processor cores and the queue depth of the target completion queue;

[0095] Step S506, allocating the remaining credits of the target completion queue to the processor cores according to the sending mode, and obtaining the available credits of each processor core;

[0096] Step S508, when the available credit value is greater than the preset credit threshold, the control processor sends the command completion message to the target completion queue according to the sending mode, so as to transmit the command completion message to the host through the target completion queue.

[0097] Through the above steps, after the host sends the pending command to the hard disk, the hard disk (SSD) can assign it to each processor core (CPU core) for processing. The processor core generates a corresponding command completion message after processing the pending command. In the process of controlling the processor core to send the command completion message to the target completion queue, the sending mode of controlling the processor core to send the command completion message to the target completion queue can be determined by comparing the size relationship between the total number of processor cores in the hard disk and the queue depth of the target completion queue. In combination with the analysis of the remaining storage space in the target completion queue, a remaining credit value that can quantify the current message capacity of the queue is introduced, and the remaining credit value is allocated according to the sending mode, so that the processor core can adaptively adjust the sending of the command completion message without exceeding its own available credit value and the remaining credit value of the target completion queue, thereby controlling each CPU core to feed back the command completion message to the host through the target completion queue while ensuring transmission efficiency.

[0098] In the present embodiment, a transmission device for a command completion message is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made are not repeated here. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0099] Figure 6 is a structural block diagram of a transmission device for a command completion message according to an embodiment of the present application, such as Figure 6 As shown, the device comprises:

[0100] The first acquisition module 61 is used to obtain the total number of processor cores in the target hard disk and the queue depth of the target completion queue when it is determined that the processor core completes the command processing task, wherein the command processing task refers to the task of processing the pending commands sent by the host, the target hard disk refers to the hard disk that needs to transmit the command, and the total number of cores refers to the total number of all processor cores.

[0101] The first determination module 63 is used to determine a sending mode of sending a command completion message to a target completion queue according to the total number of cores and the queue depth, wherein the command completion message refers to a message generated when a processor core completes a command processing task.

[0102] The allocation module 65 is used to allocate the remaining credit value of the target completion queue according to the sending mode to obtain the available credit value of each processor core, wherein the remaining credit value is proportional to the current remaining storage space of the target completion queue, and the remaining storage space refers to the space in the target completion queue that does not store command completion messages.

[0103] The transmission module 67 is used to control the processor core to transmit the command completion message to the target completion queue according to the sending mode when the available credit value is greater than the preset credit threshold.

[0104] It should be noted here that the above-mentioned first acquisition module 61, first determination module 63, allocation module 65 and transmission module 67 correspond to steps S202 to S208 in the above-mentioned embodiments, and the four modules and the corresponding steps implement the same instances and application scenarios, but are not limited to the contents disclosed in the above-mentioned embodiments.

[0105] Through the collaborative cooperation among the four modules of the first acquisition module 61, the first determination module 63, the allocation module 65 and the transmission module 67 mentioned above in the present application, in the process of controlling the processor core to send a command completion message to the target completion queue, the sending mode of controlling the processor core to send the command completion message to the target completion queue can be determined by comparing the size relationship between the total number of processor cores in the hard disk and the queue depth of the target completion queue, and combined with the analysis of the remaining storage space in the target completion queue, a remaining credit value that can quantify the current message capacity of the queue is introduced, and the remaining credit value is allocated according to the sending mode, so that the processor core can adaptively adjust the sending of the command completion message without exceeding its own available credit value and the remaining credit value of the target completion queue, so as to avoid overloading the message volume received by a certain completion queue, thereby improving the transmission efficiency of the command completion message.

[0106] In an exemplary embodiment, the transmission device also includes: a second determination module, used to determine that the submission queue that sends pending commands to the processor core is the target submission queue before obtaining the queue depth of the target completion queue, wherein the submission queue is a cache queue of pending commands; a third determination module, used to determine that the completion queue that has a preset corresponding relationship with the target submission queue is the target completion queue, wherein the preset corresponding relationship is the corresponding relationship established when the submission queue and the completion queue are created.

[0107] In an exemplary embodiment, the third determination module includes: a first acquisition unit, used to acquire a first queue identifier of a target submission queue; a first determination unit, used to determine a queue identifier matching the first queue identifier as a second queue identifier based on the first queue identifier and an identifier mapping table, wherein the identifier mapping table is used to store preset correspondences between multiple groups of submission queues and completion queues; and a second determination unit, used to determine a completion queue whose queue identifier is the second queue identifier as a target completion queue.

[0108] In an exemplary embodiment, a first acquisition module includes: a second acquisition unit, used to acquire the initial storage space of the target completion queue, wherein the initial storage space is the storage space preset when the target completion queue is created; a third determination unit, used to determine the total number of message storage locations in the initial storage space as the queue depth, wherein the message storage location refers to the location in the target completion queue for storing command completion messages.

[0109] In an exemplary embodiment, the first determination module includes: a third acquisition unit, used to compare the total number of cores with the queue depth to obtain a first comparison result; a fourth determination unit, used to determine that the sending mode is a shared credit mode when the first comparison result indicates that the queue depth is less than the total number of cores, wherein the shared credit mode is a mode in which all processor cores share the remaining credit value to send a command completion message to the target completion queue; a fifth determination unit, used to determine that the sending mode is a non-shared credit mode when the comparison result indicates that the queue depth is greater than the total number of cores, wherein the non-shared credit mode is a mode in which the remaining credit value is evenly distributed to each processor core to send a command completion message to the target completion queue.

[0110] In an exemplary embodiment, the transmission device also includes: a second acquisition module, which is used to acquire the current queue state of the target completion queue before allocating the remaining credit value of the target completion queue according to the sending mode and obtaining the available credit value of each processor core; a fourth determination module, which is used to determine that the queue depth of the target completion queue is the remaining credit value when the target completion queue is determined to be in an initial queue state according to the current queue state, wherein the initial queue state refers to the state in which the target completion queue has not started to receive command completion messages; a first calculation module, which is used to calculate the remaining credit value of the target completion queue according to the position of the head position label and the tail position label in the target completion queue when the target completion queue is determined to be in a message transmission state according to the current queue state, wherein the message transmission state refers to the state in which the target completion queue starts to receive the command completion message sent by the processor core, the head position label refers to the label of the next message storage position in the target completion queue where the command completion message needs to be sent, and the tail position label refers to the label of the next message storage position in the target completion queue where the command completion message needs to be received.

[0111] In an exemplary embodiment, the calculation module includes: a fourth acquisition unit, which is used to compare the head position label with the tail position label to obtain a second comparison result; a sixth determination unit, which is used to determine that the queue depth of the target completion queue is the remaining credit value when the second comparison result indicates that the head position label is equal to the tail position label; and a first calculation unit, which is used to calculate the remaining credit value according to the head position label and the tail position label using a first formula when the second comparison result indicates that the head position label is greater than the tail position label, wherein the first formula is: , Indicates the remaining credit value, Indicates the head position number, represents the tail position number; and a second calculation unit, configured to calculate the remaining credit value using a second formula according to the head position number and the tail position number when the second comparison result indicates that the head position number is less than the tail position number, wherein the second formula is: , Indicates the queue depth.

[0112] In an exemplary embodiment, the allocation module includes: a seventh determination unit, which is used to determine that the available credit value of each processor core is a residual credit value when the sending mode is a shared credit mode; a fifth acquisition unit, which is used to evenly distribute the residual credit value according to the total number of cores to obtain an intermediate available credit value when the sending mode is a non-shared credit mode; an eighth determination unit, which is used to determine that the available credit value of each processor core is an intermediate available credit value when the intermediate available credit value is an integer; and a ninth determination unit, which is used to determine that the available credit value of each processor core is a target available credit value when the intermediate available credit value is not an integer, wherein the target available credit value is a maximum integer not greater than the intermediate available credit value.

[0113] In an exemplary embodiment, the transmission device also includes: an allocation unit, which is used to allocate the idle credit value of the target completion queue to the processor core according to a predetermined allocation method after determining that the available credit value of each processor core is the target available credit value, wherein the idle credit value refers to the credit value of the remaining credit value that is not allocated to the processor core.

[0114] In an exemplary embodiment, an allocation unit includes at least one of the following: a first allocation subunit, used to allocate all idle credit values ​​to any processor core; a second allocation subunit, used to allocate the idle credit values ​​one by one to multiple processor cores of the same number according to the number of idle credit values; a third allocation subunit, used to allocate the idle credit values ​​to processor cores whose credit requirements are higher than a requirement threshold, wherein the credit requirement is used to reflect the degree of requirement of the processor core for the remaining credit values; a placement subunit, used to place the idle credit values ​​in a shared credit pool, so as to apply for idle credit values ​​from the shared credit pool when the available credit value of the processor core is not greater than a preset credit threshold and a command completion message needs to be sent.

[0115] In an exemplary embodiment, a transmission module includes: a first transmission unit, which is used to control the processor core to transmit the command completion message to the target completion queue after performing a locking operation on the available credit value if the sending mode is a shared credit mode; and a second transmission unit, which is used to control the processor core to transmit the command completion message to the target completion queue if the sending mode is a non-shared credit mode.

[0116] In an exemplary embodiment, a first transmission unit includes: a determination subunit, which is used to determine that the processor core that currently needs to send a command completion message is a target processor core when the sending mode is a shared credit mode; a first control subunit, which is used to control the target processor core to perform a locking operation on the available credit value; and a second control subunit, which is used to control the target processor core to transmit the command completion message to the target completion queue during the process of locking the available credit value based on the locking operation, wherein locking means that processor cores other than the target processor core cannot apply for the available credit value to transmit the command completion message to the target completion queue.

[0117] In an exemplary embodiment, the transmission device also includes: a third control subunit, which is used to control the processor core to perform an unlocking operation on the available credit value to unlock the available credit value after the control processor core transmits the command completion message to the target completion queue after performing a locking operation on the available credit value.

[0118] In an exemplary embodiment, the transmission device also includes: a first update module, which is used to update the available credit value of the processor core to a first value reduced by 1 after the processor core sends a command completion message to the target completion queue each time, wherein the first value is not less than the value of a preset credit threshold; and a second update module, which is used to update the remaining credit value of the target completion queue to a second value reduced by 1 after the target completion queue receives a command completion message each time, wherein the second value is not less than the preset credit threshold.

[0119] In an exemplary embodiment, the transmission device also includes: a third acquisition module, which is used to obtain the current head position label and the current tail position label of the target completion queue if the remaining credit value is the same as the preset credit threshold during the process of updating the remaining credit value; a second calculation module, which is used to calculate the current remaining credit value of the target completion queue based on the current head position label and the current tail position label; and a fourth acquisition module, which is used to reallocate the current remaining credit value according to the sending mode to obtain the current available credit value of each processor core.

[0120] In an exemplary embodiment, the transmission device also includes: an execution module, which is used to perform a suspend operation on the command completion message that currently needs to be sent if the processor core needs to send a command completion message to the target completion queue when the available credit value is equal to a preset credit threshold; a storage module, which is used to store the command completion message in the suspension linked list of the target completion queue based on the suspend operation; and a transfer module, which is used to transfer the command completion message stored in the suspension linked list to the target completion queue when the current remaining credit value of the target completion queue is greater than the preset credit threshold.

[0121] In an exemplary embodiment, the transfer module includes: a sixth acquisition unit, which is used to obtain the total number of command completion messages in the suspension list; a first transfer unit, which is used to transfer all command completion messages stored in the suspension list to the target completion queue when the total number of messages is less than or equal to the current remaining credit value; a seventh acquisition unit, which is used to obtain the suspension timestamp of each command completion message in the suspension list when the total number of messages is greater than the current remaining credit value, wherein the suspension timestamp refers to the time when the command completion message is stored in the suspension list; an eighth acquisition unit, which is used to sort all command completion messages in the suspension list in ascending order according to the suspension timestamp to obtain a sorting result; and a second transfer unit, which is used to transfer the command completion messages to the target completion queue in sequence according to the sorting result until the current remaining credit value is the same as the preset credit threshold.

[0122] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0123] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0124] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0125] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0126] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0127] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0128] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0129] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for transmitting a command completion message, characterized in that: include: When it is determined that the processor core completes the command processing task, obtaining the total number of cores of the processor core and the queue depth of the target completion queue, wherein the command processing task refers to a task of processing a pending command sent by the host, and the total number of cores refers to the total number of all the processor cores; Determining a sending mode for sending a command completion message to the target completion queue according to the total number of cores and the queue depth, wherein the command completion message refers to a message generated when the processor core completes the command processing task; Allocating the remaining credit value of the target completion queue according to the sending mode to obtain the available credit value of each processor core, wherein the remaining credit value is proportional to the current remaining storage space of the target completion queue, and the remaining storage space refers to the space in the target completion queue that does not store the command completion message; When the available credit value is greater than a preset credit threshold, controlling the processor core to transmit the command completion message to the target completion queue according to the sending mode; Among them, determining a sending mode for sending a command completion message to the target completion queue according to the total number of cores and the queue depth includes: comparing the total number of cores with the queue depth to obtain a first comparison result; when the first comparison result indicates that the queue depth is less than the total number of cores, determining the sending mode to be a shared credit mode, wherein the shared credit mode is a mode in which all the processor cores share the remaining credit value to send the command completion message to the target completion queue; when the comparison result indicates that the queue depth is greater than the total number of cores, determining the sending mode to be a non-shared credit mode, wherein the non-shared credit mode is a mode in which the remaining credit value is evenly distributed to each of the processor cores to send the command completion message to the target completion queue.

2. The method according to claim 1, characterized in that Before obtaining the queue depth of the target completion queue, the method further includes: Determine a submission queue for sending the pending command to the processor core as a target submission queue, wherein the submission queue is a cache queue of the pending command; A completion queue that has a preset corresponding relationship with the target submission queue is determined as the target completion queue, wherein the preset corresponding relationship is a corresponding relationship established when the submission queue and the completion queue are created.

3. The method according to claim 2, characterized in that Determining a completion queue that has a preset corresponding relationship with the target submission queue as the target completion queue includes: Obtain a first queue identifier of the target submission queue; Determine, according to the first queue identifier and an identifier mapping table, a queue identifier matching the first queue identifier as a second queue identifier, wherein the identifier mapping table is used to store the preset correspondence between multiple groups of the submission queues and the completion queues; Determine that the completion queue whose queue identifier is the second queue identifier is the target completion queue.

4. The method according to claim 1, characterized in that Get the queue depth of the target completion queue, including: Acquire the initial storage space of the target completion queue, wherein the initial storage space is the storage space preset when the target completion queue is created; The total number of message storage positions in the initial storage space is determined as the queue depth, wherein the message storage position refers to a position in the target completion queue for storing the command completion message.

5. The method according to claim 1, characterized in that Before allocating the remaining credit value of the target completion queue according to the sending mode to obtain the available credit value of each processor core, the method further includes: Obtain the current queue state of the target completion queue; In a case where it is determined according to the current queue state that the target completion queue is in an initial queue state, determining the queue depth of the target completion queue to be the remaining credit value, wherein the initial queue state refers to a state in which the target completion queue has not started to receive the command completion message; In a case where it is determined that the target completion queue is in a message transmission state according to the current queue state, the remaining credit value of the target completion queue is calculated according to the positions of the head position label and the tail position label in the target completion queue, wherein the message transmission state refers to the state in which the target completion queue starts to receive the command completion message sent by the processor core, the head position label refers to the label of the next message storage position in the target completion queue where the command completion message needs to be sent, and the tail position label refers to the label of the next message storage position in the target completion queue where the command completion message needs to be received.

6. The method according to claim 5, characterized in that Calculating the remaining credit value of the target completion queue according to the positions of the head position number and the tail position number in the target completion queue includes: Compare the head position number with the tail position number to obtain a second comparison result; In a case where the second comparison result indicates that the head position number is equal to the tail position number, determining the queue depth of the target completion queue to be the remaining credit value; When the second comparison result indicates that the head position number is greater than the tail position number, the remaining credit value is calculated using a first formula according to the head position number and the tail position number, wherein the first formula is: , represents the remaining credit value, represents the head position number, Indicates the tail position number; When the second comparison result indicates that the head position number is less than the tail position number, the remaining credit value is calculated using a second formula according to the head position number and the tail position number, wherein the second formula is: , Indicates the queue depth.

7. The method according to claim 1, characterized in that Allocating the remaining credit value of the target completion queue according to the sending mode to obtain the available credit value of each processor core includes: When the sending mode is a shared credit mode, determining that the available credit value of each of the processor cores is the remaining credit value; When the sending mode is a non-shared credit mode, the remaining credit value is evenly distributed according to the total number of cores to obtain an intermediate available credit value; When the intermediate available credit value is an integer, determining that the available credit value of each of the processor cores is the intermediate available credit value; When the intermediate available credit value is not the integer, it is determined that the available credit value of each of the processor cores is a target available credit value, wherein the target available credit value is a maximum integer not greater than the intermediate available credit value.

8. The method according to claim 7, characterized in that After determining that the available credit value of each of the processor cores is the target available credit value, the method further includes: The idle credit value of the target completion queue is allocated to the processor core according to a predetermined allocation method, wherein the idle credit value refers to the credit value of the remaining credit value that is not allocated to the processor core.

9. The method according to claim 8, characterized in that Allocating the idle credits of the target completion queue to the processor core according to a predetermined allocation method, including at least one of the following: Allocate all of the idle credits to any one of the processor cores; Allocating the idle credit values ​​one by one to a plurality of processor cores having the same number according to the number of the idle credit values; Allocating the idle credit value to the processor core whose credit demand is higher than a demand threshold, wherein the credit demand is used to reflect the degree of demand of the processor core for the remaining credit value; The idle credit value is placed in a shared credit pool, so as to apply for the idle credit value from the shared credit pool when the available credit value of the processor core is not greater than the preset credit threshold and the command completion message needs to be sent.

10. The method according to claim 1, characterized in that When the available credit value is greater than a preset credit threshold, controlling the processor core to transmit the command completion message to the target completion queue according to the sending mode includes: If the sending mode is a shared credit mode, controlling the processor core to transmit the command completion message to the target completion queue after performing a locking operation on the available credit value; If the sending mode is a non-shared credit mode, controlling the processor core to transmit the command completion message to the target completion queue.

11. The method according to claim 10, characterized in that If the sending mode is a shared credit mode, controlling the processor core to transmit the command completion message to the target completion queue after performing a lock operation on the available credit value includes: In a case where the sending mode is the shared credit mode, determining that the processor core to which the command completion message is currently required to be sent is a target processor core; Controlling the target processor core to perform the locking operation on the available credit value; In the process of locking the available credit value based on the locking operation, the target processor core is controlled to transmit the command completion message to the target completion queue, wherein the locking indicates that the processor cores other than the target processor core cannot apply for the available credit value to transmit the command completion message to the target completion queue.

12. The method according to claim 10, characterized in that After controlling the processor core to transmit the command completion message to the target completion queue after performing a lock operation on the available credit value, the method further includes: The processor core is controlled to perform an unlocking operation on the available credit value to unlock the available credit value.

13. The method according to any one of claims 1 to 12, characterized in that The method further comprises: After the processor core sends a command completion message to the target completion queue each time, updating the available credit value of the processor core to a first value reduced by 1, wherein the first value is not less than the value of the preset credit threshold; After the target completion queue receives each command completion message, the remaining credit value of the target completion queue is updated to a second value reduced by 1, wherein the second value is not less than a preset credit threshold.

14. The method according to claim 13, characterized in that The method further comprises: During the process of updating the remaining credit value, if the remaining credit value is the same as the preset credit threshold, obtaining the current head position number and the current tail position number of the target completion queue; Calculating the current remaining credit value of the target completion queue according to the current head position number and the current tail position number; The current remaining credit value is reallocated according to the sending mode to obtain the current available credit value of each processor core.

15. The method according to claim 1, characterized in that The method further comprises: In a case where the available credit value is equal to the preset credit threshold, if the processor core needs to send the command completion message to the target completion queue, a suspend operation is performed on the command completion message that currently needs to be sent; Based on the suspend operation, storing the command completion message in the suspend linked list of the target completion queue; When the current remaining credit value of the target completion queue is greater than the preset credit threshold, the command completion message stored in the suspension linked list is transferred to the target completion queue.

16. The method according to claim 15, characterized in that When the current remaining credit value of the target completion queue is greater than the preset credit threshold, transferring the command completion message stored in the pending linked list to the target completion queue includes: Obtain the total number of command completion messages in the pending linked list; When the total number of messages is less than or equal to the current remaining credit value, all the command completion messages stored in the pending linked list are transferred to the target completion queue; When the total number of messages is greater than the current remaining credit value, obtaining a suspension timestamp of each command completion message in the suspension linked list, wherein the suspension timestamp refers to the time when the command completion message is stored in the suspension linked list; Sorting all the command completion messages in the suspension linked list in ascending order according to the suspension timestamp to obtain a sorting result; The command completion messages are transferred to the target completion queue in sequence according to the sorting result until the current remaining credit value is the same as the preset credit threshold.

17. A command completion message transmission system, characterized in that: include: A host, the host is used to send commands to be processed; A hard disk, the hard disk comprising a processor core, the hard disk is used to determine a sending mode for sending the command completion message to the target completion queue according to the total number of cores of all the processor cores and the queue depth of the target completion queue, and to allocate the remaining credit value of the target completion queue to the processor core according to the sending mode to obtain the available credit value of each processor core, the processor core is used to process the to-be-processed command to generate a command completion message, and the processor core is also used to transmit the command completion message to the target completion queue when the available credit value is greater than a preset credit threshold; Wherein, the hard disk is also used to compare the total number of cores with the queue depth to obtain a first comparison result; when the first comparison result indicates that the queue depth is less than the total number of cores, the sending mode is determined to be a shared credit mode, wherein the shared credit mode is a mode in which all the processor cores share the remaining credit value to send the command completion message to the target completion queue; when the comparison result indicates that the queue depth is greater than the total number of cores, the sending mode is determined to be a non-shared credit mode, wherein the non-shared credit mode is a mode in which the remaining credit value is evenly distributed to each of the processor cores to send the command completion message to the target completion queue.

18. A method for transmitting a command completion message, characterized in that: include: The control processor core processes the pending commands sent by the host and obtains a command completion message; Determine a sending mode for sending the command completion message to the target completion queue according to the total number of cores of all the processor cores and the queue depth of the target completion queue; Allocating the remaining credit value of the target completion queue to the processor cores according to the sending mode to obtain the available credit value of each processor core; When the available credit value is greater than a preset credit threshold, controlling the processor to send the command completion message to the target completion queue according to the sending mode, so as to transmit the command completion message to the host through the target completion queue; Among them, determining the sending mode of sending the command completion message to the target completion queue according to the total number of cores of all the processor cores and the queue depth of the target completion queue includes: comparing the total number of cores with the queue depth to obtain a first comparison result; when the first comparison result indicates that the queue depth is less than the total number of cores, determining the sending mode to be a shared credit mode, wherein the shared credit mode is a mode in which all the processor cores share the remaining credit value to send the command completion message to the target completion queue; when the comparison result indicates that the queue depth is greater than the total number of cores, determining the sending mode to be a non-shared credit mode, wherein the non-shared credit mode is a mode in which the remaining credit value is evenly distributed to each of the processor cores to send the command completion message to the target completion queue.

19. A transmission device for a command completion message, characterized in that: include: A first acquisition module is used to acquire the total number of cores of the processor cores in the target hard disk and the queue depth of the target completion queue when it is determined that the processor core completes the command processing task, wherein the command processing task refers to a task of processing a pending command sent by the host, the target hard disk refers to a hard disk to which command transmission is required, and the total number of cores refers to the total number of all the processor cores; a first determining module, configured to determine a sending mode of sending a command completion message to the target completion queue according to the total number of cores and the queue depth, wherein the command completion message refers to a message generated when the processor core completes the command processing task; an allocation module, configured to allocate the remaining credit value of the target completion queue according to the sending mode to obtain the available credit value of each processor core, wherein the remaining credit value is proportional to the current remaining storage space of the target completion queue, and the remaining storage space refers to the space in the target completion queue that does not store the command completion message; a transmission module, configured to control the processor core to transmit the command completion message to the target completion queue according to the sending mode when the available credit value is greater than a preset credit threshold; Among them, the first determination module includes: a third acquisition unit, used to compare the total number of cores with the queue depth to obtain a first comparison result; a fourth determination unit, used to determine that the sending mode is a shared credit mode when the first comparison result indicates that the queue depth is less than the total number of cores, wherein the shared credit mode is a mode in which all the processor cores share the remaining credit value to send the command completion message to the target completion queue; a fifth determination unit, used to determine that the sending mode is a non-shared credit mode when the comparison result indicates that the queue depth is greater than the total number of cores, wherein the non-shared credit mode is a mode in which the remaining credit value is evenly distributed to each of the processor cores to send the command completion message to the target completion queue.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 16, or implements the steps of the method described in claim 18.

21. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the processor implements the steps of the method described in any one of claims 1 to 16, or implements the steps of the method described in claim 18.

Images