Accelerator chip instruction operation analysis method, device, equipment, medium and product

Abstract

The invention relates to an accelerator chip instruction operation analysis method and device, equipment, a medium and a product. The method comprises the following steps: obtaining a plurality of data streams obtained by executing a binary file corresponding to a target kernel function by an accelerator chip, then obtaining a plurality of assembly instruction codes corresponding to the binary file according to the binary file, and then obtaining a plurality of assembly instruction codes corresponding to the binary file according to a time sequence of a clock cycle, performing matching processing on each assembly instruction code and a data stream corresponding to the assembly instruction code in sequence to obtain an instruction code analysis result corresponding to the assembly instruction code, the instruction code analysis result comprises at least one of the number of clock cycles required by the accelerator chip to execute the assembly instruction code and the number of execution times corresponding to the assembly instruction code. By adopting the method, the accuracy of analysis results can be improved.

Description

Technical Field

[0001] The present application relates to the field of high-performance computer technology, and in particular to an accelerator chip instruction operation analysis method, device, equipment, medium and product. Background Art

[0002] With the development of computer technology, high-performance computers are widely used. High-performance computers refer to computer systems that are accelerated by clusters and dedicated accelerator chips. They have the characteristics of high computational complexity and large amount of computational data, and are usually used in scientific computing, deep learning training and reasoning, and other fields. In order to optimize the computing performance of high-performance computers, it is usually necessary to study the dedicated program of the accelerator chip - the kernel function.

[0003] In the prior art, ROC Prof (GPU performance analysis tool) is usually used to analyze the running status of the kernel function running on the accelerator chip. The analysis result of the kernel function can display the running process of various instructions contained in the kernel function. However, the analysis result obtained by the above method has the problem of low accuracy. Summary of the invention

[0004] Based on this, it is necessary to provide an accelerator chip instruction operation analysis method, device, equipment, medium and product that can improve the accuracy of the analysis results of the kernel function in response to the above technical problems.

[0005] In a first aspect, the present application provides an accelerator chip instruction operation analysis method. The method comprises:

[0006] Acquire multiple data streams obtained by the accelerator chip executing the binary file corresponding to the target kernel function;

[0007] According to the binary file, obtaining a plurality of assembly instruction codes corresponding to the binary file;

[0008] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the data stream corresponding to the assembly instruction code in turn to obtain an instruction code analysis result corresponding to the assembly instruction code, wherein the instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code.

[0009] The data stream corresponding to each assembly instruction code is analyzed on the clock cycle, and the instruction code analysis result obtained can accurately reflect the running process of each assembly instruction code, for example, it can reflect the number of clock cycles required to execute the assembly instruction code, the number of executions corresponding to the assembly instruction code, etc., thereby avoiding the problem of low accuracy of the analysis result caused by the use of ROC Prof in the traditional technology to analyze the kernel function running on the accelerator chip, where the analysis result can only roughly reflect the running process of each type of assembly instruction code. The accelerator chip instruction running analysis method provided in the embodiment of the present application refines the analysis granularity of the kernel function analysis, and the instruction code analysis result obtained is more accurate.

[0010] In one embodiment, obtaining multiple assembly instruction codes corresponding to the binary file according to the binary file includes:

[0011] The binary file is disassembled by using a performance analysis tool to obtain multiple assembly instruction codes corresponding to the binary file.

[0012] In this embodiment, a performance analysis tool with disassembly capability is directly used to automatically disassemble the binary file, thereby improving the efficiency of disassembly.

[0013] In one embodiment, each assembly instruction code is matched with a data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycles to obtain an instruction code analysis result corresponding to the assembly instruction code, including:

[0014] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the data stream corresponding to the assembly instruction code in turn to determine the execution start time, execution end time and execution count corresponding to the assembly instruction code;

[0015] Based on the execution start time and the execution end time, determine the number of clock cycles required to execute the assembly instruction code.

[0016] In this embodiment, the computer device matches each assembly instruction code with each data stream in sequence according to the chronological order. The matching method is more convenient. After the matching process, the execution start time and execution end time corresponding to each assembly instruction code, the number of execution times of the assembly instruction code and the required number of clock cycles are determined, so that developers can quickly determine where the target kernel function needs to be optimized and improved based on the instruction code analysis results obtained in the above embodiment, thereby improving the efficiency of developers in optimizing the target kernel function.

[0017] In one embodiment, the method further comprises:

[0018] According to the preset display mode, the instruction code analysis results corresponding to each assembly instruction code are visually displayed.

[0019] In this embodiment, the computer device visualizes the instruction code analysis results corresponding to each assembly instruction code in a preset display mode, which more intuitively reflects the instruction code analysis results corresponding to each assembly instruction code, allowing developers to more intuitively and accurately determine the running status of each assembly instruction code, thereby improving the efficiency of the optimization target kernel function.

[0020] In one embodiment, the instruction code analysis results corresponding to each assembly instruction code are visually displayed according to a preset display mode, including:

[0021] Determine the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category;

[0022] In a preset display interface, analysis results of each instruction code under an instruction category are displayed correspondingly to the computing unit identifier of the computing unit corresponding to the instruction category.

[0023] In the process of visually displaying the instruction code analysis results, this embodiment not only displays the instruction code analysis results corresponding to the assembly instruction code, but also displays the instruction categories and computing units corresponding to each assembly instruction code, making the display dimension richer.

[0024] In one embodiment, in a preset display interface, the analysis results of each instruction code under the instruction category are displayed correspondingly to the computing unit identifier of the computing unit corresponding to the instruction category, including:

[0025] For each instruction category corresponding to the computing unit identifier, a timeline control corresponding to the instruction category is displayed in the display interface in the chronological order of the clock cycles to display the analysis results of each instruction code of each assembly instruction code under the instruction category.

[0026] In this embodiment, the timeline control can more vividly display the analysis results of each instruction code in time sequence.

[0027] In one embodiment, the timeline control is used to display the clock cycles in which each assembly instruction code under the instruction category is executed, and the method further includes:

[0028] If a click operation on the target timeline control is detected, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position of the display interface.

[0029] In this embodiment, the instruction code analysis result is displayed in more detail at a preset position.

[0030] In a second aspect, the present application also provides an accelerator chip instruction operation analysis device. The device comprises:

[0031] A first acquisition module is used to acquire multiple data streams obtained by the accelerator chip executing a binary file corresponding to a target kernel function;

[0032] A second acquisition module is used to acquire multiple assembly instruction codes corresponding to the binary file according to the binary file;

[0033] The matching module is used to match each assembly instruction code with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycle, and obtain the instruction code analysis result corresponding to the assembly instruction code. The instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code.

[0034] In a third aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the method described in the first aspect are implemented.

[0035] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0036] In a fifth aspect, the present application further provides a computer program product, wherein the computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0037] The above-mentioned accelerator chip instruction operation analysis method, device, equipment, medium and product obtain multiple data streams obtained by obtaining a binary file corresponding to the target kernel function executed by the accelerator chip, and then obtain multiple assembly instruction codes corresponding to the binary file according to the binary file, and then match each of the assembly instruction codes with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycle to obtain the instruction code analysis result corresponding to the assembly instruction code, and the instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code. In this way, the data stream corresponding to each assembly instruction code is analyzed in the clock cycle, and the obtained instruction code analysis result can accurately reflect the running process of each assembly instruction code, for example, it can reflect the number of clock cycles required to execute the assembly instruction code, the number of executions corresponding to the assembly instruction code, etc., thereby avoiding the problem of low accuracy of the analysis result caused by the use of ROC Prof in traditional technology to analyze the kernel function running on the accelerator chip, where the analysis result can only roughly reflect the running process of each type of assembly instruction code. The accelerator chip instruction running analysis method provided in the embodiment of the present application refines the analysis granularity of the kernel function analysis, and the obtained instruction code analysis result is more accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A schematic diagram of a flow chart of an accelerator chip instruction operation analysis method in one embodiment;

[0040] Figure 2 is a schematic flow chart of step 102 in another embodiment;

[0041] Figure 3 is a schematic flow chart of step 103 in another embodiment;

[0042] Figure 4 A schematic diagram of a flow chart for visually displaying instruction code analysis results in another embodiment;

[0043] Figure 5 is a flow chart of step 401 in another embodiment;

[0044] Figure 6A display interface for visually displaying an exemplary instruction code analysis result in another embodiment;

[0045] Figure 7 is a schematic flow chart of step 501 in another embodiment;

[0046] Figure 8 A display interface for visually displaying an exemplary instruction code analysis result in another embodiment;

[0047] Fig. 9 It is a structural block diagram of an accelerator chip instruction operation analysis device in one embodiment;

[0048] Fig.10 A schematic diagram of a flow chart of an accelerator chip instruction operation analysis method executed by an accelerator chip instruction operation analysis device in another embodiment;

[0049] Fig.11 It is a structural block diagram of an accelerator chip instruction operation analysis device in one embodiment;

[0050] Fig.12 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0052] With the development of computer technology, high-performance computers are widely used. High-performance computers refer to computer systems accelerated by clusters and dedicated accelerator chips. They have the characteristics of high computational complexity and large amounts of computational data, and have high requirements for computational efficiency, computational algorithms, and efficient and reasonable use of system resources. Currently, in the fields of scientific computing, deep learning training and reasoning, which involve a large amount of data calculation, clusters and heterogeneous computing are used for acceleration. For the research and development and optimization process of heterogeneous computing applications, more attention is paid to the acceleration effect, performance optimization and improvement effect, and optimization tools and means.

[0053] At present, in the process of programming accelerator chips, in addition to writing the usual CPU program to control the overall logic, it is also necessary to separately write a dedicated program for the accelerator chip - the kernel function. For the performance of the overall accelerator chip, the performance improvement of the kernel function is crucial. In the process of optimizing the performance of the kernel function, there is also a strong dependence on performance analysis related tools.

[0054] Therefore, in order to optimize the computing performance of high-performance computers, it is usually necessary to study the kernel function, the dedicated program of the accelerator chip. ROC Prof (GPU performance analysis tool) is a performance analysis tool for the current rocm computing platform (an open source computing architecture of AMD). It can analyze the running status of the kernel function running on the accelerator chip. It currently provides the display of hardware performance counting indicators and performs indicator counting statistics on the hardware behavior during the kernel function running process.

[0055] The problem with the above method is that ROC Prof can only display the running status of various instructions contained in the kernel function, and cannot be refined to the fine-grained execution process of the assembly instruction. Therefore, the kernel function optimization based on the analysis result needs to rely on continuous guesswork and trial and error, which is a time-consuming and laborious task, and requires a high level of experience from the optimizer. In some scenarios that pursue extreme optimization, it is usually difficult to achieve the ideal effect, that is, the analysis results cannot accurately reflect the name and parameters of each assembly instruction code, and the accuracy is low.

[0056] In view of this, the embodiments of the present application provide an accelerator chip instruction operation analysis method, device, equipment, medium and product, which obtains multiple data streams by obtaining a binary file corresponding to a target kernel function executed by the accelerator chip, and then obtains multiple assembly instruction codes corresponding to the binary file according to the binary file, and then matches each of the assembly instruction codes with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycles to obtain an instruction code analysis result corresponding to the assembly instruction code, wherein the instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code. In this way, the data stream corresponding to each assembly instruction code is analyzed in the clock cycle, and the obtained instruction code analysis result can accurately reflect the running process of each assembly instruction code, for example, it can reflect the number of clock cycles required to execute the assembly instruction code, the number of executions corresponding to the assembly instruction code, etc., thereby avoiding the problem of low accuracy of the analysis result caused by the use of ROC Prof in traditional technology to analyze the kernel function running on the accelerator chip, where the analysis result can only roughly reflect the running process of each type of assembly instruction code. The accelerator chip instruction running analysis method provided in the embodiment of the present application refines the analysis granularity of the kernel function analysis, and the obtained instruction code analysis result is more accurate.

[0057] The embodiment of the present application provides an accelerator chip instruction operation analysis method, which can be applied to a computer device, which can be an accelerator chip instruction operation analysis device, which can be a server or a terminal, wherein the terminal can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, Internet of Things devices and portable wearable devices, and the Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The server can be implemented as an independent server or a server cluster consisting of multiple servers.

[0058] In an exemplary embodiment, Figure 1 As shown, a method for analyzing the operation of accelerator chip instructions is provided, which is described by taking the application of the method to a computer device as an example, and includes steps 101 to 103.

[0059] Step 101: Acquire multiple data streams obtained by an accelerator chip executing a binary file corresponding to a target kernel function.

[0060] The target kernel function can be a dedicated program written for the accelerator chip. The target kernel function in the embodiment of the present application is a kernel function to be run analyzed. In the embodiment of the present application, when the computer device analyzes the running status of the target kernel function, it is necessary to send the target kernel function to the accelerator chip, and the accelerator chip executes the target kernel function to obtain the running status of the target kernel function.

[0061] In a possible implementation, before the computer device sends the target kernel function to be analyzed to the accelerator chip for execution, it is necessary to determine whether the system environment variables in the current system meet the preset system environment variables.

[0062] For a method for a computer device to determine whether a system environment variable conforms to a preset system environment variable, in a possible implementation, the computer device detects the system environment variable through a runtime system (runtime system), and matches the detected system environment variable with the preset system environment variable. Optionally, if the match is successful, it means that the system environment variable configured by the current system supports the accelerator chip to execute the target kernel function, and the computer device executes other steps of the embodiment of the present application; optionally, if the match fails, the computer device configures the system environment accordingly according to the preset system environment variable, so that the system environment variable of the current system conforms to the preset system environment variable.

[0063] When the system environment variables in the system meet the preset system environment variables, for the target kernel function to be analyzed, the computer device converts the target kernel function into a file that can be recognized and executed by the accelerator chip, and then sends the binary file corresponding to the target kernel function to the accelerator chip via the computer device, and the accelerator chip executes the target kernel function.

[0064] The accelerator chip may be a GPU (Graphic Process Unit), and the computer device may send a binary file corresponding to the target kernel function to the accelerator chip through a runtime system.

[0065] The binary file contains multiple assembly instruction codes. When the accelerator chip sequentially executes the assembly instruction codes contained in the binary file, data streams corresponding to each assembly instruction code will be generated. These data streams will be stored in the registers on the accelerator chip. Regarding the method for the computer device to obtain the data stream, optionally, a preset size of memory space is applied. For example, a 64MB accelerator chip and the computer device can operate on the memory space. When the accelerator chip finishes executing the binary file, the data stream stored in the register can be written into the memory space, so that the computer device can obtain the data stream through the memory space; optionally, a buffer is established, and the accelerator chip and the computer device can operate on the buffer. When the accelerator chip executes the binary file, the corresponding data stream will be stored in the register. The accelerator chip can write the contents stored in the register into the buffer in real time, so that the computer device can obtain multiple data streams generated when the accelerator chip executes the binary file in real time through the buffer. Here, there is no restriction on the method for the computer device to obtain the data stream.

[0066] Step 102: According to the binary file, a plurality of assembly instruction codes corresponding to the binary file are obtained.

[0067] Regarding the method for a computer device to obtain assembly instruction codes corresponding to a binary file, in one possible implementation, the computer device disassembles the binary file through a disassembly tool to obtain multiple assembly instruction codes corresponding to the binary file; optionally, the computer device obtains multiple assembly instruction codes corresponding to a binary file input by other devices.

[0068] Step 103 , matching each assembly instruction code with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycles, and obtaining the instruction code analysis result corresponding to the assembly instruction code.

[0069] When the accelerator chip executes a binary file, the data stream is generated sequentially one by one when the accelerator chip executes the assembly instruction code contained in the binary file. In a possible implementation, using the clock cycle as the timing unit, the computer device matches each assembly instruction code line by line according to the execution order in the timing with the sequentially generated data streams to obtain a mapping relationship between each assembly instruction code and each data stream.

[0070] The computer device can analyze the execution process of the assembly instruction code according to the data stream corresponding to each assembly instruction code to obtain the instruction code analysis result corresponding to the assembly instruction code, wherein the instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code.

[0071] In a possible implementation, after the computer device matches each assembly instruction code with the data stream corresponding to the assembly instruction code, it counts each executed assembly instruction code to determine the number of times the assembly instruction code is repeatedly executed.

[0072] In another possible implementation, when the computer device sequentially matches each assembly instruction code according to the data stream generated in each time sequence, it can determine the clock cycle at which each assembly instruction code starts to execute and the clock cycle at which the execution ends; and for an assembly instruction code, the computer device can determine the number of clock cycles required for the accelerator chip to execute the assembly instruction code by making a difference between the clock cycle at which the execution ends and the clock cycle at which the execution starts corresponding to the assembly instruction code.

[0073] The above-mentioned accelerator chip instruction operation analysis method obtains multiple data streams obtained by obtaining a binary file corresponding to the target kernel function executed by the accelerator chip, and then obtains multiple assembly instruction codes corresponding to the binary file according to the binary file, and then matches each of the assembly instruction codes with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycles to obtain the instruction code analysis result corresponding to the assembly instruction code, and the instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code. In this way, the data stream corresponding to each assembly instruction code is analyzed in the clock cycle, and the obtained instruction code analysis result can accurately reflect the running process of each assembly instruction code, for example, it can reflect the number of clock cycles required to execute the assembly instruction code, the number of executions corresponding to the assembly instruction code, etc., thereby avoiding the problem of low accuracy of the analysis result caused by the use of ROC Prof in traditional technology to analyze the kernel function running on the accelerator chip, where the analysis result can only roughly reflect the running process of each type of assembly instruction code. The accelerator chip instruction running analysis method provided in the embodiment of the present application refines the analysis granularity of the kernel function analysis, and the obtained instruction code analysis result is more accurate.

[0074] In one embodiment, based on the above Figure 1 The embodiment shown, see Figure 2 This embodiment relates to a process of obtaining multiple assembly instruction codes corresponding to a binary file according to a binary file. Figure 2 As shown, step 102 may include step 201 .

[0075] Step 201 , using a performance analysis tool, disassembles the binary file to obtain a plurality of assembly instruction codes corresponding to the binary file.

[0076] The computer device analyzes the operation of the target kernel function on the accelerator chip through a performance analysis tool. In one possible implementation, the performance analysis tool has a disassembly capability to convert a binary file into assembly instruction code. The computer device can use the performance analysis tool to disassemble the acquired binary file to obtain multiple assembly instruction codes corresponding to the binary file.

[0077] In this embodiment, a performance analysis tool with disassembly capability is directly used to automatically disassemble the binary file, thereby improving the efficiency of disassembly.

[0078] In one embodiment, based on the above Figure 1 The embodiment shown, see Figure 3This embodiment involves a process of matching each assembly instruction code with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycle to obtain the instruction code analysis result corresponding to the assembly instruction code. Figure 3 As shown, step 103 may include step 301 and step 302 .

[0079] Step 301, in accordance with the timing sequence of the clock cycles, each assembly instruction code is matched with the data stream corresponding to the assembly instruction code in turn to determine the execution start time and execution end time corresponding to the assembly instruction code and the number of executions corresponding to the assembly instruction code.

[0080] When the accelerator chip executes a binary file, the data stream is generated sequentially one by one when the accelerator chip executes the assembly instruction codes contained in the binary file. Therefore, the computer device uses the clock cycle as the timing unit, and matches each assembly instruction code line by line according to the execution order in the timing with the sequentially generated data streams, so as to obtain the mapping relationship between each assembly instruction code and each data stream. Since the data stream is generated sequentially in timing, for a mapping relationship, the computer device can determine the execution start time and execution end time of each assembly instruction code according to the generation time and end time of the data stream.

[0081] In a possible implementation, the computer device performs statistics on each mapping relationship, and counts the number of repeatedly executed assembly instruction codes. The obtained number of repeatedly executed assembly instruction codes is the number of execution times of the assembly instruction codes.

[0082] Step 302: Determine the number of clock cycles required to execute the assembly instruction code according to the execution start time and the execution end time.

[0083] In a possible implementation, for an assembly instruction code, the computer device can determine the number of clock cycles required for the accelerator chip to execute the assembly instruction code by subtracting the execution start time and the execution end time corresponding to the assembly instruction code.

[0084] In this embodiment, the computer device matches each assembly instruction code with each data stream in sequence according to the chronological order. The matching method is more convenient. After the matching process, the execution start time and execution end time corresponding to each assembly instruction code, the number of execution times of the assembly instruction code and the required number of clock cycles are determined, so that developers can quickly determine where the target kernel function needs to be optimized and improved based on the instruction code analysis results obtained in the above embodiment, thereby improving the efficiency of developers in optimizing the target kernel function.

[0085] In one embodiment, based on the above Figure 1 The embodiment shown, see Figure 4 , this embodiment relates to the process of visually displaying the results of instruction code analysis. Figure 4 As shown, the accelerator chip instruction execution analysis method of this embodiment may further include step 401.

[0086] Step 401 : Visually display the instruction code analysis results corresponding to each assembly instruction code according to a preset display mode.

[0087] In a possible implementation, in order to enable the instruction code analysis results obtained in the embodiments of the present application to more intuitively and accurately display the execution status of each assembly instruction code to the user, the computer device visualizes the instruction code analysis results corresponding to each assembly instruction code according to a preset display method.

[0088] Regarding the preset display mode, optionally, the computer device directly displays each assembly instruction code and its corresponding instruction code analysis result in a table on a preset display interface; optionally, the computer device determines the calculation unit corresponding to each assembly instruction code, and then performs statistics on each assembly instruction code and its corresponding instruction code analysis result according to the calculation unit, and displays the statistical results on the display interface. Here, the preset display mode is not specifically limited.

[0089] When the accelerator chip executes the binary file corresponding to the target kernel function, hundreds or thousands of threads on the accelerator chip execute the assembly instruction code contained in the binary file in parallel. Therefore, in order to optimize the target kernel function to achieve the purpose of improving the performance of the accelerator chip, in addition to understanding the hardware counting indicators, developers also need to analyze the running process of each assembly instruction code. Existing analysis tools cannot intuitively reflect the running status of specific assembly instruction codes. In this embodiment, the computer device visualizes the analysis results of the instruction codes corresponding to each assembly instruction code according to a preset display method, which more intuitively reflects the analysis results of the instruction codes corresponding to each assembly instruction code, so that developers can more intuitively and accurately determine the running status of each assembly instruction code, thereby improving the efficiency of optimizing the target kernel function.

[0090] In one embodiment, based on the above Figure 4 The embodiment shown, see Figure 5 This embodiment relates to a process of visually displaying the analysis results of the instruction codes corresponding to each assembly instruction code according to a preset display mode. Figure 5 As shown, step 401 may include step 501 and step 502 .

[0091] Step 501 , determining the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category.

[0092] The accelerator chip includes hundreds of parallel computing units, each of which can execute various assembly instruction codes corresponding to the binary file received by the accelerator chip, that is, one computing unit can execute assembly instruction codes of multiple instruction types, and one instruction type includes multiple assembly instruction codes.

[0093] Step 502: In a preset display interface, the analysis results of the instruction codes under the instruction categories are displayed in correspondence with the computing unit identifiers of the computing units corresponding to the instruction categories.

[0094] In a possible implementation, for a computing unit, the computer device counts multiple assembly instruction codes executed by the computing unit, and then displays the computing unit representation of each computing unit and the instruction code analysis result corresponding to the assembly instruction code executed by the computing unit according to the instruction category corresponding to each assembly instruction code. Figure 6 As shown, after the computer device obtains the preset query instruction, a statistical table of instruction code analysis results corresponding to multiple assembly instruction codes executed by a computing unit is displayed on a preset display page, the leftmost column of the statistical table is the assembly instruction code name corresponding to each assembly instruction code, the middle column is the number of repeated executions of each assembly instruction code, and the rightmost column is the total number of clock cycles for each assembly instruction code to run (the sum of the number of clock cycles required for each execution of an assembly instruction code).

[0095] In the process of visually displaying the instruction code analysis results, this embodiment not only displays the instruction code analysis results corresponding to the assembly instruction code, but also displays the instruction categories and computing units corresponding to each assembly instruction code, making the display dimension richer.

[0096] In one embodiment, based on the above Figure 5 The embodiment shown, see Figure 7 This embodiment relates to a process of displaying the analysis results of each instruction code under an instruction category and the computing unit identifier of the computing unit corresponding to the instruction category in a preset display interface. Figure 7 As shown, step 501 may include step 701 .

[0097] Step 701, for each instruction category corresponding to the computing unit identifier, a timeline control corresponding to the instruction category is displayed in a display interface in a chronological order of clock cycles to display the analysis results of each instruction code of each assembly instruction code under the instruction category.

[0098] In one possible implementation, a timeline control is used to display the data flow generated when each assembly instruction code under an instruction category is executed. Exemplarily, the timeline control can be displayed in the form of a progress bar on the timeline, and the timeline represents the overall timing of the target kernel function being executed by the accelerator chip, with the clock cycle as the timing unit, and the progress bar represents the running process in the timing when the assembly instruction code included in an instruction category is executed. Each progress bar can represent the sequential relationship of the parallel logic of each assembly instruction code. The starting node of the progress bar is the execution start time corresponding to the assembly instruction code, and the ending node is the execution end time corresponding to the assembly instruction code. The length of the progress bar and the corresponding part of the timeline can represent the number of clock cycles required for the execution of the assembly instruction code.

[0099] In a possible implementation, if a click operation on a target timeline control is detected, a target assembly instruction code corresponding to the target timeline control is determined, and an instruction code analysis result of the target assembly instruction code is displayed in a preset position of the display interface.

[0100] In one possible implementation, when a computer device clicks on a target timeline control, the name of the target assembly instruction code corresponding to the target timeline control may be displayed on the timeline control, and then the instruction code analysis result of the target instruction code may be displayed in a preset position of the display landmark assembly surface. Optionally, the preset position may also display basic attribute information of the target assembly instruction code, such as the name of the target assembly instruction code, the corresponding computing unit, etc.

[0101] like Figure 8 As shown, the computer device displays the analysis results of each instruction code on a preset display interface according to the display mode provided by this embodiment. The display interface arranges display controls on the left side to display the computing unit identification, see Figure 8 , the computing unit identification includes SIMD0, SIMD1, SIMD2, and SIMD3. Under each computing unit identification, the instruction category of the assembly instruction code included in each computing unit is set. The instruction categories include SALU, VALU, Memory, Branch, and WARP_END. The time axis is displayed on the upper right side, and the timing unit of the time axis is clock cycle. The timeline controls corresponding to each instruction category included in each computing unit are displayed below the time axis. See Figure 8The marked timeline control is the timeline control corresponding to the SALU instruction category under the SIMD1 computing unit. The time corresponding to the timeline control on the time axis can reflect the timing process of the SIMD1 computing unit executing the assembly instruction code of the SALU instruction category, and the sequence of each timeline control can characterize the sequence relationship of the parallel logic of each assembly instruction code; click a target timeline control to determine the name of the target assembly instruction code corresponding to the target timeline control, and display the instruction code analysis results of the target assembly instruction code and the basic attribute information of the target assembly instruction code at the preset position below, such as the name of the target assembly instruction code, the corresponding computing unit, etc., see Figure 8 , this preset position displays the name of the target assembly instruction code (Tittle), the start time of the target assembly instruction code (Start), the required execution time (Wall Duration), etc.

[0102] Thus, the above embodiment introduces a method for a computer device to visually display the instruction code analysis results of each assembly instruction code on a display interface according to a preset display method, so that each instruction code analysis result can be displayed more intuitively.

[0103] In one embodiment, an exemplary accelerator chip instruction execution analysis method is provided, the method is used in a computer device, and the method includes:

[0104] In step a, a computer device obtains multiple data streams obtained by an accelerator chip executing a binary file corresponding to a target kernel function.

[0105] Step b: The computer device uses a performance analysis tool to disassemble the binary file to obtain multiple assembly instruction codes corresponding to the binary file.

[0106] In step c, the computer device matches each assembly instruction code with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycle, and determines the execution start time and execution end time corresponding to the assembly instruction code and the execution number of the assembly instruction code.

[0107] Step d: The computer device determines the number of clock cycles required to execute the assembly instruction code according to the execution start time and the execution end time.

[0108] The instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code.

[0109] In step e, the computer device determines the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category.

[0110] Step f, for each instruction category corresponding to the computing unit identifier, the computer device displays a timeline control corresponding to the instruction category in the display interface in the chronological order of the clock cycle to display the instruction code analysis results of each assembly instruction code under the instruction category.

[0111] The timeline control is used to display the clock cycles in which each assembly instruction code under the instruction category is executed.

[0112] Step g: if a click operation on the target timeline control is detected, the computer device determines the target assembly instruction code corresponding to the target timeline control, and displays the instruction code analysis result of the target assembly instruction code in a preset position of the display interface.

[0113] The above method steps of the accelerator chip instruction operation analysis method of the embodiment of the present application can be executed by different functional modules in the computer device. Fig. 9 , wherein the computer device may be provided with a performance analysis tool, a runtime system and an accelerator chip, combined with Fig. 9 The functional modules shown in the figure illustrate the accelerator chip instruction operation analysis method:

[0114] Step 1), the performance analysis tool obtains multiple data streams obtained by the accelerator chip executing the binary file corresponding to the target kernel function.

[0115] Step 2), the performance analysis tool disassembles the binary file to obtain multiple assembly instruction codes corresponding to the binary file.

[0116] Step 3), the performance analysis tool matches each assembly instruction code with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycle, and determines the execution start time and execution end time corresponding to the assembly instruction code and the number of executions corresponding to the assembly instruction code.

[0117] Step 4), the performance analysis tool determines the number of clock cycles required to execute the assembly instruction code based on the execution start time and the execution end time.

[0118] The instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code.

[0119] Step 5), the performance analysis tool determines the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category.

[0120] Step 6), for each instruction category corresponding to the computing unit identifier, the performance analysis tool displays the timeline control corresponding to the instruction category in the display interface according to the timing sequence of the clock cycle to display the analysis results of each instruction code of each assembly instruction code under the instruction category.

[0121] The timeline control is used to display the clock cycles in which each assembly instruction code under the instruction category is executed.

[0122] Step 7), if a click operation on the target timeline control is detected, the performance analysis tool determines the target assembly instruction code corresponding to the target timeline control, and displays the instruction code analysis result of the target assembly instruction code in a preset position of the display interface.

[0123] In the embodiment of the present application, before the performance analysis tool obtains the multiple data streams obtained by the binary file corresponding to the accelerator chip executing the target kernel function, it also involves the system operating environment configuration process, the target kernel function issuance, and the operation process, please refer to Fig.10 , combined with the above-mentioned system operating environment configuration process, target kernel function issuance, operation and other processes, the accelerator chip instruction operation analysis method of the present application embodiment is described:

[0124] Step 1001: The performance analysis tool obtains the target kernel function and the executed data.

[0125] Step 1002: The Runtime system configures the system environment and sends down the target kernel function.

[0126] Step 1003: The Runtime system applies for memory space.

[0127] Step 1004: The accelerator chip executes the binary file of the target kernel function to generate a corresponding data stream.

[0128] Step 1005: The memory space obtains the data stream and the executed binary file.

[0129] Regarding the process after the performance analysis tool obtains multiple data streams obtained by the binary file corresponding to the target kernel function executed by the accelerator chip, please refer to the above steps 1) to 7) and will not be repeated here.

[0130] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0131] Based on the same inventive concept, the embodiment of the present application also provides an accelerator chip instruction operation analysis device for implementing the accelerator chip instruction operation analysis method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of one or more accelerator chip instruction operation analysis devices provided below can refer to the limitations of the accelerator chip instruction operation analysis method above, and will not be repeated here.

[0132] In an exemplary embodiment, Fig.11 As shown, an accelerator chip instruction operation analysis device is provided, comprising:

[0133] A first acquisition module 1101 is used to acquire multiple data streams obtained by the accelerator chip executing a binary file corresponding to a target kernel function;

[0134] The second acquisition module 1102 is used to acquire multiple assembly instruction codes corresponding to the binary file according to the binary file;

[0135] The matching module 1103 is used to match each assembly instruction code with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycles, and obtain the instruction code analysis result corresponding to the assembly instruction code. The instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code.

[0136] In one embodiment, the second acquisition module 1102 includes:

[0137] The disassembly unit is used to disassemble the binary file through a performance analysis tool to obtain multiple assembly instruction codes corresponding to the binary file.

[0138] In one embodiment, the matching module 1103 includes:

[0139] The matching processing unit is used to match each assembly instruction code with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycle, and determine the execution start time and execution end time corresponding to the assembly instruction code and the execution number of the assembly instruction code.

[0140] The first determining unit is used to determine the number of clock cycles required to execute the assembly instruction code according to the execution start time and the execution end time.

[0141] In one embodiment, the accelerator chip instruction operation analysis device further includes:

[0142] The visualization module is used to visualize the instruction code analysis results corresponding to each assembly instruction code according to a preset display mode.

[0143] In one embodiment, the visualization module includes:

[0144] A second determining unit is used to determine the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category;

[0145] The display unit is used to display the analysis results of each instruction code under the instruction category and the calculation unit identification of the calculation unit corresponding to the instruction category in a preset display interface.

[0146] In one embodiment, the display unit is further configured to perform the following steps:

[0147] For each instruction category corresponding to the computing unit identifier, a timeline control corresponding to the instruction category is displayed in the display interface in the chronological order of the clock cycles to display the analysis results of each instruction code of each assembly instruction code under the instruction category.

[0148] In one embodiment, the timeline control is used to display the clock cycles in which each assembly instruction code under the instruction category is executed, and the display unit is further used to perform the following steps:

[0149] If a click operation on the target timeline control is detected, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position of the display interface.

[0150] Each module in the above-mentioned accelerator chip instruction operation analysis device can be implemented in whole or in part by software, hardware and their combination. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0151] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Fig.12 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store accelerator chip operation data analysis data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, an accelerator chip instruction operation analysis method is implemented.

[0152] Those skilled in the art will understand that Fig.12 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0153] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0154] Acquire multiple data streams obtained by the accelerator chip executing the binary file corresponding to the target kernel function;

[0155] According to the binary file, multiple assembly instruction codes corresponding to the binary file are obtained;

[0156] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the data stream corresponding to the assembly instruction code in turn to obtain the instruction code analysis result corresponding to the assembly instruction code, and the instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code.

[0157] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0158] The binary file is disassembled by using a performance analysis tool to obtain multiple assembly instruction codes corresponding to the binary file.

[0159] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0160] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the data stream corresponding to the assembly instruction code in turn to determine the execution start time and execution end time corresponding to the assembly instruction code and the number of executions corresponding to the assembly instruction code;

[0161] Based on the execution start time and the execution end time, determine the number of clock cycles required to execute the assembly instruction code.

[0162] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0163] According to the preset display mode, the instruction code analysis results corresponding to each assembly instruction code are visually displayed.

[0164] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0165] Determine the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category;

[0166] In a preset display interface, analysis results of each instruction code under an instruction category are displayed correspondingly to the computing unit identifier of the computing unit corresponding to the instruction category.

[0167] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0168] For each instruction category corresponding to the computing unit identifier, a timeline control corresponding to the instruction category is displayed in the display interface in the chronological order of the clock cycles to display the analysis results of each instruction code of each assembly instruction code under the instruction category.

[0169] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0170] If a click operation on the target timeline control is detected, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position of the display interface.

[0171] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0172] Acquire multiple data streams obtained by the accelerator chip executing the binary file corresponding to the target kernel function;

[0173] According to the binary file, multiple assembly instruction codes corresponding to the binary file are obtained;

[0174] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the data stream corresponding to the assembly instruction code in turn to obtain the instruction code analysis result corresponding to the assembly instruction code, and the instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code.

[0175] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0176] The binary file is disassembled by using a performance analysis tool to obtain multiple assembly instruction codes corresponding to the binary file.

[0177] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0178] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the data stream corresponding to the assembly instruction code in turn to determine the execution start time and execution end time corresponding to the assembly instruction code and the number of executions corresponding to the assembly instruction code;

[0179] Based on the execution start time and the execution end time, determine the number of clock cycles required to execute the assembly instruction code.

[0180] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0181] According to the preset display mode, the instruction code analysis results corresponding to each assembly instruction code are visually displayed.

[0182] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0183] Determine the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category;

[0184] In a preset display interface, analysis results of each instruction code under an instruction category are displayed correspondingly to the computing unit identifier of the computing unit corresponding to the instruction category.

[0185] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0186] For each instruction category corresponding to the computing unit identifier, a timeline control corresponding to the instruction category is displayed in the display interface in the chronological order of the clock cycles to display the analysis results of each instruction code of each assembly instruction code under the instruction category.

[0187] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0188] If a click operation on the target timeline control is detected, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position of the display interface.

[0189] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0190] Acquire multiple data streams obtained by the accelerator chip executing the binary file corresponding to the target kernel function;

[0191] According to the binary file, multiple assembly instruction codes corresponding to the binary file are obtained;

[0192] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the data stream corresponding to the assembly instruction code in turn to obtain the instruction code analysis result corresponding to the assembly instruction code, and the instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code.

[0193] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0194] The binary file is disassembled by using a performance analysis tool to obtain multiple assembly instruction codes corresponding to the binary file.

[0195] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0196] According to the timing sequence of the clock cycles, each assembly instruction code is matched with the data stream corresponding to the assembly instruction code in turn to determine the execution start time and execution end time corresponding to the assembly instruction code and the number of executions corresponding to the assembly instruction code;

[0197] Based on the execution start time and the execution end time, determine the number of clock cycles required to execute the assembly instruction code.

[0198] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0199] According to the preset display mode, the instruction code analysis results corresponding to each assembly instruction code are visually displayed.

[0200] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0201] Determine the instruction category to which each assembly instruction code belongs, and the computing unit in the accelerator chip corresponding to the instruction category;

[0202] In a preset display interface, analysis results of each instruction code under an instruction category are displayed correspondingly to the computing unit identifier of the computing unit corresponding to the instruction category.

[0203] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0204] For each instruction category corresponding to the computing unit identifier, a timeline control corresponding to the instruction category is displayed in the display interface in the chronological order of the clock cycles to display the analysis results of each instruction code of each assembly instruction code under the instruction category.

[0205] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0206] If a click operation on the target timeline control is detected, the target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position of the display interface.

[0207] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0208] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0209] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0210] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the present application. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for analyzing the operation of an accelerator chip instruction, characterized in that: The method comprises: Acquire multiple data streams obtained by the accelerator chip executing the binary file corresponding to the target kernel function; According to the binary file, obtaining a plurality of assembly instruction codes corresponding to the binary file; According to the timing sequence of the clock cycles, each assembly instruction code is matched with the data stream corresponding to the assembly instruction code in turn to obtain an instruction code analysis result corresponding to the assembly instruction code, wherein the instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code.

2. The method according to claim 1, characterized in that The step of obtaining, according to the binary file, a plurality of assembly instruction codes corresponding to the binary file comprises: The binary file is disassembled by using a performance analysis tool to obtain the multiple assembly instruction codes corresponding to the binary file.

3. The method according to claim 1, characterized in that The step of matching each of the assembly instruction codes with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycles to obtain the instruction code analysis result corresponding to the assembly instruction code includes: Matching each assembly instruction code with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycles, and determining the execution start time, execution end time and execution count corresponding to the assembly instruction code; The number of clock cycles required to execute the assembly instruction code is determined according to the execution start time and the execution end time.

4. The method according to claim 1, characterized in that: The method further comprises: Determine the instruction category to which each of the assembly instruction codes belongs, and the computing unit in the accelerator chip corresponding to the instruction category; In a preset display interface, the analysis results of each instruction code under the instruction category are displayed correspondingly to the computing unit identifier of the computing unit corresponding to the instruction category.

5. The method according to claim 4, characterized in that The corresponding display of the analysis results of the instruction codes under the instruction category and the computing unit identifiers of the computing units corresponding to the instruction category in the preset display interface includes: For each instruction category corresponding to the computing unit identifier, a timeline control corresponding to the instruction category is displayed in the display interface in the chronological order of the clock cycles to display the instruction code analysis results of each assembly instruction code under the instruction category.

6. The method according to claim 5, characterized in that The timeline control is used to display the clock cycle of each assembly instruction code under the instruction category being executed, and the method further includes: If a click operation on a target timeline control is detected, a target assembly instruction code corresponding to the target timeline control is determined, and the instruction code analysis result of the target assembly instruction code is displayed in a preset position of the display interface.

7. An accelerator chip instruction operation analysis device, characterized in that: The device comprises: A first acquisition module is used to acquire multiple data streams obtained by the accelerator chip executing a binary file corresponding to a target kernel function; A second acquisition module, used for acquiring a plurality of assembly instruction codes corresponding to the binary file according to the binary file; A matching module is used to match each of the assembly instruction codes with the data stream corresponding to the assembly instruction code in sequence according to the timing sequence of the clock cycles to obtain an instruction code analysis result corresponding to the assembly instruction code, wherein the instruction code analysis result includes at least one of the number of clock cycles required for the accelerator chip to execute the assembly instruction code and the number of executions corresponding to the assembly instruction code.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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