A register structure and writing method for writing multi-bit width data to a memory

Abstract

The present invention discloses a register structure and a writing method for writing multi-bit width data to a memory, wherein the register structure includes: a command receiving register group and a parameter cache register group. The command receiving register group is used to receive input commands and identify command data, and output a command completion signal to trigger the start of the parameter cache register group after completing the reception of the command data; the parameter cache register group receives input commands and identifies parameter data, so as to receive and pack corresponding parameter data according to the type of command data after receiving the command completion signal, and generate a data packing completion signal of the corresponding parameter data, so as to input the parameter data into the corresponding target storage unit. The present invention realizes the recognition of command types and the flexible transmission of multi-bit width data, improves data transmission efficiency, reduces hardware resource waste, and ensures the accuracy of data transmission and the overall performance of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of digital circuits, and in particular to a register structure and a writing method for writing multi-bit width data into a memory. Background Art

[0002] With the rapid development of information technology, memory, as a key component for data storage and processing, plays a vital role in IoT devices, industrial control systems and other high-demand fields. However, with the diversification of application requirements, the traditional register structure faces many challenges and limitations when processing data of various bit widths written into the memory.

[0003] In the prior art, a typical register structure usually adopts a fixed bit width data processing method. For example, some register group designs only support data transmission with a specific bit width such as 8 bits, 16 bits or 32 bits. This fixed bit width design is not flexible enough when processing commands of different lengths and complexities. In addition, for large data volume write operations, the existing register structure often requires multiple data transmissions and additional control logic, resulting in low data transmission efficiency and high hardware resource usage. Moreover, the traditional command and parameter processing mechanism is usually serial and independent, lacking an efficient collaborative working mechanism, which not only increases the delay time of command parsing, but also may cause synchronization problems between commands and parameters, thereby affecting the accuracy and reliability of memory data writing.

[0004] Therefore, the prior art still needs to be improved and developed. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a register structure and a writing method for writing multi-bit-width data to a memory, so as to solve the problems of low data transmission efficiency, high hardware resource occupancy and lack of an efficient collaborative working mechanism in the application of processing multi-bit-width data writing to the memory by the conventional register structure.

[0006] The technical solution of the present invention is as follows:

[0007] In a first aspect, the present invention provides a register structure for writing multi-bit width data to a memory, comprising: a command receiving register group and a parameter buffer register group;

[0008] The command receiving register group is connected to the parameter cache register group, and the command receiving register group is used to receive input commands and identify command data, and output a command completion signal to trigger the parameter cache register group to start after completing the reception of the command data; the input command includes command data and parameter data, and the types of different command data correspond to the number of bits of parameter data;

[0009] The parameter cache register group is used to connect to the target storage unit, to receive input commands and identify parameter data, to receive and pack corresponding parameter data according to the type of command data after receiving the command completion signal, and to generate a data packing completion signal for the corresponding parameter data, so as to input the parameter data into the corresponding target storage unit.

[0010] According to a further configuration of the present invention, the command receiving register group includes a plurality of first triggers and a command recognition unit;

[0011] The first triggers are connected in sequence; wherein the data input terminal of the first first trigger is connected to the input command, and the output terminal of the first first trigger is respectively connected to the data input terminal of the next first trigger and the data input terminal of the command recognition unit;

[0012] The command recognition unit is connected to the parameter cache register group, and is used to judge the reception status of the command data, and when it is judged that the reception of the command data is completed, output a command completion signal to indicate that the reception of the command data is completed, and input the command completion signal to the parameter cache register group;

[0013] The clock input terminal of the first trigger and the clock input terminal of the command recognition unit are connected to a clock signal.

[0014] According to a further configuration of the present invention, the first triggers include at least 8, each of which corresponds to a bit; and the first triggers are D triggers.

[0015] In a further configuration of the present invention, the parameter cache register group includes a plurality of second triggers and parameter identification units;

[0016] The second triggers are connected in sequence; wherein the data input terminal of the first second trigger is connected to the input command, and the output terminal of the first second trigger is respectively connected to the input terminal of the next second trigger and the data input terminal of the parameter identification unit;

[0017] The command data input terminal of the parameter identification unit is connected to the output terminal of the command identification unit, the trigger signal input terminal of the parameter identification unit is connected to the enable terminal of the command identification unit, the output terminal of the parameter identification unit is connected to the target storage unit, and the signal trigger terminal of the parameter identification unit is connected to the target storage unit;

[0018] The parameter identification unit is used to receive and pack corresponding parameter data according to the type of command data after receiving the command completion signal, and generate a data packing completion signal of the corresponding parameter data to input the parameter data into the corresponding target storage unit;

[0019] The clock input terminals of the second trigger and the parameter identification unit are connected to a clock signal.

[0020] According to a further configuration of the present invention, the second triggers include at least 280, and each second trigger corresponds to a bit.

[0021] According to a further configuration of the present invention, the second trigger is a D trigger.

[0022] According to a further configuration of the present invention, when the command completion signal is at a high level, it indicates that the reception of the command data is completed.

[0023] According to a further configuration of the present invention, when the data packing completion signal is at a high level, it indicates that the reception of the parameter data is completed, and corresponding read and write operations are performed on the target storage unit.

[0024] According to a further configuration of the present invention, the input command includes a status register configuration command, a read command and a write command.

[0025] In a second aspect, the present invention provides a method for writing multi-bit-width data to a memory based on the register structure for writing multi-bit-width data to a memory as described above, comprising:

[0026] The control command receiving register group identifies and receives the command data in the input command;

[0027] After receiving the command data, a command completion signal is output and the parameter cache register group is triggered to start;

[0028] According to the type of command data, the parameter buffer register group is controlled to identify and receive the parameter data of the input command, and the corresponding parameter data is packaged;

[0029] After completing the packing of the parameter data, a corresponding data packing completion signal of the parameter data is generated, and the parameter data is input into the corresponding target storage unit.

[0030] The present invention provides a register structure and writing method for writing multi-bit width data to a memory, wherein the register structure includes: a command receiving register group and a parameter cache register group. The command receiving register group is used to receive input commands and identify command data, and output a command completion signal to trigger the startup of the parameter cache register group after completing the reception of the command data; the input command includes command data and parameter data, and the types of different command data correspond to the number of bits of the parameter data. The parameter cache register group receives input commands and identifies parameter data, so as to receive and pack corresponding parameter data according to the type of command data after receiving the command completion signal, and generate a data packing completion signal of the corresponding parameter data, so as to input the parameter data into the corresponding target storage unit. In this way, the present invention can realize the identification of command types and the flexible transmission of multi-bit width data through the collaborative work of the command receiving register group and the parameter cache register group, improve the data transmission efficiency, reduce the waste of hardware resources, and reduce the waiting time for command data identification and parameter data reception, thereby ensuring the accuracy of data transmission and the overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary personnel in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0032] Figure 1 It is a schematic diagram of the overall structure of the register structure for writing multi-bit width data into the memory in the present invention.

[0033] Figure 2 It is a schematic diagram of the command receiving register group in the present invention.

[0034] Figure 3 It is a schematic diagram of the parameter cache register group in the present invention.

[0035] Figure 4 It is a timing diagram of writing 8-bit parameter data in one embodiment of the present invention.

[0036] Figure 5 It is a timing diagram of writing 24-bit parameter data in one embodiment of the present invention.

[0037] Figure 6 It is a timing diagram of writing 280 bits of parameter data in one embodiment of the present invention.

[0038] Figure 7It is a flowchart of a writing method for writing multi-bit width data into a memory in the present invention.

[0039] The symbols in the accompanying drawings are: 100, command receiving register group; 110, command identification unit; 200, parameter cache register group; 210, parameter identification unit. DETAILED DESCRIPTION

[0040] The present invention provides a register structure and a writing method for writing multi-bit width data to a memory. In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0041] In the embodiments and the scope of the patent application, unless the text specifically defines the article, "a", "an", "the" and "the" may also include plural forms. If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0042] It should be further understood that the wording "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can also be an intermediate element. In addition, the "connection" or "coupling" used here can include wireless connection or wireless coupling. The wording "and / or" used here includes all or any unit and all combinations of one or more items listed in association.

[0043] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as herein.

[0044] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0045] The inventors have found that conventional register structures have problems such as low data transmission efficiency and high hardware resource usage in applications where multi-bit width data is written to memory, which limits the overall performance of the system. First, existing register groups usually only support data transmission with a fixed bit width and cannot flexibly adapt to the requirements of multi-bit width data under different command types, resulting in additional control overhead when processing complex commands and parameter transmissions. Secondly, the separate processing of commands and parameters written to the memory is often insufficient in existing designs, and there is a long waiting time between command recognition and parameter reception, which further limits the system's response speed and hardware resource utilization efficiency.

[0046] In response to the above technical problems, the present invention proposes a register structure and a writing method for writing multi-bit-width data to a memory. Through the coordinated work of a command receiving register group and a parameter cache register group, the command type can be identified and multi-bit-width data can be flexibly transmitted, thereby improving data transmission efficiency, reducing hardware resource waste, and reducing the waiting time for command data identification and parameter data reception, thereby ensuring the accuracy of data transmission and the overall performance of the system.

[0047] Please also see Figures 1 to 6 The present invention provides a preferred embodiment of a register structure for writing multi-bit width data into a memory.

[0048] In some embodiments, Figure 1 As shown, the present invention provides a register structure for writing multi-bit width data to a memory, which includes: a command receiving register group 100 and a parameter cache register group 200. The command receiving register group 100 is connected to the parameter cache register group 200, and the command receiving register group 100 is used to receive an input command and identify the command data, and output a command completion signal to trigger the startup of the parameter cache register group 200 after completing the reception of the command data; the input command includes command data and parameter data, and the types of different command data correspond to the number of bits of the parameter data; the parameter cache register group 200 is used to connect to a target storage unit, and is used to receive an input command and identify the parameter data, so as to receive and pack the corresponding parameter data according to the type of the command data after receiving the command completion signal, and generate a data packing completion signal of the corresponding parameter data, so as to input the parameter data into the corresponding target storage unit.

[0049] Specifically, the target storage unit includes but is not limited to a status register, a read data latch, a write data latch, etc. Correspondingly, the input command includes but is not limited to a status register configuration command, a read command, and a write command, etc. The corresponding status register configuration command (8'h01) has 8 bits of parameter data, and a read command (8'h03) for address information requires a wider bit width, that is, 24 bits of parameter data, and a write command (8'h02) for large data volume transmission requires 280 bits of parameter data.

[0050] The command receiving register set 100 has a data input terminal, a clock input terminal, an output terminal and an enable terminal. The parameter cache register set 200 has a data input terminal, a clock input terminal, a command data input terminal and a trigger signal input terminal.

[0051] The data input end of the command receiving register group 100 is connected to the input command (MOSI), and the shift register function is realized under the control of the clock signal (CLK). When the command data (cmd[7:0]) is not completed, the command receiving register group 100 will continue to shift and receive until the shift forms a specific command structure. When the command data (cmd[7:0]) is completed, the command completion signal (cmd_complete) is output to indicate that the command reception has been completed. The command data is input to the command data input end of the parameter cache register group 200 through the output end of the command receiving register group 100, and the command completion signal (cmd_complete) is input to the trigger signal input end of the parameter cache register group 200 through the enable end, so as to trigger the parameter cache register group 200 to start as an activation signal, so that the parameter cache register group 200 immediately enters the parameter receiving state in the next clock cycle.

[0052] When the command completion signal (cmd_complete) is at a high level, it indicates that the reception of the command data is completed. When the parameter cache register group 200 receives a high-level command completion signal (cmd_complete), the parameter cache register group 200 shifts the reference data bit by bit from the data input terminal according to the type of the command data. When it is determined that the reference data is packaged, a data packaging completion signal (package_complete) is generated according to the command type, wherein when the data packaging completion signal (package_complete) is at a high level, it indicates that the reception of the parameter data (package [X:0]) is completed, and the corresponding read and write operations are performed on the target storage unit.

[0053] It can be seen that the present invention can realize the recognition of command types and flexible transmission of multi-bit width data (dynamic adaptation of different bit width data) through the coordinated work of the command receiving register group 100 and the parameter cache register group 200. Compared with the traditional fixed bit width data transmission scheme, the data transmission efficiency is improved, the waste of hardware resources is reduced, and the waiting time for command data recognition and parameter data reception is reduced (the waiting time for switching between command data and parameter data is avoided), thereby ensuring the accuracy of data transmission and the overall performance of the system, wherein the overall performance improvement can be reflected in the improvement of response speed and the improvement of hardware resource utilization efficiency.

[0054] In some embodiments, Figure 1 and Figure 2 As shown, the command receiving register group 100 includes a plurality of first triggers and a command identification unit 110. The first triggers are connected in sequence; wherein, the data input end of the first first trigger is connected to the input command, and the output end of the first first trigger is connected to the data input end of the next first trigger and the data input end of the command identification unit 110 respectively; the command identification unit 110 is connected to the parameter cache register group 200, and the command identification unit 110 is used to judge the receiving state of the command data, and when it is judged that the reception of the command data is completed, a command completion signal is output to indicate that the reception of the command data is completed, and the command completion signal is input to the parameter cache register group 200; the clock input end of the first trigger and the clock input end of the command identification unit 110 are connected to the clock signal.

[0055] Specifically, since the command data has 8 bits, the first trigger has 8 bits (i.e. Figure 2 Q00-Q07, where Q 00 -Q 07 represents the output end of the first trigger), the first trigger is a D trigger, wherein the data input end of the first first trigger is connected to the input command, the output end is connected to the data input end of the next first trigger and the data input end of the command recognition unit 110, the inverting output end is vacant, each trigger corresponds to a bit, and the first trigger realizes the function of shift register under the control of the clock signal. The input end of the command recognition unit 110 is the data input end, the output end is the output end of the command receiving register group 100, and the enable end is the enable end of the command receiving register group 100.

[0056] The command recognition unit 110 can judge the receiving state of the command data. Once the preset complete command is met, the command completion signal (cmd_complete) will be output to indicate that the reception of the command data has been completed. In addition, the command completion signal not only indicates that the reception of the current command data has been completed, but can also be input as an activation signal to the parameter cache register group 200 to trigger the startup of the parameter cache register group 200, so that the parameter cache register group 200 immediately enters the parameter receiving state in the next clock cycle, avoiding the waiting time for switching between command data and parameter data, and improving the response speed of the system.

[0057] In some embodiments, Figures 1 to 3 As shown, the parameter cache register group 200 includes a plurality of second triggers and a parameter identification unit 210. The second triggers are connected in sequence; wherein the data input end of the first second trigger is connected to the input command, and the output end of the first second trigger is connected to the input end of the next second trigger and the data input end of the parameter identification unit 210 respectively; the command data input end of the parameter identification unit 210 is connected to the output end of the command identification unit 110, the trigger signal input end of the parameter identification unit 210 is connected to the enable end of the command identification unit 110, the output end of the parameter identification unit 210 is connected to the target storage unit, and the signal trigger end of the parameter identification unit 210 is connected to the target storage unit; the parameter identification unit 210 is used to receive and pack the corresponding parameter data according to the type of the command data after receiving the command completion signal, and generate a data packing completion signal of the corresponding parameter data to input the parameter data into the corresponding target storage unit; the second trigger and the clock input end of the parameter identification unit 210 are connected to the clock signal.

[0058] Specifically, in order to flexibly cope with the writing of multi-bit width data, the second triggers include at least 280. For example, in this embodiment, there are 280 (i.e. Figure 3 Q0-Q279, where Q0-Q 279 Represents the output end of the second trigger), each of the second trigger corresponds to a bit, and the second trigger can be a D trigger.

[0059] The parameter identification unit 210 has a data input terminal, a clock signal terminal, an output terminal, a trigger signal input terminal, and a signal output terminal.

[0060] The input command (MOSI) is input from the data input terminal of the first second flip-flop. After the parameter identification unit 210 receives the high-level command completion signal (cmd_complete), the parameter identification unit 210 is activated. The parameter identification unit 210 can determine the bit width of the parameter data according to the type of command data. Under the control of the clock signal (CLK), the parameter data is shifted into the parameter identification unit 210 through the second flip-flop bit by bit. The parameter identification unit 210 can perform and pack the received parameter data, and can determine whether the data packing is completed according to the command type and the preset bit width. For example, when transmitting an 8-bit data packet for status register configuration, the parameter identification unit 210 will detect the 8-bit data and regenerate the data packing completion signal (package_complete). In the read operation of the 24-bit data packet, the parameter identification unit 210 will wait for the 24-bit data to regenerate the data packing completion signal. For the write operation, the parameter identification unit 210 will detect the 280-bit data packet before generating the data packing completion signal. That is, when it is determined that the data packaging is completed, the parameter identification unit 210 will generate a data packaging completion signal (package_complete), so as to flexibly and efficiently complete data reception and processing according to the length and requirements of different command types.

[0061] like Figure 4 , Figure 5 and Figure 6 As shown, Figure 4 , Figure 5 and Figure 6 The timing diagrams for writing 8-bit, 24-bit, and 280-bit parameter data are shown respectively. Through the collaborative work of the command receiving register group 100 and the parameter cache register group 200, the data of different types of commands can be smoothly and accurately transmitted to the target storage unit. When the command receiving register group 100 receives the input command and generates a command completion signal (cmd_complete), the parameter cache register group 200 will be activated and receive a data packet of the corresponding bit width according to the command type. Once the parameter cache register group 200 completes data packaging and generates a data packaging completion signal, the system will transfer the data packet to the specified target storage unit, such as a status register, a read data latch, or a write data latch. At this time, the system can perform corresponding read and write operations on the memory according to the data in the status register, the read data latch, or the write data latch when the data packaging completion signal (package_complete) is at a high level. In practical applications, the present invention can support data packets of different bit widths such as 8 bits, 24 bits, and 280 bits, and is suitable for different operation scenarios from simple state configuration to large data volume writing.

[0062] In some embodiments, Figure 7As shown, the present invention provides a method for writing multi-bit-width data to a memory based on the register structure for writing multi-bit-width data to a memory as described above, which comprises the steps of:

[0063] S100, controlling the command receiving register group to identify and receive command data in an input command; the details are as described in an embodiment of a register structure for writing multi-bit width data into a memory, which will not be described in detail here.

[0064] S200, after receiving the command data, output a command completion signal and trigger the start of the parameter cache register group; the details are as described in an embodiment of a register structure for writing multi-bit width data to a memory, which will not be repeated here.

[0065] S300, controlling the parameter cache register group to identify and receive the parameter data of the input command according to the type of command data, and packing the corresponding parameter data; the specific details are as described in an embodiment of a register structure for writing multi-bit width data to a memory, which will not be repeated here.

[0066] S400: after completing the packing of the parameter data, generate a corresponding parameter data packing completion signal, and input the parameter data into the corresponding target storage unit. The details are as described in an embodiment of a register structure for writing multi-bit width data into a memory, and will not be described in detail here.

[0067] In summary, the register structure and writing method for writing multi-bit width data to a memory provided by the present invention have the following beneficial effects:

[0068] The coordinated work of the command receiving register group and the parameter buffer register group can realize the recognition of command types and the flexible transmission of multi-bit width data, which improves the data transmission efficiency and reduces the waste of hardware resources.

[0069] The command completion signal generated by the command receiving register group not only indicates that the current command data reception has been completed, but can also be input as an activation signal to the parameter cache register group to trigger the start of the parameter cache register group, so that the parameter cache register group immediately enters the parameter receiving state in the next clock cycle, avoiding the waiting time for switching between command data and parameter data, and ensuring the accuracy of data transmission and the overall performance of the system.

[0070] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A register structure for writing multi-bit width data to a memory, characterized in that: include: Command receiving register group and parameter buffer register group; The command receiving register group is connected to the parameter cache register group, and the command receiving register group is used to receive input commands and identify command data, and output a command completion signal to trigger the parameter cache register group to start after completing the reception of the command data; the input command includes command data and parameter data, and the types of different command data correspond to the number of bits of parameter data; The command receiving register group includes a plurality of first triggers and a command recognition unit; The first triggers are connected in sequence; wherein the data input terminal of the first first trigger is connected to the input command, and the output terminal of the first first trigger is respectively connected to the data input terminal of the next first trigger and the data input terminal of the command recognition unit; The command recognition unit is connected to the parameter cache register group, and is used to judge the reception status of the command data, and when it is judged that the reception of the command data is completed, output a command completion signal to indicate that the reception of the command data is completed, and input the command completion signal to the parameter cache register group; A clock signal is connected to a clock input terminal of the first trigger and a clock input terminal of the command recognition unit; The parameter cache register group is used to connect with the target storage unit, to receive the input command and identify the parameter data, to receive and pack the corresponding parameter data according to the type of the command data after receiving the command completion signal, and to generate a data packing completion signal of the corresponding parameter data, so as to input the parameter data into the corresponding target storage unit; The parameter cache register group includes a plurality of second triggers and parameter identification units; The second triggers are connected in sequence; wherein the data input terminal of the first second trigger is connected to the input command, and the output terminal of the first second trigger is respectively connected to the input terminal of the next second trigger and the data input terminal of the parameter identification unit; The command data input terminal of the parameter identification unit is connected to the output terminal of the command identification unit, the trigger signal input terminal of the parameter identification unit is connected to the enable terminal of the command identification unit, the output terminal of the parameter identification unit is connected to the target storage unit, and the signal trigger terminal of the parameter identification unit is connected to the target storage unit; The parameter identification unit is used to receive and pack corresponding parameter data according to the type of command data after receiving the command completion signal, and generate a data packing completion signal of the corresponding parameter data to input the parameter data into the corresponding target storage unit; The clock input terminals of the second trigger and the parameter identification unit are connected to a clock signal.

2. The register structure for writing multi-bit width data to a memory according to claim 1, characterized in that: The first triggers include at least 8, each of which corresponds to a bit; the first trigger is a D trigger.

3. The register structure for writing multi-bit width data to a memory according to claim 1, characterized in that: The second triggers include at least 280, and each second trigger corresponds to a bit.

4. The register structure for writing multi-bit width data to a memory according to claim 3, characterized in that: The second flip-flop is a D flip-flop.

5. The register structure for writing multi-bit width data into a memory according to claim 1, characterized in that: When the command completion signal is at a high level, it indicates that the reception of the command data is completed.

6. The register structure for writing multi-bit width data into a memory according to claim 1, characterized in that: When the data packing completion signal is at a high level, it indicates that the reception of the parameter data is completed, and corresponding read and write operations are performed on the target storage unit.

7. The register structure for writing multi-bit width data into a memory according to claim 1, characterized in that: The input commands include status register configuration commands, read commands, and write commands.

8. A method for writing multi-bit-width data into a memory based on the register structure for writing multi-bit-width data into a memory according to any one of claims 1 to 7, characterized in that: include: The control command receiving register group identifies and receives the command data in the input command; After receiving the command data, a command completion signal is output and the parameter cache register group is triggered to start; According to the type of command data, the parameter buffer register group is controlled to identify and receive the parameter data of the input command, and the corresponding parameter data is packaged; After completing the packing of the parameter data, a corresponding data packing completion signal of the parameter data is generated, and the parameter data is input into the corresponding target storage unit.

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