Non-volatile memory write interference mitigation method and system based on block selection

Abstract

According to the non-volatile memory write interference relieving method and system based on block selection, models and metadata needed by block selection are stored on a traditional DRAM, old data are processed and classified through the characteristics of write interference, and a proper write-in position is selected for new to-be-written-in data so as to reduce write interference errors; the write interference tendency vector extraction technology can abstract the maximum write interference error number when each bit of old data is written; according to the old data block classification technology, old data blocks with similar write interference tendency are classified into the same class by utilizing a clustering algorithm; the write-in category selection technology comprises the following steps: firstly, extracting an attack vector for new data according to whether each bit can cause a write interference error during write-in, and selecting an old data category by using the attack vector; in the intra-class write-in position selection technology, a hash algorithm is used, and the most appropriate write-in position is selected for new data, so that write interference errors are further reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of non-volatile memory reliability, and in particular to a non-volatile memory write disturbance mitigation method and system based on block selection. Background Art

[0002] As the physical limits of traditional memory technology are gradually approaching, DRAM is unable to cope with the rapidly growing amount of data. Non-volatile memory (NVM) brings hope for further expansion of memory with its DRAM-like access speed, disk-like persistence, and high storage density. However, NVM still faces the technical challenge of write disturbance in its application. Write disturbance causes the value of NVM cells to change incorrectly when writing, which not only seriously affects the reliability of the memory, but also reduces its access performance. In addition, NVM pursues higher storage density by reducing the spacing between cells, resulting in write disturbance errors becoming a major obstacle to its widespread application. Therefore, in order to promote the practical application of NVM in modern memory centers, it is crucial to study and explore effective write disturbance error mitigation strategies.

[0003] At present, Verify and Correct (VnC) technology is the most commonly used error correction method to deal with write disturbance problems. The working principle of this technology is that before writing data, the original data in the storage cells that are susceptible to write disturbance is read first. After the write operation is completed, the data in these cells is read again and compared with the original data. If the data is found to be inconsistent, the original data is rewritten until the data in all storage cells is accurate. Although VnC technology can effectively reduce errors caused by write disturbance, it also introduces additional read and write operations, which further widens the gap between NVM and DRAM in performance and life. In addition to VnC technology, error correction code (ECC) is also used to deal with write disturbance problems. However, ECC technology requires a large amount of memory space to store verification information, and as write disturbance errors continue to accumulate, even if ECC has a strong error correction capability, it may not be able to completely correct all errors. Therefore, how to balance error correction capability and memory usage is a key issue that ECC technology needs to solve in practical applications. In order to cope with the challenges faced by traditional technologies and alleviate the performance and reliability issues caused by write disturbance errors, existing research mainly starts from the following three aspects: (1) Data encoding technology is used to reduce the probability of data patterns that may cause write disturbance errors, thereby reducing the number of write disturbance error cells (L. Jiang, Y. Zhang, and J. Yang. Mitigating writedisturbance in superdense phase change memories. In DSN, 2014; R. Wang, L. Jiang, Y. Zhang, L. Wang, and J. Yang. Exploit imbalanced cell writes to mitigate writedisturbance in dense phase change memory. In DAC, 2015; M. K. Tavana and D. Kaeli. Cost-effective write disturbance mitigation techniques for advancing pcm density. In ICCAD, 2017; M. Imran, T. Kwon, and J. Yang. Effective writedisturbance mitigation encoding scheme for high-density pcm. In DATE, 2020; M. Imran, T. Kwon, NA Touba, and J.-S. Yang.Cent: An efficient architecture to eliminate intra-array write disturbance in pcm. IEEE Transactions on Computers, 2021); (2) By optimizing the verification method, the error correction overhead of write disturbance errors can be concealed to reduce the performance impact on writes (R. Wang, L. Jiang, Y. Zhang, and J. Yang. Sd-pcm: Constructing reliable super dense phase change memory under write disturbance. In ASPLOS, 2015; S. Swami and K. Mohanram. Adam: Architecture for write disturbance mitigation inscaled phase change memory. In DATE, 2018); (3) Use page mapping or write-private cache to avoid frequent writing to the same memory area to avoid the increase in memory temperature and the increase in the probability of write disturbance errors (R. Wang, S. Mittal, Y. Zhang, and J. Yang. Decongest: Accelerating super-dense pcm underwrite disturbance by hot page remapping. IEEE Computer Architecture Letters, 2017; J.Jang, W.Shin, J.Choi, Y.Kim, and L.-S.Kim. Sparse-insertion write cache tomitigate write disturbance errors in phase change memory.IEEE Transactions on Computers, 2019). Existing research usually considers mitigating the write disturbance problem in the case of local updates, that is, using new data to directly overwrite the original data, so that the occurrence of write disturbance errors depends on the pattern difference between the new and old data (i.e., the difference in the distribution of RESET units). However, NVM is also deployed in large-scale storage systems, where off-site updates are more commonly used to obtain better performance, such as key-value storage, log-structured file systems, hash indexes, and separate memory. Therefore, analyzing the data writing and pattern differences in off-site write scenarios, and how to design a write disturbance mitigation framework based on the characteristics of off-site writes, is still a valuable problem in the field of NVM reliability. . Summary of the invention

[0004] In response to the technical problems mentioned above, the purpose of this application is to propose a non-volatile memory write disturbance mitigation method and system based on block selection, which saves the model and metadata required for block selection on traditional DRAM memory, uses the characteristics of write disturbance to process and classify old data, and selects a suitable write location for new data to be written to reduce write disturbance errors. The write disturbance tendency vector extraction technology can abstract the maximum number of write disturbance errors when each bit of old data is written; the old data block classification technology uses a clustering algorithm to divide old data blocks with similar write disturbance tendencies into the same category; the write category selection technology first extracts an attack vector for the new data based on whether each bit will cause a write disturbance error when written, and uses the attack vector to select the old data class; the intra-class write location selection technology uses a hash algorithm to select the most suitable write location for the new data to further reduce write disturbance errors.

[0005] The technical solution of the present invention is as follows.

[0006] In a first aspect, a non-volatile memory write disturbance mitigation method based on block selection comprises the following steps:

[0007] Write disturb tendency vector extraction step S1, for each old data block read, a write disturb tendency vector is generated and stored; the write disturb tendency vector indicates the number of write disturb errors that may be caused when the old data block is overwritten;

[0008] The old data block classification step S2 classifies the write disturbance tendency vectors of the old data blocks based on the clustering algorithm, obtains cluster labels, and divides the old data blocks into multiple categories, each of which has a similar write disturbance tendency distribution;

[0009] New data block writing class selection step S3, extracting the write disturbance attack vector of the new data block to be written, and selecting the old data class with the smallest inner product as the new data writing class;

[0010] In the intra-class write position selection step S4, the new data block is shuffled according to a predetermined hash permutation function, and a hash value is obtained, and a write address is selected from an available address table according to the hash value; the available address table stores the hash value and clustering label of the old data block.

[0011] Preferably, the write disturbance tendency vector extraction step S1 specifically includes:

[0012] S11, for the available old data block, read it into DRAM and record its address in NVM;

[0013] S12, for each read old data block, checking whether writing to it may cause a write disturb error, and generating a write disturb tendency vector;

[0014] S13, setting each value of the write disturbance tendency vector to the maximum value of the number of write disturbance errors that may be caused in the same word row when each bit in the old data block is written.

[0015] Preferably, the old data block classification step S2 specifically includes:

[0016] S21, determining the parameters of the clustering algorithm, including the number of clusters and the selected clustering algorithm;

[0017] S22, using the initialized clustering algorithm to classify the tendency vectors of the old data blocks, so that the old data blocks with similar write disturbance tendency vectors can be classified into the same class;

[0018] S23, for each class, the average of the tendency vectors of all old data blocks of the class is calculated as the basis for subsequent class selection; the available data block address table is initialized to record the addresses of available old data blocks and the class corresponding to each address.

[0019] Preferably, the new data block writing class selection step S3 specifically includes:

[0020] S31, based on the characteristics of write disturbance, extracting the write disturbance attack vector of the new data block to be written, that is, the bit that may cause word-row write disturbance when writing;

[0021] S32, respectively calculating the inner product of the write disturbance attack vector of the new data block and each old data category to represent the average value of the maximum number of write disturbance errors written by the new data block to each category;

[0022] S33, selecting the old data category with the smallest inner product as the write category of the new data to probabilistically reduce write disturbance errors.

[0023] Preferably, the intra-class writing position selection step S4 specifically includes:

[0024] S41, determining the number of selected hash functions, and generating a permutation function for each hash function for subsequent scrambling of data blocks;

[0025] S42, calculating the hash value of each old data block, that is, using the permutation function to shuffle the old data block, and setting the position where the first bit 1 is located as its hash value;

[0026] S43, storing the hash value of each old data block in the available data address table, and using it together with the category value as an index of the address;

[0027] S44, calculating the hash value of the new data block to be written, and selecting the old data address from the address table for writing in combination with the value of the selected category.

[0028] In a second aspect, a non-volatile memory write disturbance mitigation system based on block selection includes:

[0029] A write disturb tendency vector extraction module is used to generate and store a write disturb tendency vector for each old data block read; the write disturb tendency vector indicates the number of write disturb errors that may be caused when the old data block is overwritten;

[0030] An old data block classification module is used to classify the write disturbance tendency vectors of old data blocks based on a clustering algorithm, obtain cluster labels, and divide the old data blocks into multiple categories, each of which has a similar write disturbance tendency distribution;

[0031] A new data block write class selection module is used to extract the write disturbance attack vector of the new data block to be written, and select the old data class with the smallest inner product as the write class of the new data;

[0032] The intra-class write position selection module is used to shuffle the new data block according to a predetermined hash permutation function, obtain a hash value, and select a write address from an available address table according to the hash value; the available address table stores the hash value and clustering label of the old data block.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] (1) The block selection-based write disturb mitigation scheme proposed in the present invention can complement the existing research to further reduce the number of write disturb errors;

[0035] (2) The old data tendency vector extraction technology proposed in the present invention utilizes the write disturbance characteristic to indicate the maximum number of write disturbance errors that may be caused when the old data block is written, and effectively indicates the write disturbance tendency of the old data block;

[0036] (3) The old data block classification technology proposed in the present invention can dynamically classify old data blocks with similar write disturbance tendencies into one category, and can show the distribution of the write disturbance tendency of each category;

[0037] (4) The write category selection technique proposed in the present invention utilizes the inner product to select the appropriate write category, which can probabilistically reduce the number of write disturb errors;

[0038] (5) The intra-class address selection technology proposed in the present invention utilizes a hash algorithm to select similar old data blocks for writing new data, which can improve the write durability of NVM. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A flowchart of a non-volatile memory write disturbance mitigation method based on block selection according to an embodiment of the present invention;

[0041] Figure 2 This is an example diagram of a write disturb tendency vector extraction technology according to an embodiment of the present invention;

[0042] Figure 3 This is an example diagram of an old data block classification technology based on a clustering algorithm according to an embodiment of the present invention;

[0043] Figure 4 This is an example diagram of a new data block writing class selection technology according to an embodiment of the present invention;

[0044] Figure 5 This is an example diagram of a hash-based intra-class write location selection technology according to an embodiment of the present invention;

[0045] Figure 6 is an overall overview of an embodiment of the present invention;

[0046] Figure 7 A diagram showing simulation results of the number of write disturbance errors in a block selection framework according to an embodiment of the present invention;

[0047] Figure 8 A diagram showing simulation results of the write overhead of the block selection framework according to an embodiment of the present invention;

[0048] Fig. 9 A diagram showing simulation results of writing power consumption of a block selection framework according to an embodiment of the present invention;

[0049] Fig.10Simulation experiment result graph of the write latency of the block selection framework according to the embodiments of the present invention;

[0050] Fig.11 Block diagram of the non-volatile memory write interference mitigation system based on block selection according to the embodiments of the present invention. Detailed implementation manners

[0051] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0052] Figure 1 There is shown a non-volatile memory write interference mitigation method based on block selection provided by an embodiment of the present application, including the following steps.

[0053] Write interference tendency vector extraction step S1: For each read old data block, generate a write interference tendency vector and store it; the write interference tendency vector represents the number of write interference errors that may be caused when the old data block is overwritten.

[0054] The specific implementation of the write interference tendency vector extraction step S1 is as follows.

[0055] S11: Read available old data blocks into the DRAM in the background, and record the address of each old data block at the same time.

[0056] S12: For each old data block, calculate in sequence whether a write interference error will occur when the block (l-bit data block) is written, and generate a write interference tendency vector D[i] (1 < i < l). If the old data bit value is 0, or the bit value is 1 and its adjacent two bits are both 1, the tendency vector corresponding to the data bit is set to 0, indicating that no write interference error of the same word line will be caused when the data bit is written; if the old data bit value is 1 and there is a bit 0 stored in its adjacent bits, the tendency vector corresponding to the data bit will be set to the number of bit 1s stored around it (that is, 1 or 2).

[0057] S13: Store each tendency vector in the DRAM, that is, the maximum number of write interference errors that may be caused when each old data block is written, for subsequent classification of old data.

[0058] As can be seen from the above, the write disturbance tendency vector extraction step S1 calculates the write disturbance tendency vector according to the characteristics of the write disturbance. When the bit 1 in the old data is overwritten by the bit 0 of the new data, it may interfere with the bit 0 stored around it. Therefore, the tendency vector can be extracted for the old data block based on this to understand the number of write disturbance errors that may be caused when the old data block is written. Figure 2 The figure shows an example of the write disturbance tendency vector extraction technology. For an 8-bit data block, the bit value of each bit of data is multiplied by the number of bits 0 around it. For example, if the bit value of the third bit is 1 and there are two 0s around it, the corresponding tendency vector is set to 2. Similarly, the value of the tendency vector corresponding to each bit is extracted.

[0059] In the old data block classification step S2, the write disturbance tendency vectors of the old data blocks are classified based on a clustering algorithm to obtain cluster labels, and the old data blocks are divided into multiple categories, each of which has a similar write disturbance tendency distribution.

[0060] The old data block classification step S2 is specifically implemented as follows.

[0061] S21, select a suitable clustering algorithm and select parameters according to the characteristics of the clustering algorithm. For example, if the K-means algorithm is selected, it is necessary to determine the number of categories into which the data is divided, the number of iterations during training, and other parameters.

[0062] S22, when clustering old data blocks, first randomly select k tendency vectors of the old data blocks extracted by S12 as the centers of clusters, and use all tendency vectors as input to train the clustering algorithm. In each iteration, the mean of the tendency vectors contained in each category is used as the new cluster center, and the iteration is continued until the cluster center no longer changes or the upper limit of the number of iterations is reached.

[0063] S23, after clustering is completed, obtain the label of each tendency vector, that is, the number of the class to which it is divided, and initialize the available address table based on the clustering label and the corresponding address to indicate the class to which each old data address belongs.

[0064] In the new data block writing class selection step S3, the write disturbance attack vector of the new data block to be written is extracted, and the old data class with the smallest inner product is selected as the writing class of the new data.

[0065] As can be seen from the above, the old data block classification step S2 is responsible for classifying the old data blocks. According to the previously obtained write disturbance tendency vector, the old data blocks can be divided into multiple categories, so that the write disturbance tendency distribution of each category is similar, which is conducive to the rapid selection of write blocks. Figure 3The figure shows an example of clustering old data blocks. In order to divide the tendency vectors of 5 old data blocks into 2 categories, first select the first and fourth as cluster centers, calculate the Euler distance from each tendency vector to the two cluster centers, and select the class with the smallest Euler distance. After the iteration is completed, update the cluster center to the mean of all vectors in the class. Iterate again and find that the cluster center has not changed, and end the old data clustering training.

[0066] The new data block writing class selection step S3 is specifically implemented as follows.

[0067] S31, since the write interference problem is caused by the RESET operation interfering with the idle bits 0 stored around it, that is, writing 0 may affect the bits 0 stored around it. Based on this, the attack vector A of the new data block is extracted: when the bit of the new data block is 0 and the data stored around it is 0, the corresponding attack vector is set to 1, otherwise the corresponding attack vector is set to 0.

[0068] S32, the attack vector indicates whether a write disturb error will occur when new data is written, and the tendency vector indicates the number of write disturb errors that may be caused when old data is overwritten. Therefore, the attack vector A of the new data and the k cluster centers C are calculated respectively. i The inner product of (1<=i<=k) is used to represent the average number of write disturbance errors that may be generated when new data overwrites a certain type.

[0069] S33, selecting the class where the cluster center with the smallest inner product belongs as the class where the new data is finally written, so as to probabilistically reduce the number of write disturbance errors.

[0070] As can be seen from the above, the new data block write class selection step S3 is responsible for selecting the appropriate write class for the new data. Since the write disturbance problem is caused by the RESET operation disturbing the idle bits 0 stored around it, if there are 0s around the new data bit 0, the corresponding attack vector is set to 1. In addition, the inner product of the attack and tendency vectors can represent the average number of write disturbance errors of the new data write class. Figure 4 The figure shows an example of extracting attack vectors and determining categories. For a new data block, the second bit is 0 and the surrounding bits are 1, so the corresponding vector value is set to 0, while the fourth bit is 0 and there are 0s around it, so the corresponding vector is set to 1, and so on to obtain the attack tendency vector. Then the inner product of the attack vector to the center of each class is calculated in turn, and finally class 1 is selected as the class for writing new data.

[0071] In the intra-class write position selection step S4, the new data block is shuffled according to a predetermined hash permutation function, and a hash value is obtained, and a write address is selected from an available address table according to the hash value; the available address table stores the hash value and clustering label of the old data block.

[0072] The step S4 of selecting the writing position within the class is specifically implemented as follows.

[0073] S41, determine the number h of selected hash functions and the bits b occupied by each hash function. For each hash function, generate a permutation function for scrambling the data block, and store each hash function.

[0074] S42: For each old data block, use h hash functions to scramble the bits of the old data block. The hash value considers the position of the first bit 1. If the first bit 1 is in the second b If the hash value is the real position of the first 1, otherwise, the hash value is set to 2. b .

[0075] S43, the hash value of the old data block is also stored in the available address table, and the hash value and the clustering label are used together as the index of the old data address in the available address table, so as to quickly locate the appropriate writing position from the table.

[0076] S44, for the newly written data block, use h hash functions to calculate the hash value, and combine the write category determined in S33 to select a suitable old data address to reduce write disturbance errors.

[0077] As can be seen from the above, the class write location selection step S4 is responsible for selecting a specific write location from the class. First, the new data block is shuffled according to a predetermined hash permutation function, and a hash value is obtained. Then, a write address is selected from the available address table according to the hash value, such as Figure 5 An example diagram of a hash-based write location selection technique is shown in FIG. For a new data block B', a hash value of 2 is calculated, and it should be written into class 1, so a data address of class 1 and a hash value of 2 is selected from the table for writing to find a more similar old data block.

[0078] In summary, the core of the embodiments of the present invention is to utilize the discovery that appropriate write block selection can alleviate write disturb errors, and to implement a high-reliability and high-performance NVM memory based on the characteristics of clustering algorithms and block selection.

[0079] The system structure prototype implemented by the present invention is as follows Figure 6 As shown in FIG. 1 , it includes a write disturbance tendency vector extraction step, an old data block classification step based on a clustering algorithm, a new data block write class selection step, and a hash-based intra-class write position selection step. The write disturbance tendency vector extraction step extracts the write disturbance tendency distribution of the old data, the old data block classification step based on a clustering algorithm divides the old data blocks with similar write disturbance tendencies into the same class, the new data block write class selection step uses the inner product of the attack vector and the tendency vector to select a suitable write category for the new data, and the hash-based intra-class write position selection module uses local hashing to select the most similar old data block for the new data to write.

[0080] The performance test process and results of the present invention are given below.

[0081] The simulation experiment of the present invention uses 15 real data sets from the UCI machine learning database and the Kaggle database, covering data types such as text, multimedia and numerical values. The experiment sets the data block size of the NVM to 512-bit, and considers the 128-bit parallel writing method. The experimental simulation uses 9.9% and 11.5% to evaluate the write interference error rate of the word line and the bit line, respectively, and sets the write power consumption of the RESET and SET operations to 0.013733nJ / bit and 0.0268nJ / bit, respectively, and the write latency is set to 100ns / time and 200ns / time, respectively. In addition, the latency and power consumption of the read operation are set to 100ns / time and 1.075nJ / cache line. Since the present scheme is a complementary experimental setting to the existing encoding scheme, the comparison schemes of the experiment are (1) RandSel, randomly selecting an old data block from the optional old data blocks for writing; (2) LearnWD, which represents the combination of the modules of the present invention. To verify the complementarity, the above two schemes are combined with the following encoding schemes: (1) DCW, which reads the old data in advance and only writes the changed bits between the new data and the old data to reduce bit flips; (2) DIN, which adopts an extended encoding scheme based on FPC to alleviate the write disturbance problem and adds a 20-bit BCH code to protect the encoded data; (3) DMPart, which selects the data pattern with the minimum frequency as the mask pattern for data encoding to reduce the number of data patterns with consecutive 0s to alleviate write disturbance errors; (4) MinWD, which uses level-shift (i.e., shifting every 2-bit data pattern) to minimize the number of victim units and the number of bit flips. To track the writing of the data set, 50,000 blocks are first selected from each data set as old data blocks and their addresses are recorded in the available address table. Then, data is continuously extracted from the data set to simulate another 50,000 write requests. Only write access operations are considered, and the four indicators of the number of write disturbance errors, write overhead, write power consumption, and write delay are considered respectively.

[0082] 1. Simulation test of the number of memory write disturbance errors.

[0083] The write disturbance error simulation test used 15 data sets to test and evaluate the number of write disturbance errors of the present invention and other comparison systems under different data. The test results are as follows: Figure 7As shown. When combined with four representative data encoding methods, LearnWD can further reduce the number of write disturb errors by 9.5-31.2% on different data sets compared to RandSel. Specifically, when deployed on DCW, DIN, DMPart and MinWD, LearnWD can further reduce write disturb errors by 31.2%, 28.4%, 9.5% and 11.1% on average, which shows that LearnWD is complementary to existing encoding mechanisms and can help existing encoding mechanisms further reduce the number of write disturb errors.

[0084] 2. Memory write overhead simulation test.

[0085] The memory write overhead simulation test used 15 data sets, where the write overhead was set to the cost of 2 RESET operations equal to the cost of 1 SET operation. The test evaluated the write overhead of the present invention and other comparison systems under different data sets. The test results are as follows: Figure 8 When deployed with existing data encoding methods, LearnWD will further reduce the write overhead by 21.9%.

[0086] 3. Memory write power consumption simulation test.

[0087] The memory write power consumption simulation test used 15 data sets to test and evaluate the write power consumption of the present invention and other comparison systems under different benchmarks. The simulation experimental results are as follows: Fig. 9 As shown in the figure, the results of the same type of data sets are presented as averages. Since LearnWD can reduce the number of write disturbance errors and write overhead, it can reduce the power consumption required for verification and writing. Experimental results show that when combined with DCW, DIN, DMPart and MinWD, LearnWD reduces the write power consumption by 15.6%, 13.4%, 4.5% and 7.8% respectively on average.

[0088] 4. Memory write delay simulation test.

[0089] The memory write latency simulation test used 15 data sets to test and evaluate the write latency of the present invention and other comparison systems under different benchmarks. The simulation results are as follows: Fig.10 As shown in the figure, the results of the same type of data sets are presented as averages. For different data types, when DCW, DIN, DMPart, and MinWD are deployed simultaneously, LearnWD further shortens the write latency by an average of 16.4%, 14.3%, 5.2%, and 8.1% compared to RandSel. This is because LearnWD can effectively reduce the number of checks required to ensure data reliability.

[0090] The present invention uses the discovery that write block selection can reduce write disturb errors, and proposes a write disturb mitigation framework based on machine learning and off-site writing (wherein block selection is used in off-site writing scenarios; clustering algorithm is a machine learning algorithm). Existing write disturb mitigation schemes usually only consider local writing, and do not consider reducing write disturb errors by selecting write locations. The present invention uses the characteristics of write disturb and proposes an effective write block selection mechanism, which can be combined with existing encoding mechanisms to further reduce write disturb errors and optimize the access performance and service life of NVM memory.

[0091] Further Fig.11 As shown, as an implementation of the methods shown in the above figures, the present application provides an embodiment of a non-volatile memory write disturbance mitigation system based on block selection, and the device embodiment is similar to Figure 1 Corresponding to the method embodiment shown, the device can be specifically applied to various electronic devices.

[0092] The embodiment of the present application provides a non-volatile memory write disturbance mitigation system based on block selection, including:

[0093] A write disturb tendency vector extraction module 1101 is used to generate and store a write disturb tendency vector for each old data block read; the write disturb tendency vector indicates the number of write disturb errors that may be caused when the old data block is overwritten;

[0094] An old data block classification module 1102 is used to classify the write disturbance tendency vectors of the old data blocks based on a clustering algorithm, obtain cluster labels, and classify the old data blocks into multiple categories, each category having a similar write disturbance tendency distribution;

[0095] A new data block write class selection module 1103 is used to extract the write disturbance attack vector of the new data block to be written, and select the old data class with the smallest inner product as the write class of the new data;

[0096] The intra-class write location selection module 1104 is used to shuffle the new data block according to a predetermined hash permutation function, obtain a hash value, and select a write address from an available address table according to the hash value; the available address table stores the hash value and clustering label of the old data block.

[0097] The specific implementation of each module of a non-volatile memory write disturb mitigation system based on block selection is the same as the non-volatile memory write disturb mitigation method based on block selection, and the present embodiment will not repeat the description.

[0098] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above invention concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A non-volatile memory write disturb mitigation method based on block selection, characterized in that: The following steps are involved: Write disturb tendency vector extraction step S1, for each old data block read, a write disturb tendency vector is generated and stored; the write disturb tendency vector indicates the number of write disturb errors that may be caused when the old data block is overwritten; The old data block classification step S2 classifies the write disturbance tendency vectors of the old data blocks based on the clustering algorithm, obtains cluster labels, and divides the old data blocks into multiple categories, each of which has a similar write disturbance tendency distribution; New data block writing class selection step S3, extracting the write disturbance attack vector of the new data block to be written, and selecting the old data class with the smallest inner product as the new data writing class; In the intra-class write position selection step S4, the new data block is shuffled according to a predetermined hash permutation function, and a hash value is obtained, and a write address is selected from an available address table according to the hash value; the available address table stores the hash value and clustering label of the old data block.

2. The non-volatile memory write disturb mitigation method based on block selection according to claim 1, characterized in that: The write disturbance tendency vector extraction step S1 specifically includes: S11, for the available old data block, read it into DRAM and record its address in NVM; S12, for each read old data block, checking whether writing to it may cause a write disturb error, and generating a write disturb tendency vector; S13, setting each value of the write disturbance tendency vector to the maximum value of the number of write disturbance errors that may be caused in the same word row when each bit in the old data block is written.

3. The non-volatile memory write disturb mitigation method based on block selection according to claim 1, characterized in that: The old data block classification step S2 specifically includes: S21, determining the parameters of the clustering algorithm, including the number of clusters and the selected clustering algorithm; S22, using the initialized clustering algorithm to classify the tendency vectors of the old data blocks, so that the old data blocks with similar write disturbance tendency vectors can be classified into the same class; S23, for each class, the average of the tendency vectors of all old data blocks of the class is calculated as the basis for subsequent class selection; the available data block address table is initialized to record the addresses of available old data blocks and the class corresponding to each address.

4. The non-volatile memory write disturb mitigation method based on block selection according to claim 1, characterized in that: The new data block writing class selection step S3 specifically includes: S31, based on the characteristics of write disturbance, extracting the write disturbance attack vector of the new data block to be written, that is, the bit that may cause word-row write disturbance when writing; S32, respectively calculating the inner product of the write disturbance attack vector of the new data block and each old data category to represent the average value of the maximum number of write disturbance errors written to each category by the new data block; S33, selecting the old data category with the smallest inner product as the write category of the new data to probabilistically reduce write disturbance errors.

5. The non-volatile memory write disturb mitigation method based on block selection according to claim 1, characterized in that: The intra-class writing position selection step S4 specifically includes: S41, determining the number of selected hash functions, and generating a permutation function for each hash function for subsequent scrambling of data blocks; S42, calculating the hash value of each old data block, that is, using the permutation function to shuffle the old data block, and setting the position where the first bit 1 is located as its hash value; S43, storing the hash value of each old data block in the available data address table, and using it together with the category value as an index of the address; S44, calculating the hash value of the new data block to be written, and selecting the old data address from the address table for writing in combination with the value of the selected category.

6. A non-volatile memory write disturb mitigation system based on block selection, characterized in that: include: A write disturbance tendency vector extraction module is used to generate and store a write disturbance tendency vector for each old data block read; The write disturb tendency vector indicates the number of write disturb errors that may be caused when the old data block is overwritten; An old data block classification module is used to classify the write disturbance tendency vectors of old data blocks based on a clustering algorithm, obtain cluster labels, and divide the old data blocks into multiple categories, each of which has a similar write disturbance tendency distribution; A new data block write class selection module is used to extract the write disturbance attack vector of the new data block to be written, and select the old data class with the smallest inner product as the write class of the new data; The intra-class write position selection module is used to shuffle the new data block according to a predetermined hash permutation function, obtain a hash value, and select a write address from an available address table according to the hash value; the available address table stores the hash value and clustering label of the old data block.

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