Intra-domain communication method and device, electronic equipment, chip and medium

Abstract

The invention provides an intra-domain communication method and device, electronic equipment, a chip and a medium, and relates to the field of communication. The intra-domain communication method comprises the steps that first data are sent to a micro-control unit of a vehicle through a first serial bus in serial peripheral interface buses, and the serial peripheral buses at least comprise the first serial bus and a second serial bus, the first serial bus comprises a first chip selection signal line, a first clock signal line and a first master device output / slave device input signal line; and receiving second data sent by the micro-control unit through a second serial bus, wherein the second serial bus comprises a second chip selection signal line, a second clock signal line and a second master device output / slave device input signal line. Through the technical scheme provided by the invention, the problem that bidirectional independent communication between the micro-control unit and the system-on-chip can not be realized through the serial peripheral interface bus is solved, the system-on-chip and the micro-control unit can independently send data through the serial peripheral interface bus during HU intra-domain communication, and the data sending efficiency is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of communications, and in particular to an intra-domain communication method, device, electronic device, chip, and medium. Background Art

[0002] In the related art, in the domain controller of the vehicle cockpit, the system on chip (SOC) and the microcontroller unit (MCU) communicate through the serial peripheral interface (SPI) bus. SPI is a full-duplex synchronous communication mechanism bus with two data lines: Master Output Slave Input (MOSI) and Master Input Slave Output (MISO). However, the data transmission of SPI requires the clock of the master device to drive it, and each clock corresponds to one bit of data. Due to the inconsistent length of each frame of data in actual applications, the time of the SPI master device controlling the clock is different, resulting in the inability to perform two-way communication at the same time. Summary of the invention

[0003] The present disclosure provides a method, device, electronic device, chip and medium for intra-domain communication, so as to solve the problem that the MCU and the SOC cannot communicate independently in both directions through the SPI bus. By modifying the SPI communication bus between the SOC and the MCU, the MISO signal line is removed, and the SOC and the MCU communicate through the two-way modified SPI bus. Through the technical solution provided by the present disclosure, the SOC and the MCU can independently send data through the SPI bus when communicating in the domain of the vehicle head unit (HU), thereby improving the efficiency of data transmission.

[0004] A first aspect of the present disclosure provides an intra-domain communication method, the method comprising:

[0005] Sending first data to a micro control unit of the vehicle via a first serial bus in a serial peripheral interface bus, wherein the serial peripheral interface bus includes at least a first serial bus and a second serial bus, and the first serial bus includes a first chip select signal line, a first clock signal line, and a first master device output / slave device input signal line;

[0006] The second data sent by the micro control unit is received via a second serial bus, where the second serial bus includes a second chip selection signal line, a second clock signal line, and a second master device output / slave device input signal line.

[0007] In one embodiment of the present disclosure, sending first data to a micro control unit of a vehicle through a first serial bus in a serial peripheral interface bus includes:

[0008] Obtaining a low level for the first chip select signal line and starting communication with the micro control unit;

[0009] generating a first clock signal of a first clock signal line, the first clock signal being used for synchronizing communication with a micro control unit;

[0010] Based on the first clock signal, first data is sent to the micro control unit through the first master device output / slave device input signal line.

[0011] In one embodiment of the present disclosure, receiving second data sent by the micro control unit through the second serial bus includes:

[0012] Acquire a second clock signal based on a serial peripheral interface protocol agreement;

[0013] Based on the second clock signal, second data sent by the micro control unit through the second master device output / slave device input signal line is received.

[0014] In one embodiment of the present disclosure, the method further includes:

[0015] A high level is obtained for the first chip selection signal line, and communication with the micro control unit is stopped.

[0016] A second aspect of the present disclosure provides an intra-domain communication method, the method comprising:

[0017] Sending second data to the on-chip system of the vehicle via a second serial bus in the serial peripheral interface bus, the serial peripheral interface bus at least comprising the second serial bus and the first serial bus, the second serial bus comprising a second chip select signal line, a second clock signal line, and a second master device output / slave device input signal line;

[0018] First data sent by the system on chip is received through a first serial bus, where the first serial bus includes a first chip selection signal line, a first clock signal line, and a first master device output / slave device input signal line.

[0019] In one embodiment of the present disclosure, sending second data to a system on chip of a vehicle through a second serial bus in a serial peripheral interface bus includes:

[0020] Obtain a low level for the second chip select signal line and start communicating with the on-chip system;

[0021] generating a second clock signal for a second clock signal line, the second clock signal being used for synchronizing communication with the system on chip;

[0022] Based on the second clock signal, second data is sent to the system on chip through the second master output / slave input signal line.

[0023] In one embodiment of the present disclosure, receiving first data sent by a system on chip through a first serial bus includes:

[0024] Acquire a first clock signal based on a serial peripheral interface protocol agreement;

[0025] Based on the first clock signal, first data sent by the on-chip system through the first master output / slave input signal line is received.

[0026] In one embodiment of the present disclosure, the method further includes:

[0027] A high level is obtained for the second chip select signal line to stop communicating with the on-chip system.

[0028] A third aspect of the present disclosure provides an intra-domain communication system, the system comprising a system on chip, a microcontroller unit and a serial peripheral interface bus, the system on chip and the microcontroller unit are connected via the serial peripheral interface bus, the serial peripheral interface bus comprises a first serial bus and a second serial bus, the first serial bus comprises a first chip select signal line, a first clock signal line and a first master device output / slave device input signal line, the second serial bus comprises a second chip select signal line, a second clock signal line and a second master device output / slave device input signal line;

[0029] The system on chip is used to send first data to the micro control unit through a first serial bus;

[0030] The micro control unit is used for sending second data to the system on chip through the second serial bus.

[0031] In one embodiment of the present disclosure, the system on chip is used for:

[0032] A low level is obtained for the first chip selection signal line, and the system on chip starts communicating with the micro control unit;

[0033] Generate a first clock signal of a first clock signal line, the first clock signal is used to synchronize the communication between the system on chip and the micro control unit;

[0034] Based on the first clock signal, first data is sent to the micro control unit through the first master device output / slave device input signal line.

[0035] In one embodiment of the present disclosure, the microcontroller unit is used to:

[0036] A low level is obtained for the second chip selection signal line, and the micro control unit starts communicating with the on-chip system;

[0037] generating a second clock signal for a second clock signal line, the second clock signal being used to synchronize the communication between the microcontroller unit and the system on chip;

[0038] Based on the second clock signal, second data is sent to the system on chip through the second master output / slave input signal line.

[0039] In one embodiment of the present disclosure, the serial peripheral interface bus does not include a master device input / slave device output signal line.

[0040] A fourth aspect of the present disclosure provides an intra-domain communication device, the device comprising:

[0041] A sending module, sending first data to a micro control unit of a vehicle through a first serial bus in a serial peripheral interface bus, wherein the serial peripheral interface bus includes at least a first serial bus and a second serial bus, and the first serial bus includes a first chip select signal line, a first clock signal line, and a first master device output / slave device input signal line;

[0042] The receiving module receives second data sent by the micro control unit through a second serial bus, wherein the second serial bus includes a second chip selection signal line, a second clock signal line and a second master device output / slave device input signal line.

[0043] A fifth aspect of the present disclosure provides an intra-domain communication device, the device comprising:

[0044] a sending module, used for sending second data to the on-chip system of the vehicle through a second serial bus in the serial peripheral interface bus, the serial peripheral interface bus at least comprising the second serial bus and the first serial bus, the second serial bus comprising a second chip select signal line, a second clock signal line and a second master device output / slave device input signal line;

[0045] The receiving module is used to receive first data sent by the on-chip system through a first serial bus, wherein the first serial bus includes a first chip selection signal line, a first clock signal line and a first master device output / slave device input signal line.

[0046] The sixth aspect embodiment of the present disclosure proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any one of the methods in the first aspect or second aspect embodiment of the present disclosure.

[0047] The seventh aspect embodiment of the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions, characterized in that the computer instructions are used to enable a computer to execute the method in the first aspect or second aspect embodiment of the present disclosure.

[0048] The eighth aspect embodiment of the present disclosure proposes a computer program product, characterized in that it includes a computer program, and when the computer program is executed by a processor, it implements the method of any one of the first aspect or second aspect embodiments of the present disclosure.

[0049] The ninth aspect embodiment of the present disclosure proposes a chip, characterized in that it includes one or more interface circuits and one or more processors; the interface circuit is used to receive signals from the memory of the electronic device and send signals to the processor, the signals include computer instructions stored in the memory, and when the processor executes the computer instructions, the electronic device executes any one of the methods in the first or second aspect embodiments of the present disclosure.

[0050] In summary, according to the intra-domain communication method proposed in the present disclosure, the first data is sent to the micro control unit of the vehicle through the first serial bus in the serial peripheral interface bus, the serial peripheral interface bus includes at least the first serial bus and the second serial bus, the first serial bus includes the first chip select signal line, the first clock signal line and the first master device output / slave device input signal line, so that the system on chip sends data to the micro control unit through the serial peripheral interface bus during the intra-HU domain communication. The second data sent by the micro control unit is received through the second serial bus, and the second serial bus includes the second chip select signal line, the second clock signal line and the second master device output / slave device input signal line. The system on chip receives the data sent by the micro control unit through the serial peripheral interface bus, which ensures the independent transmission of the data of the system on chip and the micro control unit, and improves the efficiency of data transmission.

[0051] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute improper limitations on the present disclosure.

[0053] Figure 1 A communication diagram of adding dual IO control signals to SPI in the related art;

[0054] Figure 2 A flowchart of an intra-domain communication method according to an embodiment of the present disclosure;

[0055] Figure 3 A flowchart of sending first data to a micro control unit of a vehicle through a first serial bus in a serial peripheral interface bus according to an embodiment of the present disclosure;

[0056] Figure 4This is a flow chart of receiving second data sent by a micro control unit through a second serial bus according to an embodiment of the present disclosure;

[0057] Figure 5 A flowchart of an intra-domain communication method according to an embodiment of the present disclosure;

[0058] Figure 6 A flowchart of an embodiment of the present disclosure for sending second data to a system on chip of a vehicle via a second serial bus in a serial peripheral interface bus;

[0059] Figure 7 This is a flowchart of receiving first data sent by the system on chip through the first serial bus according to an embodiment of the present disclosure;

[0060] Figure 8 A schematic diagram of an intra-domain communication method according to an embodiment of the present disclosure;

[0061] Fig. 9 It is a structural schematic diagram of an intra-domain communication device according to an embodiment of the present disclosure;

[0062] Fig.10 It is a structural schematic diagram of an intra-domain communication device according to an embodiment of the present disclosure;

[0063] Fig.11 It is a block diagram of an electronic device for implementing the intra-domain communication method disclosed in the present invention according to an exemplary embodiment. DETAILED DESCRIPTION

[0064] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout identify the same or similar originals or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0065] In the automotive field, the vehicle host HU domain controller is a central control system that integrates multimedia and navigation functions. It can be operated in a variety of ways such as touch screen, buttons, voice control, etc., including audio playback, phone answering, navigation guidance, temperature control and other functions. The relevant systems of each function use the SPI bus for communication.

[0066] SPI is a high-speed, full-duplex, synchronous communication bus, which is an important communication method for intra-domain communication between SOC and MCU in HU domain controller. The SPI bus occupies four wires (CS, CLOCK, MOSI, MISO) on the pin. CS is the abbreviation of ChipSelect, which is used to select the slave device; CLOCK is the clock signal, which is generated by the master device and used for synchronous data transmission; MOSI is the data signal output by the master device and input by the slave device; MISO is the data signal input by the master device and output by the slave device. The communication process includes sending and receiving data by the master device and the slave device, but only the master device can control the clock of data transmission for data transmission.

[0067] In the related art, since SOC is the master device of SPI communication and MCU is the slave device, in actual application, MCU will also have a lot of data to send to SOC master device, but MCU cannot control the SPI clock. Therefore, dual IO control signals are added.

[0068] Figure 1 The following is a communication diagram of adding dual IO control signals to SPI in the related art. Figure 1 The data links shown are as follows:

[0069] SPI_MISO: The data signal line that the master device outputs and the slave device inputs.

[0070] SPI_MOSI: The data signal line that the master device outputs and the slave device inputs.

[0071] SPI_CLK: SPI clock signal line, used for synchronous data transmission.

[0072] SPI_CS: Chip select signal line, used to select the slave device.

[0073] MCU_READY: MCU transmission ready signal line, low level by default.

[0074] SOC_READY: SOC transmission ready signal line, low level by default.

[0075] When SOC_READY is at a high level, the master device SOC sends data to the slave device MCU by controlling the SPI bus. Specifically, the chip select signal line SPI_CS selects the MCU connected to the current master device SOC as the slave device, and the SOC and MCU begin to communicate; at this time, the clock signal of the SPI clock signal line SPI_CLK is generated. Driven by this clock signal, the master device SOC sends data to the slave device MCU through SPI_MOSI, and each clock of SPI_CLK corresponds to one bit of data; the slave device MCU receives the data sent by the SOC through the clock signal controlled by the master device SOC. In this way, the master device SOC can transmit data to the slave device MCU through the SPI bus.

[0076] When MCU_READY is at a high level, the slave MCU sends data to the master SOC through SPI_MISO, and the data transmission is determined by the clock signal line SPI_CLK of the master SOC. However, the length of the data sent from the slave MCU to the master SOC is difficult to match the clock signal of the clock signal line SPI_CLK of the master SOC. As a result, the master SOC and the slave MCU cannot communicate bidirectionally.

[0077] The present invention aims to solve the problem that two-way independent communication between MCU and SOC cannot be achieved by using SPI bus. By modifying the SPI communication bus between SOC and MCU, the MISO signal line is removed, and two-way communication between SOC and MCU is achieved through two-way modified SPI bus communication between SOC and MCU.

[0078] The method proposed in the present disclosure is applied to the field of SPI bus communication, and its application has a wide range of scenarios, mainly in HU domain controllers. It is specifically applied to assisted driving, unmanned driving, etc. The application scenarios are not limited in the embodiments of the present disclosure.

[0079] The intra-domain communication method provided by the present application is described in detail below with reference to the accompanying drawings.

[0080] Figure 2 FIG. 1 is a flow chart of an intra-domain communication method according to an embodiment of the present disclosure. Figure 2 In the illustrated embodiment, the intra-domain communication method includes:

[0081] Step 201, sending first data to a micro control unit of a vehicle via a first serial bus in a serial peripheral interface bus, wherein the serial peripheral interface bus includes at least a first serial bus and a second serial bus, and the first serial bus includes a first chip select signal line, a first clock signal line, and a first master device output / slave device input signal line.

[0082] In this embodiment, the first serial bus is an improvement of the SPI bus, and the system on chip SOC and the microcontroller unit MCU are connected through the SPI bus, especially through the first serial bus. The first serial bus is composed of a first chip select signal line CS, a first clock signal line CLK and a first MOSI signal line. The first chip select signal line CS is used to select a slave device, the first clock signal line CLK is used to synchronize the communication between the master device and the slave device, and the first MOSI signal line is used for the master device to output and the slave device to input data for transmission, where the master device is the sender of the data and the slave device is the receiver of the data.

[0083] Step 202: receiving second data sent by the micro control unit through a second serial bus, where the second serial bus includes a second chip select signal line, a second clock signal line, and a second master device output / slave device input signal line.

[0084] In this embodiment, the second serial bus is an improvement of the SPI bus, and the MCU and the SOC are connected through the SPI bus, especially through the second serial bus. The second serial bus is composed of a second chip select signal line CS, a second clock signal line CLK, and a second MOSI signal line. The second chip select signal line CS is used to select a slave device, the second clock signal line CLK is used to synchronize the communication between the master device and the slave device, and the second MOSI signal line is used for the master device to output and the slave device to input data for transmission.

[0085] In this embodiment, the SOC is a slave device, which receives the second data sent by the master device MCU, thereby realizing the data receiving function.

[0086] In summary, according to the intra-domain communication method proposed in the present disclosure, the SOC and MCU independently send data through the SPI bus during HU intra-domain communication, thereby improving the efficiency of data transmission.

[0087] Figure 3 The present invention is a flowchart of sending first data to a micro control unit of a vehicle through a first serial bus in a serial peripheral interface bus according to an embodiment of the present invention. Figure 3 right Figure 2 Step 201 is further described based on Figure 3 The embodiment shown, Figure 3 The steps include:

[0088] Step 301, obtaining a low level for a first chip selection signal line, and starting communication with a micro control unit.

[0089] In this embodiment, the first chip select signal line CS is a pin of the master device SOC, which is used to select the slave device of the device SOC. After the chip select pins of the master device SOC and the MCU are connected through the first chip select signal CS of the SPI bus, if the first chip select signal CS is at a low level, the master device SOC and the slave device MCU can start communicating.

[0090] Step 302: Generate a first clock signal for a first clock signal line, where the first clock signal is used to synchronize communication with a micro control unit.

[0091] In this embodiment, the first clock signal is a clock signal generated by the master device SOC, and the first clock signal line CLK is used to perform continuous signal flip timing to synchronize the communication between the master device SOC and the slave device MCU.

[0092] Step 303: Based on the first clock signal, first data is sent to the micro control unit through the first master device output / slave device input signal line.

[0093] In this embodiment, the first MOSI signal line sends the first data from the master device SOC to the slave device MCU according to the first clock signal. The first data is data generated by the master device SOC and can be file data or verification data.

[0094] In this embodiment, the master device SOC sends first data to the slave device, that is, the micro control unit MCU of the vehicle, through the first serial bus, so that the SOC sends data to the MCU, and the SOC also needs to receive data sent by the MCU.

[0095] Figure 4 The present invention is a flowchart of receiving second data sent by a micro control unit through a second serial bus according to an embodiment of the present invention. Figure 4 Yes Figure 2 The specific description of step 202 is based on Figure 4 The embodiment shown comprises the following steps:

[0096] Step 401: Acquire a second clock signal based on a serial peripheral interface protocol.

[0097] In this embodiment, the serial peripheral interface SPI protocol includes the clock signal of the master device, and the second clock signal is the clock signal of the master device. Currently, the master device MCU sends the second data to the slave device SOC, and the second clock signal is the clock signal of the MCU.

[0098] Step 402: Based on the second clock signal, receive second data sent by the micro control unit through the second master device output / slave device input signal line.

[0099] In this embodiment, according to the clock signal of the MCU, the SOC receives the second data sent by the MCU through the second MOSI signal line, wherein the second data is data generated by the master device MCU, and may be file data or verification data.

[0100] In this embodiment, the data transmission from the master device MCU to the slave device SOC and the reception of the data sent by the SOC to the MCU are completed through the second serial bus.

[0101] In the embodiment of the present disclosure, the master device obtains a high level for the first chip select signal line CS, and the SOC and the MCU immediately stop communicating.

[0102] Figure 5 FIG. 1 is a flow chart of an intra-domain communication method according to an embodiment of the present disclosure. Figure 5 The embodiment shown, Figure 5 The steps include:

[0103] Step 501, sending second data to the vehicle's on-chip system through a second serial bus in the serial peripheral interface bus, the serial peripheral interface bus at least includes a second serial bus and a first serial bus, the second serial bus includes a second chip select signal line, a second clock signal line and a second master device output / slave device input signal line.

[0104] In this embodiment, the second serial bus is an improvement of the SPI bus, and the SOC and the MCU are connected through the SPI bus, especially through the second serial bus. The second serial bus is composed of a second chip select signal line CS, a second clock signal line CLK, and a second MOSI signal line. The second chip select signal line CS is used to select a slave device, the second clock signal line CLK is used to synchronize the communication between the master device and the slave device, and the second MOSI signal line is used for the master device to output and the slave device to input data for transmission. Here, the master device is the sender of the data, and the slave device is the receiver of the data.

[0105] Step 502: Receive first data sent by the system on chip through a first serial bus, where the first serial bus includes a first chip select signal line, a first clock signal line, and a first master device output / slave device input signal line.

[0106] In this embodiment, the first serial bus is an improvement of the SPI bus, and the MCU and the SOC are connected through the SPI bus, especially through the first serial bus. The first serial bus is composed of a first chip select signal line CS, a first clock signal line CLK and a first MOSI signal line. The first chip select signal line CS is used to select a slave device, the first clock signal line CLK is used to synchronize the communication between the master device and the slave device, and the first MOSI signal line is used for the master device to output and the slave device to input data for transmission.

[0107] In this embodiment, the MCU is a slave device, which receives the first data sent by the master device SOC, thereby realizing the data receiving function.

[0108] Figure 6 The present invention is a flowchart of sending second data to a system on chip of a vehicle through a second serial bus in a serial peripheral interface bus according to an embodiment of the present invention. Figure 6 right Figure 5 Step 501 is specifically described based on Figure 6 The embodiment shown comprises the following steps:

[0109] Step 601, obtaining a low level for a second chip select signal line, and starting communication with the system on chip.

[0110] In this embodiment, the second chip select signal line CS is a pin of the master device MCU, which is used to select the slave device of the device MCU. After the chip select pins of the master device MCU and the SOC are connected through the first chip select signal CS of the SPI bus, if the first chip select signal CS is at a low level, the master device MCU and the slave device SOC can start communicating.

[0111] Step 602: Generate a second clock signal for a second clock signal line, where the second clock signal is used to synchronize communication with the system on chip.

[0112] In this embodiment, the second clock signal is a clock signal generated by the master device MCU, and continuous flip timing of the signal is performed through the second clock signal line CLK to synchronize the communication between the master device MCU and the slave device SOC.

[0113] Step 603: Based on the second clock signal, second data is sent to the system on chip through the second master output / slave input signal line.

[0114] In this embodiment, the second MOSI signal line sends the second data from the master device MCU to the slave device SOC according to the second clock signal. The second data is data generated by the master device MCU and can be file data or verification data.

[0115] In this embodiment, the master device MCU sends the second data to the slave device, ie, the system on chip SOC of the vehicle, through the second serial bus, so that the MCU sends data to the SOC, and the MCU also needs to receive data sent by the SOC.

[0116] Figure 7 The present invention is a flowchart of receiving first data sent by a system on chip through a first serial bus according to an embodiment of the present invention. Figure 7 Yes Figure 5 Step 502 is specifically described, based on Figure 7 The embodiment shown comprises the following steps:

[0117] Step 701: Acquire a first clock signal based on a serial peripheral interface protocol.

[0118] In this embodiment, the SPI protocol includes the clock signal of the master device, and the first clock signal is the clock signal of the master device. Currently, the master device SOC sends the first data to the slave device MCU, and the first clock signal is the clock signal of the SOC.

[0119] Step 702: Based on the first clock signal, receive first data sent by the system on chip through a first master output / slave input signal line.

[0120] In this embodiment, according to the clock signal of the SOC, the MCU receives first data sent by the SOC through the first MOSI signal line, wherein the first data is data generated by the master device SOC, and may be file data or verification data.

[0121] In this embodiment, the data transmission from the master device SOC to the slave device MCU and the reception of the data sent by the SOC by the MCU are completed through the first serial bus.

[0122] In the disclosed embodiment, the master device obtains a high level for the second chip select signal line CS, and the MCU and the SOC immediately stop communicating.

[0123] Figure 8 FIG. 1 is a schematic diagram of an intra-domain communication method according to an embodiment of the present disclosure. Figure 8 In the embodiment shown, the SOC and the MCU communicate via an SPI bus, which includes a first serial bus and a second serial bus. The first serial bus is composed of a first chip select signal line SPI_CS, a first clock signal line SPI_CLK, and a first serial bus_MOSI signal line, and the second SIP is composed of a second chip select signal line SPI_CS, a second clock signal line SPI_CLK, and a second serial bus_MOSI signal line, thereby realizing bidirectional independent communication between the SOC and the MCU and improving the efficiency of data transmission.

[0124] In an embodiment of an intra-domain communication system disclosed in the present invention, the system includes a system on chip SOC, a microcontroller unit MCU and a serial peripheral interface SPI bus, the SOC and the MCU are connected via the SPI bus, the SPI bus includes a first serial bus and a second serial bus, the first serial bus includes a first chip select signal line CS, a first clock signal line CLK and a first MOSI signal line, the second serial bus includes a second chip select signal line CS, a second clock signal line CLK and a second MOSI signal line;

[0125] The SOC is used to send first data to the MCU through the first serial bus;

[0126] The MCU is used for sending the second data to the SOC through the second serial bus.

[0127] In some embodiments, the SOC is used to:

[0128] Obtaining the low level of the first chip select signal line CS, the SOC and MCU start communicating;

[0129] Generate a first clock signal of a first clock signal line CLK, the first clock signal is used to synchronize the communication between the SOC and the MCU;

[0130] Based on the first clock signal, first data is sent to the MCU through the first MOSI signal line.

[0131] In some embodiments, the MCU is used to:

[0132] Obtaining the low level for the second chip select signal line CS, the MCU and the SOC begin to communicate;

[0133] Generate a second clock signal of a second clock signal line CLK, the second clock signal is used to synchronize the communication between the MCU and the SOC;

[0134] Based on the second clock signal, second data is sent to the SOC through the second MOSI signal line.

[0135] In some embodiments, the SPI bus does not include a MISO signal line.

[0136] The intra-domain communication system uses the first serial bus and the second serial bus. The first serial bus is composed of a first chip select signal line CS, a first clock signal line CLK and a first MOSI signal line. The second SIP is composed of a second chip select signal line CS, a second clock signal line CLK and a second MOSI signal line. At the same time, the first serial bus and the second serial bus both remove the MISO signal line in the SPI bus, thereby realizing two-way independent communication between the SOC and the MCU and improving the efficiency of data transmission.

[0137] Corresponding to the methods and systems provided in the above-mentioned embodiments, the present disclosure also provides an intra-domain communication device. Since the device provided in the embodiments of the present disclosure corresponds to the methods provided in the above-mentioned embodiments, the implementation method of the method is also applicable to the device provided in this embodiment and will not be described in detail in this embodiment.

[0138] Fig. 9 FIG. 9 is a schematic diagram of the structure of an intra-domain communication device 900 according to an embodiment of the present disclosure. Fig. 9 As shown, the intra-domain communication device includes:

[0139] The sending module 910 sends first data to the micro control unit of the vehicle through the first serial bus in the serial peripheral interface bus. The serial peripheral interface bus includes at least a first serial bus and a second serial bus. The first serial bus includes a first chip select signal line, a first clock signal line and a first master device output / slave device input signal line.

[0140] The receiving module 920 receives second data sent by the micro control unit through a second serial bus, where the second serial bus includes a second chip selection signal line, a second clock signal line and a second master device output / slave device input signal line.

[0141] In some embodiments, the sending module 910 is used to:

[0142] Obtaining a low level for the first chip select signal line and starting communication with the micro control unit;

[0143] generating a first clock signal of a first clock signal line, the first clock signal being used for synchronizing communication with a micro control unit;

[0144] Based on the first clock signal, first data is sent to the micro control unit through the first master device output / slave device input signal line.

[0145] In some embodiments, the receiving unit 920 is configured to:

[0146] Acquire a second clock signal based on a serial peripheral interface protocol agreement;

[0147] Based on the second clock signal, second data sent by the micro control unit through the second master device output / slave device input signal line is received.

[0148] In some embodiments, the intra-domain communication device is further configured to:

[0149] A high level is obtained for the first chip selection signal line, and communication with the micro control unit is stopped.

[0150] Fig.10 FIG. 1 is a schematic diagram of the structure of an intra-domain communication device 1000 according to an embodiment of the present disclosure. Fig.10 As shown, the intra-domain communication device includes:

[0151] The sending module 1010 is used to send second data to the vehicle's on-chip system through a second serial bus in the serial peripheral interface bus, the serial peripheral interface bus at least includes a second serial bus and a first serial bus, the second serial bus includes a second chip select signal line, a second clock signal line and a second master device output / slave device input signal line.

[0152] The receiving module 1020 is used to receive first data sent by the on-chip system through a first serial bus, where the first serial bus includes a first chip selection signal line, a first clock signal line, and a first master device output / slave device input signal line.

[0153] In some embodiments, the sending module 1010 is used to:

[0154] Obtain a low level for the second chip select signal line and start communicating with the on-chip system;

[0155] generating a second clock signal for a second clock signal line, the second clock signal being used for synchronizing communication with the system on chip;

[0156] Based on the second clock signal, second data is sent to the system on chip through the second master output / slave input signal line.

[0157] In some embodiments, the receiving module 1020 is used to:

[0158] Acquire a first clock signal based on a serial peripheral interface protocol agreement;

[0159] Based on the first clock signal, first data sent by the on-chip system through the first master output / slave input signal line is received.

[0160] In some embodiments, the intra-domain communication device is further configured to:

[0161] A high level is obtained for the second chip selection signal line CS, and the MCU stops communicating with the SOC.

[0162] In summary, the first data is sent to the microcontroller unit MCU of the vehicle through the first serial bus through the intra-domain communication device, wherein the SOC is connected to the MCU through the SPI bus, the SPI bus includes the first serial bus, and the first serial bus includes the first chip select signal line CS, the first clock signal line CLK and the first MOSI signal line. This device solves the problem that the MCU and the SOC cannot communicate bidirectionally and independently through the SPI bus, and improves the efficiency of data transmission. In addition, the device has rich application scenarios, and the device can realize bidirectional independent communication between the SOC and the MCU in all devices using intra-HU communication, especially in vehicle assisted driving, unmanned driving and other aspects.

[0163] In the embodiments provided in the present application, the methods and devices provided in the embodiments of the present application are introduced. In order to implement the functions in the methods provided in the embodiments of the present application, the electronic device may include a hardware structure and a software module, and implement the functions in the form of a hardware structure, a software module, or a hardware structure plus a software module. A function of the functions may be executed in the form of a hardware structure, a software module, or a hardware structure plus a software module.

[0164] Fig.11 It is a block diagram of an electronic device 1100 for implementing the above intra-domain communication method according to an exemplary embodiment.

[0165] For example, the electronic device 1100 may be a mobile phone, a computer, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0166] Reference Fig.11 , the electronic device 1100 may include one or more of the following components: a processing component 1102 , a memory 1104 , a power component 1106 , a multimedia component 1108 , an audio component 1110 , an input / output (I / O) interface 1112 , a sensor component 1114 , and a communication component 1116 .

[0167] The processing component 1102 generally controls the overall operation of the electronic device 1100, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 1102 may include one or more processors 1120 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 1102 may include one or more modules to facilitate the interaction between the processing component 1102 and other components. For example, the processing component 1102 may include a multimedia module to facilitate the interaction between the multimedia component 1108 and the processing component 1102.

[0168] The memory 1104 is configured to store various types of data to support operations on the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 1100, contact data, phone book data, messages, pictures, videos, etc. The memory 1104 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0169] The power supply component 1106 provides power to various components of the electronic device 1100. The power supply component 1106 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 1100.

[0170] The multimedia component 1108 includes a screen that provides an output interface between the electronic device 1100 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1108 includes a front camera and / or a rear camera. When the electronic device 1100 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0171] The audio component 1110 is configured to output and / or input audio signals. For example, the audio component 1110 includes a microphone (MIC), and when the electronic device 1100 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 1104 or sent via the communication component 1116. In some embodiments, the audio component 1110 also includes a speaker for outputting audio signals.

[0172] I / O interface 1112 provides an interface between processing component 1102 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0173] The sensor assembly 1114 includes one or more sensors for providing various aspects of status assessment for the electronic device 1100. For example, the sensor assembly 1114 can detect the open / closed state of the electronic device 1100, the relative positioning of components, such as the display and keypad of the electronic device 1100, and the sensor assembly 1114 can also detect the position change of the electronic device 1100 or a component of the electronic device 1100, the presence or absence of user contact with the electronic device 1100, the orientation or acceleration / deceleration of the electronic device 1100, and the temperature change of the electronic device 1100. The sensor assembly 1114 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 1114 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1114 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0174] The communication component 1116 is configured to facilitate wired or wireless communication between the electronic device 1100 and other devices. The electronic device 1100 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio) or a combination thereof. In an exemplary embodiment, the communication component 1116 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1116 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0175] In an exemplary embodiment, the electronic device 1100 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0176] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1104 including instructions, and the instructions can be executed by a processor 1120 of the electronic device 1100 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0177] The embodiments of the present disclosure further provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the intra-domain communication method described in the above embodiments of the present disclosure.

[0178] An embodiment of the present disclosure further provides a computer program product, including a computer program, which executes the intra-domain communication method described in the above embodiment of the present disclosure when a processor is used to execute the computer program.

[0179] An embodiment of the present disclosure also proposes a chip, which includes one or more interface circuits and one or more processors; the interface circuit is used to receive signals from a memory of an electronic device and send signals to the processor, the signals include computer instructions stored in the memory, and when the processor executes the computer instructions, the electronic device executes the intra-domain communication method described in the above embodiments of the present disclosure.

[0180] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0181] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0182] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0183] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processing module, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (control method), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.

[0184] It should be understood that the various parts of the embodiments of the present disclosure can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0185] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0186] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium. The above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0187] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present disclosure. A person skilled in the art may make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A method for intra-domain communication, characterized in that: The method comprises: Sending first data to a micro control unit of a vehicle via a first serial bus in a serial peripheral interface bus, wherein the serial peripheral interface bus includes at least the first serial bus and a second serial bus, and the first serial bus includes a first chip select signal line, a first clock signal line, and a first master device output / slave device input signal line; The second data sent by the micro control unit is received via the second serial bus, where the second serial bus includes a second chip selection signal line, a second clock signal line, and a second master device output / slave device input signal line.

2. The method according to claim 1, characterized in that The sending of the first data to the micro control unit of the vehicle through the first serial bus in the serial peripheral interface bus comprises: Acquire a low level for the first chip select signal line and start communicating with the micro control unit; generating a first clock signal of the first clock signal line, wherein the first clock signal is used to synchronize communication with the micro control unit; Based on the first clock signal, the first data is sent to the micro control unit through the first master device output / slave device input signal line.

3. The method according to claim 1, characterized in that The receiving, through the second serial bus, the second data sent by the micro control unit comprises: Acquire a second clock signal based on a serial peripheral interface protocol agreement; Based on the second clock signal, the second data sent by the micro control unit through the second master device output / slave device input signal line is received.

4. The method according to claim 1, characterized in that: The method further comprises: A high level is obtained for the first chip selection signal line, and communication with the micro control unit is stopped.

5. An intra-domain communication method, characterized in that: The method comprises: Sending second data to the on-chip system of the vehicle via a second serial bus in the serial peripheral interface bus, wherein the serial peripheral interface bus at least includes the second serial bus and the first serial bus, and the second serial bus includes a second chip select signal line, a second clock signal line, and a second master device output / slave device input signal line; The first data sent by the system on chip is received through the first serial bus, where the first serial bus includes a first chip select signal line, a first clock signal line, and a first master device output / slave device input signal line.

6. The method according to claim 5, characterized in that The sending of the second data to the on-chip system of the vehicle through the second serial bus in the serial peripheral interface bus comprises: Acquire a low level for the second chip select signal line and start communicating with the system on chip; generating a second clock signal of the second clock signal line, wherein the second clock signal is used to synchronize communication with the system on chip; Based on the second clock signal, the second data is sent to the system on chip through the second master output / slave input signal line.

7. The method according to claim 5, characterized in that The receiving, through the first serial bus, first data sent by the system on chip comprises: Acquire a first clock signal based on a serial peripheral interface protocol agreement; Based on the first clock signal, the first data sent by the system on chip through the first master output / slave input signal line is received.

8. The method according to claim 5, characterized in that The method further comprises: A high level is obtained for the second chip selection signal line, and communication with the on-chip system is stopped.

9. An intra-domain communication system, characterized in that: The system includes a system on chip, a micro control unit and a serial peripheral interface bus, wherein the system on chip and the micro control unit are connected via the serial peripheral interface bus, wherein the serial peripheral interface bus includes a first serial bus and a second serial bus, wherein the first serial bus includes a first chip select signal line, a first clock signal line and a first master device output / slave device input signal line, and wherein the second serial bus includes a second chip select signal line, a second clock signal line and a second master device output / slave device input signal line; The system on chip is used to send first data to the micro control unit through the first serial bus; The micro control unit is used for sending second data to the system on chip through the second serial bus.

10. The intra-domain communication system according to claim 9, characterized in that: The system on chip is used to: Acquiring a low level for the first chip selection signal line, the system on chip starts communicating with the micro control unit; generating a first clock signal of the first clock signal line, wherein the first clock signal is used to synchronize the communication between the system on chip and the micro control unit; Based on the first clock signal, the first data is sent to the micro control unit through the first master device output / slave device input signal line.

11. The intra-domain communication system according to claim 9, characterized in that: The micro control unit is used for: Acquiring a low level for the second chip selection signal line, the micro control unit starts communicating with the system on chip; generating a second clock signal of the second clock signal line, wherein the second clock signal is used to synchronize the communication between the micro control unit and the system on chip; Based on the second clock signal, the second data is sent to the system on chip through the second master output / slave input signal line.

12. The intra-domain communication system according to claim 9, characterized in that: The serial peripheral interface bus does not include a master input / slave output signal line.

13. An intra-domain communication device, characterized in that: The device comprises: A sending module, used for sending first data to a micro control unit of a vehicle through a first serial bus in a serial peripheral interface bus, wherein the serial peripheral interface bus at least includes the first serial bus and a second serial bus, and the first serial bus includes a first chip select signal line, a first clock signal line, and a first master device output / slave device input signal line; The receiving module is used to receive the second data sent by the micro control unit through the second serial bus, wherein the second serial bus includes a second chip selection signal line, a second clock signal line and a second master device output / slave device input signal line.

14. An intra-domain communication device, characterized in that: The device comprises: a sending module, configured to send second data to the on-chip system of the vehicle through a second serial bus in the serial peripheral interface bus, wherein the serial peripheral interface bus at least includes the second serial bus and the first serial bus, and the second serial bus includes a second chip select signal line, a second clock signal line, and a second master device output / slave device input signal line; The receiving module is used to receive the first data sent by the on-chip system through the first serial bus, wherein the first serial bus includes a first chip selection signal line, a first clock signal line and a first master device output / slave device input signal line.

15. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-4 or 5-8.

16. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-4 or 5-8.

17. A computer program product, characterized in that It comprises a computer program which, when executed by a processor, implements the method according to any one of claims 1-4 or 5-8.

18. A chip, characterized in that: It includes one or more interface circuits and one or more processors; the interface circuit is used to receive a signal from a memory of an electronic device and send the signal to the processor, the signal includes a computer instruction stored in the memory, and when the processor executes the computer instruction, the electronic device executes the method described in any one of claims 1-4 or 5-8.

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