Time sequence anomaly detection method, device and equipment of integrated circuit and medium

Abstract

The invention provides a time sequence anomaly detection method and device of an integrated circuit, equipment and a medium. The time sequence anomaly detection method comprises the steps of traversing time sequence information of each circuit path in a target integrated circuit under a preset window interval through a sliding window; performing feature engineering processing on the time sequence information of each circuit path, and extracting a time sequence feature of each circuit path; inputting the time sequence characteristics of each circuit path to a multi-head self-attention network layer, a normalization processing network layer, a sparse conversion network layer and a full-connection network layer of a time sequence anomaly detection model for time sequence anomaly detection processing, and outputting abnormal time sequence information of the integrated circuit; wherein the time sequence anomaly detection model is obtained by performing iterative training on a sparse conversion network model. When a large number of circuit paths exist in the integrated circuit, time sequence anomaly detection is carried out on the integrated circuit through other network layers such as a sparse conversion network layer in the time sequence anomaly detection model, and the accuracy and efficiency of abnormal time sequence detection can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit detection, and in particular to a timing anomaly detection method, device, equipment and medium for integrated circuits. Background Art

[0002] In the field of Electronic Design Automation (EDA), Static Timing Analysis (STA) is a key technology used to ensure that digital circuits meet their performance requirements. STA tools use static analysis methods to evaluate and verify the timing behavior in integrated circuit (IC) designs. As the scale of integrated circuit design continues to expand, the number of components in the circuit has increased dramatically, and the interconnection structure has become more complex. This complexity requires the STA tool to process a large amount of data and paths when counting delays, which increases the difficulty and computational complexity of the analysis. The reduction in feature size has made the resistance and capacitance of interconnect lines have an increasingly greater impact on signal propagation. This leads to the so-called "interconnect dominance" phenomenon, in which the interconnection delay exceeds the delay of the transistor itself. Accurately extracting parameters such as parasitic resistance and capacitance from the physical layout is a complex task, and inaccurate parasitic parameters can lead to deviations in STA results. Therefore, how to quickly and accurately detect timing anomalies in integrated circuits has become a technical issue that cannot be underestimated. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a method, device, equipment and medium for detecting timing anomalies in an integrated circuit. When there are a large number of circuit paths in the integrated circuit, the accuracy and efficiency of abnormal timing detection can be improved when timing anomaly detection is performed on the integrated circuit through other network layers such as a sparse transition network layer in a timing anomaly detection model.

[0004] The present application provides a timing anomaly detection method for an integrated circuit, the timing anomaly detection method comprising: Traversing the timing information of each circuit path in the target integrated circuit at a preset window interval by using a sliding window; Performing feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path; The timing features of each circuit path are input into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and the abnormal timing information of the integrated circuit is output; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model.

[0005] In a possible implementation manner, for each of the timing characteristics of the circuit path, timing anomaly detection processing is performed through the following steps: Inputting the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing, and outputting the attention features; Inputting the attention feature into the normalization processing network layer for processing, and outputting the normalized attention feature; Inputting the normalized attention features into multiple forward feedback sub-network layers of the sparse transformation network layer for forward feedback processing, and outputting target features; The target feature is input into the fully connected network layer for linear processing, and whether the target feature is abnormal time series information is output.

[0006] In a possible implementation manner, the inputting the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing and outputting the attention features includes: Performing attention mechanism processing on the timing features of the circuit path to determine a query tensor, a key tensor, and a value tensor corresponding to the timing features; Calculating the attention score between the query tensor and the key tensor based on the activation function to determine the probability matrix of the time series feature; The time series feature and the probability matrix are multiplied to output the attention feature.

[0007] In a possible implementation manner, the normalized attention features are input into a plurality of feedforward sub-network layers of the sparse transformation network layer for feedforward processing, and the target features are output, including: Processing the normalized attention features based on the first linear transformation weight matrix corresponding to each of the forward feedback sub-network layers to obtain a plurality of reference features; Sparse processing is performed based on the weight values ​​of multiple reference features so that the reference feature with the maximum weight value is used as the target feature.

[0008] In a possible implementation manner, whether the target feature is abnormal time series information is determined in the following manner:

[0009] Among them, if the category of Y is 1, the target feature F is abnormal time series information, and if the category of Y is 0, the target feature F is normal time series information. is the second linear transformation matrix.

[0010] In a possible implementation manner, the time series anomaly detection model is determined by the following steps: Inputting the sample timing features of the sample circuit path into the sparse switching network model to perform timing anomaly detection processing, and determining the prediction label of the sample timing features; The sparse transformation network model is iteratively trained based on the real labels of the sample time series features and the loss values ​​between the predicted labels to determine the time series anomaly detection model.

[0011] In a possible implementation manner, the iterative training of the sparse transformation network model based on the real label of the sample time series feature and the loss value between the predicted label to determine the time series anomaly detection model includes: Detecting whether the loss value is greater than a preset threshold; If yes, the network parameters of the sparse transformation network model are updated, and the updated sparse transformation network model is continuously iterated for training; If not, the iterative training of the sparse transformation network model is stopped to determine the time series anomaly detection model.

[0012] The embodiment of the present application further provides a timing anomaly detection device for an integrated circuit, the timing anomaly detection device comprising: A timing information extraction module, used to traverse the timing information of each circuit path in the target integrated circuit at a preset window interval using a sliding window; A feature processing module, used to perform feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path; A detection module is used to input the timing features of each circuit path into the multi-head self-attention network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and output abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model.

[0013] An embodiment of the present application also provides an electronic device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the steps of the timing anomaly detection method for the integrated circuit as described above are performed.

[0014] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the timing anomaly detection method for an integrated circuit as described above are executed.

[0015] The embodiment of the present application provides a timing anomaly detection method, device, equipment and medium for integrated circuits, the timing anomaly detection method comprising: traversing the timing information of each circuit path in the target integrated circuit at a preset window interval with a sliding window; performing feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path; inputting the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and outputting the abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model. When there are a large number of circuit paths in the integrated circuit, the accuracy and efficiency of abnormal timing detection can be improved when the integrated circuit is subjected to timing anomaly detection through other network layers such as the sparse transition network layer in the timing anomaly detection model.

[0016] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A flowchart of a timing anomaly detection method for an integrated circuit provided in an embodiment of the present application; Figure 2 A schematic diagram of the processing process of the timing anomaly detection model provided in an embodiment of the present application; Figure 3 One of the structural schematic diagrams of a timing anomaly detection device for an integrated circuit provided in an embodiment of the present application; Figure 4 A second structural diagram of a timing anomaly detection device for an integrated circuit provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, each other embodiment obtained by those skilled in the art without making creative work belongs to the scope of protection of the present application.

[0020] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0021] In order to enable those skilled in the art to use the contents of this application, the following implementation methods are provided in combination with the specific application scenario of "detecting timing anomalies of integrated circuits". For those skilled in the art, the general principles defined here can be applied to other embodiments and application scenarios without departing from the spirit and scope of this application.

[0022] The following methods, devices, electronic devices or computer-readable storage media of the embodiments of the present application can be applied to any scenario where timing anomalies of an integrated circuit need to be detected. The embodiments of the present application are not limited to specific application scenarios. Any scheme using the timing anomaly detection method, device, equipment and medium of an integrated circuit provided by the embodiments of the present application is within the scope of protection of the present application.

[0023] First, the application scenarios to which the present application is applicable are introduced. The present application can be applied in the field of integrated circuit detection technology.

[0024] It has been found that in the field of Electronic Design Automation (EDA), Static Timing Analysis (STA) is a key technology used to ensure that digital circuits meet their performance requirements. The STA tool uses static analysis methods to evaluate and verify the timing behavior in integrated circuit (IC) design. As the scale of integrated circuit design continues to expand, the number of components in the circuit has increased dramatically, and the interconnection structure has become more complex. This complexity requires the STA tool to process a large amount of data and paths when counting delays, which increases the difficulty and computational complexity of the analysis. The reduction in feature size has made the resistance and capacitance of interconnect lines have an increasingly greater impact on signal propagation. This leads to the so-called "interconnect dominance" phenomenon, in which the interconnection delay exceeds the delay of the transistor itself. Accurately extracting parameters such as parasitic resistance and capacitance from the physical layout is a complex task, and inaccurate parasitic parameters will lead to deviations in STA results. Therefore, how to quickly and accurately detect timing anomalies in integrated circuits has become a technical issue that cannot be underestimated.

[0025] Based on this, an embodiment of the present application provides a timing anomaly detection method for an integrated circuit. When there are a large number of circuit paths in the integrated circuit, the accuracy and efficiency of abnormal timing detection can be improved when timing anomaly detection is performed on the integrated circuit through other network layers such as a sparse transition network layer in a timing anomaly detection model.

[0026] See also Figure 1 , Figure 1 This is a flow chart of a timing anomaly detection method for an integrated circuit provided in an embodiment of the present application. Figure 1 As shown in , the timing anomaly detection method provided by the embodiment of the present application includes: S101: traversing the timing information of each circuit path in the target integrated circuit at a preset window interval using a sliding window.

[0027] In this step, the timing information of each circuit path in the target integrated circuit at a preset window interval is traversed according to the sliding window.

[0028] The timing information includes characteristic data information when the circuit path is working at each time point, and the characteristic data information includes resistance information, capacitance information, and pin information.

[0029] S102: Perform feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path.

[0030] In this step, feature engineering is performed on the timing information of each circuit path to extract the timing features of each path.

[0031] S103: Input the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and output abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model.

[0032] In this step, the timing features of each circuit path are input into the multi-head self-attention network layer, normalization processing network layer, sparse transformation network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and the abnormal timing information of the integrated circuit is output.

[0033] The time series anomaly detection model is obtained by iteratively training a sparse transition network model.

[0034] Here, the Sparse Transformer network model is a model designed to optimize the architectural computational complexity and memory consumption of the traditional neural network model. It adopts a sparse mechanism to reduce the computational complexity of the self-attention mechanism, making it more efficient when processing long sequences, thereby improving the efficiency of abnormal timing detection in integrated circuits.

[0035] Among them, the sparse transformation network layer includes multiple feedforward sub-network layers (FNN).

[0036] In a possible implementation manner, for each of the timing characteristics of the circuit path, timing anomaly detection processing is performed through the following steps: A: The timing characteristics of the circuit path are input into the multi-head self-attention network layer for attention mechanism processing, and the attention characteristics are output.

[0037] Here, the timing features of the circuit path are input into the multi-head self-attention network layer for attention mechanism processing, and the attention features are output.

[0038] In a possible implementation manner, the inputting the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing and outputting the attention features includes: a: Perform an attention mechanism on the timing features of the circuit path to determine the query tensor, key tensor, and value tensor corresponding to the timing features.

[0039] Here, through three transformation matrices Get the query tensor Q, key tensor V, and value tensor K:

[0040] in, is the output of the previous self-attention network layer.

[0041] b: Calculate the attention score between the query tensor and the key tensor based on the activation function to determine the probability matrix of the time series feature.

[0042] Here, a matrix is ​​constructed for the query tensor and the key tensor, and the attention score between the query tensor and the key tensor in the matrix is ​​calculated according to the activation function to determine the probability matrix of the time series feature.

[0043] Among them, the formula of the softmax operator is as follows, for each element of the matrix Calculate the attention score:

[0044] in, To query a tensor, j is the key tensor, k is the total number of features, For the To query a tensor, j is the attention score between the key tensors.

[0045] c: Normalize the time series features and the attention weight vector, and output the attention features.

[0046] Here, the time series features and the probability matrix are multiplied to output the attention features.

[0047] B: Input the attention feature into the normalization processing network layer for processing, and output the normalized attention feature.

[0048] Here, the attention feature is input into the normalization processing network layer for processing, and the normalized attention feature is output.

[0049] C: Input the normalized attention features into multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing, and output the target features.

[0050] Here, the normalized attention features are input into multiple feedforward sub-network layers of the sparse transformation network layer for feedforward processing, and the target features are output.

[0051] In a possible implementation manner, the normalized attention feature is input into a plurality of feedforward sub-network layers of the sparse transformation network layer for feedforward processing, and the target feature is output, including: (1): Based on the first linear transformation weight matrix corresponding to each of the forward feedback sub-network layers, the normalized attention features are processed to obtain multiple reference features.

[0052] Here, the normalized attention features are processed according to the first linear transformation weight matrix corresponding to each of the forward feedback sub-network layers to obtain multiple reference features and corresponding weight values.

[0053] Among them, the reference features are obtained by:

[0054] Among them, X is the normalized attention feature, For the i The first linear transformation weight matrix of the FFN, For the i Reference features of FFN.

[0055] (2) Sparse processing is performed based on the weight values ​​of multiple reference features so that the reference feature with the maximum weight value is used as the target feature.

[0056] Here, sparse processing is performed according to the weight values ​​of multiple reference features, and the reference feature with the maximum weight value is used as the target feature.

[0057] Among them, for indivual , only one is taken through the sparse operation, and the sparse function of this application is as follows:

[0058] Here, F is the target feature.

[0059] D: Input the target feature into the fully connected network layer for linear processing, and output whether the target feature is abnormal time series information.

[0060] Here, the target feature is input into the fully connected network layer for linear processing, and the output is whether the target feature is abnormal time series information.

[0061] In a possible implementation manner, whether the target feature is abnormal time series information is determined in the following manner:

[0062] Among them, if the category of Y is 1, the target feature F is abnormal time series information, and if the category of Y is 0, the target feature F is normal time series information. is the second linear transformation matrix.

[0063] For further information, see Figure 2 , Figure 2 This is a schematic diagram of the processing process of the timing anomaly detection model provided in the embodiment of the present application. Figure 2 As shown, the timing features X1 and X2 of the circuit path are inputted into the multi-head self-attention network layer of the timing anomaly detection model for processing to obtain the attention features of the timing feature X1 and the attention features of the timing feature X2, and the attention features of the timing feature X1 and the attention features of the timing feature X2 are inputted into the normalization processing network layer for processing to obtain the normalized attention features of the timing feature X1 and the normalized attention features of the timing feature X2. The normalized attention features are inputted into the multiple forward feedback sub-network layers FFN of the sparse transformation network layer for forward feedback processing to obtain the reference features and the corresponding weight values, and the reference features corresponding to the maximum weight value are inputted into the fully connected network layer for linear processing, and the output is whether X1 and X2 are abnormal timing information.

[0064] In a possible implementation manner, the time series anomaly detection model is determined by the following steps: I: Inputting the sample timing features of the sample circuit path into the sparse switching network model to perform timing anomaly detection processing, and determining the predicted label of the sample timing features.

[0065] Here, the sample timing features of the sample circuit path are input into the sparse transition network model for timing anomaly detection processing to determine the predicted label of the sample timing features.

[0066] Among them, the process of determining the prediction label is consistent with the process of determining the above-mentioned abnormal timing information, and will not be repeated in this part.

[0067] Here, we traverse all circuits and extract the features of each path as a sample set: including relevant information such as resistance, capacitance, and pins, and obtain the mean, variance, etc. through feature engineering. For each path, if the delay difference exceeds a certain threshold, its label is 1, that is, an outlier. These data are divided into training sets and test sets.

[0068] II: Iteratively train the sparse transformation network model based on the real labels of the sample time series features and the loss values ​​between the predicted labels to determine the time series anomaly detection model.

[0069] Here, the sparse transformation network model is iteratively trained according to the real labels of the sample time series features and the loss values ​​between the predicted labels to determine the time series anomaly detection model.

[0070] In a possible implementation manner, the iterative training of the sparse transformation network model based on the real label of the sample time series feature and the loss value between the predicted label to determine the time series anomaly detection model includes: i: Detect whether the loss value is greater than a preset threshold.

[0071] Here, it is detected whether the loss value is greater than a preset threshold.

[0072] ii: If yes, the network parameters of the sparse transition network model are updated, and the iterative training of the updated sparse transition network model continues; if no, the iterative training of the sparse transition network model is stopped, and the timing anomaly detection model is determined.

[0073] Here, if yes, the network parameters of the sparse transition network model are updated, and the iterative training of the updated sparse transition network model continues; if no, the iterative training of the sparse transition network model is stopped, and the timing anomaly detection model is determined.

[0074] The embodiment of the present application provides a timing anomaly detection method for an integrated circuit, the timing anomaly detection method comprising: traversing the timing information of each circuit path in the target integrated circuit at a preset window interval with a sliding window; performing feature engineering processing on the timing information of each circuit path, extracting the timing features of each circuit path; inputting the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and outputting the abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model. When there are a large number of circuit paths in the integrated circuit, when the timing anomaly detection of the integrated circuit is performed through other network layers such as the sparse transition network layer in the timing anomaly detection model, the accuracy and efficiency of abnormal timing detection can be improved.

[0075] See also Figure 3 , Figure 4 , Figure 3 One of the structural schematic diagrams of a timing anomaly detection device for an integrated circuit provided in an embodiment of the present application; Figure 4 This is a second structural diagram of a timing anomaly detection device for an integrated circuit provided in an embodiment of the present application. Figure 3 As shown in FIG. , the timing anomaly detection device 300 for an integrated circuit includes: A timing information extraction module 310 is used to traverse the timing information of each circuit path in the target integrated circuit at a preset window interval using a sliding window; A feature processing module 320, configured to perform feature engineering processing on the timing information of each circuit path to extract the timing feature of each circuit path; The detection module 330 is used to input the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and output the abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model.

[0076] Furthermore, the detection module 330 is used to perform timing anomaly detection processing for the timing characteristics of each circuit path through the following steps: Inputting the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing, and outputting the attention features; Inputting the attention feature into the normalization processing network layer for processing, and outputting the normalized attention feature; Inputting the normalized attention features into multiple forward feedback sub-network layers of the sparse transformation network layer for forward feedback processing, and outputting target features; The target feature is input into the fully connected network layer for linear processing, and whether the target feature is abnormal time series information is output.

[0077] Furthermore, when the detection module 330 is used to input the timing characteristics of the circuit path into the multi-head self-attention network layer for attention mechanism processing and output the attention characteristics, the detection module 330 is specifically used to: Performing attention mechanism processing on the timing features of the circuit path to determine a query tensor, a key tensor, and a value tensor corresponding to the timing features; Calculating the attention score between the query tensor and the key tensor based on the activation function to determine the probability matrix of the time series feature; The time series feature and the probability matrix are multiplied to output the attention feature.

[0078] Further, the detection module 330 performs feedforward processing in the plurality of feedforward sub-network layers for inputting the normalized attention features into the sparse transformation network layer, and outputting the target features. The detection module 330 is specifically used to: Processing the normalized attention features based on the first linear transformation weight matrix corresponding to each of the forward feedback sub-network layers to obtain a plurality of reference features; Sparse processing is performed based on the weight values ​​of multiple reference features so that the reference feature with the maximum weight value is used as the target feature.

[0079] Furthermore, the detection module 330 determines whether the target feature is abnormal time series information by:

[0080] Among them, if the category of Y is 1, the target feature F is abnormal time series information, and if the category of Y is 0, the target feature F is normal time series information. is the second linear transformation matrix.

[0081] Further, such as Figure 4 As shown, the timing anomaly detection device 300 for integrated circuits includes a model training module 340, and the model training module 340 determines the timing anomaly detection model through the following steps: Inputting the sample timing features of the sample circuit path into the sparse switching network model to perform timing anomaly detection processing, and determining the prediction label of the sample timing features; The sparse transformation network model is iteratively trained based on the real labels of the sample time series features and the loss values ​​between the predicted labels to determine the time series anomaly detection model.

[0082] Further, when the model training module 340 is used to iteratively train the sparse transformation network model based on the real label of the sample time series feature and the loss value between the predicted label to determine the time series anomaly detection model, the model training module 340 is specifically used to: Detecting whether the loss value is greater than a preset threshold; If yes, the network parameters of the sparse transformation network model are updated, and the updated sparse transformation network model is continuously iterated for training; If not, the iterative training of the sparse transformation network model is stopped to determine the time series anomaly detection model.

[0083] The embodiment of the present application provides a timing anomaly detection device for an integrated circuit, the timing anomaly detection device comprising: a timing information extraction module, used to traverse the timing information of each circuit path in the target integrated circuit at a preset window interval with a sliding window; a feature processing module, used to perform feature engineering processing on the timing information of each circuit path, and extract the timing features of each circuit path; a detection module, used to input the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transformation network layer and full connection network layer of the timing anomaly detection model for timing anomaly detection processing, and output the abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training the sparse transformation network model. When there are a large number of circuit paths in the integrated circuit, when the timing anomaly detection of the integrated circuit is performed through other network layers such as the sparse transformation network layer in the timing anomaly detection model, the accuracy and efficiency of abnormal timing detection can be improved.

[0084] See also Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 5 As shown in , the electronic device 500 includes a processor 510 , a memory 520 and a bus 530 .

[0085] The memory 520 stores machine-readable instructions executable by the processor 510. When the electronic device 500 is running, the processor 510 communicates with the memory 520 via the bus 530. When the machine-readable instructions are executed by the processor 510, the above-mentioned Figure 1 as well as Figure 2 The steps of the method for detecting timing anomalies of an integrated circuit in the method embodiment shown in the figure, and the specific implementation manner can be referred to the method embodiment, which will not be described in detail here.

[0086] The present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the computer program can execute the above-mentioned Figure 1 as well as Figure 2 The steps of the method for detecting timing anomalies of an integrated circuit in the method embodiment shown in the figure, and the specific implementation manner can be referred to the method embodiment, which will not be described in detail here.

[0087] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0088] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0089] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0090] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0091] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0092] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A timing anomaly detection method for an integrated circuit, characterized in that: The timing anomaly detection method comprises: Traversing the timing information of each circuit path in the target integrated circuit at a preset window interval by using a sliding window; Performing feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path; The timing features of each circuit path are input into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and the abnormal timing information of the integrated circuit is output; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model.

2. The timing anomaly detection method according to claim 1, characterized in that: For the timing characteristics of each circuit path, timing anomaly detection processing is performed through the following steps: Inputting the timing features of the circuit path into the multi-head self-attention network layer for attention mechanism processing, and outputting the attention features; Inputting the attention feature into the normalization processing network layer for processing, and outputting the normalized attention feature; Inputting the normalized attention features into multiple forward feedback sub-network layers of the sparse transformation network layer for forward feedback processing, and outputting target features; The target feature is input into the fully connected network layer for linear processing, and whether the target feature is abnormal time series information is output.

3. The timing anomaly detection method according to claim 2, characterized in that: The timing features of the circuit path are input into the multi-head self-attention network layer for attention mechanism processing, and the attention features are output, including: Performing attention mechanism processing on the timing features of the circuit path to determine a query tensor, a key tensor, and a value tensor corresponding to the timing features; Calculating the attention score between the query tensor and the key tensor based on the activation function to determine the probability matrix of the time series feature; The time series feature and the probability matrix are multiplied to output the attention feature.

4. The timing anomaly detection method according to claim 2, characterized in that: The step of inputting the normalized attention features into a plurality of feedforward sub-network layers of the sparse transformation network layer for feedforward processing and outputting target features comprises: Processing the normalized attention features based on the first linear transformation weight matrix corresponding to each of the forward feedback sub-network layers to obtain a plurality of reference features; Sparse processing is performed based on the weight values ​​of multiple reference features so that the reference feature with the maximum weight value is used as the target feature.

5. The timing anomaly detection method according to claim 2, characterized in that: Whether the target feature is abnormal time series information is determined in the following manner: Among them, if the category of Y is 1, the target feature F is abnormal time series information, and if the category of Y is 0, the target feature F is normal time series information. is the second linear transformation matrix.

6. The timing anomaly detection method according to claim 1, characterized in that: The time series anomaly detection model is determined by the following steps: Inputting the sample timing features of the sample circuit path into the sparse switching network model to perform timing anomaly detection processing, and determining the prediction label of the sample timing features; The sparse transformation network model is iteratively trained based on the real labels of the sample time series features and the loss values ​​between the predicted labels to determine the time series anomaly detection model.

7. The timing anomaly detection method according to claim 6, characterized in that: The iterative training of the sparse transformation network model based on the real label of the sample time series feature and the loss value between the predicted label to determine the time series anomaly detection model includes: Detecting whether the loss value is greater than a preset threshold; If yes, the network parameters of the sparse transformation network model are updated, and the updated sparse transformation network model is continuously iterated for training; If not, the iterative training of the sparse transformation network model is stopped to determine the time series anomaly detection model.

8. A timing anomaly detection device for an integrated circuit, characterized in that: The timing anomaly detection device comprises: A timing information extraction module, used to traverse the timing information of each circuit path in the target integrated circuit at a preset window interval using a sliding window; A feature processing module, used to perform feature engineering processing on the timing information of each circuit path to extract the timing features of each circuit path; A detection module is used to input the timing features of each circuit path into the multi-head self-attention network layer, normalization processing network layer, sparse transition network layer and fully connected network layer of the timing anomaly detection model for timing anomaly detection processing, and output abnormal timing information of the integrated circuit; wherein the timing anomaly detection model is obtained by iteratively training the sparse transition network model.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and the machine-readable instructions are executed by the processor to execute the steps of the timing anomaly detection method for an integrated circuit as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the timing anomaly detection method for an integrated circuit as claimed in any one of claims 1 to 7 are executed.

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