A hardware Trojan detection and recovery system based on lightweight neural network

Abstract

The present invention discloses a hardware Trojan detection and recovery system based on a lightweight neural network, including a RISC-V processor, a hardware Trojan detection device and a recovery device; the RISC-V processor includes: an instruction fetch unit, a decoding unit, an execution unit, and a general-purpose register group; the instruction fetch unit, the decoding unit and the execution unit constitute a three-stage pipeline architecture; the hardware Trojan detection device is used to record the execution path and timing characteristics of each RISC-V instruction on the RISC-V processor, and based on the timing characteristics, the corresponding execution path is subjected to hardware Trojan detection using a constructed lightweight neural network; the recovery device is used to back up the storage information of the general-purpose register group in real time, and when a hardware Trojan is detected, the RISC-V processor is restored to a normal state. The hardware Trojan detection and recovery system proposed by the present invention has higher reliability and flexibility, faster speed and lower power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer intelligent prevention and control, and in particular relates to a hardware Trojan detection and recovery system based on a lightweight neural network. Background Art

[0002] In today's era of rapid global informatization and digitalization, processor chips, as core components of electronic devices such as computers, have a vital impact on corporate interests and personal privacy protection. With the increasing complexity of chip design and manufacturing, and the increasingly prominent trend of supply chain globalization, the threats and challenges facing chip security are becoming more severe. Various computer systems, embedded systems, processors or coprocessors are widely used in various key fields, including communications, transportation, energy, finance, and medical care. Therefore, any processor vulnerability or malicious tampering may lead to serious consequences. In order to ensure that the functions of processors for various applications can operate normally, hardware security testing is particularly important.

[0003] In an era of globalization and rapid technological development, the fifth-generation reduced instruction set RISC-V, as a completely open source instruction set architecture (ISA), has quickly become a popular choice for chip design and processor development due to its flexibility, efficiency and openness, allowing anyone to freely design and manufacture processor chips and related software based on this architecture. As RISC-V is increasingly integrated into critical systems, including the Internet of Things (IoT), edge computing, artificial intelligence (AI), and consumer electronics, its security is crucial to the reliability of device functions and the overall stability of the system. However, precisely because of its openness, the potential security risks it brings are more obvious. While openness provides designers with a high degree of freedom, it also increases the possibility of hardware Trojans (HT) being inserted during the processor design or production process. Therefore, comprehensive security testing of RISC-V processors has become a technical issue that needs to be solved urgently.

[0004] Whether the hardware Trojan is maliciously designed and implanted by an attacker or caused by the designer's negligence or design defects, it will cause a series of problems when it is triggered under certain conditions. These problems may manifest as a significant decrease in circuit performance, abnormal or changed functions, leakage of key information, and may even cause the entire processor chip to fail completely. In response to the attack on the processor's General Purpose Registers (GPRs), existing hardware Trojan detection methods have proposed some detection mechanisms and architectures. However, there is still a lot of room for optimization in the current technology in terms of hardware Trojan detection speed, information backup efficiency, and rapid recovery of the processor to normal state after an attack. In addition, many existing technologies only focus on the detection of hardware Trojans, and do not provide elimination measures for hardware Trojans or a complete solution for processor function recovery. How to effectively restore processor functions and reduce or eliminate the adverse effects of hardware Trojans is crucial to ensuring the normal operation of RISC-V processors. The introduction of this recovery function is particularly necessary to improve the security and reliability of chips and promote the application of RISC-V processors. Summary of the invention

[0005] In order to solve the above technical problems, the present invention proposes a hardware Trojan detection and recovery system for a computer system with a RISC-V processor as the core, which uses a lightweight neural network to quickly and accurately detect the hardware Trojans in the processor, and quickly restore the function of the RISC-V processor after the hardware Trojan is detected, and quickly eliminate the impact caused by the hardware Trojan. The technical solution proposed by the present invention is suitable for the detection and function recovery of various hardware Trojans that attack the instruction execution path on the RISC-V processor, and is particularly suitable for the rapid detection and recovery of hardware Trojans with low probability of triggering, so as to solve the problems existing in the above-mentioned prior art.

[0006] To achieve the above objectives, the present invention provides a hardware Trojan detection and recovery system based on a lightweight neural network, comprising: a RISC-V processor, a hardware Trojan detection device, and a recovery device.

[0007] The RISC-V processor comprises: an instruction fetch unit, a decoding unit, an execution unit, and a general-purpose register group; the instruction fetch unit, the decoding unit and the execution unit constitute a three-stage pipeline architecture;

[0008] The instruction fetch unit is used to read a RISC-V instruction from the external storage at each time step; the decoding unit is used to sequentially decode the RISC-V instructions read at each time step to obtain control information and data information required to execute the instructions; the execution unit is used to access the general purpose register group according to the control information and data information obtained by decoding;

[0009] The hardware Trojan detection device is used to record the execution path and timing characteristics of each RISC-V instruction on the RISC-V processor, and based on the timing characteristics, use the constructed lightweight neural network to perform hardware Trojan detection on the corresponding execution path;

[0010] The recovery device is used to back up the storage information of the general-purpose register group in real time, and when the hardware Trojan detection device detects a hardware Trojan, flush the stored data on the three-stage pipeline architecture, start the instruction fetch unit to re-fetch instructions, and write the backed-up correct information back to the register in the general-purpose register group where the Trojan information is written, so as to restore the RISC-V processor to a normal state.

[0011] In a preferred implementation, the hardware Trojan detection device includes a coverage information collection unit and a Trojan detection unit.

[0012] The coverage information collection unit is used to collect the path coverage of each RISC-V instruction after it is executed on the RISC-V processor; the Trojan detection unit is used to perform hardware Trojan detection on the corresponding execution path based on the timing characteristics using the constructed lightweight neural network when the path coverage does not reach a preset coverage threshold; when the path coverage reaches the coverage threshold, stop the hardware Trojan detection.

[0013] Furthermore, the hardware Trojan detection device also includes: a path detection unit and a timing feature extraction unit.

[0014] The path detection unit is used to obtain all execution paths of each RISC-V instruction on the RISC-V processor according to the instruction decoding information output by the decoding unit;

[0015] The timing feature extraction unit is used to extract the propagation delays of multiple RISC-V instructions executed within a preset time window on their corresponding critical paths; the critical path is the execution path with the longest propagation delay; the time window includes multiple time steps;

[0016] The timing feature extraction unit is further used to normalize the propagation delays of the critical paths corresponding to the RISC-V instructions executed sequentially in the time window one by one, and generate binary logic values ​​of multiple time steps;

[0017] The timing feature extraction unit is further used to sequentially splice the binary logic values ​​at the multiple time steps according to the instruction execution order to generate the critical path timing feature;

[0018] The Trojan detection unit is used to input the critical path timing characteristics as the timing characteristics into the lightweight neural network for identification, so as to determine whether there is a hardware Trojan in the RISC-V processor.

[0019] Furthermore, the hardware Trojan detection device also includes a path node division unit.

[0020] The path node division unit is used to divide a plurality of path nodes on the critical path of each RISC-V instruction according to the instruction type;

[0021] The timing feature extraction unit is further used to collect the node delay of each RISC-V instruction between every two adjacent path nodes;

[0022] The timing feature extraction unit is further used to normalize each of the node delays to generate binary logic values ​​of multiple path nodes for each RISC-V instruction;

[0023] The timing feature extraction unit is further used to splice the binary logic values ​​of the multiple path nodes according to the instruction propagation direction to obtain the path node timing features of each RISC-V instruction;

[0024] The Trojan detection unit is also used to input the path node timing characteristics of each RISC-V instruction as the timing characteristics into the lightweight neural network for identification, so as to determine whether there is a hardware Trojan on the critical path of each RISC-V instruction.

[0025] Preferably, the lightweight neural network is an unsupervised trained spiking neural network.

[0026] In one achievable manner, the pulse neural network includes: an input layer, a hidden layer and an output layer.

[0027] The input layer includes one or more input terminals, which are used to sequentially access the timing characteristics of each RISC-V instruction when it is executed on the RISC-V processor according to the time step; the hidden layer includes a plurality of spiking neurons; the output layer includes two spiking neurons; the spiking neurons of the hidden layer are fully connected to the spiking neurons of the output layer; the spiking neurons are used to activate and reset according to a preset neuron dynamics model;

[0028] The hidden layer is used to process the timing characteristics through a plurality of the pulse neurons to obtain the circuit operation characteristics of the RISC-V processor;

[0029] The output layer is used to generate and output the probability of the presence of a hardware Trojan and the probability of the absence of a hardware Trojan in the RISC-V processor according to the circuit operation characteristics.

[0030] Preferably, the neuron dynamics model comprises:

[0031] Charging Model: ,

[0032] Discharge model: ,

[0033] Among them, V(t) is the neuron membrane potential at the current time step, V(t-1) is the neuron membrane potential at the previous time step, ΔV i (t) is the membrane potential increment generated by the timing characteristics of the i-th input pulse neuron access at the current time step, is the synaptic weight of the i-th input spike neuron, is the neuron baseline potential; V(t - ) is the membrane potential of the spiking neuron before reset at the current time step; V(t + ) is the reset membrane potential of the spiking neuron at the current time step, V th is the activation threshold of the spiking neuron; is the membrane potential attenuation factor.

[0034] Furthermore, the pulse neural network also includes: an online learning unit.

[0035] The online learning unit is used to update the synaptic weight and activation threshold of the pulse neuron according to the timing characteristics input in real time.

[0036] Preferably, the recovery device comprises: a backup unit and a recovery control unit;

[0037] The backup unit is used to back up the storage information of the general-purpose register group in real time when the three-stage pipeline architecture executes RISC-V instructions to obtain correct backup information;

[0038] The recovery control unit includes a pause logic, a write-back logic, and a restart logic;

[0039] The pause logic is used to pause the operation of the three-stage pipeline architecture and reset all stored data in the three-stage pipeline architecture when a hardware Trojan is detected on any execution path;

[0040] The write-back logic is used to retrieve the corresponding original information from the backed-up correct information according to the execution path where the hardware Trojan is located, and write it back to the register at the corresponding position in the general-purpose register group;

[0041] The restart logic is used to restore the operation of the three-stage pipeline and restart the instruction fetch unit to re-fetch instructions according to the current program count value after the write-back logic is completed.

[0042] Furthermore, the backup unit is also used to record the branch jump history of each RISC-V instruction after it is executed on the RISC-V processor;

[0043] The restart logic is also used to restore the current program count value to the program count value before the jump if the currently input RISC-V instruction is a branch jump instruction.

[0044] Compared with the prior art, the present invention has the following advantages and technical effects:

[0045] The hardware Trojan detection and recovery system based on lightweight neural network proposed by the present invention uses a neural network model to accurately, quickly and intelligently identify hardware Trojan features for the instruction execution path of the RISC-V processor, and can extract potential key features from a large amount of hardware data, avoiding the cumbersome process of manually designing features. In addition, the neural network provided by the present invention has an online learning function, does not require Trojan labels for supervised training, and the network scale is small. It can use a small amount of calculation to capture the circuit operation characteristics of the RISC-V processor on the corresponding execution path during the execution of multiple rounds of RISC-V instructions, while capturing circuit characteristics and starting the training of the neural network model, improving learning ability, and thus higher intelligence and flexibility. Since the present invention is for hardware Trojan detection on the execution path of each input RISC-V instruction, there is no need for complex analysis of the intermediate links, and it can directly output whether there is a hardware Trojan and its possible path position. In addition, the present invention also provides a technical solution for quickly restoring the function of the RISC-V processor when a hardware Trojan is identified, with high speed and low power consumption.

[0046] In summary, the present invention utilizes the powerful learning ability, pattern recognition ability and generalization of the neural network model to achieve fast and accurate hardware Trojan detection of the instruction execution path of the RISC-V processor, and achieves fast functional recovery of the RISC-V processor through a simple recovery device. The present invention can provide a stronger guarantee for chip security detection of various computer systems based on RISC-V processors, and also provides a technical reference for chip security detection of processors of other instruction architecture types. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0048] Figure 1 A structural schematic diagram of a hardware Trojan detection and recovery system based on a lightweight neural network provided by an embodiment of the present invention;

[0049] Figure 2 A schematic diagram of the structure of a hardware Trojan detection device according to an embodiment of the present invention;

[0050] Figure 3 A schematic diagram of a structure of a pulse neural network according to an embodiment of the present invention;

[0051] Figure 4 A structural schematic diagram of a recovery device according to an embodiment of the present invention;

[0052] Figure 5 A flowchart of a RISC-V processor fast recovery method after a hardware Trojan is detected according to an embodiment of the present invention;

[0053] Figure 6 A circuit structure diagram of a recovery device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] It should be noted that, under the premise that no conflict occurs, the embodiments and their representative features mentioned in the present invention application can be flexibly combined. In order to elaborate on the content of this application in detail, the following will be through the drawings and specific embodiments.

[0055] It should be noted that each step in the flowchart shown in the accompanying drawings can be executed by a computer system, and can be completed by a series of computer-executable instructions. In addition, although the flowchart shows the logical execution order of the steps, in some cases, the execution order of these steps may be different from the order shown or described.

[0056] Figure 1 This is a structural diagram of a hardware Trojan detection and recovery system based on a lightweight neural network provided by an embodiment of the present invention. This embodiment proposes a hardware Trojan (HT) detection and recovery system based on a lightweight neural network, including: a RISC-V processor 100, a hardware Trojan detection device 200, and a recovery device 300.

[0057] The RISC-V processor 100 includes: an instruction fetch unit 101, a decoding unit 102, an execution unit 103, and a general-purpose register group 104. The instruction fetch unit 101, the decoding unit 102, and the execution unit 103 constitute a three-stage pipeline architecture. Among them, the instruction fetch unit 101 is used to read a RISC-V instruction from the external storage at each time step; the decoding unit 102 is used to sequentially decode the RISC-V instructions read in each time step to obtain the control information and data information required to execute the instruction; the execution unit 103 is used to access the general-purpose register group 104 according to the control information and the data information obtained by decoding. In specific implementation, the general-purpose register group 104 is composed of a plurality of general-purpose data registers, address registers and other components. In the RISC-V processor 100, the main function of the general-purpose register group 104 is to store the key information required by each RISC-V instruction during the execution process, so as to provide support for the efficient execution of various types of data operations and memory operations.

[0058] The hardware Trojan detection device 200 is used to record the execution path and timing characteristics of each RISC-V instruction on the RISC-V processor 100, and based on the timing characteristics, use the constructed lightweight neural network to perform hardware Trojan detection on the corresponding execution path.

[0059] The recovery device 300 is used to back up the storage information of the general-purpose register group 104 in real time, and when the hardware Trojan detection device 200 detects a hardware Trojan, flush the stored data on the three-stage pipeline architecture, start the instruction fetch unit 101 to re-fetch instructions, and write the backed-up correct information back to the register in the general-purpose register group 104 where the Trojan information is written, so as to restore the RISC-V processor 100 to a normal state.

[0060] In specific implementation, the RISC-V processor 100 refers to a processor designed using the RISC-V instruction set architecture. Different RISC-V processors can support instruction sets and corresponding hardware implementation architectures and functional complexity depending on the designer's ideas or application needs. The RISC-V instruction set can be classified into a basic integer instruction set (such as RV32I / RV64I / RV128I) and an extended instruction set according to function. Among them, the extended instruction set adds some instructions that meet specific application requirements on the basis of the basic integer instruction set. For example, the M instruction set includes multiplication, division, remainder and other instructions, which are added to the basic instruction set to form instruction sets such as RV32IM / RV64IM / RV128IM. The technical solution to be protected by the present invention is applicable to hardware Trojan detection and function recovery of RISC-V processors designed based on all these RISC-V architectures. In the RISC-V instruction set architecture, its instruction types mainly include register type instructions (R type instructions), immediate number instructions (I type instructions), storage instructions (S type instructions), unconditional jump instructions (J type instructions), conditional jump instructions / branch instructions (B type instructions), etc. In addition to the customized extended instructions, the functions and data bit allocations of RISC-V instructions of various instruction types have been standardized in the corresponding RISC-V instruction set architecture, which will not be repeated here. The technical focus of the embodiments of the present invention is how to perform hardware Trojan detection on these common RISC-V processors and perform rapid functional recovery when a hardware Trojan is detected.

[0061] It should be noted that although the RISC-V instruction set architecture has provided standard definitions for various types of instruction formats, the RISC-V instruction set is only an interface standard between hardware circuits and software programs, and the RISC-V processor is a specific hardware circuit system implemented according to this standard. Therefore, based on this RISC-V instruction set architecture, RISC-V processors with completely different hardware circuit structures, different operating effects and efficiencies can be designed.

[0062] In particular, in an embodiment of the present invention, hardware Trojan detection is performed on the RISC-V processor with a three-stage pipeline structure for the three common stages of instruction fetch, decoding and execution in the RISC-V processor, and by restoring the instruction cycle, it is ensured that the processor can be restored to a normal operating state.

[0063] When implementing it, Figure 2 As shown, the hardware Trojan detection device 200 includes a coverage information collection unit 201 and a Trojan detection unit 202 .

[0064] The coverage information collection unit 201 is used to collect the path coverage rate ρ of each RISC-V instruction after it is executed on the RISC-V processor 100; the Trojan detection unit 202 is used to detect the path coverage rate ρ when the path coverage rate ρ does not reach a preset coverage rate threshold ρ th , based on the timing characteristics, the constructed lightweight neural network is used to perform hardware Trojan detection on the corresponding execution path; when the path coverage rate ρ reaches the coverage rate threshold ρ th Stop hardware Trojan detection when .

[0065] In specific implementation, after designing the hardware circuit of the RISC-V processor 100, the coverage information acquisition unit 201 needs to use test cases or test sets to count and analyze the execution of the RTL (Register Transfer Level) code in the design to determine which part of the code in the overall circuit is executed or not executed. Some existing electronic design automation (EDA) tools, such as Mentor's ModelSim tool and Synopsys's Verilog simulator VCS, can provide corresponding coverage test tools. However, they are only tools. How users use these test tools to achieve correct and complete code coverage testing is decisive for the test methods and test cases they adopt.

[0066] The coverage information collection unit 201 needs to ensure that each line of statement in the RTL code is executed at least once. Furthermore, the coverage information collection unit 201 needs to ensure that all possible execution paths involved in all RISC-V instructions compiled and generated in the input program have been executed once, so as to determine and verify all possible execution paths and generate the path coverage rate ρ. After obtaining the path coverage rate ρ of each RISC-V instruction after execution on the RISC-V processor 100, if all the verified paths are tested, it is highly likely that there is no hardware Trojan (HT) on the RISC-V processor 100. Therefore, in order to improve the efficiency of Trojan detection, this embodiment further determines whether the path coverage rate of each instruction after execution on the RISC-V processor 100 reaches the expected coverage rate threshold ρ th , decide whether to do a deeper level of detection. Specifically, if the path coverage rate ρ of the currently input RISC-V instruction reaches the preset coverage rate threshold ρ th , it is considered that there is no hardware Trojan in the RISC-V processor 100, and the hardware Trojan detection is stopped. Otherwise, it means that there may be an untriggered hardware Trojan in the RISC-V processor 100, and it is necessary to continue the detection.

[0067] The hardware Trojan detection and recovery system for RISC-V processors proposed in this embodiment realizes hardware Trojan detection of the processor based on the three-stage pipeline architecture of the RISC-V processor. When a hardware Trojan is found on the execution path of the detection, measures can be taken quickly to restore the normal function of the processor. By using the embodiment proposed by the present invention, the time taken for the processor to recover from an unexpected abnormal state to a normal state can be shortened, and the effect of rapid detection of hardware Trojans in various RISC-V processors can be achieved, and the negative impact of the hardware Trojan can be minimized as much as possible through the recovery device.

[0068] In the specific implementation, the key to hardware Trojan detection is how to reasonably select the detection path. In this embodiment, the detection path is mainly divided into two categories for the type of RISC-V instructions: address execution path and data execution path. The detection of the above two execution paths involves multiple situations such as register address detection, register data detection, load instruction address detection, store instruction address detection, and store instruction data detection. When executing any RISC-V instruction, all associated execution paths are found according to the execution pipeline corresponding to the instruction. It is necessary to select the path and divide the nodes of the address or data path in the internal pipeline architecture of the RISC-V processor 100, so as to quickly and accurately complete the detection task of the hardware Trojan in the processor in a parallel manner. In this embodiment, the selection of the critical path is used as the main target object of Trojan detection. It should be noted that the critical path described in this embodiment is not the same concept as the critical path with the longest delay generated in the combinational logic circuit in the digital circuit, thereby determining the highest operating frequency of the processor. In this embodiment, the critical path is used to represent the longest execution path among all execution paths involved in the step-by-step execution of each pipeline unit in the RISC-V processor when a RISC-V instruction is executed. When executing different instruction types, the same operating principle is followed to complete the corresponding detection path (critical path) selection, node division and result analysis in sequence.

[0069] Furthermore, if Figure 2 As shown, the hardware Trojan detection device 200 also includes: a path detection unit 203 and a timing feature extraction unit 204.

[0070] The path detection unit 203 is used to obtain all execution paths of each RISC-V instruction on the RISC-V processor 100 according to the instruction decoding information output by the decoding unit 102.

[0071] The timing feature extraction unit 204 is used to extract the propagation delays of multiple RISC-V instructions executed within a preset time window on their corresponding critical paths; the critical path is the execution path with the longest propagation delay; the time window includes multiple time steps.

[0072] The timing feature extraction unit 204 is also used to normalize the propagation delays of the critical paths corresponding to the RISC-V instructions executed sequentially within the time window one by one, and generate binary logic values ​​of multiple time steps.

[0073] The timing feature extraction unit 204 is further configured to sequentially concatenate the binary logic values ​​at the multiple time steps according to the instruction execution order to generate a critical path timing feature.

[0074] The Trojan detection unit 202 is used to input the critical path timing characteristics as the timing characteristics into the lightweight neural network for identification, so as to determine whether there is a hardware Trojan in the RISC-V processor 100.

[0075] During specific implementation, for the time window T, it includes multiple time steps t, and each time step inputs a RISC-V instruction to the RISC-V processor 100 for execution. For single-cycle RISC-V instructions executed sequentially, each time step t is 1 clock cycle, but for branch jump instructions and multi-cycle instructions, the time step t> 1 clock cycle. In addition, although the coverage information acquisition unit 201 can detect the code coverage and the path coverage of each instruction, each RISC-V instruction usually involves a large number of execution paths when executed. Although it is feasible to perform hardware Trojans on each related execution path one by one, the workload is large and the efficiency is low. In this embodiment, the critical path of instruction execution is the execution path with the longest propagation time required for the instruction from the input of the RISC-V processor 100 to the output of the RISC-V processor 100. Therefore, the embodiment of the present invention mainly performs Trojan detection on the critical path of each input RISC-V instruction to improve the detection efficiency.

[0076] Assume that there are t RISC-V instructions to be executed in a preset time window T, that is, the time window T is divided into t time steps. When the timing feature extraction unit 204 collects the propagation delays of the t RISC-V instructions executed in the time window T on their respective corresponding critical paths, the data as integer or floating-point values ​​still has a large amount of calculation in the neural network model, and it is necessary to pre-process the input data of the neural network before performing efficient calculations. Specifically, the timing feature extraction unit 204 can use the following method to normalize the propagation delays of each RISC-V instruction executed in the time window T on its respective corresponding critical path: if the propagation delay Tp of the critical path corresponding to a RISC-V instruction is within the first time fluctuation region, a logical value "0" is generated; otherwise, a logical value "1" is generated; wherein the first time fluctuation region is determined according to the instruction type of each input instruction, that is, the first time fluctuation region of each instruction type can be different, and its actual setting can be determined by traversing multiple instructions of the same type and counting their average execution delay ± standard deviation. After the propagation delay is normalized, the timing feature extraction unit 204 will output a "0" or "1" for each RISC-V instruction after execution. Therefore, t time steps of "0" or "1" can be generated within the time window T. The critical path timing features in the form of a pulse sequence are obtained by executing multiple RISC-V instructions.

[0077] From the above critical path timing feature collection process, we can know that a RISC-V instruction can only generate a binary data value, which is not enough to be input into the neural network as a representative feature signal and enable the neural network to accurately determine whether there is a hardware Trojan on its critical path. Although more critical path timing features of RISC-V instructions can be collected by expanding the time window, it will take longer data collection time. Therefore, in order to improve the accuracy of Trojan detection, it is necessary to collect more feature information on the critical path.

[0078] Furthermore, the hardware Trojan detection device 200 also includes a path node division unit 205.

[0079] The path node division unit 205 is used to divide a plurality of path nodes on the critical path of each RISC-V instruction according to the instruction type. In specific implementation, the number and setting position of the path nodes are determined according to the instruction type of the current RISC-V instruction and the function module nodes flowing on the RISC-V processor 100. For example, for an R-type instruction, it must pass through all unit modules of the decoding unit 102, the execution unit 103 and the general purpose register group 104. Therefore, the nodes between these modules should preferably be path nodes, and more path nodes can also be set inside each unit module, for example, the read port and write port of the address and data of the general purpose register group 104.

[0080] The timing feature extraction unit 204 is also used to collect the node delay of each RISC-V instruction between every two adjacent path nodes.

[0081] The timing feature extraction unit 204 is also used to normalize the node delays and generate binary logic values ​​of multiple path nodes for each RISC-V instruction.

[0082] The timing feature extraction unit 204 is also used to splice the binary logic values ​​of the multiple path nodes according to the instruction propagation direction to obtain the path node timing features of each RISC-V instruction.

[0083] The Trojan detection unit 202 is also used to input the path node timing characteristics of each RISC-V instruction as the timing characteristics into the lightweight neural network for identification, so as to determine whether there is a hardware Trojan on the critical path of each RISC-V instruction.

[0084] When the timing feature extraction unit 204 normalizes the node delay, the normalization method adopted is similar to the normalization method of the propagation delay on the critical path mentioned above. Specifically,

[0085] If the delay Tn of each node on a critical path is within the second time fluctuation region, a logical value "0" is generated; otherwise, a logical value "1" is generated; wherein the second time fluctuation region can be determined by multiple tests to determine the empirical value, and the fluctuation range of the delay Tn of each node on the same critical path may not be the same, and it is specifically determined according to the role of each instruction in each functional unit module. Therefore, after adding the acquisition of the path node characteristic signal, the timing characteristics generated by the instruction at each time step are no longer just a binary "0" or "1", but a series of binary pulse sequences. These binary pulse sequences are input into the lightweight neural network as path node features for hardware Trojan detection, which can effectively improve the accuracy of Trojan detection. In addition, by increasing the time step, that is, continuously executing multiple RISC-V instructions one by one in a time window, a richer data source for online learning can be provided for the neural network, and the circuit operation characteristics of the RISC-V processor 100 can be learned, thereby further improving the correct recognition rate of the neural network for hardware Trojans.

[0086] In a preferred implementation, since the input data of the neural network can be processed as data in the form of a binary pulse sequence, the lightweight neural network can use a pulse neural network (SNN) with a simpler network structure than a convolutional neural network (CNN) to realize the recognition of the timing characteristics, thereby determining whether a hardware Trojan exists on the corresponding critical path.

[0087] Preferably, the lightweight neural network is an unsupervised trained pulse neural network. Existing convolutional neural networks usually improve recognition accuracy based on multi-core convolution and increasing the depth of network layers, but the cost is also obvious, that is, the number of participants and the amount of calculation of deep convolutional neural networks are huge, which is very unfriendly to hardware implementation, and ultimately causes the hardware implementation to present negative effects such as slow speed, high resource consumption, and high power consumption. Compared with CNN, the pulse neural network is closer to the biological neural principle, and the computational model of neurons is much less than that of the convolutional neural network, and the CNN model is usually difficult to achieve accurate online learning and training. The present invention uses a pulse neural network that can be learned online and trained without supervision to realize the lightweight neural network.

[0088] like Figure 3As shown, in a preferred implementation, the spiking neural network includes: an input layer, a hidden layer, and an output layer. The input layer includes one or more input terminals, which are used to sequentially access the timing characteristics of each RISC-V instruction when it is executed on the RISC-V processor according to the time step; the hidden layer includes multiple spiking neurons; the output layer includes two spiking neurons; the spiking neurons of the hidden layer are fully connected to the spiking neurons of the output layer; the spiking neurons are used to activate and reset according to a preset neuron dynamics model.

[0089] The hidden layer is used to process the timing features through multiple pulse neurons to obtain the circuit operation features of the RISC-V processor. In specific implementation, the number of hidden layers may not be 1, that is, multiple hidden layers may be formed to improve the extraction and identification of Trojan features. The number of pulse neurons in each hidden layer is not 1, and the characteristics of the timing features accessed by the input layer are learned through multiple pulse neurons.

[0090] The output layer is used to generate and output the probability of the presence of a hardware Trojan and the probability of the absence of a hardware Trojan in the RISC-V processor according to the circuit operation characteristics. The reason why the output layer has only two pulse neurons is that the present invention only needs to use a neural network to determine whether the RISC-V processor 100 has a Trojan, so there are only two types of recognition results (yes or no).

[0091] In specific implementation, when the timing feature extraction unit 204 extracts and transmits the critical path timing feature as the timing feature input to the lightweight neural network for identification, since there is only one normalized value of the total duration for each instruction, the input layer of the pulse neural network used can only set one input terminal, and multiple RISC-V instructions are connected through multiple time steps to generate multiple time steps of critical path timing features (pulse sequences) as the timing features and sent to the pulse neural network for Trojan identification. When the timing feature extraction unit 204 extracts the path node timing features of multiple path nodes of the critical path, it is necessary to set the same number of input terminals for each path node in the input layer of the pulse neural network to synchronously determine whether the node delay between each adjacent node is normal. At this time, the path node timing features of all path nodes on the critical path corresponding to each instruction need to be input in parallel to multiple independent input terminals on the input layer according to the time step. After receiving the pulse signal at each time step, the input terminal of the input layer sends it to each or part of the pulse neurons on the hidden layer for activation processing. When the spiking neural network has only one hidden layer, it is preferred to fully connect the input terminal with the hidden layer spiking neurons, and to fully connect the hidden layer spiking neurons with the output layer spiking neurons, so as to extract richer signal features and thus improve recognition accuracy.

[0092] Preferably, the neuron dynamics model includes a charging model and a discharging model.

[0093] Charging Model: ,

[0094] Discharge model: ,

[0095] Among them, V(t) is the neuron membrane potential at the current time step, V(t-1) is the neuron membrane potential at the previous time step, ΔV i (t) is the membrane potential increment generated by the timing characteristics of the i-th input pulse neuron access at the current time step, is the synaptic weight of the i-th input spike neuron, is the neuron baseline potential; V(t - ) is the membrane potential of the spiking neuron before reset at the current time step; V(t + ) is the reset membrane potential of the spiking neuron at the current time step, V th is the activation threshold of the spiking neuron; is the membrane potential attenuation factor.

[0096] During specific implementation, each spiking neuron calculates its own real-time membrane potential according to a preset neuron charging model and decides whether to fire a pulse to the spiking neurons in the next layer of the network. The neuron charging model adopted in this embodiment is to attenuate the input pulses, and the increment of the membrane potential generated by each input pulse timing signal also participates in the attenuation. Therefore, the change of the overall membrane potential of the spiking neurons provided in this embodiment takes into account both the influence of the input membrane potential increment and the natural decay of the membrane potential relative to the reset potential. The membrane potential decay factor α is a time constant, which can be determined according to the requirements of the neuron model, biological rationality, etc. If the spiking neuron needs to respond quickly to rapidly changing input timing features, a larger decay factor α is selected so that the membrane potential can decay faster; vice versa, spiking neurons related to memory and learning usually have a smaller decay factor. And for the neuron reference potential settings, it is preferably set to be lower than the resting membrane potential E, aiming to make the spiking neuron in the refractory period after excitation, simulate the real behavior of biological neurons, and prevent over-activation. In addition, when the spiking neuron discharges, the spiking neuron provided in this embodiment does not need to reset the membrane potential , but realizes the reset of the membrane potential according to the decay factor α and the activation threshold of the current spiking neuron.

[0097] Furthermore, as Figure 3 shown, the spiking neural network further includes: an online learning unit. The online learning unit is used to update the synaptic weights and activation thresholds of the spiking neurons according to the real-time input timing features.

[0098] In a preferred implementation, the mechanism for the online learning unit to update the synaptic weights and activation thresholds of the spiking neurons is: if the difference between the membrane potential and the activation threshold of the spiking neuron in the previous time step is greater than a preset threshold, then

[0099]

[0100]

[0101] wherein, represents the synaptic weight at the current time step, represents the synaptic weight at the previous time step, represents the neuron activation threshold at the current time step, represents the neuron activation threshold at the previous time step, represents the time difference between the firing of the previous neuron and the next neuron, a and b represent two different synaptic weight update amplitudes, and 0 < a < b; c represents the update amplitude of the neuron activation threshold, and c > 0. Since It only represents the time difference between the release of the pulse of the front and rear neurons, that is, if the rear neuron releases the pulse before the front neuron, then If it is greater than 0, it is considered to be less than 0. Compared with the traditional algorithm, this embodiment no longer needs to store a large amount of historical parameter information, thereby reducing the excessive demand for storage space.

[0102] Otherwise, if the difference between the membrane potential of the spiking neuron in the previous time step and the activation threshold is less than or equal to the preset threshold, the synaptic weight and neuron activation threshold of the spiking neuron in the current time step remain unchanged.

[0103] This embodiment can use the above mechanism to perform online learning and model parameter update on all spiking neurons in the spiking neural network. However, in resource-constrained hardware implementation, such operation will bring about a large amount of calculation and resource consumption. Therefore, the embodiment of the present invention adopts a competitive learning strategy to update only the most active neurons, which can significantly reduce the consumption of computing resources.

[0104] Specifically, Figure 3 As shown, the online learning unit includes a competitive learner, a target arbitrator, a random learner and a parameter updater. Among them, the competitive learner is used to compare and obtain the activation states of different spiking neurons, and select the most active spiking neuron based on the pulse emission rate. The specific operation includes steps S1 to S5:

[0105] Step S1: Perform weighted summation on each pulse signal in the input timing feature and the synaptic weight corresponding to the current pulse neuron to obtain the cumulative membrane potential of the input pulse sequence;

[0106] Step S2: subtracting the accumulated membrane potential from the activation threshold of the current pulse neuron to obtain a cumulative difference;

[0107] Step S3: Assign trigger timings to each pulse signal in the timing feature in sequence; and perform weighted summation on each pulse signal with trigger timing and the synaptic weight corresponding to the current pulse neuron to obtain the timing weighted membrane potential of the timing feature. In particular, the pulse neurons that need to perform cumulative calculations can be further screened before weighted summation. For example, whether each pulse signal with a trigger timing is greater than or equal to 1, if it is greater than or equal to 1, it will be selected as a candidate neuron, and the membrane potential of each candidate neuron and the synaptic weight are weighted summed to obtain the timing weighted membrane potential.

[0108] Step S4: taking the ratio of the time-series weighted membrane potential to the accumulated difference as the normalized pulse emission duration of the current pulse neuron;

[0109] Step S5: Compare the normalized pulse emission durations of all the pulse neurons in the hidden layer one by one, and select the pulse neuron corresponding to the minimum value as the most active physical neuron in the hidden layer; compare the normalized pulse emission durations of all the pulse neurons in the output layer one by one, and select the neuron corresponding to the minimum value as the most active pulse neuron in the output layer.

[0110] The target arbitrator is responsible for receiving the comparison results of the competitive learner, taking into account the membrane potential and synaptic weight of the current spiking neuron, and evaluating its contribution to the overall performance of the network, and finally deciding the spiking neuron that needs to be updated. The more active the neuron, the more likely it is that the synaptic weight will be updated, which is in line with the basic characteristics of biological learning.

[0111] The random learner is used to generate a pseudo-random number based on a linear feedback shift register, and the generated pseudo-random number is used as a preset threshold of the difference between the membrane potential of the spiking neuron in the previous time step and the activation threshold. This embodiment increases the flexibility and versatility of the network by introducing a certain amount of randomness.

[0112] The parameter updater is used for the random online learning strategy based on historical weights, and updates the synaptic weight and activation threshold of the most active physical neuron using the pseudo-random number and the synaptic weight currently stored in the neuron. That is, in the above-mentioned mechanism for updating the synaptic weight and activation threshold of the spiking neuron, parameter updates are no longer performed for all spiking neurons, but only for the most active spiking neuron obtained by arbitration. This method reduces unnecessary computational overhead and improves learning efficiency.

[0113] A simplified online learning method proposed in an embodiment of the present invention realizes the update of the synaptic weights and activation thresholds of one or more of the most active spiking neurons in the hidden layer, reduces the computational complexity, reduces the computational complexity of the weight update stage and reasonably allocates the consumption of hardware resources, and at the same time, improves the accuracy of online training and learning and the reasoning accuracy of the spiking neural network processor based on hardware implementation.

[0114] In this embodiment, the critical path of the input instruction is a detection path, and the detection path is node-divided to generate multiple detection nodes. It should be noted that the number of path nodes of each detection path is not fixed, and depends on the path conditions.

[0115] In an achievable manner, the data of each path node on the critical path can be further compared in pairs, and the judgment dimension of detecting whether a hardware Trojan exists can be increased on the basis of the timing characteristics, thereby improving the accuracy of Trojan detection. Specifically, during the data or address transmission process, the information (data or address) collected by the starting node of each detection path can be used as a detection benchmark. Since the system adopts a pipeline circuit architecture, the information of the front-end node will be transmitted before the back-end node. Therefore, when the information of a node on the path changes due to a hardware Trojan attack, the information transmitted by the subsequent nodes will also become erroneous modified information instead of the original information transmitted by the starting node. This erroneous information will continue to be transmitted on the path until a hardware Trojan attack occurs again, causing the information to be tampered with again. Secondly, the information between each adjacent node on the detection path, as well as the information of the two nodes at the starting point and the end point, are compared in pairs: if the information of the two nodes is the same, the comparison result is represented by a binary number "0", that is, a low level; if there is a difference, it is represented by a binary number "1", that is, a high level. After the comparison is completed, all the comparison results of the detection path need to be spliced. For example, when a detection path has four nodes a, b, c, and d, where a is the starting point and d is the end point, the information represented by the four nodes is data or address. The comparison result of the beginning and end of a and d is "1", and the comparison results of the three adjacent nodes of the four nodes a, b, c, and d are "0", "0", and "1" respectively, then the final splicing result is represented as 4 bits of "1100". Of course, those skilled in the art can also use other splicing methods, as long as it is ensured that in the subsequent detection judgment, specific data bits can be correctly selected for comparison, which will not affect the final hardware Trojan detection result. The above method is effective on the premise that if the hardware Trojan attack is not suffered during the detection process, the data or address information in the default detection path will not change. The above method can increase the judgment dimension of detecting Trojans based on the critical path delay and node delay, which can improve the accuracy of Trojan detection, but it needs to consume certain additional computing resources.

[0116] When a hardware Trojan is detected, the RISC-V processor 100 needs to be quickly functionally restored.

[0117] Furthermore, if Figure 4 FIG. 1 is a schematic diagram of a structure of an embodiment of a recovery device 300 provided by the present invention. Preferably, the recovery device 300 includes: a backup unit 301 and a recovery control unit 302 .

[0118] The backup unit 301 is used to perform real-time backup of the storage information of the general-purpose register group 104 when the three-stage pipeline architecture executes RISC-V instructions to obtain correct backup information.

[0119] The recovery control unit 302 includes a pause logic 3021 , a write-back logic 3022 , and a restart logic 3023 .

[0120] The pause logic 3021 is used to pause the operation of the three-stage pipeline architecture and reset all stored data in the three-stage pipeline architecture when a hardware Trojan is detected on any execution path.

[0121] The write-back logic 3022 is used to retrieve the corresponding original information from the backed-up correct information according to the execution path where the hardware Trojan is located, and write it back to the register at the corresponding position in the general-purpose register group 104.

[0122] The restart logic 3023 is used to restore the operation of the three-stage pipeline and restart the instruction fetch unit 101 to re-fetch instructions according to the current program counter value after the write-back logic 3022 is completed.

[0123] like Figure 5 , which is a flow chart of a method for restoring the program function of a RISC-V processor provided by the present invention. Specifically, the method steps for restoring the program function of a RISC-V processor include:

[0124] Step S51: Pause the pipeline architecture of the RISC-V processor 100;

[0125] Step S52: flushing registers in the pipeline architecture;

[0126] Step S53: the general-purpose register set 104 retrieves the correct information from the backup unit 301 and writes the correct information into the attacked register therein;

[0127] Step S54: resetting the registers at the same address position in the backup unit 301, and stopping the information backup of the general purpose register group 104;

[0128] Step S55: rolling back the address of the instruction fetch unit 101 to the address of the instruction corresponding to the hardware Trojan attack, that is, the address pointed to by the program counter value generated by the program counter (PC), and re-obtaining the instruction attacked by the hardware Trojan;

[0129] Step S56: the decoding unit 102 decodes the retrieved instruction and obtains the correct information in the general purpose register group 104;

[0130] Step S57: the backup unit 301 continues to back up the normal information newly written into the registers in the general-purpose register group 104;

[0131] Step S58: the execution unit 103 re-executes the instruction, so that the processor recovers from the abnormal state to the normal state.

[0132] When the RISC-V processor 100 executes the input RISC-V instruction, the backup unit 301 backs up the information written to the general purpose register group 104 in real time to obtain the corresponding backup information. In the pipeline architecture of the RISC-V processor, one or more execution paths are selected through a certain strategy to perform hardware Trojan detection operations, and the detection results of each detection path are obtained. If a hardware Trojan attack occurs, the information written to the register group may be maliciously tampered with, resulting in error information being stored in the general purpose register 104. If not intervened in time, the impact of the hardware Trojan attack will gradually spread to other units, causing greater harm. Therefore, in order to prevent the error caused by the hardware Trojan attack from continuing to spread, it is first necessary to suspend the pipeline operation of the RISC-V processor, prevent the error information from spreading further, and take recovery measures to ensure that the system function is stable and reliable. Specifically, the backup information is used to restore the original information tampered with by the hardware Trojan, and the required backup information is written back to the corresponding position in the general purpose register group 104. When the data in the general-purpose register group 104 is written back, the instruction fetch unit 101, the decoding unit 102 and the execution unit 103 in the control pipeline architecture execute the instruction fetch, decoding and execution operations in order again, and finally the write-back information in the general-purpose register group 104 enables the RISC-V processor to be restored to a normal working state.

[0133] In special cases, before the RISC-V processor 100 accesses the external device, neither the load instruction nor the store instruction will write information to the general purpose register group 104. Therefore, when an HT attack is detected and a recovery operation is performed, steps S53, S54, S56 and S57 can be omitted, and the processor can execute the instruction normally after step S55. In addition, since the function of the store instruction is to access the external device, when an HT attack occurs that affects the information transmission path of the store instruction, this embodiment will effectively prevent the impact of the HT attack from further spreading to the external device by sending a "stop writing" enable signal to the external device.

[0134] It should be noted that due to the concealment of hardware Trojans, hardware Trojans are usually not triggered immediately when the processor is just started. Therefore, the hardware Trojan detection and recovery technical solution proposed in the present invention is to detect low-probability hardware Trojan triggers. Based on the hardware Trojan detection mechanism of the present invention, the Trojan detection process takes two clock cycles (the specific clock cycle length depends on the circuit structure of different pipeline designs), and the process of restoring the processor function takes three clock cycles. Therefore, the hardware Trojan detection and recovery technical solution provided by the present invention requires at least five clock cycles to complete Trojan detection and processor function recovery. For the RISC-V processor 100 with three-stage pipelines, if the probability of each instruction being executed is 0.5, that is, the probability of triggering a Trojan in each clock cycle is 0.5, if the hardware Trojan trigger frequency is high, it may cause the detection and recovery operations to be executed too late. Therefore, this embodiment is suitable for hardware Trojan detection that requires more than five clock cycles to trigger. In actual applications, a single clock cycle is very short. Hardware Trojans, due to their concealment, often require much longer than five clock cycles and will only be triggered under certain conditions. If they are triggered within five clock cycles, it is equivalent to triggering the hardware Trojan as soon as the processor is powered on. In this case, technicians can easily find that the processor is malfunctioning and will not be put into use. In addition, by inputting instructions at multiple time steps, more reliable hardware delay detection can be obtained, thereby improving the accuracy of hardware Trojan detection.

[0135] In order to back up the information in the general purpose register set 104, this embodiment designs a novel hardware structure of a recovery device for backing up and writing back data to the general purpose register set. Figure 6 FIG. 1 is a schematic diagram of the specific structure of a preferred embodiment of the recovery device provided by the present invention.

[0136] In the RISC-V processor, whenever information is written to the general purpose register group 104, although the register group includes multiple registers (such as 32 32-bit general purpose registers Reg0 to Reg 31 for the RV32I instruction set), this embodiment only quickly backs up the register to which the new information is written by the currently executed instruction. The structure of this backup information can be obtained by Figure 6 The circuit shown is implemented.

[0137] Specifically, when the instruction is executed normally and no hardware Trojan attack is detected, the data written into the general purpose register group 104 is normal, and the backup unit 301 will contain registers Reg_b0~Reg_b31 equal to the number of general purpose register groups 104, so as to back them up one by one, but the backup operation has a delay of one clock cycle relative to the information writing operation. In particular, since the register Reg0 at the 0th position is already occupied in the RISC-V instruction set and no new data will be written, it is also possible not to back up the register Reg0 at the 0th position, but only to back up the 31 other registers Reg1~Reg31, such as Figure 6 shown.

[0138] In specific implementation, the backup operation can be implemented by using a partial circuit of the write-back logic 3022. Specifically, according to the HT flag of the hardware Trojan, the write-back logic 3022 implements data transmission between the backup unit 301 and the general purpose register group 104, thereby realizing the backup or recovery of register data. When the HT attack is not detected, the backup information will not be rewritten back to the general purpose register group 104. Once the hardware Trojan is detected, the signal of the HT flag is high, and the abnormal information is also written into the general purpose register group 104 at the same time, causing the information in the register to be overwritten by the unexpected information. However, through the recovery device 300 provided by the present invention, in the next clock cycle, the general purpose register group 104 will retrieve the correct information before being overwritten from the backup structure through the abnormal register address, thereby restoring the information to the state before the HT attack. At the same time, the backup unit 301 will not back up the general purpose register group 104 in the clock cycle where the Trojan is detected, but reset the corresponding register in the backup unit 301 with a value of "0" to prevent the abnormal information from polluting the backup content. The write-back logic 3022 includes a combinational circuit logic for selectively writing to each register of the general purpose register group 104 and each register in the backup unit 301, which includes multiple multiplexers (MUX) and necessary delay devices, so that the correct data can be selected and written into the registers in the correct order, and at the same time, the HT flag bit is used to control whether the corresponding data in the backup unit 301 needs to be reversely written back to the general purpose register 104. The delay device is mainly used to prevent the wrong data from being written into registers with different addresses for each level of data input from the three-stage pipeline.

[0139] If a hardware Trojan is detected and the instruction fetch unit 101 has completed the rollover of the program counter value (PC), the PC value is restored to the value before the Trojan is triggered or the specified reset value, and the rollover completion flag is sent as a control signal to the write-back logic 3022 to start executing the next step of the restart logic 3023.

[0140] Furthermore, the backup unit 301 is also used to record the branch jump history of each RISC-V instruction after it is executed on the RISC-V processor 100. The restart logic 3023 is also used to restore the current program count value to the program count value before the jump if the currently input RISC-V instruction is a branch jump instruction.

[0141] The branch jump history in the backup unit 301 can be used to overwrite the program counter value prediction value recorded in the decoding unit 102 with the branch jump history by using the restart logic 3023 when the decoding unit 102 fails to predict whether the program counter value of the currently input RISC-V instruction fetches a jump.

[0142] The hardware Trojan detection and recovery scheme proposed in this embodiment can quickly detect the execution path that transmits key information, and the detection range not only covers the general-purpose register group, but also extends to the data path and address path related thereto. The hardware Trojan detection speed in this embodiment is closely related to the instruction type. When a hardware Trojan attack is detected, the processing flow of the entire design shows ideal compactness and parallelism, without showing redundant idle states or invalid information (i.e., "bubbles"). From detecting a pipeline abnormality caused by a hardware Trojan attack to restoring normal operation, for single-cycle instructions, only a maximum of 3 clock cycles are required to complete the functional recovery of the processor; other multi-cycle instructions may require a longer recovery time due to the need to flush the pipeline. Compared with existing similar detection and recovery architectures, this embodiment has significant advantages in recovery speed, and at the same time shows lower energy consumption in power consumption control, showing superior performance.

[0143] The hardware Trojan detection and recovery system of this embodiment has the following three beneficial effects: first, based on the RISC-V processor architecture, an innovative detection mechanism based on pulse neural network is proposed for hardware Trojans with low probability of being triggered, so as to realize fast, accurate and intelligent real-time detection of hardware Trojans; second, after the hardware Trojan is triggered, the RISC-V processor function can be quickly restored to prevent the influence of the hardware Trojan from further spreading to the entire system; finally, when performing Trojan detection and function recovery on the RISC-V processor, the simplest possible hardware circuit is used, and the hardware resources of each functional node are optimized to minimize power consumption.

[0144] This embodiment is based on a RISC-V processor with a three-stage pipeline, and a hardware Trojan detection and recovery system for the RISC-V processor has been implemented using digital circuits. The system was deployed on a ZYNQ7000 series FPGA (programmable gate array) platform for physical verification. The experimental results show that during the verification process, when a hardware Trojan is triggered, this embodiment can promptly detect the erroneous RISC-V instruction and its corresponding instruction address, that is, the corresponding PC value. After detecting that a hardware Trojan attack has occurred, the PC is rolled back, and the current PC value of the instruction fetch unit is restored to the original value corresponding to the erroneous instruction. The RISC-V processor re-executes the instruction in the decoding stage, and then obtains the correct information from the general-purpose register group. As a result, the RISC-V processor can quickly recover to normal operation.

[0145] It should be noted that the above content is only a preferred embodiment of the present application, and does not mean that the protection scope of the present application is limited thereto. Any equivalent changes or alternatives made by any person familiar with the technology in the field within the technical framework disclosed in the present application based on the existing technical knowledge shall all fall within the protection scope of the present application. Therefore, the protection limit of the present application shall be based on the scope defined in the attached claims.

Claims

1. A hardware Trojan detection and recovery system based on lightweight neural network, characterized in that: include: RISC-V processor, hardware Trojan detection device, and,recovery device; The RISC-V processor comprises: an instruction fetch unit, a decoding unit, an execution unit, and a general-purpose register group; the instruction fetch unit, the decoding unit, and the execution unit constitute a three-stage pipeline architecture; The instruction fetch unit is used to read a RISC-V instruction from the external storage at each time step; the decoding unit is used to sequentially decode the RISC-V instructions read at each time step to obtain control information and data information required to execute the instructions; the execution unit is used to access the general purpose register group according to the control information and data information obtained by decoding; The hardware Trojan detection device is used to record the execution path and timing characteristics of each RISC-V instruction on the RISC-V processor, and based on the timing characteristics, use the constructed lightweight neural network to perform hardware Trojan detection on the corresponding execution path; The recovery device is used to back up the storage information of the general-purpose register group in real time, and when the hardware Trojan detection device detects a hardware Trojan, flush the registered data on the three-stage pipeline architecture, start the instruction fetch unit to re-fetch instructions, and write the backed-up correct information back to the register in the general-purpose register group into which the Trojan information is written, so as to restore the RISC-V processor to a normal state; The lightweight neural network is an unsupervised trained spiking neural network; The pulse neural network comprises: an input layer, a hidden layer and an output layer; The input layer includes one or more input terminals, which are used to sequentially access the timing characteristics of each RISC-V instruction when it is executed on the RISC-V processor according to the time step; the hidden layer includes a plurality of spiking neurons; the output layer includes two spiking neurons; the spiking neurons of the hidden layer are fully connected to the spiking neurons of the output layer; the spiking neurons are used to activate and reset according to a preset neuron dynamics model; The hidden layer is used to process the timing characteristics through a plurality of the pulse neurons to obtain circuit operation characteristics of the RISC-V processor; The output layer is used to generate and output the probability of the presence of a hardware Trojan and the probability of the absence of a hardware Trojan in the RISC-V processor according to the circuit operation characteristics.

2. The hardware Trojan detection and recovery system based on lightweight neural network according to claim 1 is characterized in that: The hardware Trojan detection device comprises a coverage information collection unit and a Trojan detection unit; The coverage information collection unit is used to collect the path coverage rate of each RISC-V instruction after being executed on the RISC-V processor; The Trojan detection unit is used to perform hardware Trojan detection on the corresponding execution path based on the timing characteristics using a constructed lightweight neural network when the path coverage does not reach a preset coverage threshold; and stop hardware Trojan detection when the path coverage reaches the coverage threshold.

3. The hardware Trojan detection and recovery system based on lightweight neural network according to claim 2 is characterized in that: The hardware Trojan detection device further includes: a path detection unit and a timing feature extraction unit; The path detection unit is used to obtain all execution paths of each RISC-V instruction on the RISC-V processor according to the instruction decoding information output by the decoding unit; The timing feature extraction unit is used to extract the propagation delays of multiple RISC-V instructions executed within a preset time window on their corresponding critical paths; the critical path is the execution path with the longest propagation delay; the time window includes multiple time steps; The timing feature extraction unit is further used to normalize the propagation delays of the critical paths corresponding to the RISC-V instructions executed sequentially in the time window one by one, and generate binary logic values ​​of multiple time steps; The timing feature extraction unit is further used to sequentially splice the binary logic values ​​at the multiple time steps according to the instruction execution order to generate the critical path timing feature; The Trojan detection unit is used to input the critical path timing characteristics as the timing characteristics into the lightweight neural network for identification, so as to determine whether there is a hardware Trojan in the RISC-V processor.

4. The hardware Trojan detection and recovery system based on lightweight neural network according to claim 3 is characterized in that: The hardware Trojan detection device further includes a path node division unit; The path node division unit is used to divide a plurality of path nodes on the critical path of each RISC-V instruction according to the instruction type; The timing feature extraction unit is further used to collect the node delay of each RISC-V instruction between every two adjacent path nodes; The timing feature extraction unit is further used to normalize each of the node delays to generate binary logic values ​​of multiple path nodes for each RISC-V instruction; The timing feature extraction unit is further used to splice the binary logic values ​​of the multiple path nodes according to the instruction propagation direction to obtain the path node timing features of each RISC-V instruction; The Trojan detection unit is also used to input the path node timing characteristics of each RISC-V instruction as the timing characteristics into the lightweight neural network for identification, so as to determine whether there is a hardware Trojan on the critical path of each RISC-V instruction.

5. The hardware Trojan detection and recovery system based on lightweight neural network according to claim 1 is characterized in that: The neuron dynamics model includes: Charging Model: , Discharge model: , Among them, V(t) is the neuron membrane potential at the current time step, V(t-1) is the neuron membrane potential at the previous time step, ΔV i (t) is the membrane potential increment generated by the timing characteristics of the i-th input pulse neuron access at the current time step, is the synaptic weight of the i-th input spike neuron, is the neuron baseline potential; V(t - ) is the membrane potential of the spiking neuron before reset at the current time step; V(t + ) is the reset membrane potential of the spiking neuron at the current time step, V th is the activation threshold of the spiking neuron; is the membrane potential attenuation factor.

6. The hardware Trojan detection and recovery system based on lightweight neural network according to claim 1, characterized in that: The spiking neural network also includes: an online learning unit; The online learning unit is used to update the synaptic weight and activation threshold of the pulse neuron according to the timing characteristics input in real time.

7. The hardware Trojan detection and recovery system based on lightweight neural network according to claim 1 is characterized in that: The recovery device comprises: a backup unit and a recovery control unit; The backup unit is used to back up the storage information of the general-purpose register group in real time when the three-stage pipeline architecture executes RISC-V instructions to obtain correct backup information; The recovery control unit includes a pause logic, a write-back logic, and a restart logic; The pause logic is used to pause the operation of the three-stage pipeline architecture and reset all stored data in the three-stage pipeline architecture when a hardware Trojan is detected on any execution path; The write-back logic is used to retrieve the corresponding original information from the backed-up correct information according to the execution path where the hardware Trojan is located, and write it back to the register at the corresponding position in the general-purpose register group; The restart logic is used to restore the operation of the three-stage pipeline and restart the instruction fetch unit to re-fetch instructions according to the current program count value after the write-back logic is completed.

8. The lightweight neural network-based hardware Trojan detection and recovery system according to claim 7, characterized in that: The backup unit is further used to record the branch jump history of each RISC-V instruction after it is executed on the RISC-V processor; The restart logic is also used to restore the current program count value to the program count value before the jump if the currently input RISC-V instruction is a branch jump instruction.

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