A RISC-V-based thread warp scheduling method, device and medium

Abstract

The present invention discloses a RISC-V-based thread warp scheduling method, device and medium, which belongs to the technical field of general-purpose graphics processors and is used to solve the technical problem that the existing thread warp scheduling module is easily affected by the synchronization fence mechanism and the thread warp scheduling strategy, which leads to a decrease in thread warp scheduling efficiency and thus affects the execution efficiency of instructions. The method includes: performing instruction configuration on the current thread warp state to obtain a real-time thread warp state instruction; performing state control on the thread warp queue to obtain a state change control strategy; performing instruction fetching sequence control on the thread warp queue to determine the thread warp instruction fetching control strategy; performing address instruction fetching control on the thread warp queue to determine the address type control strategy; and performing thread warp scheduling processing based on the thread warp scheduling system architecture on the thread warp queue through the real-time thread warp state instruction and the thread warp scheduler after the strategy configuration is completed to obtain the thread warp scheduling result.

Description

Technical Field

[0001] The present application relates to the technical field of general-purpose graphics processors, and in particular to a RISC-V-based thread warp scheduling method, device, and medium. Background Art

[0002] In the existing field of general-purpose graphics processor technology, improving instruction execution efficiency by optimizing warp scheduling modules has become a hot direction for improving the computing performance of graphics processors.

[0003] The traditional warp scheduling module is affected by the synchronization fence mechanism and warp scheduling strategy, which leads to a decrease in warp scheduling efficiency, thus affecting the execution efficiency of instructions. At the same time, the RISC-V instruction set architecture (ISA), as an open standard, scalable and flexible open source processor architecture, has attracted much attention in recent years. Its modular design allows developers to customize and optimize according to specific application requirements, which provides a solution for achieving efficient warp scheduling. Therefore, there is an urgent need for a warp scheduling method based on RISC-V to improve the thread scheduling efficiency and the instruction execution efficiency of general-purpose graphics processors. Summary of the invention

[0004] The embodiments of the present application provide a RISC-V-based thread warp scheduling method, device and medium, which are used to solve the following technical problems: the existing thread warp scheduling module is affected by the synchronization fence mechanism and the thread warp scheduling strategy, which easily leads to a decrease in the thread warp scheduling efficiency, thereby affecting the execution efficiency of instructions.

[0005] The present application embodiment adopts the following technical solutions:

[0006] On the one hand, an embodiment of the present application provides a RISC-V-based thread warp scheduling method, comprising: according to the type I instruction format of the RISC-V instruction set and based on the current running requirements of thread scheduling, performing instruction configuration on the current thread warp state to obtain a real-time thread warp state instruction; controlling the state of the thread warp queue through a synchronization fence signal and a thread warp end signal to obtain a state change control strategy for the thread warp scheduler; controlling the instruction fetch order of the thread warp queue through a greedy strategy and priority sorting to determine a thread warp instruction fetch control strategy for the thread warp scheduler; performing address instruction fetch control on the thread warp queue according to an instruction fetch address flag to determine an address type control strategy for the thread warp scheduler; and generating a thread warp scheduler after policy configuration is completed based on the state change control strategy, the thread warp instruction fetch control strategy and the address type control strategy; performing thread warp scheduling processing based on the thread warp scheduling system architecture on the thread warp queue through the real-time thread warp state instruction and the thread warp scheduler after policy configuration is completed to obtain a thread warp scheduling result.

[0007] The embodiment of the present application expands the RISC-V instruction set to include dedicated thread warp synchronization fence instructions and thread warp end instructions, and also designs a thread warp scheduling system architecture and a thread warp scheduling module. This can effectively improve the thread scheduling efficiency, and then improve the instruction execution efficiency of the general graphics processor. At the same time, by optimizing the scheduling strategy, it can reduce the waste of storage resources and improve resource utilization.

[0008] In a feasible implementation manner, according to the type I instruction format of the RISC-V instruction set and based on the current running requirements of thread scheduling, the current thread warp state is configured with instructions to obtain a real-time thread warp state instruction, specifically including: constructing a thread warp state setting table based on an immediate number, a source register address, a thread warp state mode function code, a destination register address and a thread warp state instruction operation code; wherein the thread warp state mode function code includes: turning on a synchronization fence signal and turning off a synchronization fence signal; the thread warp state instruction operation code includes: a thread warp end signal and a thread warp start signal; the immediate number is configured with the current running requirements to obtain an immediate number configuration state; the thread warp state mode function code is configured with the current running requirements to obtain a thread warp state mode function code state; the thread warp state instruction operation code is configured with the current running requirements to obtain a thread warp state instruction operation code state; the current thread warp state is configured with instructions through the immediate number configuration state, the thread warp state mode function code state and the thread warp state instruction operation code state to determine the real-time thread warp state instruction.

[0009] In a feasible implementation manner, the state of the thread warp queue is controlled by the synchronization fence signal and the thread warp end signal to obtain a state change control strategy for the thread warp scheduler, which specifically includes: activating and controlling a number of the thread warp queues, and setting each thread warp to 1; when the thread warp end signal corresponding to the thread warp queue is set to 1, setting the corresponding thread warp to 0 to obtain a first control state; when each thread warp is set to 1, restarting a synchronization fence branch, and judging whether the synchronization fence signal is set to 1; if the synchronization fence signal is set to 1, setting the corresponding thread warp to 0 to obtain a second control state; generating the state change control strategy through the first control state and the second control state.

[0010] In a feasible implementation manner, the thread warp queue is subjected to instruction fetching order control through a greedy strategy and priority sorting, and a thread warp instruction fetching control strategy for the thread warp scheduler is determined, specifically including: according to the thread warp queue controlled by the state change control strategy, and based on the full signal in the instruction buffer module, the thread warp with the rightmost position set to 1 in the thread warp queue is used as the instruction fetching thread warp, and the thread warp ID corresponding to the instruction fetching thread warp is sent to the instruction cache module; if the full signal of the instruction fetching thread warp is continuously set to 1, the instruction fetching instruction is continuously executed under the instruction fetching thread warp to obtain a first instruction fetching order control state; if the full signal of the instruction fetching thread warp is set to 0, the thread warp with the rightmost position set to 1 in the current thread warp queue is used as the current instruction fetching thread warp to obtain a second instruction fetching order control state; based on the first instruction fetching order control state and the second instruction fetching order control state, the thread warp instruction fetching control strategy is obtained.

[0011] In a feasible implementation manner, according to the instruction fetch address flag, the thread warp queue is subjected to address instruction fetch control, and an address type control strategy for the thread warp scheduler is determined, which specifically includes: taking the initial address of the thread warp queue as the first instruction fetch address; judging the type of address fetch of the thread warp queue based on the first instruction fetch address received by the thread warp scheduler and the instruction fetch address flag; when the instruction fetch address flag is 00, according to the feature that each instruction in the RISC-V instruction set occupies 4 bytes, the last instruction fetch address is numerically added to obtain the current instruction fetch address, and a first address control strategy is generated; when the instruction fetch address flag is 10, the current instruction fetch address is determined as a jump address, and a second address control strategy is generated; when the instruction fetch address flag is 01 and / or 11, the current instruction fetch address is determined as an instruction fetch failure address, and a third address control strategy is generated; based on the first address control strategy, the second address control strategy and the third address control strategy, the address type control strategy is combined and obtained.

[0012] In a feasible implementation manner, before obtaining the warp scheduling result by performing warp scheduling processing on the warp queue based on the warp scheduling system architecture through the warp scheduler after the real-time warp state instruction and the policy configuration, the method further includes: connecting the warp scheduler after the policy configuration with an instruction buffer module, and the instruction buffer module is used to send a full signal to the warp scheduler, and obtain the execution warp queue; connecting the warp scheduler with an instruction cache module, and the instruction cache module is used to send an instruction fetch failure address to the warp scheduler, and obtain the instruction fetch line The thread warp scheduler and the transmission module are connected to each other, and the transmission module is used to send the synchronization fence signal, the thread warp end signal and the thread warp ID to the thread warp scheduler; the thread warp scheduler, the instruction buffer module, the instruction cache module, the decoding module and the transmission module are configured with the system architecture to obtain the thread warp scheduling system architecture.

[0013] In a feasible implementation manner, the warp scheduler after the real-time warp state instruction and the policy configuration is completed is used to perform warp scheduling processing based on the warp scheduling system architecture on the warp queue to obtain the warp scheduling result, which specifically includes: receiving the instruction fetch address of the warp queue through the warp scheduler after the policy configuration is completed, and sending the instruction fetch address to the instruction cache module; obtaining instruction information corresponding to the instruction fetch address through the instruction cache module, and sending the instruction information to the decoding module; decoding the instruction information through the decoding module, generating decoding information, and sending the decoding information to the instruction buffer module; caching the decoding information through the instruction buffer module, and sending the decoding information to the transmitting module, and receiving the execution warp queue through the warp scheduler, and sending the decoding information corresponding to the execution warp queue to the transmitting module; completing the warp scheduling processing under the warp scheduling system architecture based on the warp scheduler, the transmitting module, the instruction buffer module and the instruction cache module, and obtaining the warp scheduling result after scheduling is completed.

[0014] In a feasible implementation, after sending the decoding information corresponding to the execution thread warp queue to the transmission module, the method further includes: when the buffer of the thread warp in the instruction buffer module is full, setting the full signal returned to the thread warp scheduler to a low level, and determining the thread warp as a state where instruction fetching cannot continue; through the transmission module, sending the synchronization fence signal from the synchronization fence and the thread warp end of the end instruction to the thread warp scheduler to obtain thread warp change information used to change the current thread warp state.

[0015] In a second aspect, an embodiment of the present application further provides a RISC-V-based thread warp scheduling device, the device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, so that the at least one processor can execute a RISC-V-based thread warp scheduling method described in any of the above embodiments.

[0016] In a third aspect, an embodiment of the present application further provides a non-volatile computer storage medium, which is a non-volatile computer-readable storage medium, and which stores at least one program, each of which includes instructions, which, when executed by a terminal, enable the terminal to execute a RISC-V-based thread warp scheduling method described in any of the above-mentioned embodiments.

[0017] The present application provides a RISC-V-based thread warp scheduling method, device, and medium. Compared with the prior art, the embodiments of the present application have the following beneficial technical effects:

[0018] 1. Flexibility of instruction configuration: By configuring instructions according to the type I instruction format of the RISC-V instruction set and the current running requirements of thread scheduling, it can adapt to different scheduling scenarios and improve the flexibility of the scheduling strategy.

[0019] 2. Efficiency of state control: Using synchronization fence signals and warp end signals to control the state of warp queues can effectively manage the state transition of warps and improve the efficiency of state management.

[0020] 3. Scheduling strategy optimization: By controlling the instruction fetching order of the thread warp queue through greedy strategy and priority sorting, the scheduling order of the thread warp can be optimized and the overall scheduling efficiency can be improved.

[0021] 4. Accuracy of address fetch control: Address fetch control based on the fetch address flag can accurately manage the allocation of address types and reduce the possibility of address errors and conflicts.

[0022] 5. Improvement of overall scheduling performance: Combining the state change control strategy, warp instruction fetch control strategy and address type control strategy, the generated warp scheduler can process warp queues more effectively, thereby improving the performance of the entire warp scheduling system.

[0023] 6. Real-time and responsiveness: The introduction of real-time warp state instructions enables the scheduler to quickly respond to changes in warp state, improving the real-time and responsiveness of the system.

[0024] 7. Adaptability to system architecture: This method can perform scheduling processing under the thread warp scheduling system architecture, has good architecture adaptability, and can work together with other system components.

[0025] 8. Reduce resource consumption: By optimizing the scheduling strategy, the waste of storage resources can be reduced and resource utilization can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0027] Figure 1 A flow chart of a RISC-V based thread warp scheduling method provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of a warp state instruction provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of a thread warp scheduling system architecture provided in an embodiment of the present application;

[0030] Figure 4 A partial functional logic flow chart of a warp scheduler provided in an embodiment of the present application;

[0031] Figure 5 A logic flow chart of obtaining address value of a warp scheduler provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of the structure of a RISC-V based thread warp scheduling device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0034] The embodiment of the present application provides a thread warp scheduling method based on RISC-V, such as Figure 1 As shown, the thread warp scheduling method based on RISC-V specifically includes steps S101-S105:

[0035] S101. According to the type I instruction format of the RISC-V instruction set and based on the current running requirements of the thread scheduling, the current thread warp state is configured with instructions to obtain a real-time thread warp state instruction.

[0036] Specifically, it is necessary to first construct a warp state setting table using an immediate value, a source register address, a warp state mode function code, a destination register address, and a warp state instruction opcode. The warp state mode function code includes: a start synchronization fence signal and a stop synchronization fence signal. The warp state instruction opcode includes: a warp end signal and a warp start signal.

[0037] Furthermore, the immediate number is configured according to the current operation requirement to obtain the configuration state of the immediate number.

[0038] Furthermore, the current operation requirement configuration is performed on the warp state mode function code to obtain the warp state mode function code state.

[0039] Furthermore, the warp state instruction operation code is configured according to the current running requirement to obtain the warp state instruction operation code state.

[0040] Furthermore, the current warp state is instruction-configured through the immediate value configuration state, the warp state mode function code state and the warp state instruction operation code state, and the real-time warp state instruction is determined.

[0041] In one implementation, Figure 2 A schematic diagram of a warp state instruction provided in an embodiment of the present application is shown in FIG. Figure 2As shown, the I-type instruction format based on the RISC-V instruction set, in which the opcode stores the thread bundle state instruction operation code, which is used to identify and activate the thread bundle state setting function. Funct3 is used to indicate the thread bundle state mode. The function code can be set to 001 to indicate the synchronization fence state and 010 to indicate the thread bundle end state. Imm (immediate number) [11:0] carries the control information of the thread bundle state mode. For example, when imm[0] in the synchronization fence state is set to 1, it indicates that the thread bundle is in the synchronization fence state. When it is set to 0, it indicates that the thread bundle is out of the synchronization fence state. The imm[11:0] setting of the thread bundle end state has the same meaning.

[0042] As a feasible implementation method, a thread bundle state instruction is configured based on the type I instruction format of the RISC-V instruction set. The instruction contains parameters such as the state instruction opcode and state mode function code involved in the thread bundle state instruction, and can directly specify the state of the thread bundle as required. Specifically, the instruction is set according to the current operating requirements, and directly sets the state of the current thread bundle, thereby effectively reducing unnecessary steps and intermediate data storage, and improving the flexibility and response speed of the system for thread bundle management. It directly optimizes the core link of the thread bundle scheduling module and significantly improves the execution efficiency of thread bundle scheduling.

[0043] S102 , controlling the state of the warp queue by means of the synchronization barrier signal and the warp end signal, and obtaining a state change control strategy for the warp scheduler.

[0044] Specifically, it is also necessary to activate and control several warp queues, and set each warp to 1. When the warp end signal corresponding to the warp queue is set to 1, the corresponding warp is set to 0 to obtain the first control state. When each warp is set to 1, a synchronization fence branch is restarted, and the synchronization fence signal is set to 1. If the synchronization fence signal is set to 1, the corresponding warp is set to 0 to obtain the second control state.

[0045] Furthermore, a state change control strategy is generated through the first control state and the second control state.

[0046] In one embodiment, Figure 4 A partial functional logic flow chart of a warp scheduler provided in an embodiment of the present application is as follows: Figure 4As shown, in order to achieve the state change of the thread warp, the thread warp queues w1, w2, w3, and w4 are first activated and set to 1. When the input thread warp end signal is 1, the corresponding thread warp is set to 0. In addition, a synchronization fence branch is restarted. When the synchronization fence signal is 1, the corresponding thread warp is set to 0, and then the thread warp queue is sent to the instruction buffer module. By combining the input synchronization fence signal and the thread warp end signal, the state of the thread warp can be changed at any time. Finally, combined with the above control state, the state change control strategy of the thread warp scheduler is generated.

[0047] S103 , controlling the instruction fetching sequence of the warp queues through a greedy strategy and priority sorting, and determining a warp instruction fetching control strategy for the warp scheduler.

[0048] Specifically, after the state change control strategy is applied to the thread warp queue, based on the full signal in the instruction buffer module, the thread warp with the rightmost thread warp set to 1 in the thread warp queue is used as the instruction fetch thread warp, and the thread warp ID corresponding to the instruction fetch thread warp is sent to the instruction cache module.

[0049] Further, if the full signal of the instruction fetch warp is continuously set to 1, the instruction fetch instruction is continuously executed under the instruction fetch warp to obtain the first instruction fetch order control state. If the full signal of the instruction fetch warp is set to 0, the rightmost warp set to 1 in the current warp queue is used as the current instruction fetch warp to obtain the second instruction fetch order control state.

[0050] Furthermore, based on the first instruction fetch order control state and the second instruction fetch order control state, a warp instruction fetch control strategy is obtained.

[0051] In one embodiment, Figure 4 As shown, a method combining greedy strategy and priority sorting is adopted to determine the next thread bundle that needs to fetch instructions. The specific implementation process is as follows: the thread bundle queue after the thread bundle end signal processing in the previous process is sent to the priority sorting module after the full signal from the instruction buffer module. According to the principle of taking 1 from right to left, the thread bundle with the rightmost state of 1 in the thread bundle queue is taken as the instruction fetch thread bundle, and the thread bundle ID corresponding to the instruction fetch thread bundle is sent to the instruction cache module. When the full signal of the selected thread bundle as the instruction fetch thread bundle is always 1, the instructions are always executed under the thread bundle, which is the implementation of the greedy strategy; if the full signal of the thread bundle is 0, the thread bundle with the rightmost state of 1 in the thread queue at this moment is taken as the instruction fetch thread bundle, and then combined with the above control strategy, the thread bundle instruction fetch control strategy is obtained.

[0052] S104 . Performing address instruction fetch control on the warp queue according to the instruction fetch address flag, and determining an address type control strategy for the warp scheduler.

[0053] Specifically, the initial address of the thread warp queue needs to be used as the first instruction fetch address. Then, the thread warp scheduler receives the first instruction fetch address and determines the type of address fetch of the thread warp queue based on the instruction fetch address flag:

[0054] When the instruction fetch address flag is 00, according to the characteristic that each instruction in the RISC-V instruction set occupies 4 bytes, the last instruction fetch address is numerically added to obtain the current instruction fetch address, and a first address control strategy is generated. When the instruction fetch address flag is 10, the current instruction fetch address is determined as a jump address, and a second address control strategy is generated. When the instruction fetch address flag is 01 and / or 11, the current instruction fetch address is determined as an instruction fetch failure address, and a third address control strategy is generated.

[0055] Furthermore, based on the first address control strategy, the second address control strategy and the third address control strategy, an address type control strategy is combined and obtained.

[0056] In one embodiment, Figure 5 A logical flow chart of obtaining a value address of a warp scheduler provided in an embodiment of the present application is as follows: Figure 5 As shown in the figure, the thread warp scheduler needs to use the sent initial address, jump address, and instruction fetch failure address to obtain the instruction fetch address. First, the initial address is used as the first instruction fetch address, and then the instruction fetch address for each time is determined according to the instruction fetch address flag. When the instruction fetch address flag is 00, according to the characteristic that each instruction in the RISC-V indicator set occupies 4 bytes, the current instruction fetch address is the previous address plus 4 and then sent to the instruction cache module; when the instruction fetch address flag is 10, the instruction fetch address at this time is the jump address; when the instruction fetch address flag is 01 and 11, the instruction fetch address is the instruction fetch failure address, and the classification control of the collective address type is combined to obtain the address type control strategy.

[0057] Furthermore, the above-mentioned state change control strategy, thread warp instruction fetch control strategy and address type control strategy are combined to finally generate a thread warp scheduler after the policy configuration is completed. The thread warp scheduler after the policy configuration is completed includes the following functions: state change control strategy, which can realize the activeness of the thread warp, the rapid switching of the synchronization fence and the end state of the thread warp, so as to efficiently realize the scheduling of the thread warp. The thread warp instruction fetch control strategy, which adopts a method combining greedy strategy and priority sorting to quickly determine the next thread warp that needs to fetch instructions. The address type control strategy, combined with the instruction fetch address flag, quickly determines the instruction fetch address from the jump address and the value fetch failure address, which can reduce the instruction fetch cycle and improve the efficiency of instruction fetch.

[0058] S105 , using the real-time warp state instruction and the warp scheduler after the policy configuration is completed, performing warp scheduling processing on the warp queue based on the warp scheduling system architecture to obtain a warp scheduling result.

[0059] Specifically, Figure 3 A schematic diagram of a thread warp scheduling system architecture provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the warp scheduler and the instruction buffer module after the policy configuration are completed can be connected to each other, and the instruction buffer module is used to send a full signal to the warp scheduler and obtain the execution warp queue.

[0060] Preferably, the warp scheduler and the instruction cache module may be interconnected, and the instruction cache module is used to send an instruction fetch failure address to the warp scheduler, and obtain an instruction fetch warp ID and an instruction fetch address.

[0061] Preferably, the decoding module can also be interconnected with the instruction buffer module and the instruction cache module respectively, and the decoding module user obtains the instruction information of the instruction cache module and sends the decoding information to the instruction buffer module.

[0062] Preferably, the warp scheduler and the emission module may be connected to each other, and the emission module is used to send the synchronization fence signal, the warp end signal and the warp ID to the warp scheduler.

[0063] Furthermore, the warp scheduler, the instruction buffer module, the instruction cache module, the decoding module and the transmitting module are configured as a system architecture to obtain a warp scheduling system architecture.

[0064] Furthermore, after the policy configuration is completed, the thread warp scheduler receives the instruction fetch address of the thread warp queue and sends the instruction fetch address to the instruction cache module. Then, the instruction cache module obtains the instruction information corresponding to the instruction fetch address and sends the instruction information to the decoding module. Then, the decoding module decodes the instruction information, generates decoding information, and sends the decoding information to the instruction buffer module. The decoding information is cached by the instruction buffer module and sent to the transmitting module. At the same time, the thread warp scheduler can also receive the execution thread warp queue and send the decoding information corresponding to the execution thread warp queue to the transmitting module.

[0065] As a feasible implementation, when the buffer of the thread warp in the instruction buffer module is full, the full signal returned to the thread warp scheduler is set to a low level, and the thread warp is determined to be in a state where instruction fetching cannot continue. Through the emission module, the synchronization fence signal from the synchronization fence and the thread warp end of the end instruction are both sent to the thread warp scheduler to obtain the thread warp change information used to change the current thread warp state.

[0066] In one embodiment, Figure 3 As shown, the thread warp scheduler first receives the thread warp queue to be scheduled and the initial address of the value. After the thread warp scheduler obtains the value address, it sends it to the instruction cache module for instruction acquisition; then the instruction cache module sends the instruction to the decoding module for decoding; then the decoded information is sent to the instruction buffer module for caching. The instruction buffer module also receives the execution thread warp queue scheduled from the thread warp scheduler, and sends the decoding information under the thread warp queue to the emission module. At the same time, the instruction buffer module can set the instruction buffer depth corresponding to each thread warp. When the buffer of the thread warp is full, the full signal returned to the thread warp scheduler is immediately set to a low level, indicating that the thread warp cannot continue to fetch instructions, thereby realizing the rapid switching of the instruction fetching thread warp. Hello, colleagues, the emission module sends the synchronization fence signal from the synchronization fence and the thread warp end of the end instruction to the thread warp scheduler, so that the thread warp scheduler can quickly change the state of the thread warp, so as to reduce the impact of the synchronization fence mechanism.

[0067] Furthermore, based on the warp scheduler, the emission module, the instruction buffer module and the instruction cache module, the warp scheduling process under the warp scheduling system architecture is completed, and the warp scheduling result after the scheduling is completed is obtained. The architecture integrates the instruction cache module, the decoding module, the instruction buffer module and the instruction emission module to work together to achieve efficient warp scheduling. This architecture can directly send the instruction fetch address to the instruction cache module, thereby eliminating the complex design of the traditional instruction fetch module and accelerating the instruction acquisition process. At the same time, it can also work with the instruction buffer module to quickly switch the state of the executable warp queue.

[0068] In addition, the embodiment of the present application also provides a RISC-V based thread warp scheduling device, such as Figure 6 As shown, the RISC-V-based thread warp scheduling device 600 specifically includes:

[0069] At least one processor 601. And a memory 602 in communication with the at least one processor 601. The memory 602 stores instructions that can be executed by the at least one processor 601, so that the at least one processor 601 can execute:

[0070] According to the type I instruction format of the RISC-V instruction set and based on the current running requirements of the thread scheduling, the current thread warp state is configured with instructions to obtain a real-time thread warp state instruction;

[0071] By synchronizing the fence signal and the warp end signal, the warp queue is controlled in state, and a state change control strategy for the warp scheduler is obtained;

[0072] Through the greedy strategy and priority sorting, the thread warp queue is controlled to fetch instructions in order, and the thread warp fetch control strategy for the thread warp scheduler is determined;

[0073] According to the instruction fetch address flag, the thread warp queue is controlled to perform address fetching, and the address type control strategy for the thread warp scheduler is determined; and based on the state change control strategy, the thread warp instruction fetching control strategy and the address type control strategy, the thread warp scheduler after the policy configuration is completed is generated;

[0074] Through the real-time warp state instruction and the warp scheduler after the policy configuration is completed, the warp queue is processed by warp scheduling based on the warp scheduling system architecture to obtain the warp scheduling result.

[0075] The embodiment of the present application expands the RISC-V instruction set to include dedicated thread warp synchronization fence instructions and thread warp end instructions, and also designs a thread warp scheduling system architecture and a thread warp scheduling module. This can effectively improve the thread scheduling efficiency, and then improve the instruction execution efficiency of the general graphics processor. At the same time, by optimizing the scheduling strategy, it can reduce the waste of storage resources and improve resource utilization.

[0076] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0077] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0078] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0079] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0080] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0082] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0083] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0084] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0085] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0086] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the specification of the present application.

Claims

1. A thread warp scheduling method based on RISC-V, characterized in that: The method comprises: According to the type I instruction format of the RISC-V instruction set and based on the current running requirements of the thread scheduling, the current thread warp state is configured with instructions to obtain a real-time thread warp state instruction; By synchronizing the fence signal and the warp end signal, the warp queue is controlled in state, and a state change control strategy for the warp scheduler is obtained; By using a greedy strategy and priority sorting, the thread warp queue is controlled in an instruction fetching order, and a thread warp instruction fetching control strategy for the thread warp scheduler is determined; According to the instruction fetch address flag, the thread warp queue is subjected to address instruction fetch control to determine the address type control strategy for the thread warp scheduler; and based on the state change control strategy, the thread warp instruction fetch control strategy and the address type control strategy, a thread warp scheduler after the strategy configuration is completed is generated; The warp scheduler after the real-time warp state instruction and the policy configuration is completed performs warp scheduling processing on the warp queue based on the warp scheduling system architecture to obtain the warp scheduling result.

2. The RISC-V based thread warp scheduling method according to claim 1, characterized in that: According to the type I instruction format of the RISC-V instruction set and based on the current running requirements of the thread scheduling, the current thread warp state is configured with instructions to obtain the real-time thread warp state instructions, which specifically include: Based on the immediate value, the source register address, the warp state mode function code, the destination register address and the warp state instruction operation code, a warp state setting table is constructed; wherein the warp state mode function code includes: turning on the synchronization fence signal and turning off the synchronization fence signal; the warp state instruction operation code includes: the warp end signal and the warp start signal; Performing current operation requirement configuration on the immediate number to obtain the configuration state of the immediate number; Performing current operation requirement configuration on the warp state mode function code to obtain the warp state mode function code state; Performing current operation requirement configuration on the warp state instruction operation code to obtain the warp state instruction operation code state; The current warp state is instruction configured according to the immediate value configuration state, the warp state mode function code state and the warp state instruction operation code state, and the real-time warp state instruction is determined.

3. The RISC-V based thread warp scheduling method according to claim 1, characterized in that: Through the synchronization fence signal and the warp end signal, the state of the warp queue is controlled to obtain the state change control strategy for the warp scheduler, which specifically includes: Activate and control the plurality of thread warp queues, and set each thread warp to 1 for processing; When the warp end signal corresponding to the warp queue is set to 1, the corresponding warp is set to 0 to obtain a first control state; When each thread warp is set to 1 for processing, a synchronization barrier branch is restarted, and the synchronization barrier signal is set to 1 for judgment; If the synchronization fence signal is set to 1, the corresponding thread warp is set to 0 to obtain a second control state; The state change control strategy is generated through the first control state and the second control state.

4. The RISC-V based thread warp scheduling method according to claim 1, characterized in that: The thread warp queue is controlled in instruction fetching order by using a greedy strategy and priority sorting, and a thread warp instruction fetching control strategy for the thread warp scheduler is determined, specifically including: According to the thread warp queue controlled by the state change control strategy and based on the full signal in the instruction cache module, the thread warp with the rightmost thread warp set to 1 in the thread warp queue is used as an instruction fetch thread warp, and the thread warp ID corresponding to the instruction fetch thread warp is sent to the instruction cache module; If the full signal of the instruction fetch warp is continuously kept set to 1, the instruction fetch instruction is continuously executed in the instruction fetch warp to obtain a first instruction fetch sequence control state; If the full signal of the instruction fetch warp is set to 0, the rightmost warp in the current warp queue is set to 1 as the current instruction fetch warp to obtain a second instruction fetch order control state; The warp instruction fetch control strategy is obtained based on the first instruction fetch order control state and the second instruction fetch order control state.

5. The RISC-V based thread warp scheduling method according to claim 1, characterized in that: According to the instruction fetch address flag, address instruction fetch control is performed on the thread warp queue to determine an address type control strategy for the thread warp scheduler, specifically including: Using the initial address of the thread warp queue as the first instruction fetch address; Determining the type of address fetching of the thread warp queue based on the first instruction fetching address received by the thread warp scheduler and the instruction fetching address flag; When the instruction fetch address flag is 00, according to the feature that each instruction in the RISC-V instruction set occupies 4 bytes, the last instruction fetch address is numerically added to obtain the current instruction fetch address, and a first address control strategy is generated; When the instruction fetch address flag is 10, the current instruction fetch address is determined as the jump address, and a second address control strategy is generated; When the instruction fetch address flag is 01 and / or 11, the current instruction fetch address is determined as an instruction fetch failure address, and a third address control strategy is generated; The address type control policy is combined and obtained based on the first address control policy, the second address control policy and the third address control policy.

6. The RISC-V based thread warp scheduling method according to claim 1, characterized in that: Before the warp scheduler after the real-time warp state instruction and the policy configuration are completed performs warp scheduling processing on the warp queue based on the warp scheduling system architecture to obtain the warp scheduling result, the method further includes: The warp scheduler after the policy configuration is completed is connected to the instruction buffer module, and the instruction buffer module is used to send a full signal to the warp scheduler and obtain the execution warp queue; The thread warp scheduler and the instruction cache module are connected to each other, and the instruction cache module is used to send an instruction fetch failure address to the thread warp scheduler, and obtain an instruction fetch thread warp ID and an instruction fetch address; The decoding module is connected to the instruction buffer module and the instruction cache module respectively, and the decoding module user obtains the instruction information of the instruction cache module and sends the decoding information to the instruction buffer module; The warp scheduler and the transmitting module are connected to each other, and the transmitting module is used to send the synchronization fence signal, the warp end signal and the warp ID to the warp scheduler; The warp scheduler, the instruction buffer module, the instruction cache module, the decoding module and the transmitting module are configured with a system architecture to obtain the warp scheduling system architecture.

7. The RISC-V based thread warp scheduling method according to claim 6, characterized in that: Through the real-time warp state instruction and the warp scheduler after the policy configuration is completed, the warp queue is subjected to warp scheduling processing based on the warp scheduling system architecture to obtain the warp scheduling result, which specifically includes: Receiving the instruction fetch address of the thread warp queue through the thread warp scheduler after the policy configuration is completed, and sending the instruction fetch address to the instruction cache module; Acquire instruction information corresponding to the instruction fetch address through the instruction cache module, and send the instruction information to the decoding module; The instruction information is decoded by the decoding module to generate decoding information, and the decoding information is sent to the instruction buffer module; The instruction buffer module caches the decoded information and sends the decoded information to the transmitting module, and the warp scheduler receives the executing warp queue and sends the decoded information corresponding to the executing warp queue to the transmitting module; Based on the warp scheduler, the emission module, the instruction buffer module and the instruction cache module, warp scheduling processing under the warp scheduling system architecture is completed to obtain the warp scheduling result after the scheduling is completed.

8. The RISC-V based thread warp scheduling method according to claim 7, characterized in that: After sending the decoding information corresponding to the execution warp queue to the transmitting module, the method further includes: When the buffer of the thread warp in the instruction buffer module is full, the full signal returned to the thread warp scheduler is set to a low level, and the thread warp is determined to be in a state where instruction fetching cannot continue; The transmission module sends the synchronization barrier signal from the synchronization barrier and the warp end of the end instruction to the warp scheduler to obtain warp change information for changing the current warp state.

9. A thread warp scheduling device based on RISC-V, characterized in that: The device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, so that the at least one processor can execute a RISC-V-based thread warp scheduling method according to any one of claims 1-8.

10. A non-volatile computer storage medium, characterized in that: The storage medium is a non-volatile computer-readable storage medium, and the non-volatile computer-readable storage medium stores at least one program, each of which includes instructions, and when the instructions are executed by a terminal, the terminal executes a RISC-V-based thread warp scheduling method according to any one of claims 1-8.

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