Gate driving circuit and electroluminescent display device including the same

Abstract

The invention relates to a gate driving circuit and an electroluminescent display device including the same. The electroluminescent display device includes a display panel including a display area including a plurality of pixel lines and a non-display area including a gate driving circuit supplying a gate signal to the plurality of pixel lines, and each of the plurality of pixel lines including a plurality of pixels, each of the plurality of pixels includes a pixel driving circuit and a light emitting device, each of the pixel driving circuit and the gate driving circuit is implemented using a p-type transistor and an n-type transistor, and the gate driving circuit supplies a gate signal to the n-type transistor of the pixel driving circuit, so that a stable output can be provided, and the light emitting device can emit light. And the non-display area of the display panel can be reduced.

Description

[0001] This application is a divisional application of the Chinese patent application filed on September 2, 2021, with application number 202111027786.2 and invention name “Gate drive circuit and electroluminescent display device including a gate drive circuit”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of Korean Patent Application No. 10-2020-0162580 filed in the Korean Intellectual Property Office on November 27, 2020, and Korean Patent Application No. 10-2021-0078582 filed in the Korean Intellectual Property Office on June 17, 2021, the entire contents of which are incorporated herein by reference as if fully set forth herein. Technical Field

[0004] The present disclosure relates to a gate driving circuit having enhanced driving performance and an electroluminescent display device including the gate driving circuit. Background Art

[0005] As information technology advances, the market for display devices that serve as a connection medium between users and information continues to grow. As a result, the use of various types of display devices such as electroluminescent display devices, liquid crystal display devices, organic light emitting display devices, and quantum dot display devices has increased.

[0006] Among various types of display devices, electroluminescent display devices have fast response time, high emission efficiency and wide viewing angle. Generally, in an electroluminescent display device, a data voltage is applied to the gate of a driving transistor by using a transistor turned on based on a scan signal, and the data voltage supplied to the driving transistor is charged into a storage capacitor. In addition, the light-emitting device emits light by outputting the data voltage charged into the storage capacitor based on an emission control signal. The light-emitting device may include an organic light-emitting device, an inorganic light-emitting device and a quantum dot device.

[0007] The gate signal and the data signal are provided to the electroluminescent display device, and the gate signal includes a scan signal and an emission signal. The electroluminescent display device is driven by using the emission signal and one or more scan signals. Generally, the gate drive circuit for generating the scan signal may include a shift register for sequentially outputting the gate signal.

[0008] The display panel, which is the smallest device for displaying an image, may include a pixel array arranged therein, and may be divided into a display area for displaying an image and a non-display area for not displaying an image. The gate drive circuit is attached to the display panel in a chip on film (COF) type or a chip on glass (COG) type, or is implemented as a gate in panel (GIP) type, which is formed by a combination of thin film transistors (TFTs) in a border area as a non-display area of ​​the display panel. The GIP type gate drive circuit includes a plurality of stages based on the number of gate lines, and each of the plurality of stages outputs a gate pulse to be provided to a gate line corresponding thereto. The gate line transmits the gate signal to the pixel array arranged in the display area, thereby enabling the light-emitting device to emit light.

[0009] Therefore, it is necessary to develop a method for improving the driving performance and reliability of a gate driving circuit so as to transmit accurate signals to a pixel array. Summary of the invention

[0010] As described above, the electroluminescent display device includes a pixel array and a gate driving circuit for providing one or more emission signals and scanning signals to the pixel array.

[0011] Each of the plurality of pixels included in the pixel array includes a light emitting device and a pixel driving circuit for providing a driving current to the light emitting device. The pixel driving circuit can be implemented in various types for providing an accurate current to the light emitting device. A method for reducing the leakage current of a transistor by using an n-type transistor is studied so that the pixel driving circuit has reliability. Therefore, a gate driving circuit for stably providing a single gate to an n-type transistor is needed.

[0012] In order to overcome the above-mentioned problems of the related art, the present disclosure may provide a gate driving circuit for outputting a gate signal to be provided to an n-type transistor and an electroluminescent display device including the gate driving circuit.

[0013] The present disclosure may provide a gate driving circuit for reducing a non-display area of ​​a display panel and an electroluminescent display device including the gate driving circuit.

[0014] The present disclosure can provide a gate driving circuit for maintaining a stable output even based on low-frequency driving, and an electroluminescent display device including the gate driving circuit.

[0015] To achieve these and other advantages, and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, the gate drive circuit includes: a pull-down unit controlled by the Q node to transmit a low-level voltage to the output node; a pull-up unit controlled by the QB node to transmit a high-level voltage of the third clock signal to the output node; a Q node controller controlled by the first clock signal to transmit a start signal to the Q node; a QB node controller controlled by the Q node to transmit a high-level voltage to the QB node; and a Q node holding unit controlled by the Q node and the fourth clock signal, the Q node holding unit including a second capacitor connected to the Q node. In addition, the QB node controller includes an n-type transistor and a p-type transistor connected to the Q node. Therefore, a stable output can be provided in a low-frequency-based drive.

[0016] In another aspect of the present disclosure, an electroluminescent display device includes: a display panel including a display area and a non-display area, the display area including a plurality of pixel lines, the non-display area including a gate drive circuit that supplies a gate signal to the plurality of pixel lines. In addition, each of the plurality of pixel lines includes a plurality of pixels, each of the plurality of pixels includes a pixel drive circuit and a light-emitting device, each of the pixel drive circuit and the gate drive circuit is implemented using a p-type transistor and an n-type transistor, and the gate drive circuit supplies a gate signal to the n-type transistor of the pixel drive circuit. Therefore, a stable output can be provided, and the non-display area of ​​the display panel can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the present disclosure and are included in and constitute a part of the present disclosure. The accompanying drawings illustrate aspects of the present disclosure and together with the description are used to explain the principles of the present disclosure. In the accompanying drawings:

[0018] Figure 1 is a block diagram of an electroluminescent display device according to aspects of the present disclosure;

[0019] Figure 2 is a block diagram of a gate drive circuit according to the first aspect of the present disclosure;

[0020] Figure 3 is a circuit diagram of a gate drive circuit according to the first aspect of the present disclosure;

[0021] Figure 4 is a waveform diagram of a gate signal input to a gate drive circuit according to the first aspect of the present disclosure;

[0022] Figure 5 is a block diagram of a gate drive circuit according to the second aspect of the present disclosure;

[0023] Figure 6 is a circuit diagram of a gate drive circuit according to the second aspect of the present disclosure;

[0024] Figure 7 is a waveform diagram of a gate signal input to a gate drive circuit according to the second aspect of the present disclosure;

[0025] Figure 8 is a circuit diagram of a gate drive circuit according to a third aspect of the present disclosure; and

[0026] Fig. 9 is a waveform diagram of a gate signal input to a gate driving circuit according to the third aspect of the present disclosure. DETAILED DESCRIPTION

[0027] The following aspects described with reference to the accompanying drawings will illustrate the advantages and features of the present disclosure and their implementation methods. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the aspects set forth herein. On the contrary, these aspects are provided to make the present disclosure comprehensive and complete, and these embodiments will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0028] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings used to describe various aspects of the present disclosure are exemplary only, and the present disclosure is not limited thereto. The same reference numerals refer to the same elements throughout the text. Throughout this specification, the same elements are represented by the same reference numerals. As used herein, the terms "including", "having", "comprising", etc. imply that other parts can be added, unless the term "only" is used. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "a kind of", and "the" are also intended to include plural forms.

[0029] Elements in the various aspects of the present disclosure are interpreted as including a range of errors even if not explicitly stated.

[0030] When describing a positional relationship, for example, when the positional relationship between two components is described as "on," "over," "under," and "near," unless "just" or "directly" is used, one or more other parts may be disposed between the two components.

[0031] When describing a time relationship, for example, when a time sequence is described as “after,” “subsequently,” “near,” and “before,” discontinuous cases may be included unless “just” or “directly” is used.

[0032] The features of various aspects of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate with each other in various ways and be driven technically as those skilled in the art can fully understand. The aspects of the present disclosure may be performed independently of each other, or may be performed together in a common dependency relationship.

[0033] In the specification, the gate drive circuit provided on the substrate of the display panel can be implemented with an n-type or p-type transistor. For example, the transistor can be implemented as a transistor having a metal oxide semiconductor field effect transistor (MOSFET) structure. The transistor can be a three-electrode element including a gate electrode, a source electrode and a drain electrode. The source electrode can transfer carriers to the transistor. In the transistor, the carriers can move from the source electrode. The drain electrode can be an electrode that enables the carriers to move to the outside of the transistor. The source electrode and the drain electrode of the transistor may not be fixed, but can be switched between them based on the voltage applied thereto.

[0034] Hereinafter, the gate-on voltage may be a voltage of a gate signal for turning on a transistor, and the gate-off voltage may be a voltage for turning off a transistor.

[0035] Hereinafter, a gate driving circuit and an electroluminescent display device including the gate driving circuit according to aspects of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a block diagram of an electroluminescent display device 100 according to aspects of the present disclosure.

[0037] Reference Figure 1 According to aspects of the present disclosure, an electroluminescent display device 100 may include a display panel 110, in which a plurality of data lines DL and a plurality of gate lines GL are provided, a plurality of sub-pixels PX connected to the plurality of data lines DL and the plurality of gate lines GL are arranged, and a driving circuit for providing a driving signal to the display panel 110.

[0038] Figure 1 It is shown that the plurality of sub-pixels PX are arranged in a matrix type to configure a pixel array, but the plurality of sub-pixels are not limited thereto and may be arranged in various types.

[0039] The driving circuit may include a data driving circuit 120 that provides data signals to the plurality of data lines DL, a gate driving circuit GD that provides gate signals to the plurality of gate lines GL, and a controller 130 that controls the data driving circuit 120 and the gate driving circuit GD.

[0040] The display panel 110 may include a display area DA displaying an image and a non-display area NDA as an outer area of ​​the display area DA. A plurality of sub-pixels PX may be disposed in the display area DA. Data lines DL for transmitting data signals to the plurality of sub-pixels PX and gate lines GL for transmitting gate signals to the plurality of sub-pixels PX may be disposed in the display area DA.

[0041] A plurality of data lines DL disposed in the display area DA may extend to the non-display area NDA and may be electrically connected to the data driving circuit 120. The data line DL may electrically connect the sub-pixel PX to the data driving circuit 120 and may be implemented as a single line or may be implemented by connecting a plurality of lines through contact holes using link lines.

[0042] A plurality of gate lines GL disposed in the display area DA may extend to the non-display area NDA and may be electrically connected to the gate drive circuit GD. The gate lines GL may electrically connect the sub-pixels PX to the gate drive circuit GD. Additionally, a plurality of gate drive-related lines required for the gate drive circuit GD to generate or drive gate signals may be disposed in the non-display area NDA. For example, the gate drive-related lines may include one or more high-level gate voltage lines for transmitting a high-level gate voltage to the gate drive circuit GD, one or more low-level gate voltage lines for transmitting a low-level gate voltage to the gate drive circuit GD, a plurality of clock lines for transmitting a plurality of clock signals to the gate drive circuit GD, and one or more start lines for transmitting one or more start signals to the gate drive circuit GD.

[0043] In the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may be provided in the subpixel PX. For example, the plurality of data lines DL and the plurality of gate lines GL may be arranged in rows or columns, and for ease of description, it may be assumed that the plurality of data lines DL are arranged in columns, and the plurality of gate lines GL are arranged in rows.

[0044] The controller 130 may start performing scanning based on the timing achieved in each frame, and may convert input video data received from the outside to generate and output image data based on the data signal format applied to the data driving circuit 120. In addition, the controller 130 may control data driving based on scanning.

[0045] The controller 130 may receive input video data and timing signals from the outside, including a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a clock signal. The controller 130 having received the timing signal may generate and output a control signal for controlling the data driving circuit 120 and the gate driving circuit GD.

[0046] For example, the controller 130 may output various data control signals including a source start pulse, a source sampling clock, and a source output enable signal for controlling the data driving circuit 120. The source start pulse may control the data sampling start timing of one or more data signal generating circuits configuring the data driving circuit 120. The source sampling clock may be a clock signal for controlling the sampling timing of data of each of the one or more data signal generating circuits. The source output enable signal may control the output timing of the data driving circuit 120.

[0047] In addition, the controller 130 may output a gate control signal including a gate start pulse, a gate shift clock, and a gate output enable signal for controlling the gate drive circuit GD. The gate start pulse may control the operation start timing of one or more gate signal generating circuits configuring the gate drive circuit GD. The gate shift clock may be a clock signal commonly input to one or more gate signal generating circuits, and may control the shift timing of the scan signal (or gate pulse). The gate output enable signal may indicate timing information about one or more gate signal generating circuits.

[0048] The controller 130 may be a timing controller used in a general display device technology, or may be a control apparatus that includes a timing controller and also performs another control function.

[0049] The controller 130 may be implemented as a separate element independently of the data driving circuit 120 , or may be integrated with the data driving circuit 120 , and thus may be implemented as one integrated circuit.

[0050] The data driving circuit 120 may be implemented to include one or more data signal generating circuits. The data signal generating circuit may include a shift register, a latch circuit, a digital-to-analog converter, and an output buffer. Depending on the situation, the data signal generating circuit may also include an analog-to-digital converter.

[0051] The data signal generating circuit may be connected to a bonding pad of the display panel 110 in a tape automated bonding (TAB) type, a chip on glass (COG) type, or a chip on panel (COP) type, or may be directly provided in the display panel 110, or may be integrated into and provided in the display panel 110. In addition, a plurality of data signal generating circuits may be implemented as a chip on film (COF) type mounted on a source circuit film connected to the display panel 110.

[0052] The gate driving circuit GD may sequentially supply a scan signal to the plurality of gate lines GL and thus may drive the sub-pixels PX connected to the plurality of gate lines GL. The gate driving circuit GD may include a shift register and a level shifter.

[0053] The gate driving circuit GD may be connected to a bonding pad of the display panel 110 in a TAB type, a COG type, or a COP type, or may be implemented as a GIP type, or may be integrated into and disposed in the display panel 110. In addition, a plurality of gate signal generating circuits may be implemented as a COF type mounted on a gate circuit film connected to the display panel 110. Hereinafter, for ease of description, an example will be described in which the gate driving circuit GD includes a plurality of gate signal generating circuits and the plurality of gate signal generating circuits are implemented as a GIP type and disposed in the non-display area NDA.

[0054] The gate driving circuit GD may sequentially supply a scan signal having a transistor-on voltage or a transistor-off voltage to the plurality of gate lines GL based on the control of the controller 130. When a specific gate line is enabled by the gate driving circuit GD, the data driving circuit 120 may convert image data received from the controller 130 into an analog data signal, and may supply the analog data signal to the plurality of data lines DL, respectively.

[0055] The data driving circuit 120 may be disposed at one side of the display panel 110. For example, the data driving circuit 120 may be disposed at the upper side, the lower side, the left side, or the right side of the display panel 110. In addition, the data driving circuit 120 may be disposed at both sides of the display panel 110 based on a driving method or a panel design method. For example, the data driving circuit 120 may be disposed at the upper side and the lower side, or the left side and the right side of the display panel 110.

[0056] The gate driving circuit GD may be disposed at one side of the display panel 110. For example, the gate driving circuit GD may be disposed at the upper side, the lower side, the left side, or the right side of the display panel 110. In addition, the gate driving circuit GD may be disposed at both sides of the display panel 110 based on a driving method or a panel design method. For example, the gate driving circuit GD may be disposed at the upper side and the lower side, or the left side and the right side of the display panel 110.

[0057] Hereinafter, an example will be described in which the data driving circuit 120 is disposed at the upper side of the display panel 110 and the gate driving circuit GD is disposed at the left and right sides of the display panel 110. In this case, the width W of the area occupied by the gate driving circuit GD in the display panel 110 may be referred to as a bezel. In addition, as the bezel is reduced, the aesthetic effect of the electroluminescent display device 100 may be enhanced, and thus the gate driving circuit GD may need to be simplified to reduce the bezel.

[0058] The plurality of gate lines GL provided in the display panel 110 may include a plurality of scan lines and a plurality of emission control lines. The plurality of scan lines and the plurality of emission control lines may be lines that transmit different kinds of gate signals to gate nodes of different transistors.

[0059] Therefore, the gate driving circuit GD may include: a plurality of scan driving circuits which output scan signals to a plurality of scan lines corresponding to one gate line GL; and a plurality of emission driving circuits which output emission control signals to a plurality of emission control lines corresponding to another gate line GL.

[0060] Figure 2 is a block diagram of a gate drive circuit GD according to the first aspect of the present disclosure. Figure 2 A gate driving circuit GD according to aspects of the present disclosure and a pixel line PG to which a signal output from the gate driving circuit GD is applied are shown.

[0061] The display area DA may include a plurality of sub-pixels PX, and may display an image based on the grayscale displayed by each of the sub-pixels PX. As described above, for example, each of the plurality of sub-pixels PX may be connected to a data line DL arranged along a column line, and may be connected to a gate line GL arranged along a row line (or pixel line). In this case, the sub-pixels PX arranged in the same row line may be referred to as a pixel line PG, and the sub-pixels PX arranged in the same pixel line may share the same gate line GL, and may be provided with gate signals at the same time. Therefore, the sub-pixel PX connected to the first gate line may be referred to as the first pixel line PG(1), and the sub-pixel PX connected to the nth gate line may be referred to as the nth pixel line PG(n). When the number of pixel lines arranged in the display area DA is p, the first pixel line to the pth pixel line may be sequentially driven in synchronization with the gate signal generating circuit.

[0062] As described above, the display panel 110 may include a display area DA that displays an image based on the sub-pixels PX and a non-display area NDA in which signal lines, a driver, etc. are disposed and no image is displayed.

[0063] Each of the sub-pixels PX may include a light emitting device and a pixel driving circuit that controls the amount of current applied to the light emitting device. The pixel driving circuit may include a driving transistor that controls the amount of current so that a specific current flows in the light emitting device. The light emitting device may emit light in an emission period and may not emit light in a period other than the emission period. In a period other than the emission period, the pixel driving circuit may be initialized, a scan signal may be input to the pixel driving circuit, and a programming period and a pixel driving circuit compensation period may be performed. For example, the pixel driving circuit compensation operation may be an operation to compensate for the threshold voltage of the driving transistor. In a period other than the emission period, a current that enables the light emitting device to emit light with a specific brightness may be provided to be non-constant, and therefore the light emitting device should not emit light. For example, a method of making the light emitting device non-emitting may connect an emission transistor to the anode of the light emitting device and the driving transistor. The emission transistor may be connected to an emission line and may be controlled by an emission signal output from an emission driver. In the emission period, the emission signal may be an on voltage, and in a period other than the emission period, the emission signal may be an off voltage.

[0064] The gate signal for driving the subpixel PX included in the display panel 110 may include a scan signal and an emission signal. Therefore, the gate driving circuit GD may include a driver for applying a scan signal and a driver for applying an emission signal, respectively. The scan signal may be applied to the pixel line PG through the scan line, and the emission signal may be applied to the pixel line PG through the emission line.

[0065] exist Figure 2 In the gate drive circuit GD, only the driver for applying the scanning signal is shown. When the number of pixel lines included in the display area DA is p, the gate drive circuit GD according to aspects of the present disclosure may include a first gate signal generating circuit SGD(1) to a pth gate signal generating circuit SGD(p). Figure 2 In FIG. 1 , only the nth to (n+3)th gate signal generating circuits SGD(n) to SGD(n+3) are shown. In this case, both p and n may be natural numbers, and 1≤n≤p.

[0066] The gate driving circuit GD may include a plurality of lines for transmitting a first clock signal GCLK1, a second clock signal GCLK2, a low level voltage VGL, a high level voltage VGH, a first start signal Vst1, and a second start signal Vst2. For example, the low level voltage VGL may be about -4.5V to about -6.5V, and the high level voltage VGH may be about 12V to about 13V. The nth gate signal generating circuit SGD(n) may provide a scanning signal to the nth pixel line PG(n) while shifting the first start signal Vst1 based on the first clock signal GCLK1.

[0067] The first start signal Vst1 may be input to the first gate signal generating circuit SGD(1), and the second start signal Vst2 may be input to the second gate signal generating circuit SGD(2). Each of the third gate signal generating circuit SGD(3) to the pth gate signal generating circuit SGD(p) may operate based on a scan signal output by a previous gate generating circuit and received as a start signal. Specifically, the nth output signal Vgout(n) of the nth gate signal generating circuit SGD(n) may be output as a start signal of the (n+2)th gate signal generating circuit SGD(n+2), and may be input to the nth pixel line PG(n).

[0068] Each of the first clock signal GCLK1 and the second clock signal GCLK2 may swing between a high level voltage and a low level voltage and may have the same period. The first clock signal GCLK1 and the second clock signal GCLK2 may have different phases. Specifically, the second clock signal GCLK2 may be a signal obtained by shifting the phase of the first clock signal GCLK1 by 180 degrees.

[0069] exist Figure 2 , it is shown that the first clock signal GCLK1 is input to the nth gate signal generating circuit SGD(n) and the (n+2)th gate signal generating circuit SGD(n+2), and the second clock signal GCLK2 is input to the (n+1)th gate signal generating circuit SGD(n+1) and the (n+3)th gate signal generating circuit SGD(n+3). That is, Figure 2 It is shown that the first clock signal GCLK1 is input to an odd number of gate signal generating circuits included in the gate driving circuit GD according to the first aspect of the present disclosure, and the second clock signal GCLK2 is input to an even number of gate signal generating circuits included in the gate driving circuit GD according to the first aspect of the present disclosure. The first clock signal GCLK1 and the second clock signal GCLK2 may be sequentially and alternately connected to a plurality of gate signal generating circuits, but the order thereof is not limited thereto.

[0070] Figure 3 is a circuit diagram of a gate signal generating circuit according to the first aspect of the present disclosure. Figure 3 is a diagram describing an example of an n-th gate signal generating circuit SGD(n) configuring the gate driving circuit GD.

[0071] Reference Figure 3 , the nth gate signal generating circuit SGD(n) may include a pull-down unit PD, a pull-up unit PU, a Q-node controller CQ, and a QB-node controller CQB.

[0072] The pull-down unit PD may output the nth output signal Vgout(n) as an off voltage in response to the voltage of the Q node, and the pull-up unit PU may output the nth output signal Vgout(n) as an on voltage in response to the voltage of the QB node. The nth output signal Vgout(n) determined by the pull-down unit PD and the pull-up unit PU may be applied to the nth pixel line PG(n).

[0073] The Q node controller CQ may be an element for charging or discharging the Q node, and may apply an on voltage or an off voltage to the Q node based on the first start signal Vst1. When n is a natural number of 3 or greater, the nth gate signal generating circuit SGD(n) may use the (n-2)th output signal Vgout(n-2) of the (n-2)th gate signal generating circuit SGD(n-2) as a start signal.

[0074] The QB node controller CQB may be an element for charging or discharging the QB node, and may apply an on voltage or an off voltage to the QB node based on a voltage of the Q node applied by the Q node controller CQ.

[0075] The turn-off voltage may vary based on the type of transistor to which the turn-off voltage is applied. In a p-type transistor, the turn-off voltage may be a high level voltage, while in an n-type transistor, the turn-off voltage may be a low voltage. In addition, in a p-type transistor, the turn-on voltage may be a low level voltage, while in an n-type transistor, the turn-on voltage may be a high level voltage. The nth gate signal generating circuit SGD(n) according to aspects of the present disclosure may include all transistors in an n-type transistor and a p-type transistor. The nth output signal Vgout(n) of the nth gate signal generating circuit SGD(n) may be provided to a pixel driving circuit included in an nth pixel line PG(n). In particular, when a pixel driving circuit is implemented using an n-type transistor and a p-type transistor, the nth output signal Vgout(n) may control the turning on and off of the n-type transistor, but is not limited thereto.

[0076] The detailed circuit structure and operation of the nth gate signal generating circuit SGD(n) will be described in detail below.

[0077] Figure 4 is a waveform diagram of a gate signal input to a gate signal generating circuit according to the first aspect of the present disclosure.

[0078] Reference Figure 3 and Figure 4 , each of the first start signal Vst1 and the second start signal Vst2 has a high level pulse for four horizontal periods 4H, and the second start signal Vst2 is a signal shifted by two horizontal periods 2H from the first start signal Vst1. Each of the first clock signal GCLK1 and the second clock signal GCLK2 has a period of four horizontal periods 4H. Each of the first clock signal GCLK1 and the second clock signal GCLK2 has a low level pulse corresponding to a period shorter than two horizontal periods 2H and a high level pulse corresponding to a period longer than two horizontal periods 2H. Therefore, each of the first clock signal GCLK1 and the second clock signal GCLK2 has a low level pulse shorter than half a period and a high level pulse longer than half a period. For example, when the time point when the low level voltage of the first start signal Vst1 shifts to the high level voltage overlaps with the low level pulse of the first clock signal GCLK1, the problem of not generating an output signal may occur. In order to solve this problem, the length of the low level pulse of the first clock signal GCLK1 can be shorter than the length of its high level pulse. Similar to the first clock signal GCLK1 , the length of a low level pulse of the second clock signal GCLK2 may be shorter than the length of a high level pulse thereof.

[0079] The high level pulse of the first start signal Vst1 applied to the nth gate signal generating circuit SGD(n) overlaps the high level pulse and the low level pulse of the first clock signal GCLK1 .

[0080] First, a first period 1 of the first clock signal GCLK1 that starts before a high-level pulse of the second start signal Vst2 is input to the n-th gate signal generating circuit SGD(n) will be described.

[0081] The Q node controller CQ can be implemented using a first transistor T1 and a second transistor T2. The first transistor T1 and the second transistor T2 can be connected in series to each other, and can both be implemented as p-type transistors. The first transistor T1 can be controlled by the first clock signal GCLK1, and can provide the first start signal Vst1 to the second transistor T2. In addition, the second transistor T2 can be controlled by a low level voltage VGL, and can provide the first start signal Vst1 transmitted from the first transistor T1 to the Q node. The second transistor T2 can always remain in a conductive state based on the low level voltage VGL. The second transistor T2 can be connected between the Q node and the first transistor T1, and can buffer the voltage of the Q node. The first period 1 of the first clock signal GCLK1 can start with a low level voltage of the first clock signal GCLK1, and the first start signal Vst1 can have a low level voltage. Therefore, the Q node controller CQ can provide a low level voltage to the Q node.

[0082] In the low level pulse period of the first clock signal GCLK1, the first start signal Vst1 provided to the Q node may have a low level voltage, and the low level voltage may be provided to the pull-down unit PD. The pull-down unit PD may be implemented using the seventh transistor T7 and the first capacitor Cq1. The seventh transistor T7 may be implemented as a p-type transistor. The seventh transistor T7 may be controlled by the Q node and may output a low level voltage VGL. The first capacitor Cq1 may be connected to the gate node of the seventh transistor T7 and the output node VO outputting the nth output signal Vgout(n). The first capacitor Cq1 may bootstrap the voltage of the Q node to cause it to drop, and thus may enable the nth output signal Vgout(n) to maintain the low level voltage VGL, and may maintain the low level voltage of the Q node after outputting the low level voltage VGL of the nth output signal Vgout(n).

[0083] The Q node can control the QB node controller CQB. The QB node controller CQB can be implemented using a third transistor T3 and a fourth transistor T4. The third transistor T3 and the fourth transistor T4 can be connected in series to each other and can all be controlled by the Q node. The third transistor T3 can be implemented as an n-type transistor, and the fourth transistor T4 can be implemented as a p-type transistor, and therefore in the same period, the off / on state of the third transistor T3 can be opposite to the off / on state of the fourth transistor T4. Therefore, the third transistor T3 can be turned off by the low level voltage of the Q node, and the fourth transistor T4 can be turned on by the low level voltage of the Q node. The high level voltage VGH can be provided to the QB node by the turned-on fourth transistor T4. Since the third transistor T3 is implemented as an n-type transistor, the connection of the circuit can be simplified, and therefore the width W of the gate drive circuit GD can be reduced. In addition, the active layer of the n-type transistor may include an oxide, and therefore the threshold voltage margin of the third transistor T3 can be ensured, and the voltage provided to the third transistor T3 can be normally transmitted to the third transistor T3.

[0084] During the low level pulse period of the first clock signal GCLK1, the high level voltage VGH provided to the QB node may be provided to the pull-up unit PU. The pull-up unit PU may be implemented using the eighth transistor T8. In addition, the eighth transistor T8 may be implemented as a p-type transistor. The eighth transistor T8 may be controlled and turned off by the QB node.

[0085] Subsequently, during a first period 1 of the first clock signal GCLK1, the first clock signal GCLK1 may shift from a low level voltage to a high level voltage, and the first start signal Vst1 may shift from a low level voltage to a high level voltage. The first clock signal GCLK1 having a high level voltage may turn off the first transistor T1.

[0086] The second transistor T2 can be connected between the first transistor T1 and the Q node, and the first transistor T1 can be turned off, and thus the Q node can float but cannot be greatly shaken. In addition, the voltage of the Q node and the nth output signal Vgout(n) can be maintained as a low level voltage VGL by the first capacitor Cq1.

[0087] Therefore, during the first period 1 of the first clock signal GCLK1 , the output signal Vgout(n) of the nth gate signal generating circuit SGD(n) may be the low level voltage VGL.

[0088] Next, the second period 2 of the first clock signal GCLK1 will be described. The second period 2 of the first clock signal GCLK1 may start based on a low level voltage, and the first start signal Vst1 may be in a state corresponding to a high level voltage.

[0089] The first transistor T1 may be controlled by the first clock signal GCLK1 and may provide the first start signal Vst1 to the second transistor T2. In addition, the second transistor T2 may be controlled by the low level voltage VGL and may provide the first start signal Vst1 transmitted from the first transistor T1 to the Q node. That is, the Q node controller CQ may provide a high level voltage to the Q node.

[0090] In the low level pulse period of the first clock signal GCLK1 , the first start signal Vst1 supplied to the Q node may be a high level voltage, and the high level voltage may be supplied to the pull-down unit PD. Therefore, the seventh transistor T7 may be controlled and turned off by the Q node.

[0091] In addition, the Q node can be controlled by the QB node controller CQB, and therefore, the third transistor T3 can be turned on by the high level voltage of the Q node, and the fourth transistor T4 can be turned off by the high level voltage of the Q node. The turned-on third transistor T3 can provide a low level voltage VGL to the QB node.

[0092] During the low level pulse period of the first clock signal GCLK1 , the low level voltage VGL supplied to the QB node may be supplied to the pull-up unit PU. The eighth transistor T8 may be turned on by the QB node and may output the high level voltage VGH to the output node VO.

[0093] Subsequently, during the second period 2 of the first clock signal GCLK1, the first clock signal GCLK1 may shift from a low level voltage to a high level voltage, and the first start signal Vst1 may shift from a high level voltage to a low level voltage. There may be a slight difference between the moment when the low level voltage of the first clock signal GCLK1 shifts to a high level voltage and the moment when the high level voltage of the first start signal Vst1 shifts to a low level voltage. The first clock signal GCLK1 having a high level voltage may turn off the first transistor T1. The Q node may maintain a high level voltage, and the QB node may maintain a low level voltage.

[0094] Therefore, during the second period 2 of the first clock signal GCLK1, the nth output signal Vgout(n) of the nth gate signal generating circuit SGD(n) may be a high level voltage VGH. The nth output signal Vgout(n) having the high level voltage VGH may be maintained during four horizontal periods 4H and may be provided to the nth pixel line to turn on the n-type transistor.

[0095] Figure 5 is a block diagram of a gate drive circuit GD according to the second aspect of the present disclosure. Specifically, Figure 5A gate driving circuit GD according to aspects of the present disclosure and a pixel line PG to which a signal output from the gate driving circuit GD is applied are shown.

[0096] Hereinafter, when describing the second aspect, description of elements that are the same as or similar to those of the first aspect may be omitted.

[0097] exist Figure 5 In, similar to Figure 2 , the gate drive circuit GD may include only a driver for applying a scan signal. When the number of pixel lines included in the display area DA is p, the gate drive circuit GD according to aspects of the present disclosure may include a first gate signal generating circuit SGD(1) to a p-th gate signal generating circuit SGD(p). Figure 5 In FIG. 1 , only the nth to (n+3)th gate signal generating circuits SGD(n) to SGD(n+3) are shown. In this case, p and n may both be natural numbers, and 1≤n≤p.

[0098] The gate driving circuit GD may include a plurality of lines for transmitting a first clock signal GCLK1, a second clock signal GCLK2, a low level voltage VGL, a high level voltage VGH, a third clock signal OCLK1, a fourth clock signal OCLK2, and a start signal Vst. Based on the first clock signal GCLK1, the nth gate signal generating circuit SGD(n) may provide a scanning signal to the nth pixel line PG(n) while shifting the start signal Vst.

[0099] The start signal Vst may be input to the first gate signal generating circuit SGD(1), and each of the second gate signal generating circuit SGD(2) to the pth gate signal generating circuit SGD(p) may operate based on a scan signal output by a previous gate generating circuit and received as a start signal. Specifically, the nth output signal Vgout(n) of the nth gate signal generating circuit SGD(n) may be input as a start signal of the (n+1)th gate signal generating circuit SGD(n+1), and may be input to the nth pixel line PG(n).

[0100] Each of the first clock signal GCLK1 and the second clock signal GCLK2 may swing between a high level voltage and a low level voltage and may have the same period. The first clock signal GCLK1 and the second clock signal GCLK2 may have different phases. Specifically, the second clock signal GCLK2 may be a signal obtained by shifting the phase of the first clock signal GCLK1 by 180 degrees.

[0101] exist Figure 5, it is shown that the first clock signal GCLK1 is input to the nth gate signal generating circuit SGD(n) and the (n+2)th gate signal generating circuit SGD(n+2), and the second clock signal GCLK2 is input to the (n+1)th gate signal generating circuit SGD(n+1) and the (n+3)th gate signal generating circuit SGD(n+3). That is, Figure 5 It is shown that the first clock signal GCLK1 is input to the odd-numbered gate signal generating circuit included in the gate driving circuit GD according to the second aspect of the present disclosure, and the second clock signal GCLK2 is input to the even-numbered gate signal generating circuit included in the gate driving circuit GD according to the second aspect of the present disclosure. The first clock signal GCLK1 and the second clock signal GCLK2 may be sequentially and alternately connected to a plurality of gate signal generating circuits, but the order thereof is not limited thereto.

[0102] Each of the third clock signal OCLK1 and the fourth clock signal OCLK2 may swing between a high level voltage and a low level voltage and may have the same period. The third clock signal OCLK1 and the fourth clock signal OCLK2 may have different phases. Specifically, the fourth clock signal OCLK2 may be a signal obtained by shifting the phase of the third clock signal OCLK1 by 180 degrees.

[0103] Figure 6 is a circuit diagram of a gate signal generating circuit according to the second aspect of the present disclosure. Figure 6 is a diagram describing an example of an n-th gate signal generating circuit SGD(n) constituting the gate driving circuit GD.

[0104] Reference Figure 6 , the nth gate signal generating circuit SGD(n) may include a pull-down unit PD, a pull-up unit PU, a Q-node controller CQ, a QB-node controller CQB, and a Q-node holding unit KQ.

[0105] The pull-down unit PD may output the nth output signal Vgout(n) as an off voltage in response to the voltage of the Q node, and the pull-up unit PU may output the nth output signal Vgout(n) as an on voltage in response to the voltage of the QB node. The nth output signal Vgout(n) determined by the pull-down unit PD and the pull-up unit PU may be applied to the nth pixel line PG(n).

[0106] The Q-node controller CQ may be an element for charging or discharging the Q-node, and may apply an on-voltage or an off-voltage to the Q-node based on a start signal Vst. The start signal Vst may be input to the first gate signal generating circuit SGD1, and the second gate signal generating circuit SGD2 and subsequent gate signal generating circuits may use the previous output signal as a start signal. When n is a natural number of 2 or greater, the nth gate signal generating circuit SGD(n) may use the (n-1)th output signal Vgout(n-1) of the (n-1)th gate signal generating circuit SGD(n-1) as a start signal.

[0107] The QB node controller CQB may be an element for charging or discharging the QB node, and may apply an on voltage or an off voltage to the QB node based on a voltage of the Q node applied by the Q node controller CQ.

[0108] The electroluminescent display device 100 according to aspects of the present disclosure can change the frequency and can be driven based on the changed frequency to reduce power consumption. For example, the electroluminescent display device 100 can be driven at a low frequency of about 1 Hz during a period of displaying a still image, a picture and / or a text instead of a moving image. In the low-frequency-based drive, since the power consumption is reduced but the movement of the screen is slow, a slight change in brightness can be identified as flickering, and therefore, the output signal of the gate drive circuit GD should be kept constant. When the output signal of the gate signal generating circuit is a low-level voltage VGL, the Q-node holding unit KQ included in the gate signal generating circuit according to the second aspect of the present disclosure can enable the Q-node to maintain the voltage for turning on the pull-down unit PD.

[0109] The nth gate signal generating circuit SGD(n) according to the second aspect of the present disclosure may include all of n-type transistors and p-type transistors. The nth output signal Vgout(n) of the nth gate signal generating circuit SGD(n) may be provided to a pixel driving circuit included in the nth pixel line PG(n), and specifically, may control the on and off of the n-type transistor, but is not limited thereto.

[0110] The detailed circuit structure and operation of the nth gate signal generating circuit SGD(n) will be described below.

[0111] Figure 7 is a waveform diagram of a gate signal input to the gate signal generating circuit according to the second aspect of the present disclosure.

[0112] Reference Figure 6 and Figure 7, the start signal Vst has a high level pulse of a horizontal period of 1H. Each of the first clock signal GCLK1 and the second clock signal GCLK2 has a period of two horizontal periods of 2H. Each of the first clock signal GCLK1 and the second clock signal GCLK2 has a low level pulse corresponding to a period shorter than a horizontal period of 1H and a high level pulse corresponding to a period longer than a horizontal period of 1H. Therefore, each of the first clock signal GCLK1 and the second clock signal GCLK2 has a low level pulse shorter than half of the period and a high level pulse longer than half of the period. For example, when the low level voltage of the start signal Vst is shifted to a high level voltage and overlaps with the low level pulse of the first clock signal GCLK1, the problem of not generating an output signal may occur. In order to solve this problem, the length of the low level pulse of the first clock signal GCLK1 can be shorter than the length of its high level pulse. Similar to the first clock signal GCLK1, the length of the low level pulse of the second clock signal GCLK2 can be shorter than the length of its high level pulse.

[0113] Each of the third clock signal OCLK1 and the fourth clock signal OCLK2 may have a period of two horizontal periods 2H. Each of the third clock signal OCLK1 and the fourth clock signal OCLK2 has a low level pulse and a high level pulse of one horizontal period 1H. Figure 6 , unlike the first clock signal GCLK1, each of the third clock signal OCLK1 and the fourth clock signal OCLK2 is a signal connected to the output unit, and thus does not affect the generation of the output signal. Therefore, the low level pulse and the high level pulse of each of the third clock signal OCLK1 and the fourth clock signal OCLK2 can be implemented to have the same length.

[0114] The high level pulse of the start signal Vst applied to the n-th gate signal generating circuit SGD(n) overlaps with the low level pulse of the first clock signal GCLK1 .

[0115] First, a first period 1 of the first clock signal GCLK1 that starts before the start signal Vst is input to the nth gate signal generating circuit SGD(n) will be described.

[0116] The Q node controller CQ can be implemented with a first transistor T1 and a second transistor T2. The first transistor T1 and the second transistor T2 can be connected in series with each other and can be implemented as p-type transistors. The first transistor T1 can be controlled by the first clock signal GCLK1, and the start signal Vst can be provided to the second transistor T2. In addition, the second transistor T2 can be controlled by a low level voltage VGL, and the start signal Vst transmitted from the first transistor T1 can be provided to the Q node. The second transistor T2 can always remain in a conductive state based on the low level voltage VGL. The first period 1 of the first clock signal GCLK1 can start based on the low level voltage of the first clock signal GCLK1, and the start signal Vst can be a low level voltage. Therefore, the Q node controller CQ can provide a low level voltage to the Q node.

[0117] In the low level pulse period of the first clock signal GCLK1, the start pulse Vst provided to the Q node may have a low level voltage, and the low level voltage may be provided to the pull-down unit PD. The pull-down unit PD may be implemented with a seventh transistor T7. The seventh transistor T7 may be implemented as a p-type transistor. The seventh transistor T7 may be controlled by the Q node, and may output a low level voltage VGL.

[0118] In addition, the Q node can control the QB node controller CQB. The QB node controller CQB can be implemented with a third transistor T3 and a fourth transistor T4. The third transistor T3 and the fourth transistor T4 can be connected in series with each other and can be controlled by the Q node. The third transistor T3 can be implemented as an n-type transistor, and the fourth transistor T4 can be implemented as a p-type transistor. Therefore, in the same period, the off / on state of the third transistor T3 can be opposite to the off / on state of the fourth transistor T4. Therefore, the third transistor T3 can be turned off by the low level voltage of the Q node, and the fourth transistor T4 can be turned on by the low level voltage of the Q node. The high level voltage VGH can be provided to the QB node by the turned-on fourth transistor T4. Since the third transistor T3 is implemented as an n-type transistor, the connection of the circuit can be simplified, and therefore the width W of the gate drive circuit GD can be reduced. In addition, the active layer of the n-type transistor may include an oxide, and therefore, the threshold voltage margin of the third transistor T3 can be ensured, and the voltage provided to the third transistor T3 can be normally transmitted to the third transistor T3.

[0119] During the low level pulse period of the first clock signal GCLK1, the high level voltage VGH provided to the QB node can be provided to the pull-up unit PU. The pull-up unit PU can be implemented with the eighth transistor T8 and the third capacitor Cqb. The eighth transistor T8 can be implemented as a p-type transistor. The third capacitor Cqb can be connected to the output node VO and the QB node, and can be charged with the low level voltage VGL of the output node VO and the high level voltage VGH of the QB node. The eighth transistor T8 can be controlled and turned off by the QB node.

[0120] In addition, the Q node and the fourth clock signal OCLK2 can control the Q node holding unit KQ. The Q node holding unit KQ can be implemented with a fifth transistor T5, a sixth transistor T6 and a second capacitor Cq2. The fifth transistor T5 and the sixth transistor T6 can each be implemented as a p-type transistor. The fifth transistor T5 can be turned on by the low level voltage of the fourth clock signal OCLK2, the sixth transistor T6 can be turned on by the low level voltage of the Q node, and the low level voltage of the fourth clock signal OCLK2 can be provided to the A node. The second capacitor Cq2 can be connected to the A node and the Q node, and can be charged with a voltage provided to each of the A node and the Q node.

[0121] Subsequently, during a first period 1 of the first clock signal GCLK1 , the first clock signal GCLK1 may shift from a low level voltage to a high level voltage, and the first transistor T1 may be turned off.

[0122] The second transistor T2 may be connected between the first transistor T1 and the Q node, and the first transistor T1 may be turned off, so the Q node may float, but the voltage of the Q node may be maintained as a low level voltage by the Q node holding unit KQ. The seventh transistor T7 may maintain a turned-on state, and the nth output signal Vgout(n) may be maintained as a low voltage VGL.

[0123] Therefore, during the first period 1 of the first clock signal GCLK1, the output signal Vgout(n) of the nth gate signal generating circuit SGD(n) can maintain the low level voltage VGL. In the low frequency based driving, the electroluminescent display device 100 according to aspects of the present disclosure can maintain a constant voltage of the Q node through the Q node holding unit KQ, and thus, the nth gate signal generating circuit SGD(n) can be stably driven.

[0124] Second, the second period 2 of the first clock signal GCLK1 will be described. The second period 2 of the first clock signal GCLK1 may start based on a low level voltage, and the start signal Vst may shift from the low level voltage to the high level voltage before the first period 1 of the first clock signal GCLK1 ends, and may be in a state corresponding to the high level voltage.

[0125] The first transistor T1 may be controlled by the first clock signal GCLK1 and may provide the start signal Vst to the second transistor T2. In addition, the second transistor T2 may be controlled by the low level voltage VGL and may provide the start signal Vst transmitted from the first transistor T1 to the Q node. That is, the Q node controller CQ may provide a high level voltage to the Q node.

[0126] In the low level pulse period of the first clock signal GCLK1, the start signal Vst provided to the Q node may be a high level voltage, and the high level voltage may be provided to the pull-down unit PD. Therefore, the seventh transistor T7 may be controlled and turned off by the Q node.

[0127] In addition, the Q node can be controlled by the QB node controller QB, and therefore, the third transistor T3 can be turned on by the high level voltage of the Q node and can provide the low level voltage VGL to the B node. In addition, the fourth transistor T4 can be turned off by the high level voltage of the Q node and can turn off the high level voltage VGH provided to the QB node.

[0128] In addition, the fifth transistor T5 may be turned off by the high level voltage of the fourth clock signal OCLK2 and may turn off the B node and the QB node, and the sixth transistor T6 may be turned off by the high level voltage of the Q node.

[0129] During the low level pulse period of the first clock signal GCLK1 , the QB node may maintain the high level voltage VGH by using the third capacitor Cqb of the pull-up unit PU, and the off state of the eighth transistor T8 may be maintained.

[0130] Subsequently, during the second period 2 of the first clock signal GCLK1, the first clock signal GCLK1 may shift from a low level voltage to a high level voltage, and the start signal Vst may shift from a high level voltage to a low level voltage. The first clock signal GCLK1 having a high level voltage may turn off the first transistor T1. However, the high level voltage of the Q node may be maintained by the Q node holding unit KQ.

[0131] The third transistor T3 of the QB node controller CQB may be turned on by the high level voltage of the Q node and may apply the low level voltage VGL to the B node, and the fourth transistor T4 may be turned off by the high level voltage of the Q node.

[0132] The fifth transistor T5 of the Q node holding unit KQ can be turned on by the low level voltage of the fourth clock signal OCLK2, and can transmit the low level voltage VGL of the B node to the QB node. The sixth transistor T6 can be turned off by the high level voltage of the Q node. In addition, the second capacitor Cq2 can maintain the voltage of the Q node.

[0133] The low level voltage VGL transmitted to the QB node can control the pull-up unit PU. Specifically, the eighth transistor T8 can be turned on by the low level voltage VGL of the QB node, and can output the high level voltage of the third clock signal OCLK1 as the nth output signal Vgout(n). During a horizontal period 1H in which the third clock signal OCLK1 maintains a high level voltage, the nth output signal Vgout(n) can maintain a high level voltage.

[0134] In addition, before the second period 2 of the first clock signal GCLK1, the third clock signal OCLK1 may be shifted from a high level voltage to a low level voltage, and the fourth clock signal OCLK2 may be shifted from a low level voltage to a high level voltage. In this case, the fifth transistor T5 may be turned off by the fourth clock signal OCLK2, but may not affect the voltage of the Q node. In addition, the low level voltage of the third clock signal OCLK1 may be transmitted to the output node VO through the turned-on eighth transistor T8, and therefore, the voltage change of the output node VO may affect the QB node based on the coupling effect of the third capacitor Cqb. The voltage of the QB node may reduce the difference between the high level voltage and the low level voltage of the third clock signal OCLK1, and at the same time, the falling time of the voltage of the output node VO may be reduced.

[0135] Therefore, during the second period 2 of the first clock signal GCLK1, the nth output signal Vgout(n) of the nth gate signal generating circuit SGD(n) can output a high level voltage VGH corresponding to one horizontal period 1H. In this case, the third capacitor Cqb can be provided in the pull-up unit PU, and thus the nth gate signal generating circuit SGD(n) can reduce the falling time of the nth output signal Vgout(n), and can enhance the reliability of the output signal.

[0136] Figure 8 is a circuit diagram of a gate drive circuit according to a third aspect of the present disclosure. Figure 8 is a diagram describing an example of an n-th gate signal generating circuit SGD(n) configuring the gate driving circuit GD.

[0137] In the following, when describing the third aspect, the description of the same or similar elements as the first aspect may be omitted. Figure 2 Block diagram of the gate drive circuit GD.

[0138] refer to Figure 8 , the nth gate signal generating circuit SGD(n) may include a pull-down unit PD, a pull-up unit PU, a Q-node controller CQ, and a QB-node controller CQB.

[0139] The pull-down unit PD may output an nth output signal Vgout(n) in response to the off voltage of the voltage of the Q node, and the pull-up unit PU may output an nth output signal Vgout(n) in response to the off voltage of the voltage of the QB node. The pull-down unit PD and the pull-up unit PU may be connected to each other in series and may share an output node VO. The nth output signal Vgout(n) determined by the pull-down unit PD and the pull-up unit PU may be applied to the nth pixel line PG(n).

[0140] The Q node controller CQ may be an element for charging or discharging the Q node, and may apply an on voltage or an off voltage to the Q node based on the start signal Vst. When n is a natural number of 3 or greater, the nth gate signal generating circuit SGD(n) may use the (n-2)th output signal Vgout(n-2) of the (n-2)th gate signal generating circuit SGD(n-2) as a start signal.

[0141] The QB node controller CQB may be an element for charging or discharging the QB node, and may apply an on voltage or an off voltage to the QB node based on a voltage of the Q node applied by the Q node controller CQ.

[0142] The nth gate signal generating circuit SGD(n) according to aspects of the present invention may include all n-type transistors and p-type transistors. The nth output signal Vgout(n) of the nth gate signal generating circuit SGD(n) may be provided to a pixel driving circuit included in the nth pixel line PG(n). Specifically, when the pixel driving circuit is implemented using n-type transistors and p-type transistors, the nth output signal Vgout(n) may control the on and off of the n-type transistors, but is not limited thereto.

[0143] The detailed circuit structure and operation of the nth gate signal generating circuit SGD(n) according to the third aspect of the present disclosure will be described in detail below.

[0144] Fig. 9 is a waveform diagram of a gate signal input to a gate driving circuit according to the third aspect of the present disclosure.

[0145] refer to Figure 8 and Fig. 9, each start signal Vst has a high level pulse of two horizontal periods 2H. The first clock signal GCLK1 has a high level pulse corresponding to a period shorter than one horizontal period 1H and a low level pulse corresponding to a period longer than one horizontal period 1H. For example, when the time point when the low level voltage of the start signal Vst shifts to the high level voltage overlaps with the high level pulse of the first clock signal GCLK1, the problem of not generating an output signal may occur. In order to solve this problem, the length of the high level pulse of the first clock signal GCLK1 can be shorter than the length of its low level pulse.

[0146] The high level pulse of the start signal Vst applied to the n-th gate signal generating circuit SGD(n) overlaps the high level pulse and the low level pulse of the first clock signal GCLK1.

[0147] First, a first period 1 of the first clock signal GCLK1 that starts before the first start signal Vst1 is input to the nth gate signal generating circuit SGD(n) will be described.

[0148] The Q node controller CQ can be implemented using a first transistor T1 and a second transistor T2. The first transistor T1 and the second transistor T2 can be connected in series with each other, the first transistor T1 can be implemented as an n-type transistor, and the second transistor T2 can be implemented as a p-type transistor. The first transistor T1 can be controlled by a first clock signal GCLK1, and a start signal Vst can be provided to the second transistor T2. In addition, the second transistor T2 can be controlled by a low level voltage VGL, and a start signal Vst transmitted from the first transistor T1 can be provided to the Q node. The second transistor T2 can always remain in a conducting state based on the low level voltage VGL. The second transistor T2 can be connected between the Q node and the first transistor T1, and can buffer the voltage of the Q node.

[0149] The first period 1 of the first clock signal GCLK1 may start with a low level voltage of the first clock signal GCLK1, and the start pulse Vst may have a low level voltage. Subsequently, when the first clock signal GCLK1 has a low level voltage, the start signal Vst may be shifted to a high level voltage. When the first clock signal GCLK1 has a low level voltage, the first transistor T1 may be in an off state.

[0150] When the first clock signal GCLK1 has a high level voltage in a first period 1 of the first clock signal GCLK1 , the start signal Vst may maintain a high level voltage.

[0151] The first transistor T1 may be turned on by a high level pulse of the first clock signal GCLK1 , and thus the Q-node controller CQ may provide a high level voltage of the start signal Vst to the Q-node.

[0152] During the high level pulse period of the first clock signal GCLK1, the start signal Vst provided to the Q node may have a high level voltage, and the high level voltage may be provided to the pull-down unit PD. The pull-down unit PD may be implemented using a seventh transistor T7 and a first capacitor Cq1, which are connected to a line powered by a low level voltage VGL. The seventh transistor T7 may be implemented as a p-type transistor, and therefore, the seventh transistor T7 may be turned off by the high level voltage of the Q node.

[0153] The Q node can control the QB node controller CQB. The QB node controller CQB can be implemented using a third transistor T3 and a fourth transistor T4. The third transistor T3 and the fourth transistor T4 can be connected to each other in series through the QB node, and each of the third transistor T3 and the fourth transistor T4 can be implemented as an n-type transistor. The gate of the third transistor T3 can be connected to the Q node, its first electrode can be connected to a line provided with a low level voltage VGL, and its second electrode can be connected to the QB node. The gate and the first electrode of the fourth transistor T4 can be connected to a line provided with a high level voltage VGH to form a diode contact, and its second electrode can be connected to the QB node. Therefore, the third transistor T3 can be controlled by the Q node, and the fourth transistor T4 can be controlled by the high level voltage VGH. The fourth transistor T4 can always maintain a conductive state based on the high level voltage VGH, and therefore can substantially maintain the state of the QB node as a high level voltage VGH. In this case, the third transistor T3 can be turned on by the high level voltage of the Q node, and a low level voltage VGL can be provided to the QB node.

[0154] During the high level pulse period of the first clock signal GCLK1, the low level voltage GVL provided to the QB node can be provided to the pull-up unit PU. The pull-up PU can be implemented using an eighth transistor T8 connected to a line powered by a high level voltage VGH. In addition, the eighth transistor T8 can be implemented as a p-type transistor. The eighth transistor T8 can be turned on by a low level voltage VGL provided to the QB node, and a high level voltage VGH can be provided as the nth output signal Vgout(n). Therefore, during the low level pulse period of the first clock signal GCLK1 in the first period 1 of the first clock signal GCLK1, the output signal Vgout(n) of the nth gate signal generating circuit SGD(n) can be a low level voltage VGL, and during the high level pulse period of the first clock signal GCLK1, the output signal Vgout(n) of the nth gate signal generating circuit SGD(n) can be a high level voltage VGH.

[0155] Second, the second period 2 of the first clock signal GCLK1 will be described. The second period 2 of the first clock signal GCLK1 may start based on a low level voltage, and the start signal Vst may start based on a high level voltage. When the first clock signal GCLK1 has a low level voltage, the start signal Vst may shift from a high level voltage to a low level voltage.

[0156] In the low level pulse period of the first clock signal GCLK1, the first transistor T1 can be turned off, and the Q node can maintain a high level voltage. The second transistor T2 can be connected between the first transistor T1 and the Q node, and the first transistor T1 can be turned off, and thus the Q node can float, but the voltage of the Q node may not be greatly jittered by the second transistor T2. The high level voltage can keep the seventh transistor T7 in the off state.

[0157] In addition, the Q node may be controlled by the QB node controller CQB, and thus the third transistor T3 may be maintained in a turn-on state based on the high level voltage of the Q node and may provide the low level voltage VGL to the QB node.

[0158] During the low level pulse period of the first clock signal GCLK1, the low level voltage VGL provided to the QB node may be provided to the pull-up unit PU. The eighth transistor T8 may be turned on through the QB node and may output the high level voltage VGH to the output node VO. The output node VO may be a node shared by the pull-down unit PD and the pull-up unit PU connected in series to each other, and may be a node to which the output signal Vgout(n) is provided.

[0159] Subsequently, during the second period 2 of the first clock signal GCLK1, the first clock signal GCLK1 may shift from a low level voltage to a high level voltage, and the start signal Vst may be a high level voltage. The time point at which the low level voltage of the first clock signal GCLK1 shifts to a high level voltage may be later than the time point at which the high level voltage of the first start signal Vst1 shifts to a low level voltage.

[0160] The first clock signal GCLK1 having a high level voltage may turn on the first transistor T1. The Q node controller CQ may transmit the low level voltage of the start signal Vst to the Q node. The Q node may control the pull-down unit PD, and thus the seventh transistor T7 may output a low level voltage VGL based on the Q node. The first capacitor Cq1 may include a first node connected to the Q node and a second node connected to an output node VO outputting the nth output signal Vgout(n). The first capacitor Cq1 may bootstrap the voltage of the Q node to cause it to drop, and thus enable the nth output signal Vgout(n) to maintain the low level voltage VGL, and may maintain the low level voltage of the Q node after outputting the low level voltage VGL of the nth output signal Vgout(n).

[0161] In addition, the third transistor T3 may be turned off by the low level voltage of the Q node, and the QB node may be shifted to the high level voltage VGH by the fourth transistor T4 .

[0162] Therefore, during the second period 2 of the first clock signal GCLK1, the output signal Vgout(n) of the nth gate signal generating circuit SGD(n) can maintain the high level voltage VGH and then can be shifted to the low level voltage VGL. The output signal Vgout(n) having the high level voltage VGH can be maintained during the two horizontal periods 2H and can be provided to the nth pixel line to turn on the n-type transistor. However, the present disclosure is not limited thereto and can be connected to the p-type transistor to turn off the p-type transistor.

[0163] The n-th gate signal generating circuit SGD(n) may include a first transistor T1, a third transistor T3, and a fourth transistor T4 implemented as n-type transistors, and a diode contact may be formed by using the fourth transistor T4, and thus the connection of the circuit may be simplified, thereby reducing the width W of the gate driving circuit GD. In addition, the active layer of the n-type transistor may include an oxide, and thus the leakage current of the first transistor T1 and the third transistor T3 may be reduced, and a threshold voltage margin may be ensured, thereby normally transmitting a voltage to each transistor.

[0164] A gate driving circuit and an electroluminescent display device according to aspects of the present disclosure will be described below.

[0165] In a gate drive circuit according to aspects of the present disclosure, the gate drive circuit includes: a pull-down unit, which is controlled by a Q node to transmit a low-level voltage to an output node; a pull-up unit, which is controlled by a QB node to transmit a high-level voltage of a third clock signal to an output node; a Q node controller, which is controlled by a first clock signal to transmit a start signal to a Q node; a QB node controller, which is controlled by a Q node to transmit a high-level voltage to a QB node; and a Q node holding unit, which is controlled by a Q node and a fourth clock signal, the Q node holding unit including a second capacitor connected to the Q node. In addition, the QB node controller includes an n-type transistor and a p-type transistor connected to the Q node. Therefore, a stable output can be provided in a low-frequency-based drive.

[0166] According to another feature of the present disclosure, the pull-down unit and the pull-up unit may be connected to the output node, the pull-up unit may include a third capacitor, and the third capacitor may be connected to the output node and the QB node.

[0167] According to another feature of the present disclosure, the start signal may have a high level voltage at a period corresponding to one horizontal period.

[0168] According to another feature of the present disclosure, at a period corresponding to two horizontal periods, the third clock signal and the fourth clock signal may have a phase difference of 180 degrees therebetween.

[0169] According to another feature of the present disclosure, a high level voltage of the third clock signal transmitted to the output node through the pull-up unit may be synchronized with the third clock signal.

[0170] According to another feature of the present disclosure, at a period corresponding to two horizontal periods, a length of a low level voltage of the first clock signal may be shorter than a length of a high level voltage of the first clock signal.

[0171] According to another feature of the present disclosure, the Q-node controller may include a transistor connected to a low-level voltage to always maintain an on state, and the transistor may be connected to the Q-node.

[0172] In an electroluminescent display device according to an embodiment of the present disclosure, the electroluminescent display device includes a display panel, the display panel including: a display area including a plurality of pixel lines; and a non-display area including a gate drive circuit for supplying gate signals to the plurality of pixel lines. In addition, each of the plurality of pixel lines includes a plurality of pixels, each of the plurality of pixels includes a pixel drive circuit and a light-emitting device, each of the pixel drive circuit and the gate drive circuit is implemented with a p-type transistor and an n-type transistor, and the gate drive circuit supplies the gate signal to the n-type transistor of the pixel drive circuit. Therefore, a stable output can be provided, and the non-display area of ​​the display panel can be reduced.

[0173] According to another feature of the present disclosure, the gate drive circuit GD may include a pull-down unit PD controlled by the Q node and a pull-up unit PU controlled by the QB node, and the pull-down unit PD and the pull-up unit PU may be connected to each other to provide a low level voltage VGL or a high level voltage VGH as a gate signal to the n-type transistor of the pixel drive circuit. In addition, the pull-down unit PD may be connected to a line supplied with a low level voltage VGL, and the pull-up unit PU may be connected to a line supplied with a high level voltage VGH. In addition, the pull-up unit PU may include a first capacitor Cq1, which includes a first electrode connected to the Q node and a second electrode connected to a node shared by the pull-up unit PU and the pull-down unit PD. In addition, the gate drive circuit GD may include a Q node controller CQ controlled by a first clock signal GCLK1 and a low level voltage VGL to transmit a start signal Vst to the Q node, and the Q node controller CQ may include two different types of transistors. In addition, the gate drive circuit GD may include a QB node controller CQB controlled by the Q node, and the QB node controller CQB may include two n-type transistors.

[0174] According to another feature of the present disclosure, the QB node controller CQB may include: a transistor controlled by the Q node and connected to a line provided with a low-level voltage VGL; and a transistor including a gate and an electrode (both connected to a line provided with a high-level voltage VGH). In addition, the two transistors may be connected to each other and may share the QB node.

[0175] According to aspects of the present disclosure, by using a gate signal generating circuit including a pull-down unit, a pull-up unit, a Q-node controller, and a QB-node controller, the image quality of a display panel may be enhanced, and power consumption may be reduced.

[0176] Furthermore, according to an embodiment of the present disclosure, by using a gate signal generating circuit including all of an n-type transistor and a p-type transistor, a bezel area of ​​a display panel can be reduced, and reliability of the gate signal generating circuit can be ensured.

[0177] Furthermore, according to aspects of the present disclosure, by using a gate signal generating circuit including a Q-node holding unit that holds a voltage of a Q-node, the reliability of a signal output from the gate signal generating circuit may be enhanced.

[0178] Regarding the implementation methods including the above embodiments, the following technical solutions are also disclosed:

[0179] Solution 1. A gate drive circuit comprising:

[0180] a pull-down unit, which is controlled by the Q node to transmit a low-level voltage to the output node;

[0181] a pull-up unit controlled by the QB node to transmit a high-level voltage of a third clock signal to the output node;

[0182] A Q-node controller, which is controlled by a first clock signal to transmit a start signal to the Q-node;

[0183] A QB node controller, which is controlled by the Q node to transmit a high level voltage to the QB node; and

[0184] a Q-node holding unit controlled by the Q-node and a fourth clock signal, the Q-node holding unit comprising a second capacitor connected to the Q-node,

[0185] The QB node controller includes an n-type transistor and a p-type transistor connected to the Q node.

[0186] Solution 2. The gate drive circuit according to Solution 1, wherein

[0187] The pull-down unit and the pull-up unit are connected to the output node,

[0188] The pull-up unit includes a third capacitor, and

[0189] The third capacitor is connected to the output node and the QB node.

[0190] Solution 3. The gate driving circuit according to Solution 1, wherein the start signal has a high-level voltage in a period corresponding to one horizontal period.

[0191] Solution 4. The gate driving circuit according to Solution 1, wherein, at a period corresponding to two horizontal periods, the third clock signal has a phase difference of 180 degrees with the fourth clock signal.

[0192] Solution 5. The gate driving circuit according to Solution 1, wherein a high-level voltage of the third clock signal transmitted to the output node through the pull-up unit is synchronized with the third clock signal.

[0193] Solution 6. The gate driving circuit according to Solution 1, wherein, at a period corresponding to two horizontal periods, a length of a low-level voltage of the first clock signal is shorter than a length of a high-level voltage of the first clock signal.

[0194] Solution 7. The gate driving circuit according to Solution 1, wherein the Q-node controller includes a transistor that is controlled by the low-level voltage to always remain in an on state, and the transistor is connected to the Q-node.

[0195] Solution 8. An electroluminescent display device, comprising:

[0196] A display panel comprising a display area and a non-display area, wherein the display area comprises a plurality of pixel lines, and the non-display area comprises a gate driving circuit for supplying gate signals to the plurality of pixel lines.

[0197] in

[0198] Each of the plurality of pixel lines includes a plurality of pixels,

[0199] Each of the plurality of pixels includes a pixel driving circuit and a light emitting device,

[0200] Each of the pixel driving circuit and the gate driving circuit is implemented using a p-type transistor and an n-type transistor, and

[0201] The gate driving circuit supplies a gate signal to an n-type transistor of the pixel driving circuit.

[0202] Solution 9. The electroluminescent display device according to Solution 8, wherein the gate driving circuit includes a pull-down unit controlled by the Q node and a pull-up unit controlled by the QB node, and

[0203] The pull-down unit and the pull-up unit are connected to each other to provide a low-level voltage or a high-level voltage as a gate signal to an n-type transistor of the pixel driving circuit.

[0204] Solution 10. The electroluminescent display device according to Solution 9, wherein the pull-down unit is connected to a line supplied with a low-level voltage, and the pull-up unit is connected to a line supplied with a high-level voltage.

[0205] Option 11. An electroluminescent display device according to Option 9, wherein the pull-down unit includes a first capacitor, the first capacitor including a first electrode connected to the Q node and a second electrode connected to a node shared by the pull-up unit and the pull-down unit.

[0206] Option 12. An electroluminescent display device according to Option 9, wherein the gate drive circuit includes a Q-node controller, the Q-node controller is controlled by a first clock signal and a low-level voltage to transmit a start signal to the Q node, and the Q-node controller includes two transistors of different types.

[0207] Option 13. An electroluminescent display device according to Option 9, wherein the gate driving circuit includes a QB node controller controlled by the Q node, and the QB node controller includes two n-type transistors.

[0208] Solution 14. The electroluminescent display device according to Solution 13, wherein the two transistors include:

[0209] a transistor controlled by the Q node and connected to a line supplied with a low level voltage; and

[0210] A transistor including a gate and an electrode, both of which are connected to a line supplied with a high level voltage.

[0211] Embodiment 15. The electroluminescent display device according to Embodiment 13, wherein the two transistors are connected to each other and share the QB node.

[0212] The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.

[0213] While the present disclosure has been particularly shown and described with reference to exemplary aspects thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A gate drive circuit, comprising: a first output unit controlled by the Q node to transmit a low level voltage to an output node; a second output unit controlled by the QB node to transmit a high level voltage to the output node; A Q-node controller, which is controlled by a first clock signal to transmit a start signal to the Q-node; as well as A QB node controller, which is controlled by the Q node to transmit the high level voltage or the low level voltage to the QB node, The QB node controller includes an n-type transistor and a p-type transistor connected to the Q node.

2. The gate drive circuit according to claim 1, wherein: The second output unit and the first output unit are connected to the output node, The first output unit includes a first capacitor, and The first capacitor is connected to the output node and the Q node.

3. The gate driving circuit according to claim 1, wherein: The start signal has a high level voltage at a period corresponding to four horizontal periods.

4. The gate driving circuit according to claim 3, wherein: The first clock signal has a period of the four horizontal periods.

5. The gate driving circuit according to claim 4, wherein: The first clock signal has a low level pulse shorter than half of the period and a high level pulse longer than half of the period.

6. The gate driving circuit according to claim 4, wherein: A high level pulse of the start signal overlaps with a high level pulse and a low level pulse of the first clock signal.

7. The gate driving circuit according to claim 4, wherein: The first clock signal has a first period starting before the start signal is input to the Q-node controller and a second period starting after the start signal is input to the Q-node controller, The first period of the first clock signal starts with a low level voltage of the first clock signal, and the start signal has a low level voltage, When the first clock signal has a high level voltage in the first period of the first clock signal, the start signal shifts from a low level voltage to a high level voltage and maintains the high level voltage.

8. The gate driving circuit according to claim 7, wherein: The second period of the first clock signal starts based on a low level voltage, and the start signal starts based on the high level voltage, and When the first clock signal has the high level voltage in the second period of the first clock signal, the start signal shifts from the high level voltage to the low level voltage.

9. The gate driving circuit according to claim 1, wherein: When n is a natural number of 3 or more, the start signal is the (n-2)th output signal of the (n-2)th gate signal generating circuit.

10. A gate drive circuit comprising: a first output unit controlled by the Q node to transmit a low level voltage to an output node; a second output unit controlled by the QB node to transmit a high level voltage to the output node; A Q-node controller, which is controlled by a first clock signal to transmit a start signal to the Q-node; as well as A QB node controller, which is controlled by the Q node to transmit the high level voltage or the low level voltage to the QB node, Wherein, the QB node controller includes an n-type transistor.

11. The gate driving circuit according to claim 10, wherein: The first output unit and the second output unit are connected to the output node, The second output unit includes a first capacitor, and The first capacitor is connected to the output node and the Q node.

12. The gate driving circuit according to claim 10, wherein: The start signal has a high level voltage at a period corresponding to two horizontal periods.

13. The gate driving circuit according to claim 12, wherein: The first clock signal has a period of the two horizontal periods.

14. The gate driving circuit according to claim 13, wherein: The first clock signal has a high-level pulse corresponding to a period shorter than one horizontal period and a low-level pulse corresponding to a period longer than the one horizontal period.

15. The gate driving circuit according to claim 13, wherein: A high level pulse of the start signal overlaps with a high level pulse and a low level pulse of the first clock signal.

16. The gate driving circuit according to claim 13, wherein: The first clock signal has a first period starting before the start signal is input to the Q-node controller and a second period starting after the start signal is input to the Q-node controller, The first period of the first clock signal starts with a low level voltage of the first clock signal, and the start signal has a low level voltage, When the first clock signal has a low level voltage, the start signal shifts from the low level voltage to a high level voltage, and When the first clock signal has a high level voltage in the first period of the first clock signal, the start signal maintains the high level voltage.

17. The gate driving circuit according to claim 16, wherein: The second period of the first clock signal starts based on a low level voltage, and the start signal starts based on the high level voltage, and When the first clock signal has the low level voltage in the second period of the first clock signal, the start signal shifts from a high level voltage to a low level voltage.

18. The gate driving circuit according to claim 10, wherein: When n is a natural number of 3 or more, the start signal is the (n-2)th output signal of the (n-2)th gate signal generating circuit.

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