Method for controlling display screen and display driving circuit thereof

Abstract

The invention discloses a method for controlling a display screen and a display driving circuit thereof, the display screen comprises a plurality of pixels, and the method comprises the following steps: outputting a scanning control signal to the display screen in a plurality of frame periods. The scanning control signal has a first timing setting in a first frame period of the plurality of frame periods and has a second timing setting in a second frame period of the plurality of frame periods, and the second timing setting is different from the first timing setting. A plurality of scanning signals generated by the scanning control signal are sequentially output to the plurality of pixels, respectively.

Description

Technical Field

[0001] The present invention relates to a method for controlling a display screen, and in particular to a method for controlling an organic light-emitting diode (OLED) panel and a related display driving circuit. Background Art

[0002] In recent years, display screens are prone to dark band problems at low brightness, especially low-temperature polycrystalline oxide (LTPO) organic light-emitting diode (OLED) panels. At present, most industry insiders use pixel-level correction (demura) to compensate for the brightness difference in the dark band, but the dark band problem cannot be completely solved due to the insufficient compensation ability of pixel-level correction. In addition, some product manufacturers use a solution of dynamically adjusting the anode initial voltage of the organic light-emitting diode to solve the dark band problem, but this solution may affect other areas without dark bands. In addition, the initial voltage is used to output to the anode of the organic light-emitting diode to maintain the cross-voltage of the organic light-emitting diode constant. However, if the initial voltage is adjusted by dynamic compensation, it is impossible to use the method of controlling the anode voltage of the organic light-emitting diode to track the cathode voltage to maintain its cross-voltage constant function, resulting in the problem of image sticking on the display screen. In addition, the long-term voltage offset at the anode end of the organic light-emitting diode also causes different stresses in the pixel circuit in the dark band area, thereby reducing the reliability of the organic light-emitting diode panel. Summary of the invention

[0003] Therefore, the main purpose of the present invention is to provide a new display screen control method and a related display driving circuit to solve the above problems.

[0004] An embodiment of the present invention discloses a method for controlling a display screen, the display screen comprising a plurality of pixels. The method comprises the following steps: outputting a scan control signal to the display screen during a plurality of frame periods. The scan control signal has a first timing setting during a first frame period among the plurality of frame periods, and has a second timing setting during a second frame period among the plurality of frame periods, wherein the second timing setting is different from the first timing setting. A plurality of scan signals generated by the scan control signal are sequentially output to the plurality of pixels.

[0005] Another embodiment of the present invention discloses a display driving circuit for controlling a display screen including a plurality of pixels. The display driving circuit is used to output a scan control signal to the display screen during a plurality of frame periods. The scan control signal has a first timing setting during a first frame period among the plurality of frame periods, and has a second timing setting during a second frame period among the plurality of frame periods, wherein the second timing setting is different from the first timing setting. A plurality of scan signals generated by the scan control signal are sequentially output to the plurality of pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

[0007] Figure 2 The invention is a timing diagram of a display driving circuit outputting a control signal to control pixels on a display screen to reset.

[0008] Figure 3 FIG. 1 is a schematic diagram of a display system according to an embodiment of the present invention.

[0009] Figure 4 The control signals of the display driving circuit and the initial voltage shift received by the nodes in the pixels during multiple frame periods are shown.

[0010] Figure 5 A timing diagram showing a general scanning timing of a scanning control signal.

[0011] Figure 6 FIG. 4 is a timing diagram of a scanning timing of a scanning control signal according to an embodiment of the present invention.

[0012] Figure 7 It is a schematic diagram showing the dispersion of a scan control signal within a period of time and the influence of the scan control signal on the node voltage.

[0013] Figure 8 The behavior of the pulse signal in the scanning signal generated by the scanning control signal during a series of frame periods is shown.

[0014] Fig. 9 FIG. 4 is a timing diagram of a scanning timing of a scanning control signal according to an embodiment of the present invention.

[0015] Fig.10 FIG. 4 is a timing diagram of a scanning timing of a scanning control signal including four pulse signals according to an embodiment of the present invention.

[0016] Fig.11 FIG. 4 is a timing diagram of another scanning timing of the scanning control signal according to an embodiment of the present invention.

[0017] Fig.12 FIG. 4 is a timing diagram of dispersing pulse signals based on different brightness settings according to an embodiment of the present invention.

[0018] Fig.13 Schematic diagram of dark bands generated by simulating node voltage offset with and without inter-frame jitter of the scan control signal.

[0019] Fig.14 Simulated picture content showing dark band improvement is shown.

[0020] Fig.15 The figure is a flow chart of a control process according to a first embodiment of the present invention.

[0021] The reference numerals are described as follows:

[0022] 10 Pixel Circuit

[0023] C1 Storage capacitor

[0024] D1 Light Emitting Component

[0025] MN1, MN2, M1, MR1, MR2 transistors

[0026] VD Display data

[0027] I1 drive current

[0028] VinitN, VinitP, Vinit1 initial voltage

[0029] Node_A, Node_B

[0030] ELVDD, ELVSS power supply voltage

[0031] PSCAN, PSCAN2, NSCAN1, scan signal

[0032] NSCAN2

[0033] EM light control signal

[0034] PSCAN_STV, PSCAN_STV_1~ Scan control signal

[0035] PSCAN_STV_XPSCAN_CLK Scan control clock

[0036] Vsync vertical synchronization signal

[0037] Hsync horizontal synchronization signal

[0038] P1, P2, P3, P4 pulse signal

[0039] 30 Display System

[0040] 300 Display

[0041] 310 Display driver circuit

[0042] 302 Active Zone

[0043] 304_1, 304_2 Gate drive array circuit

[0044] F_0~F_N frame period

[0045] ΔV offset

[0046] ΔV' Maximum voltage drop after averaging

[0047] W1, W2, W3 Width

[0048] 150 Control Flow

[0049] 1502~1504 Steps DETAILED DESCRIPTION

[0050] In the present invention, the dark band problem on the organic light-emitting diode (OLED) panel can be improved by adjusting the scanning timing of a scanning signal for the initial voltage of an organic light-emitting diode (OLED) pixel without dynamically adjusting the initial voltage, thereby allowing the organic light-emitting diode to maintain a constant voltage and operate normally. The method of the present invention can solve the dark band problem and improve the reliability of the organic light-emitting diode panel.

[0051] Most of the organic light-emitting diode panels on the market currently use an 8T1C structure. This pixel structure uses low-temperature polycrystalline oxide (LTPO) technology to set up indium gallium zinc oxide thin-film transistors (IGZO-TFT) to reduce the leakage of storage capacitors in pixels, so as to maintain the image at a low refresh rate, thereby achieving extremely low frame rate applications. However, in recent years, the industry has found that organic light-emitting diode panels with an 8T1C structure are prone to dark band problems. This is because during the scanning process of the organic light-emitting diode pixels, the initial voltage (also called the reset voltage) of the anode of the organic light-emitting diode will have a load change, causing the initial voltage received by different areas on the panel to be offset, thus causing the dark band problem.

[0052] Figure 1Schematic diagram of a pixel circuit 10 according to an embodiment of the present invention. The pixel circuit 10 includes 8 transistors, a storage capacitor C1 and a light-emitting element D1 to realize an 8T1C structure. Among the 8 transistors, most of the transistors are P-type metal oxide semiconductor transistors (PMOS transistors), and the transistors MN1 and MN2 coupled to the storage capacitor C1 are N-type metal oxide semiconductor transistors (NMOS transistors) composed of indium gallium zinc oxide, which are used to reduce the leakage of the storage capacitor C1. The transistor M1 is a driving transistor, which is used to generate a driving current I1 according to a display data VD from a display driving circuit to provide it to the light-emitting element D1, so as to control the light-emitting element D1 to emit light. The light-emitting element D1 can be an organic light-emitting diode or any other element that can generate light, which can emit light according to the driving current I1 received from the driving transistor M1 to generate an image to be displayed.

[0053] Transistors MR1 ​​and MR2 are reset transistors, which are used to transmit initial voltages VinitN and VinitP to initialize the pixel circuit 10. More specifically, the initial voltage VinitN is transmitted to a node Node_A to initialize the light-emitting component D1. In one embodiment, the light-emitting component D1 may be an organic light-emitting diode, and the node Node_A is the anode terminal of the organic light-emitting diode. The initial voltage VinitP is transmitted to a node Node_B to initialize the driving transistor M1. In a preferred embodiment, the initial voltage VinitP may be a positive voltage and the initial voltage VinitN may be a negative voltage. In fact, the level of the initial voltage VinitP may be equal to or different from the level of the initial voltage VinitN, and the implementation methods of these initial voltages should not be used to limit the scope of the present invention. In addition, the pixel circuit 10 may also receive another initial voltage Vinit1 through the transistor MN2, and the initial voltage Vinit1 may also have any appropriate level.

[0054] The pixel circuit 10 can receive power supply voltages ELVDD and ELVSS for operation, and receive related control signals, including scan signals PSCAN, PSCAN2, NSCAN1 and NSCAN2, and a light control signal EM. Among these scan signals, the scan signal PSCAN is used to control the transistor MR1 to transmit the initial voltage VinitN to the node Node_A, and is also used to control the transistor MR2 to transmit the initial voltage VinitP to the node Node_B. Therefore, according to the scan signal PSCAN, the initial voltage VinitN can be output to initialize the light-emitting component D1, and the initial voltage VinitP can be output to initialize the driving transistor M1. Generally speaking, the scan signal PSCAN can be output to the pixels on the display screen row by row to control the pixels to receive the initial voltages VinitN and VinitP. Alternatively, in another embodiment, the transistors MR1 ​​and MR2 can be controlled by different scan signals.

[0055] In the pixel circuit 10, the brightness of the light-emitting component D1 is determined by the size of the driving current I1, and is also affected by the voltages of the nodes Node_A and Node_B. Therefore, before the driving current I1 is output to the light-emitting component D1, the relevant nodes Node_A and Node_B must be reset (i.e., initialized). In the initial stage (also called the reset stage), the transistors MR1 ​​and MR2 are turned on by the scanning signal PSCAN to output the initial voltage VinitN to the node Node_A, and the initial voltage VinitP to the node Node_B to reset the driving transistor M1 and the light-emitting component D1. The levels of the initial voltages VinitN and VinitP can be preset, and their voltage levels are used to enable the driving transistor M1 to respond quickly when receiving the display data VD, thereby reducing the image sticking phenomenon. Assuming that the light-emitting component D1 is an organic light-emitting diode, the initial voltage VinitN can be output to the anode terminal of the organic light-emitting diode to determine the cross-voltage of the organic light-emitting diode (i.e., the voltage difference between VinitN and ELVSS). Therefore, the magnitude of the initial voltage VinitN needs to be constant to avoid unexpected deviations in the brightness of the organic light emitting diode.

[0056] In order to ensure that the voltages of nodes Node_A and Node_B are well controlled, transistors MR1 ​​and MR2 should be periodically turned on to reset nodes Node_A and Node_B. Generally speaking, an 8T1C organic light emitting diode panel needs to support an extremely low frame rate (such as 1 Hz), so it can be reset 3 or 4 times during 1 frame to ensure that nodes Node_A and Node_B are always maintained at the target voltage level, thereby maintaining a constant target brightness.

[0057] Figure 2 A timing diagram of a display driving circuit outputting a control signal to control a pixel on a display screen to reset, wherein: Figure 2 The upper part (above the dotted line) shows the signals of the display drive circuit. Figure 2 The lower half (below the dotted line) shows the timing of the scanning signal PSCAN received by each row of pixels. Figure 2 As shown, the display driving circuit can output an initial voltage VinitN, a light emitting control signal EM, a scanning control signal PSCAN_STV, and a scanning control clock PSCAN_CLK to the display screen. For the convenience of explanation, Figure 2 A vertical synchronization signal Vsync and a horizontal synchronization signal Hsync are also shown, which are used to define the timing of the display driving circuit. The vertical synchronization signal Vsync can be used to define a frame period for displaying a frame of image, and the horizontal synchronization signal Hsync can be used to define a row time for controlling a row of pixels. The initial voltage VinitN represents Figure 1 The initial voltage VinitN (or VinitP) received by the pixel circuit 10 in FIG. Figure 1 The light emitting control signal EM received by the pixel circuit 10 in the display screen is used to generate the light emitting control signal EM received by the pixel circuit 10. The scanning control signal PSCAN_STV and the scanning control clock PSCAN_CLK can be output to a gate-on-array (GOA) circuit on the display screen. According to the scanning control signal PSCAN_STV and the scanning control clock PSCAN_CLK, the gate drive array circuit can generate a scanning signal PSCAN that is sequentially output to the pixel rows. Figure 2 The scan signal PSCAN shown in FIG. 1 represents the scan signal PSCAN output to different pixel rows on the display screen, such as Figure 1 The scanning signal PSCAN received by the pixel circuit 10 in the embodiment.

[0058] Figure 3Schematic diagram of a display system 30 according to an embodiment of the present invention. The display system 30 includes a display screen 300 and a display driving circuit 310. The display screen 300 includes an active area (AA) 302, and two gate driving array circuits 304_1 and 304_2 respectively disposed on the left and right sides of the active area 302. The gate driving array circuits 304_1 and 304_2 are provided with shift registers (not shown), which can receive the scan control signal PSCAN_STV and the scan control clock PSCAN_CLK from the display driving circuit 310, and generate and output the scan signal PSCAN for each row of pixels in the active area 302 by shifting. For example, each of the gate driving array circuits 304_1 and 304_2 may include a plurality of channels corresponding to a plurality of rows of pixels on the display screen 300, and the scan control signal PSCAN_STV may be shifted in these channels to sequentially generate the scan signal PSCAN for each row of pixels.

[0059] In addition, the display driving circuit 310 can output initial voltages VinitN and VinitP to the active area 302 of the display screen 300 in an initial stage to reset the pixels; and output display data VD to the active area 302 of the display screen 300 in a data writing stage. The display driving circuit 310 can also provide a light emitting control signal EM to the pixels in the active area 302. The light emitting control signal EM can be output through another gate driving array circuit on the display screen 300. For simplicity, this gate driving array circuit is omitted in FIG. Figure 3 .

[0060] In one embodiment, the display screen 300 may be an organic light emitting diode panel, a mini-LED panel, a micro-LED panel, or any other self-luminous panel. The display driver circuit 310 may be a display driver integrated circuit (DDIC) implemented in a chip, but is not limited thereto.

[0061] Please refer to Figure 3 Matching Figure 2 As shown in FIG. 1 , within a frame period defined by the vertical synchronization signal Vsync, the display driving circuit can output three pulse signals P1 to P3 in the scanning control signal PSCAN_STV, which can be converted into three pulse signals P1 to P3 in each scanning signal PSCAN, which are P1, P2, and P3 in time sequence. Through these three pulse signals P1 to P3, each pixel is reset three times within a frame period. Figure 1As shown, the transistors receiving the scan signal PSCAN in the pixel circuit 10 are all P-type metal oxide semiconductor transistors (such as MR1 ​​and MR2), so the pulse signals P1~P3 are low-active pulses, which can be used to turn on the corresponding transistors to reset the pixel circuit 10.

[0062] It should be noted that Figure 2 The upper part is used to illustrate the timing of the signals generated or output by the display driving circuit 310 , and the time axis thereof is outputted sequentially from left to right, that is, the left side represents an earlier signal and the right side represents a later signal. Figure 2 The lower half is used to illustrate the time sequence in which each row of pixels on the display screen 300 receives the scanning signal PSCAN, wherein the scanning signal PSCAN is scanned sequentially from top to bottom on the display screen 300, that is, the time when the pixels in the upper row receive any pulse signal P1~P3 of the scanning signal PSCAN is earlier than the time when the pixels in the lower row receive the same pulse signal P1~P3.

[0063] Figure 2 The lower half can also be interpreted as the scanning signal PSCAN shifting to different positions on the display screen 300, wherein each scanning signal PSCAN scans from left to right, the left side represents the top of the display screen 300 and the right side represents the bottom of the display screen 300. Therefore, under the operation of performing three resets during one frame period, when the pulse signal P1 shifts to a position of about 1 / 3 from the top to the bottom of the display screen 300, the pulse signal P2 starts scanning; when the pulse signal P1 shifts to a position of about 2 / 3 from the top to the bottom of the display screen 300, the pulse signal P2 shifts to a position of about 1 / 3, at which time the pulse signal P3 starts scanning.

[0064] The far right side includes a porch area, which is located outside the active area 302 of the display screen 300 and is not provided with any pixel circuit. In this case, the pulse signal P1 output first is located on the right side of the figure (i.e., the lower position of the display screen 300), and the pulse signal P3 output later is located on the left side of the figure (i.e., the upper position of the display screen 300). Figure 2 As shown, when the pulse signal P1 enters the corridor area, the pulse signal P2 shifts to a position of about 2 / 3 from top to bottom of the display screen 300, and the pulse signal P3 shifts to a position of about 1 / 3. When the pulse signal P1 leaves the corridor area, the first pulse signal of the next frame period enters the first row of the active area 302 and starts scanning.

[0065] It is worth noting that, according to actual needs, each pulse signal P1-P3 can have any number of pulses. In this example, the pulse signal P1 has 2 pulses but the pulse signals P2 and P3 only have 1 pulse. This is because the pulse signal P1 is controlled in conjunction with the input of the display data VD. Figure 1 As shown, the display data VD entering the pixel circuit 10 is from the node Node_B through the diode-connected circuit formed by the transistors M1 and MN1 to the storage capacitor C1, so the time when the initial voltage VinitP enters the node Node_B needs to be staggered with the time when the display data VD is written into the pixel circuit 10 to avoid interfering with the voltage level of the display data VD. Preferably, the node Node_B should be reset to reach the target level before and after the display data VD is written into the pixel circuit 10, so that the overall behavior of data writing into the pixel is consistent, and thus the start pulse is set before and after the display data VD is written to control the transistor MR2 to turn on. In other words, the display data VD is written in the time interval between the two pulses of the pulse signal P1.

[0066] In addition, since the pulse signals P2 and P3 are not written with the display data VD, only one pulse is required for each, but the state of the pulse signals P1-P3 is not limited thereto. However, it should be noted that the nodes Node_A and Node_B are both located on the current path that drives the light-emitting element D1 to emit light, so the nodes Node_A and Node_B need to be reset during the non-emitting period to prevent the light emission from being affected by the initial voltages VinitN and VinitP. In other words, the pulse signals P1-P3 can be output to the pixel while the corresponding light-emitting control signal EM is at a high level to turn off the light-emitting element D1. Figure 1 The pixel circuit 10 in FIG. 1 shows that the light emitting control signal EM is output to the P-type metal oxide semiconductor transistor. Therefore, when the light emitting control signal EM is at a high level, the light emission can be turned off, and when it is at a low level, the light emission can be turned on.

[0067] The initial voltage VinitN output to the pixels on the display screen 300 is provided by the display driving circuit 310. Generally speaking, the display driving circuit 310 can generate and output a constant initial voltage VinitN to each pixel through a voltage regulator. Figure 2 In the embodiment, three resets are performed during each frame. It is assumed that the total pulse width of each pulse signal P1 to P3 covers L rows of pixels (L is an appropriate positive integer). Therefore, most of the time, 3L rows of pixels will be charged by the initial voltage VinitN at the same time (here it is assumed that the sum of the two pulse widths of the pulse signal P1 is equal to L rows).

[0068] However, if Figure 2As shown, when the pulse signal P1 enters the corridor area, because there is no pixel circuit in the corridor area, the number of pixels charged at the same time is reduced, resulting in a reduction in the load of the voltage regulator used to output the initial voltage VinitN, causing the voltage level of the initial voltage VinitN received by the node Node_A to shift. For example, when the pulse signal P1 completely enters the corridor area, there will only be 2L rows of pixels to be charged, which means that the load faced by the initial voltage VinitN is reduced to about 2 / 3 of the original. In one embodiment, the initial voltage VinitN can be a negative voltage, so the reduction in load will cause the negative voltage to shift to a more negative level. Figure 2 As shown, the maximum offset of the initial voltage VinitN appearing on the node Node_A is ΔV, which causes the driving current I1 to decrease, thereby reducing the brightness of the light-emitting component D1. The relationship between the driving current I1 and the offset ΔV can follow the following formula:

[0069] I1=K(VinitN-VD-ΔV). (1)

[0070] According to formula (1), when the offset ΔV increases, the driving current I1 decreases, so that the brightness of the light-emitting element D1 decreases, resulting in the generation of dark bands. Generally speaking, the dark band phenomenon is more obvious under low brightness.

[0071] The above-mentioned load reduction phenomenon occurs when the pulse signal P1 is shifted to the corridor area. Therefore, when the pulse signal P1 is located in the corridor area, the position where the other two pulse signals P2 and P3 are shifted to will show a decrease in brightness. More specifically, at this time, the pulse signal P2 is shifted to a position of about 2 / 3 from top to bottom of the display screen 300, and the pulse signal P3 is shifted to a position of about 1 / 3. Assuming that the pulse signals P1-P3 in each frame period are scanned at equal intervals, when any pulse signal P1-P3 is shifted to the corridor area, the other two pulse signals in the active area must be located at positions of about 1 / 3 and 2 / 3. In other words, no matter where each pulse signal P1-P3 is scanned, the dark band appears at a roughly fixed position and range on the display screen 300. When three resets are performed within a frame period (three pulse signals are included in one frame), two dark bands will appear on the display screen; and when four resets are performed within a frame period (four pulse signals are included in one frame), three dark bands will appear on the display screen. Similarly, when N resets are performed during one frame, N-1 dark bands will appear on the display screen, that is, the position and number of dark bands depend on the scanning settings of the display screen. Most mainstream displays on the market currently use a 3-reset method for one frame, so there are 2 dark bands on the display screen to divide the display area into three equal parts, so the dark band phenomenon is also called the three-part screen phenomenon.

[0072] Regardless of the brightness or application scenario, as long as the display screen 300 is lit, if the scanning signal PSCAN continues to scan with the same timing, the dark band will remain at the same position on the display screen 300. Under long-term operation, the pixels located at the dark band position continue to receive the initial voltage VinitN with a shift of ΔV, which will form different stresses on these pixels in the long run, resulting in different degrees of loss of components within the pixels.

[0073] Figure 4 FIG. 3 shows the control signal of the display driving circuit 310 and the initial voltage VinitN received by the node Node_A in the pixel during multiple frame periods shifted by ΔV. Figure 4 As shown in the lower half (below the dotted line), from F_1 to F_N and even in all subsequent frame periods (N is an arbitrary positive integer), the offset ΔV of the initial voltage VinitN appears at the same position, thus forming a dark band at the same position. Since the initial voltage VinitN is transmitted to the light-emitting components D1 of the pixels, the light-emitting components D1 of the pixels located in the dark band area will continue to receive a lower initial voltage VinitN. In the long run, these light-emitting components D1 will be subjected to different degrees of stress compared to the light-emitting components D1 of other regions / pixels, which may cause more serious wear and tear, thereby reducing the reliability of the overall display screen 300.

[0074] Furthermore, if Figure 4 As shown in the upper part (above the dotted line), under different display brightness value (Display BrightnessValue, DBV) settings, the display driving circuit 310 can output different light control signals EM. For example, under the high display brightness value setting, the light control signal EM includes only 3 high pulses (off pulses) during one frame; under the medium display brightness value setting, the light control signal EM includes 6 high pulses during one frame, and the total pulse width is longer; under the low display brightness value setting, the light control signal EM includes 18 high pulses during one frame, and the total pulse width is the longest. Under the display brightness value settings corresponding to different brightness, the main off pulses (i.e., the longest high pulses) of the light control signal EM are all located at the same position, so the scanning control signal PSCAN_STV can be output through the same timing. In this way, no matter how the display brightness value setting changes, the position of the dark band will not change, which will cause stress problems for the light-emitting components in the dark band area in the long run.

[0075] Figure 5 FIG. 1 is a timing diagram of a general scanning timing of the scanning control signal PSCAN_STV. Specifically, Figure 5FIG. 1 shows a series of light emission control signals EM and scanning control signals PSCAN_STV outputted in frame periods F_0 to F_N, and a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync and an initial voltage VinitN are also shown. Figure 5 For ease of explanation. Figure 2 or Figure 4 Similar to the situation, the scan control signal PSCAN_STV output in each frame period F_0~F_N also includes three pulse signals P1~P3. In each frame period from F_0 to F_N, the scan control signal PSCAN_STV is output through the same timing, that is, the spacing between the pulse signal P1 and the pulse signal P2 is fixed to A line; the spacing between the pulse signal P2 and the pulse signal P3 is fixed to B line; the spacing between the pulse signal P3 and the end time of the frame period is fixed to C line, where A, B, and C are any positive integers. In this case, when the pulse signal P1 reaches the corridor area, the pulse signals P2 and P3 must shift to a fixed position, so dark bands appear at fixed positions and intervals on the display screen.

[0076] In order to improve the dark band problem, the present invention can disperse the locations where dark bands may appear by changing the output timing of the scan control signal PSCAN_STV. More specifically, by changing the timing setting, the spacing between the two pulse signals is variable between different frame periods. For example, a frame period (such as F_1) can adopt a first timing setting, wherein there is a first spacing between the pulse signals P1 and P2; and another frame period (such as F_2) can adopt a second timing setting, wherein there is a second spacing between the pulse signals P1 and P2. The first spacing and the second spacing can have different lengths to disperse the output timing of the pulse signal in the scan control signal PSCAN_STV, thereby generating dispersed pulse signals in the scan signal PSCAN. This scan signal PSCAN is a control signal used to control the node Node_A in the pixel to be reset by the initial voltage VinitN (such as Figure 1 In addition, the scan signal PSCAN can also be used to control the node Node_B in the pixel to be reset by the initial voltage VinitP.

[0077] Figure 6 FIG. 1 is a timing diagram of a scanning timing of the scanning control signal PSCAN_STV according to an embodiment of the present invention. Figure 6 FIG. 1 shows a series of light emission control signals EM and scanning control signals PSCAN_STV outputted in frame periods F_0 to F_N, and a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync and an initial voltage VinitN are also shown. Figure 6 For convenience of explanation. Figure 6As shown, the scanning control signal PSCAN_STV in the frame period F_0 is Figure 5 The same output timing is shown. In the subsequent frame period from F_1 to F_N, the pulse signals P2 and P3 of the scan control signal PSCAN_STV are sequentially delayed by one line. That is to say, between the frame periods F_0 to F_N, the output timing of the pulse signals P2 and P3 maintains a dithering with equal spacing, thereby dispersing the dark bands.

[0078] More specifically, if Figure 6 As shown, during the frame period from F_1 to F_N, the spacing between the pulse signal P1 and the pulse signal P2 is A+1 row to A+N row respectively; the spacing between the pulse signal P2 and the pulse signal P3 is fixed to B row, which means that the dispersion (such as delay) of the pulse signals P2 and P3 is the same; the spacing between the pulse signal P3 and the end time of the frame period is correspondingly configured to C-1 row to CN row to maintain a constant frame period length. It should be noted that Figure 6 The embodiment is a fixed frame rate, wherein the lengths of the frame periods F_0 to F_N are all equal. In other embodiments, if the timing setting of the extended corridor is adopted, the interval between the pulse signal P3 and the end time of the frame period can be kept fixed or adjusted according to the corridor length requirement.

[0079] Therefore, in a current frame period among F_1 to F_N, the pulse signals P2 and P3 are output with a delay of one line time relative to the same pulse signals P2 and P3 in the previous frame period. Figure 6 The delay mode is only an exemplary embodiment. In another embodiment, the pulse signal can be delayed by any number of line times between each two consecutive frame periods, which is not limited to the case described in this specification.

[0080] It is worth noting that Figure 6 The timing of the scan control signal PSCAN_STV output by the display driving circuit 310 is shown, wherein the scan control signal PSCAN_STV is a signal output to the gate driving array circuits 304_1 and 304_2 on the display screen 300, and at least one of the gate driving array circuits 304_1 and 304_2 is shifted according to the scan control signal PSCAN_STV and the scan control clock PSCAN_CLK to generate a scan signal PSCAN for each row of pixels. Therefore, the timing adjustment of the pulse signals P1-P3 in the scan control signal PSCAN_STV will also cause the pulse signals P1-P3 in the scan signal PSCAN output to the pixel to have timing jitter between different frames, thereby producing a dispersion effect.

[0081] Figure 7FIG. 4 is a schematic diagram showing the influence of a scan control signal PSCAN_STV in a period and the influence of the scan control signal PSCAN_STV on the voltage of the node Node_A. The scan control signal PSCAN_STV and the voltage of the node Node_A and the related light emitting control signal EM are shown in 20 consecutive frame periods F_1 to F_20. Figure 7 The figure shows the situation that a pulse signal of the scanning control signal PSCAN_STV is sequentially delayed by 1 line (1H) and outputted in the frame period F_1 to F_20, similar to Figure 6 The distribution of the pulse signals P2 and P3 in the corridor. Ideally, the initial voltage VinitN should be maintained at a constant voltage level, but a specific pulse signal enters the corridor area, which reduces the load of the initial voltage VinitN, so that the voltage received by the node Node_A decreases within a period of time corresponding to the corridor area, and the maximum voltage drop is ΔV (equivalent to the offset of VinitN). It should be noted that no matter how the pulse signal is shifted or jittered, it should be included in the high pulse of the light-emitting control signal EM that stops emitting light, so as not to affect the screen display, such as Figure 7 shown.

[0082] In detail, the pulse signal can cover several row times, and it enters the corridor area row by row, so that the load gradually decreases, and the behavior corresponding to the node Node_A is that the voltage decreases one by one. When the voltage of the node Node_A drops to the maximum offset ΔV, it means that the entire pulse signal has completely entered the corridor area. In this example, assuming that the voltage of the node Node_A drops by 10mV for each row of pixel load reduction, the maximum offset ΔV is equal to 40mV. If the output timing of the pulse signal is not dispersed, the difference between the Node_A voltage of the pixels in the dark band and the Node_A voltage of the pixels in other areas is essentially equal to 40mV.

[0083] Figure 7 It shows the situation that the pulse signal of the scanning control signal PSCAN_STV in the 20 frame periods F_1 to F_20 is sequentially delayed by one line time (i.e., with a 1H delay) and the voltage drop generated on the node Node_A has a corresponding delay. Therefore, averaged during the frame periods F_1 to F_20, the node Node_A in the pixels at each position produces different degrees of average voltage drops. In terms of visual effect, the final voltage drop is equivalent to the average of the voltage drops during these frame periods F_1 to F_20. Therefore, the voltage difference of 10mV in each step during each frame period is averaged, resulting in only a contribution of 0.5mV. In this example, the maximum voltage drop ΔV' of the node Node_A after averaging is reduced to approximately 26mV (the original maximum voltage offset is 40mV), and the average voltage change of the node Node_A in the area affected by the voltage drop is relatively gentle, making the dark band on the screen less obvious and difficult to be detected by the human eye. Figure 7 From the analysis of the voltage drop behavior, it can be seen that if the number of frame periods during which the pulse signal is dispersed is greater, the dark band improvement effect will be better.

[0084] Figure 8 FIG. 4 shows the behavior of the pulse signals P1 to P3 in the scanning signal PSCAN generated by the scanning control signal PSCAN_STV in a series of frame periods F_0 to F_N, wherein the light emission control signal EM is also shown in FIG. Figure 8 For ease of explanation. Figure 8 From the perspective of panel scanning timing, the shift of pulse signals P1 to P3 is explained. Figure 6 The timing of the output signal of the display driving circuit 310 corresponds to this. In this example, the shift / jitter is performed at the interval between the pulse signals P1 and P2. Due to these shifts / jitters, when the pulse signal P1 enters the corridor area, the position of the pulse signal P2 is different in different frame periods, and the position of the pulse signal P3 is also different in different frame periods. Therefore, the dark bands corresponding to the positions of the pulse signals P2 and P3 are dispersed.

[0085] It is worth noting that the above-mentioned method of sequentially shifting the pulse signal of the scanning control signal PSCAN_STV during several consecutive frames can disperse the position of the dark band, but due to the fixed frequency of the shift, water ripples or visual residues moving at a fixed frequency may appear on the displayed screen. To solve this problem, the number of shifted rows can be changed between different frames to change the frequency of the shift. For example, the spacing between the pulse signals P1 and P2 is A+1 rows in the frame period F_1, A+2 rows in the frame period F_2, A+4 rows in the frame period F_3, and A+7 rows in the frame period F_4. The spacing between each pulse signal can be arbitrarily adjusted according to system requirements, and is not limited to the examples proposed in this specification.

[0086] In order to further improve the visual effect, in one embodiment, the output timing of the pulse signal of the scan control signal PSCAN_STV can be randomly dispersed, thereby randomly dispersing the dark bands. Therefore, the interval between any two pulse signals has a random length.

[0087] Fig. 9 FIG. 1 is a timing diagram of a scanning timing of the scanning control signal PSCAN_STV according to an embodiment of the present invention. Fig. 9 FIG. 1 shows a series of light emission control signals EM and scanning control signals PSCAN_STV outputted in frame periods F_0 to F_N, and a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync and an initial voltage VinitN are also shown. Fig. 9 For convenience of explanation. Fig. 9As shown, the pulse signal P1 can be output in the same row within the frame period F_0 to F_N, and the other pulse signals P2 and P3 are output in a jittering manner, wherein the jittering time of these pulse signals P2 and P3 is random between the frame periods F_0 to F_N. The random jittering method can also improve the dark bands on the screen and avoid the problem of visual afterimage.

[0088] In addition, in the above embodiment, the scan control signal PSCAN_STV outputted during one frame period includes three pulse signals P1 to P3 to reset the light emitting components in the pixel three times, but the embodiment of the present invention is not limited thereto. In another embodiment, the scan control signal PSCAN_STV may also include four pulse signals to reset four times during one frame period, such as Fig.10 Similarly, as long as the intervals between the pulse signals P1 and P2 are changed between different frames, the output timing of the scan control signal PSCAN_STV in the subsequent frame period can generate time jitter, thereby generating time jitter in the scan signal PSCAN received by the pixels on the display screen 300. Fig.10 In the embodiment of the present invention, each pulse signal P1-P4 includes 2 pulses. In fact, in the embodiment of the present invention, each pulse signal of the scan control signal PSCAN_STV can be implemented by any number of pulses, which should not be used to limit the scope of the present invention.

[0089] In another embodiment, the interval between the pulse signals P2 and P3 (or even any subsequent pulse signals) may also be changed in a random manner. Fig.11 As shown, in addition to dynamically and randomly changing the spacing length between the pulse signals P1 and P2, the spacing length between the pulse signals P2 and P3 can also be dynamically and randomly changed, and the time after the last pulse signal P3 can be adjusted accordingly to maintain the overall frame period length fixed (or changed accordingly in response to the corridor length). In this way, the effect of dark band dispersion can be further enhanced.

[0090] In one embodiment, the adjustable range of the pulse signal can be adjusted according to the brightness setting of the display screen 300 (such as the display brightness value mentioned above). Therefore, if the output of the pulse signal has time jitter between different frame periods, the range of the time jitter can be controlled according to the brightness setting. For example, Fig.12 The timing diagram of the embodiment of the present invention for dispersing pulse signals based on different brightness settings. As mentioned above, the pulse signals P1-P3 of the scanning control signal PSCAN_STV should be included in the high pulse of the light-emitting control signal EM that stops emitting light, so as not to affect the picture display. The width and number of high pulses included in the light-emitting control signal EM during a frame period will change with the brightness setting.

[0091] Preferably, when the brightness of the display screen 300 decreases, the range of the time jitter can be increased. More specifically, when the brightness is lower, the period during which the light emitting control signal EM is at a high level is longer, so the width of the high pulse of the light emitting control signal EM is larger and / or the number of high pulses of the light emitting control signal EM is greater. Fig.12 For example, the light-emitting control signal EM under high brightness includes 3 high pulses; the light-emitting control signal EM under medium brightness includes 6 high pulses, and the high pulse width used to cover the pulse signals P1~P3 is larger; the light-emitting control signal EM under low brightness includes 18 high pulses, and the high pulse width used to cover the pulse signals P1~P3 is the largest.

[0092] More specifically, if Fig.12 As shown, in the case of high brightness, the pulse signals P1 to P3 should be included in the width W1 of the high pulse of the corresponding light-emitting control signal EM. If the spacing between the pulse signals P1 and P2 in the first scan control signal PSCAN_STV_1 is A rows, then in the subsequent scan control signal PSCAN_STV_X (X can be any positive integer other than 1), this spacing can be extended to a maximum of A+N rows (i.e., with a maximum delay of N rows), so that the pulse signal P2 is located in the range covered by the high pulse of the light-emitting control signal EM. In the case of medium brightness, the pulse signals P1 to P3 should be included in the width W2 of the high pulse of the corresponding light-emitting control signal EM, where the width W2 is greater than W1. If the spacing between the pulse signals P1 and P2 in the first scan control signal PSCAN_STV_1 is A rows, then in the subsequent scan control signal PSCAN_STV_X, this spacing can be extended to a maximum of A+M rows (i.e., with a maximum delay of M rows), so that the pulse signal P2 is located in the range covered by the high pulse of the light-emitting control signal EM. In the case of low brightness, the pulse signals P1-P3 should be included in the width W3 of the high pulse of the corresponding light emitting control signal EM, wherein the width W3 is greater than W2 and W1. If the spacing between the pulse signals P1 and P2 in the first scanning control signal PSCAN_STV_1 is A rows, then in the subsequent scanning control signal PSCAN_STV_X, this spacing can be extended to a maximum of A+O rows (i.e., with a maximum delay of O rows), so that the pulse signal P2 is within the range covered by the high pulse of the light emitting control signal EM. It should be noted that the parameters N, M and O can all be any positive integers, and under the brightness relationship of these three situations, the maximum delay will satisfy the relationship of O>M>N.

[0093] Similarly, the timing of the pulse signal P3 can also be controlled according to the corresponding light emitting control signal EM, that is, it is included in the high pulse of the light emitting control signal EM. In this way, due to the difference in the width of the high pulse of the light emitting control signal EM, the display driving circuit 310 can adjust the range of the jitter of the pulse signals P1-P3 under different brightness. In other words, the lower the brightness, the wider the high pulse of the light emitting control signal EM, so that the range of the jitter of the pulse signals P1-P3 is larger.

[0094] Generally speaking, the dark band phenomenon is more easily observed at low brightness. Therefore, when the brightness is set to be low, it is preferred to increase the pulse signal jitter range with a high pulse width of the light emitting control signal EM to enhance the dark band improvement effect. On the contrary, the dark band is less obvious at high brightness, and a smaller jitter range can achieve good results.

[0095] Fig.13 The figure is a schematic diagram of simulating the voltage offset of the node Node_A to generate dark bands when the scanning control signal PSCAN_STV has and does not have inter-frame jitter. From the formula (1) in the above paragraph, it can be seen that the voltage offset ΔV of the node Node_A is equivalent to the deviation of the display data VD, which changes the driving current I1 and affects the brightness. Therefore, it can be simulated as a change in grayscale to correspond to different brightness. Fig.13 As shown, the horizontal axis is the voltage offset ΔV on the node Node_A of multiple rows of pixels during a frame period, expressed in terms of brightness corresponding to the grayscale value, where the maximum voltage difference is, for example, 40mV. The vertical axis represents the situation of 20 or 30 consecutive frames (i.e., frame period), and the average grayscale is the average of these 20 or 30 frames, which is equivalent to the picture seen by the human eye.

[0096] like Fig.13 As shown in FIG. 1 , when the pulse signal of the scanning control signal is output at a fixed timing without inter-frame jitter, the voltage drop of the node Node_A appears at a fixed position, which is equivalent to a darker image due to an increase in the gray value, thereby forming an obvious dark band in a fixed area. When a 20-frame jitter method is adopted and the pulse signal is output at a timing delayed by one row in sequence during the 20 frames (such as Figure 6 The position of the dark band will correspond to the delay shift. After averaging over 20 frames, the brightness and darkness of the average grayscale changes become smoother. When a 30-frame jitter method is used and the pulse signal is output in a sequentially delayed sequence of one row during the 30 frames, the position of the dark band will correspond to the delay shift. After averaging over 30 frames, the position where the voltage drop of node Node_A occurs can be further dispersed, achieving a better dark band improvement effect. In this way, if the number of timing jitter frames used for the pulse signal is increased, the dark band improvement effect will be better. Fig.14The simulated picture content shown clearly shows the effect of improving dark bands.

[0097] As can be seen from the above, the method of dispersing / shifting / jittering the pulse signal of the scan control signal proposed in the embodiment of the present invention can greatly improve the voltage difference of the node Node_A in the pixel circuit, and the voltage difference of the node Node_A of the adjacent pixel rows becomes gentle, thereby improving the dark band problem. The node Node_A is a node of the light-emitting component coupled to the pixel, so the voltage offset or voltage difference of the node Node_A will affect the brightness of the pixel. This voltage offset or voltage difference can be reduced by dispersing the pulse signal of the scan control signal. In addition, since the position where the voltage difference of the node Node_A appears on each frame is not fixed, there is no problem of different long-term stress in a specific area (i.e., the dark band area), thereby improving the reliability of the display screen.

[0098] It is worth noting that the method of the present invention is not used to completely eliminate the dark bands caused by the variation of the initial voltage (such as VinitN), but to disperse the positions where the voltage difference of the node Node_A appears on different frames, so that the dark bands are staggered to reduce the impact of the dark bands on the visual effect. In some embodiments, since the average voltage difference of the node Node_A becomes gentle, this small voltage difference can be further compensated by pixel-level correction (Demura). Pixel-level correction is a compensation method commonly used in organic light-emitting diode panels. It can compensate for the slight brightness difference caused by the variation of components in the pixel circuit by adjusting the data voltage output to the display screen. Generally speaking, when the dark band is not dispersed, the brightness difference between the dark band area and other areas is usually too large, so it is difficult to process by pixel-level correction. In contrast, the present invention can first disperse the dark band by changing the output timing of the pulse signal in the scanning control signal, so that the average brightness difference at different positions on the display screen caused by the load variation of the initial voltage is reduced. When the picture is optimized to a certain extent, it is compensated by pixel-level correction to achieve further improvement.

[0099] The above operation of dispersing the dark band position can be summarized as a control process 150, such as Fig.15 The control process 150 may be implemented in a display driving circuit for controlling a display screen, such as Figure 3 The display driving circuit 310 used to control the display screen 300. Fig.15 As shown, the control process 150 includes the following steps:

[0100] Step 1502 : In a first frame period F_1 , output a scan control signal PSCAN_STV to the display screen 300 through a first timing setting.

[0101] Step 1504 : In a second frame period F_2 , output the scan control signal PSCAN_STV to the display screen 300 via a second timing setting different from the first timing setting.

[0102] According to the control process 150, the scan control signal PSCAN_STV with different timing settings can be converted into the scan signal PSCAN to be output to the pixels on the display screen 300, so as to disperse the dark bands on the display screen 300. The scan control signal PSCAN_STV with different timing settings and the scan signal PSCAN can be configured to include pulse signals output at different line times, and the detailed operation and change methods thereof can be referred to the description in the above paragraphs, which will not be repeated here.

[0103] It is worth noting that the purpose of the present invention is to propose a new display screen control method and its related display driving circuit, which can output a scanning control signal with inter-frame jitter to improve the dark band problem. Those skilled in the art can make modifications or changes accordingly, but are not limited to this. For example, in the above embodiment, since the light-emitting control signal and the scanning signal are both received by the P-type metal oxide semiconductor transistor in the pixel circuit, these signals are low-activity signals. In another embodiment, if part of the control signal of the pixel circuit is used to control the N-type metal oxide semiconductor transistor, these signals can be high-active signals, and the related implementation methods should also fall within the scope of the present invention.

[0104] In summary, the present invention can disperse the possible positions of dark bands on the display screen by changing the output timing of the scan control signal in multiple consecutive frames. The cause of the dark band is that the initial voltage used to reset the light-emitting component (such as node Node_A) has a load difference when the pulse signal shifts to the corridor area, causing the initial voltage received by the pixels located on a specific fixed row to be offset or drop, thereby generating horizontal dark bands at the positions of these rows. Therefore, the display driving circuit of the present invention can change the timing of the scan control signal used for the initial voltage to form jitter at the pulse signal output time point between different frame periods, thereby dynamically changing the position of the initial voltage offset. Under long-term display, the average voltage drop of the initial voltage for resetting the light-emitting component can be reduced, and the voltage offset between adjacent pixel rows is reduced to improve the phenomenon of dark bands. The above operation is mainly aimed at the initial voltage used to initialize the light-emitting component in the pixel circuit to avoid the offset or voltage drop of the initial voltage appearing in the pixels on the fixed row. Since the scan signal is also used to control the reset of the driving transistor (such as node Node_B), changing the output timing of the scan signal can also reduce the impact of the load variation of the source voltage of the driving transistor on the brightness.

[0105] Furthermore, the timing of the scan control signal can be adjusted in a sequential manner or dispersed in a random manner during multiple frames, as long as the position where the initial voltage offset occurs can be staggered. The method of changing the timing of the present invention can be applied to different brightness settings. Whether it is high brightness, medium brightness, or low brightness, the dark band problem can be improved by jittering the output timing of the scan control signal. In addition, a high pulse of a wider light control signal under low brightness can increase the interval range of the pulse signal adjustment to cope with the phenomenon that the dark band is more obvious under low brightness. The above method can be further combined with pixel-level correction compensation to enhance the effect of dark band dispersion.

[0106] In addition, the present invention can significantly improve the dark band problem by only adjusting the timing of the display driving circuit outputting the scanning control signal, without changing the structure of the display screen or adjusting the output level of the initial voltage. The constant output level of the initial voltage helps to control the constant voltage across the two ends of the light-emitting component, and can also maintain the response speed of data writing to avoid afterimages, and can also prevent the change of the initial voltage from affecting other non-dark band areas or causing other side effects, so as to avoid unexpected voltage / current variations and cause visual defects.

[0107] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for controlling a display screen, the display screen comprising a plurality of pixels, characterized in that: The method includes: Outputting a scanning control signal to the display screen during a plurality of frame periods; The scanning control signal has a first timing setting in a first frame period among the plurality of frame periods, and has a second timing setting in a second frame period among the plurality of frame periods; Wherein, the second timing setting is different from the first timing setting; Wherein, a plurality of scanning signals generated by the scanning control signal are respectively output to the plurality of pixels in sequence.

2. The method according to claim 1, characterized in that The plurality of scanning signals control the plurality of pixels to receive an initial voltage.

3. The method according to claim 2, characterized in that The initial voltage is output to a light emitting element of each pixel in the plurality of pixels according to the plurality of scanning signals.

4. The method according to claim 1, characterized in that The scan control signal is shifted in a plurality of channels corresponding to the plurality of pixels to generate the plurality of scan signals.

5. The method according to claim 1, characterized in that The scanning control signal includes a plurality of pulse signals located in each frame period of the plurality of frame periods.

6. The method according to claim 5, characterized in that In the first timing setting, there is a first spacing between a first pulse signal and a second pulse signal among the multiple pulse signals, and in the second timing setting, there is a second spacing between the first pulse signal and the second pulse signal, wherein the first spacing and the second spacing have different lengths.

7. The method according to claim 6, characterized in that Each of the first interval and the second interval has a random length.

8. The method according to claim 5, characterized in that Also includes: Outputting a light-emitting control signal to the display screen, wherein the light-emitting control signal has a first level for turning off a light-emitting component of the plurality of pixels; The plurality of pulse signals are output when the light emitting control signal is at the first level.

9. The method according to claim 5, characterized in that Each of the plurality of pulse signals includes one or more pulses.

10. The method according to claim 1, characterized in that The scanning control signal includes a plurality of pulse signals, and the output of a first pulse signal among the plurality of pulse signals has a time jitter between the plurality of frame periods.

11. The method according to claim 10, characterized in that The first pulse signal in a current frame period among the plurality of frame periods is outputted with a delay of a specific number of line times relative to the first pulse signal outputted in a previous frame period before the current frame period among the plurality of frame periods.

12. The method according to claim 10, characterized in that A range of the time jitter is controlled according to a brightness setting of the display screen.

13. The method according to claim 12, characterized in that As the brightness of the display screen decreases, the range of the time jitter increases.

14. A display driving circuit for controlling a display screen, the display screen comprising a plurality of pixels, characterized in that: The display driver circuit is used to: Outputting a scanning control signal to the display screen during a plurality of frame periods; The scanning control signal has a first timing setting in a first frame period among the plurality of frame periods, and has a second timing setting in a second frame period among the plurality of frame periods; Wherein, the second timing setting is different from the first timing setting; Wherein, a plurality of scanning signals generated by the scanning control signal are respectively output to the plurality of pixels in sequence.

15. The display driving circuit according to claim 14, characterized in that: The plurality of scanning signals control the plurality of pixels to receive an initial voltage.

16. The display driving circuit according to claim 15, characterized in that: The initial voltage is output to a light emitting element of each pixel in the plurality of pixels according to the plurality of scanning signals.

17. The display driving circuit according to claim 14, characterized in that: The scan control signal is shifted in a plurality of channels corresponding to the plurality of pixels to generate the plurality of scan signals.

18. The display driving circuit according to claim 14, characterized in that: The scanning control signal includes a plurality of pulse signals located in each frame period of the plurality of frame periods.

19. The display driving circuit according to claim 18, characterized in that: In the first timing setting, there is a first spacing between a first pulse signal and a second pulse signal among the multiple pulse signals, and in the second timing setting, there is a second spacing between the first pulse signal and the second pulse signal, wherein the first spacing and the second spacing have different lengths.

20. The display driving circuit according to claim 19, characterized in that: Each of the first interval and the second interval has a random length.

21. The display driving circuit according to claim 18, characterized in that: Also used to: Outputting a light-emitting control signal to the display screen, wherein the light-emitting control signal has a first level for turning off a light-emitting component of the plurality of pixels; The plurality of pulse signals are output when the light emitting control signal is at the first level.

22. The display driving circuit according to claim 18, characterized in that: Each of the plurality of pulse signals includes one or more pulses.

23. The display driving circuit according to claim 14, characterized in that: The scanning control signal includes a plurality of pulse signals, and the output of a first pulse signal among the plurality of pulse signals has a time jitter between the plurality of frame periods.

24. The display driving circuit according to claim 23, characterized in that: The first pulse signal in a current frame period among the plurality of frame periods is outputted with a delay of a specific number of line times relative to the first pulse signal outputted in a previous frame period before the current frame period among the plurality of frame periods.

25. The display driving circuit according to claim 23, characterized in that: A range of the time jitter is controlled according to a brightness setting of the display screen.

26. The display driving circuit according to claim 25, characterized in that: As the brightness of the display screen decreases, the range of the time jitter increases.

Images