Pixel circuit, display panel and display device

Abstract

The invention discloses a pixel circuit, a display panel and a display device. The pixel circuit comprises a first light-emitting control unit, a driving transistor and a compensation unit, the first end of the first light-emitting control unit is electrically connected with a first power supply signal end; the second end of the first light-emitting control unit, the first electrode of the driving transistor and the first end of the compensation unit are connected to a first node; the second end of the compensation unit is electrically connected with the compensation signal end; the control end of the first light-emitting control unit is electrically connected with a light-emitting control signal end; a light-emitting control signal of the light-emitting control signal end begins to generate first voltage jump at a first moment t1 and is kept at a first level in a first time period, a compensation signal of the compensation signal end begins to generate second voltage jump at a second moment t2 and is kept at a second level in a second time period, the first time period and the second time period are overlapped, t1 < = t2, and t2 < = t3. And the jump direction of the first voltage jump is opposite to the jump direction of the second voltage jump. According to the technical scheme, the high-frequency driving visual effect of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display, and in particular to a pixel circuit, a display panel and a display device. Background Art

[0002] With the development of display technology, organic light-emitting display panels are increasingly widely used in mobile phones, computers, televisions, car display panels, wearable devices and other display panels with display functions due to their advantages such as self-luminescence, low driving voltage, high luminous efficiency, fast response speed, light weight and high contrast.

[0003] However, the current organic light-emitting display panels still have the problem of poor uniformity of visual effects under high-frequency driving, which needs to be solved. Summary of the invention

[0004] The invention provides a pixel circuit, a display panel and a display device to improve the high-frequency driving visual effect of the display panel.

[0005] According to one aspect of the present invention, there is provided a pixel circuit, comprising: a first light emitting control unit, a driving transistor and a compensation unit;

[0006] The first end of the first light-emitting control unit is electrically connected to the first power signal end; the second end of the first light-emitting control unit, the first electrode of the driving transistor and the first end of the compensation unit are connected to the first node; the second end of the compensation unit is electrically connected to the compensation signal end; the control end of the first light-emitting control unit is electrically connected to the light-emitting control signal end;

[0007] The light-emitting control signal at the light-emitting control signal end undergoes a first voltage jump at the first moment t1 and remains at the first level in a first time period, the compensation signal at the compensation signal end undergoes a second voltage jump at the second moment t2 and remains at the second level in a second time period, the first time period at least partially overlaps with the second time period, t1≤t2, and the jumping direction of the first voltage jump is opposite to the jumping direction of the second voltage jump.

[0008] According to another aspect of the present invention, a display panel is provided, comprising the pixel circuit provided by any embodiment of the present invention.

[0009] According to another aspect of the present invention, a display device is provided, comprising the display panel provided by any embodiment of the present invention.

[0010] The technical solution of the embodiment of the present invention is to add a compensation unit so that the second end of the first light-emitting control unit, the first electrode of the driving transistor and the first end of the compensation unit are connected to the first node, the second end of the compensation unit is electrically connected to the compensation signal end, the control end of the first light-emitting control unit is electrically connected to the light-emitting control signal end, and the light-emitting control signal at the light-emitting control signal end is set to have a first voltage jump at the first moment t1 and remain at a first level in a first time period, and the compensation signal at the compensation signal end is set to have a second voltage jump at the second moment t2 and remain at a second level in a second time period, so that the first time period and the second time period at least partially overlap, t1≤t2, and The jumping direction of the first voltage jump is opposite to the jumping direction of the second voltage jump. In this way, the first voltage jump of the light-emitting control signal will have a coupling effect on the voltage of the first node. At the same time or thereafter, the second voltage jump of the compensation signal will have an opposite effect on the voltage of the first node, thereby offsetting the coupling effect of the first voltage jump on the voltage of the first node to a certain extent, improving the voltage stability of the first node, and thus improving the visual uniformity; in addition, since the first time period and the second time period at least partially overlap, it can ensure that the second voltage jump ends before the end of the first time period, thereby avoiding the second voltage jump from affecting the light-emitting stage.

[0011] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 It is a structural schematic diagram of a pixel circuit in the related art;

[0014] Figure 2 is with Figure 1 The corresponding driving timing diagram of the pixel circuit;

[0015] Figure 3 It is a schematic diagram of a local layout of a pixel circuit in the related art;

[0016] Figure 4 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0017] Figure 5 is with Figure 4 The corresponding driving timing diagram of the pixel circuit;

[0018] Figure 6 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0019] Figure 7 is with Figure 6 A corresponding driving timing diagram;

[0020] Figure 8 is with Figure 6 Another corresponding driving timing diagram;

[0021] Fig. 9 is with Figure 6 Another corresponding driving timing diagram;

[0022] Fig.10 is with Figure 6 Another corresponding driving timing diagram;

[0023] Fig.11 is with Figure 6 Another corresponding driving timing diagram;

[0024] Fig.12 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0025] Fig.13 is with Fig.12 A corresponding driving timing diagram;

[0026] Fig.14 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0027] Fig.15 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0028] Fig.16 yes Fig.15 A schematic diagram of the structure of the light-emitting driving unit;

[0029] Fig.17 is with Fig.16 A corresponding working timing diagram of a light-emitting driving unit;

[0030] Fig.18 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0032] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0033] First of all, it should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. In addition, the shapes and sizes of the components in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the content of the present invention.

[0034] In an organic light-emitting display panel, the pixel circuit is the core for controlling the light-emitting state of the light-emitting device. Figure 1 is a structural schematic diagram of a pixel circuit in the related art. Figure 2 is with Figure 1 The corresponding pixel circuit driving timing diagram, combined with Figure 1 and Figure 2As shown, the pixel circuit includes a data writing unit, a first light emitting control unit, a second light emitting control unit, a bias adjusting unit and a driving transistor M0, wherein a first end of the data writing unit is electrically connected to a data signal end for receiving a data signal DATA, a first end of the first light emitting control unit is electrically connected to a first power signal end PVDD, a first end of the bias adjusting unit is electrically connected to a bias adjusting signal end for receiving a bias adjusting signal DVH, a second end of the first light emitting control unit, a second end of the data writing unit, a second end of the bias adjusting unit and a first end of the driving transistor M0 are connected to a first node N1, a second end of the driving transistor M0 is electrically connected to a first end of the second light emitting control unit, a second end of the second light emitting control unit is electrically connected to an anode of a light emitting element OLED, a cathode of the light emitting element OLED is electrically connected to a second power signal end PVEE (a voltage of the second power signal end PVEE is less than a voltage of the first power signal end PVDD), a control end of the driving transistor M0 is electrically connected to a second node N2, and control ends of the first light emitting control unit and the second light emitting control unit are electrically connected to a light emitting control signal end respectively for receiving a light emitting control signal EMIT. The pixel circuit adopts PWM (Pulse Width Modulation) working mode. Specifically, one frame of the pixel circuit working process includes a pre-stage and a holding stage, wherein the pre-stage does not emit light, and the holding stage includes multiple alternating light-emitting stages and non-light-emitting stages. In the holding stage, the light-emitting duration of the entire holding stage is adjusted by adjusting the duration of multiple light-emitting stages, thereby adjusting the light-emitting brightness of this frame.

[0035] Figure 3 It is a local layout diagram of a pixel circuit in the related art, referring to Figure 3 In the layout design of the pixel circuit, due to the cross-line design, the light-emitting control signal line EM for transmitting the light-emitting control signal EMIT inevitably overlaps with the first node N1. Therefore, there is a parasitic capacitance between the light-emitting control signal line and the first node N1, and the voltage change on the light-emitting control signal line will affect the voltage of the first node N1. Based on this, referring to Figure 2 As shown, in the high-frequency PWM mode (the frequency of the light-emitting control signal EMIT is relatively high), due to the parasitic capacitance between the light-emitting control signal line and the first node, the voltage VN1 of the first node N1 will be pulled up a little bit under the coupling influence of the rising edge of the EMIT signal each time, resulting in unstable voltage of the first node N1, and differences in voltage of the first node N1 between pixels, which in turn leads to differences in gate-source voltage difference Vgs (Vgs=VN2-VN1) of the driving transistor M0 between pixels during the light-emitting stage, that is, differences in light-emitting current, resulting in inconsistent brightness between pixels and deterioration of visual uniformity.

[0036] To solve this problem, an embodiment of the present invention provides a pixel circuit, which includes a first light-emitting control unit, a driving transistor and a compensation unit; the first end of the first light-emitting control unit is electrically connected to the first power signal end; the second end of the first light-emitting control unit, the first electrode of the driving transistor and the first end of the compensation unit are connected to the first node; the second end of the compensation unit is electrically connected to the compensation signal end; the control end of the first light-emitting control unit is electrically connected to the light-emitting control signal end; the light-emitting control signal at the light-emitting control signal end starts to undergo a first voltage jump at a first moment t1 and remains at a first level within a first time period, the compensation signal at the compensation signal end starts to undergo a second voltage jump at a second moment t2 and remains at a second level within a second time period, the first time period and the second time period at least partially overlap, t1≤t2, and the jumping direction of the first voltage jump is opposite to the jumping direction of the second voltage jump.

[0037] With the above scheme, since the second moment t2 when the compensation signal starts to undergo the second voltage jump coincides with the first moment when the light-emitting control signal starts to undergo the first voltage jump, or the second moment t2 when the compensation signal starts to undergo the second voltage jump is located after the first moment t1 when the light-emitting control signal starts to undergo the first voltage jump, and the second level holding time period (second time period) after the second voltage jump overlaps at least partially with the first level holding time period (first time period) after the first voltage jump, and the jumping direction of the second voltage jump is opposite to the jumping direction of the first voltage jump, the voltage influence of the second voltage jump of the compensation signal on the first node can be offset by at least part of the voltage influence of the first voltage jump of the light-emitting control signal on the first node, thereby improving the voltage stability of the first node, and further improving the visual uniformity, and at the same time, it can also avoid the second voltage jump of the compensation signal from affecting the light-emitting stage.

[0038] The above is the core idea of ​​the present invention. The technical scheme of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0039] Figure 4 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention, Figure 5 is with Figure 4 The corresponding pixel circuit driving timing diagram is as follows: Figure 4 and Figure 5As shown, the pixel circuit 10 provided by the embodiment of the present invention includes a first light-emitting control unit 11, a driving transistor M0 and a compensation unit 12; the first end of the first light-emitting control unit 11 is electrically connected to the first power signal end PVDD; the second end of the first light-emitting control unit 11, the first electrode of the driving transistor M0 and the first end of the compensation unit 12 are connected to the first node N1; the second end of the compensation unit 12 is electrically connected to the compensation signal end for receiving the compensation signal XP; the control end of the first light-emitting control unit 11 is electrically connected to the light-emitting control signal end for receiving the light-emitting control signal EMIT; the light-emitting control signal EMIT at the light-emitting control signal end starts to undergo a first voltage jump J1 at a first moment t1 and remains at a first level V1 in a first time period (T1), the compensation signal XP at the compensation signal end starts to undergo a second voltage jump J2 at a second moment t2 and remains at a second level V2 in a second time period (T2), the first time period (T1) and the second time period (T2) at least partially overlap, t1≤t2, and the jump direction of the first voltage jump J1 is opposite to the jump direction of the second voltage jump J2. Wherein, T1 represents the duration of the first time period, and T2 represents the duration of the second time period.

[0040] Reference Figure 5 As described above, in the PWM working mode, the working process of the pixel circuit includes a pre-stage and a holding stage, and the holding stage includes a plurality of alternating light-emitting stages H1 and non-light-emitting stages H2. Figure 4 As shown, the pixel circuit 4 generally further includes a second light-emitting control unit 14. The control terminals of the first light-emitting control unit 11 and the second light-emitting control unit 14 are both electrically connected to the light-emitting control signal terminal, and are used to receive the light-emitting control signal EMIT. The first light-emitting control unit 11 and the second light-emitting control unit 14 are turned on and off under the control of the light-emitting control signal EMIT: when the first light-emitting control unit 11 and the second light-emitting control unit 14 are turned on, the light-emitting stage H1 is entered, and when the first light-emitting control unit 11 and the second light-emitting control unit 14 are turned off, the non-light-emitting stage H2 is entered. Therefore, the light-emitting control signal EMIT controls the transition between the light-emitting stage H1 and the non-light-emitting stage H2.

[0041] Reference Figure 5 The above-mentioned first voltage jump J1 generally refers to the voltage jump that the light-emitting control signal EMIT needs to undergo when the light-emitting stage H1 changes to the non-light-emitting stage H2. The first moment t1 generally refers to the moment when the first voltage jump J1 begins to occur, and does not represent a specific moment. The first time period (T1) generally refers to the time period during which the voltage of the light-emitting control signal EMIT remains at the first level V1 after the first voltage jump J1 is completed. It can be understood that the first time period (T1) corresponds to the non-light-emitting stage H2.

[0042] Based on the above, in the high-frequency PWM mode, the frequency of the light-emitting control signal EMIT is relatively high. Due to the parasitic capacitance between the light-emitting control signal line and the first node N1, each time the light-emitting control signal EMIT undergoes a first voltage jump J1, a coupling effect is generated on the voltage of the first node N1. In this way, the multiple coupling effects are superimposed, resulting in an unstable voltage at the first node N1, which in turn leads to a difference in the gate-source voltage difference of the driving transistor M0, that is, a difference in the light-emitting current, resulting in inconsistent brightness between pixels and deterioration of visual uniformity.

[0043] To solve this problem, the present embodiment provides a compensation unit 12 in the pixel circuit, so that two ends of the compensation unit 12 are electrically connected to the first node N1 and the compensation signal end, respectively, for receiving the compensation signal XP from the compensation signal end. Figure 5 , the compensation signal XP begins to undergo a second voltage jump J2 at the second moment t2 and remains at the second level V2 in the second time period (T2), the first time period (T1) and the second time period (T2) at least partially overlap, and the jumping direction of the first voltage jump J1 is opposite to the jumping direction of the second voltage jump J2.

[0044] The second voltage jump J2 in the compensation signal XP is set corresponding to the first voltage jump J1 in the light emitting control signal EMIT. In other words, every time the light emitting control signal EMIT has a first voltage jump J1, the compensation signal XP has a second voltage jump J2. Moreover, the jump direction of the second voltage jump J2 is opposite to the jump direction of the first voltage jump J1.

[0045] The second time t2 generally refers to the time when the second voltage jump J2 begins to occur, and does not represent a specific time. The above t1≤t2 can be understood as the second time t2 coincides with the first time t1 (at this time, t2=t1), or the second time t2 is located after the first time t1 (at this time, t2>t1). Figure 5 Only t2>t1, that is, the moment when the compensation signal XP starts to have the second voltage jump J2 (the second moment t2) is located after the moment when the light-emitting control signal EMIT starts to have the first voltage jump J1 (the first moment t1) is used as an example for illustration. In other embodiments, t1=t2 can also be set, that is, the moment when the compensation signal XP starts to have the second voltage jump J2 coincides with the moment when the light-emitting control signal EMIT starts to have the first voltage jump J1.

[0046] The second time period (T2) at least partially overlaps with the first time period (T1), which may be the case that only a portion of the second time period (T2) and the first time period (T1) overlap, or the second time period (T2) and the first time period (T1) overlap completely, that is, the two overlap. Figure 5Since t1≤t2, and the first time period (T1) and the second time period (T2) at least partially overlap, in this embodiment, the second voltage jump J2 starts at the first moment t1 or starts after the first moment t1, and ends before the end moment of the first time period (T1).

[0047] The compensation unit 12 may be any device or device combination that can transmit the voltage change of the compensation signal XP to the first node so that the voltage of the first node N1 changes accordingly. The embodiment of the present invention is not limited to this, as long as the above functions can be achieved.

[0048] In response to the first voltage jump J1 of the light-emitting control signal EMIT, the embodiment of the present invention sets a compensation unit 12 so that the compensation signal XP received by it starts to undergo a second voltage jump J2 at the second moment t2, and sets t2≥t1 (the starting moment of the first voltage jump), and the jumping direction of the first voltage jump J1 is opposite to the jumping direction of the second voltage jump J2. In this way, the first voltage jump J1 of the light-emitting control signal EMIT will have a coupling effect on the voltage of the first node N1. At the same time or thereafter, the second voltage jump J2 of the compensation signal XP will have an opposite effect on the voltage of the first node N1, thereby offsetting the coupling effect of the first voltage jump on the voltage of the first node to a certain extent, improving the voltage stability of the first node, and further improving the visual uniformity.

[0049] In addition, refer to Figure 5 , after the light-emitting control signal EMIT is maintained at the first level V1 in the first time period (T1), a third voltage jump J3 occurs, and then the light-emitting stage H1 is entered again. In this embodiment, the compensation signal XP is set to be maintained at the second level V2 in the second time period (T2) after the second voltage jump J2 occurs, and t1≤t2 is ensured, and the first time period (T1) and the second time period (T2) at least partially overlap, so that the second voltage jump J2 can be ensured to start at the first moment t1 or after the first moment t1, and end before the end moment of the first time period (T1), so that the second voltage jump J2 can be prevented from affecting the light-emitting stage H1.

[0050] In summary, the embodiment of the present invention adds a compensation unit, so that the second end of the first light-emitting control unit, the first electrode of the driving transistor and the first end of the compensation unit are connected to the first node, the second end of the compensation unit is electrically connected to the compensation signal end, the control end of the first light-emitting control unit is electrically connected to the light-emitting control signal end, and the light-emitting control signal at the light-emitting control signal end is set to have a first voltage jump at the first moment t1 and remain at the first level in the first time period, and the compensation signal at the compensation signal end is set to have a second voltage jump at the second moment t2 and remain at the second level in the second time period, so that the first time period and the second time period at least partially overlap, t1≤t2, and the first The jumping direction of the voltage jump is opposite to the jumping direction of the second voltage jump. In this way, the first voltage jump of the light-emitting control signal will have a coupling effect on the voltage of the first node. At the same time or thereafter, the second voltage jump of the compensation signal will have an opposite effect on the voltage of the first node, thereby offsetting the coupling effect of the first voltage jump on the voltage of the first node to a certain extent, improving the voltage stability of the first node, and thus improving the visual uniformity; in addition, since the first time period and the second time period at least partially overlap, it can ensure that the second voltage jump ends before the end of the first time period, thereby avoiding the second voltage jump from affecting the light-emitting stage.

[0051] Figure 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention, Figure 7 is with Figure 6 A corresponding driving timing diagram, such as Figure 6 and Figure 7 As shown, optionally, the first light emitting control unit 11 includes a first light emitting control transistor M1, and the first light emitting control transistor M1 is a P-type transistor. Figure 6 and Figure 7 As shown, optionally, the first level V1 is a high level, the second level V2 is a low level, the duration of the first time period is T1, the duration of the second time period is T2, and T1-T2≥0.

[0052] Combination Figure 6 and Figure 7When the first light-emitting control transistor M1 is a P-type transistor, when the light-emitting control signal EMIT is at a low level, the first light-emitting control transistor M1 is turned on and enters the light-emitting stage H1. When the light-emitting control signal EMIT is at a high level, the first light-emitting control transistor M1 is turned off and enters the non-light-emitting stage H2. Therefore, the first level V1 is a high level, and the jump direction of the first voltage jump J1 is from a low level to a high level. The light-emitting control signal EMIT starts to rise in voltage at the first moment t1, so that the voltage of the first node N1 is pulled up under its coupling influence. Since the jumping direction of the second voltage jump J2 is opposite to the jumping direction of the first voltage jump J1, the second level V2 is a low level. In this embodiment, the compensation signal XP is set to start voltage drop at the second moment t2 (t2≥t1), that is, the second voltage jump J2 occurs. Under the action of the compensation unit 12, the voltage of the first node N1 can be pulled down, thereby offsetting the coupling effect of the first voltage jump of the light-emitting control signal on the voltage of the first node to a certain extent, improving the voltage stability of the first node, and improving the visual effect uniformity. Since the first time period (T1) and the second time period (T2) at least partially overlap, the end time of the second voltage jump J2 is before the end time of the first time period (T1), thereby avoiding the second voltage jump J2 from affecting the light-emitting stage H1.

[0053] The first time period and the second time period at least partially overlap, which can be specifically reflected in that the difference between the duration of the first time period and the duration of the second time period is greater than or equal to zero, that is, T1-T2≥0. When the two partially overlap, T1-T2>0 can be selected, and when the two overlap, T1-T2=0 can be selected. Figure 7 After the compensation signal XP remains at the second level V2 in the second time period, a fourth voltage jump J4 in the opposite direction to the second voltage jump J2 needs to occur before the next second voltage jump J2 can be performed. In this embodiment, by setting T1-T2≥0, it is beneficial to ensure that the third voltage jump J3 of the light-emitting control signal EMIT coincides with the fourth voltage jump J4 of the compensation signal XP, thereby avoiding the fourth voltage jump J4 of the compensation signal XP from affecting the light-emitting stage H1.

[0054] As a feasible implementation method, refer to Figure 7 , optionally, when t1<t2, T1-T2=t2-t1.

[0055] In this way, after the first voltage jump J1 of the light-emitting control signal EMIT produces a coupling effect on the voltage of the first node N1, the second voltage jump J2 of the compensation signal XP produces an opposite effect on the voltage of the first node N1, thereby offsetting the coupling effect of the first voltage jump on the voltage of the first node to a certain extent, improving the voltage stability of the first node, and further improving the visual uniformity; and because T1-T2=t2-t1>0, the fourth voltage jump J4 of the compensation signal XP can coincide with the occurrence time of the third voltage jump J3 of the light-emitting control signal EMIT, thereby avoiding the fourth voltage jump J4 of the compensation signal XP from affecting the light-emitting stage H1.

[0056] As another possible implementation, Figure 8 is with Figure 6 For the corresponding driving timing diagram, refer to Figure 8 , optionally, T1=T2, t1=t2.

[0057] In this configuration, while the first voltage jump J1 of the light-emitting control signal EMIT produces a coupling effect on the voltage of the first node N1, the second voltage jump J2 of the compensation signal XP produces an opposite effect on the voltage of the first node N1, thereby offsetting the coupling effect of the first voltage jump on the voltage of the first node to a certain extent, improving the voltage stability of the first node, and further improving the visual effect uniformity; and because T1=T2, the fourth voltage jump J4 of the compensation signal XP can coincide with the occurrence time of the third voltage jump J3 of the light-emitting control signal EMIT, thereby avoiding the fourth voltage jump J4 of the compensation signal XP from affecting the light-emitting stage H1.

[0058] Reference Figure 7 or Figure 8 Optionally, the light emitting control signal EMIT has a third level V3 in the third time period (T3), the third level V3 is a low level, the third time period (T3) is before the first time period (T1), the compensation signal XP has a fourth level V4 in the fourth time period (T4), the fourth level V4 is a high level, the fourth time period (T4) is before the second time period (T2), and the fourth time period (T4) at least partially overlaps with the third time period (T3). Wherein, T3 represents the duration of the third time period, and T4 represents the duration of the fourth time period.

[0059] The third time period (T3) corresponds to the light emitting stage H1. Taking the first light emitting control transistor M1 as a P-type transistor as an example, when the light emitting control signal EMIT is at a low level (third level V3), the first light emitting control transistor M1 is turned on and is in the light emitting stage H1. Figure 7 , the first voltage jump J1 of the light emitting control signal EMIT jumps from the third level V3 to the first level V1.

[0060] Reference Figure 7 The second voltage jump J2 of the compensation signal XP jumps from the fourth level V4 to the second level V2. Since the jump direction of the second voltage jump J2 is opposite to that of the first voltage jump J1, the fourth level V4 is a high level and the second level V2 is a low level.

[0061] It should be noted that the above-mentioned "high level" and "low level" are relative concepts in the same signal. For example, in the light-emitting control signal EMIT, the first level V1 is a high level relative to the third level V3, and the third level V3 is a low level relative to the first level V1; in the compensation signal XP, the second level V2 is a low level relative to the fourth level V4, and the fourth level V4 is a high level relative to the second level V2. Although the first level V1 and the fourth level V4 are both "high levels", they belong to different signals. Therefore, this embodiment does not limit the magnitude relationship between the first level V1 and the fourth level V4. Similarly, although the third level V3 and the second level V2 are both "low levels", they belong to different signals. Therefore, this embodiment does not limit the magnitude relationship between the third level V3 and the second level V2.

[0062] In the holding stage, the voltage of the light-emitting control signal EMIT alternates between the third level V3 and the first level V1 to realize the alternation of the light-emitting stage H1 and the non-light-emitting stage H2. Specifically, after the first voltage jump J1, the voltage of the light-emitting control signal EMIT jumps from the third level V3 to the first level V1, and after the third voltage jump J3, the voltage of the light-emitting control signal EMIT jumps from the first level V1 to the third level V3. Correspondingly, in order to make the compensation signal XP have a second voltage jump J2 corresponding to each first voltage jump J1, the voltage of the compensation signal XP needs to alternate between the fourth level V4 and the second level V2. In this embodiment, by setting the third time period (T3) corresponding to the third level V3 to at least partially overlap with the fourth time period (T4) corresponding to the fourth level V4, and the first time period (T1) corresponding to the first level V1 to at least partially overlap with the second time period (T2) corresponding to the second level V2, it is possible to ensure that the start time (second time t2) of the second voltage jump J2 is not earlier than the first time t1, and the end time of the second voltage jump J2 is before the end time of the first time period (T1). While improving the voltage stability of the first node N1 and improving the uniformity of visual effects, the second voltage jump J2 can be prevented from affecting the light-emitting stage H1.

[0063] Further, the absolute value of the difference between the first level V1 and the third level V3 |V1-V3| and the absolute value of the difference between the second level V2 and the fourth level V4 |V2-V4| can optionally satisfy:

[0064] -2V≤|V1-V3|-|V2-V4|≤2V.

[0065] Among them, |V1-V3| represents the voltage jump amplitude of the first voltage jump J1, and |V2-V4| represents the voltage jump amplitude of the second voltage jump J2. At present, the difference between the high level and the low level of the electrical signal in the display panel is usually as high as more than ten volts to twenty volts. In this embodiment, by setting the difference between the voltage jump amplitude of the first voltage jump J1 and the voltage jump amplitude of the second voltage jump J2 to be within 2V, it is beneficial to reduce the coupling effect of the first voltage jump of the light-emitting control signal on the first node to a large extent through the second voltage jump of the compensation signal. In addition, by setting the difference between the voltage jump amplitude of the first voltage jump J1 and the voltage jump amplitude of the second voltage jump J2 to have a certain range, the adjustment space can be larger and the design difficulty can be reduced.

[0066] Reference Figure 6 Optionally, the compensation unit 12 includes a first capacitor Cx, a gate of the first light emission control transistor M1 is electrically connected to the light emission control signal terminal (EMIT), a first plate of the first capacitor Cx is electrically connected to the first node N1, and a second plate of the first capacitor Cx is electrically connected to the compensation signal terminal (XP). The first node N1 is connected to the compensation signal terminal through the first capacitor Cx, and the voltage change of the compensation signal XP can be transmitted to the first node N1 through the first capacitor Cx, so that the voltage of the first node changes, thereby achieving the above-mentioned design purpose.

[0067] It should be noted that Figure 6 The pixel circuit shown is only for illustration and not for limitation. Any pixel circuit design in which the voltage jump of the light emitting control signal EMIT has a coupling effect on the voltage of the first node N1 can be improved by using the solution of the embodiment of the present invention. Figure 6 The first light-emitting control transistor M1 is a P-type transistor to design the light-emitting control signal and the compensation signal. In other embodiments, if the first light-emitting control transistor M1 is an N-type transistor, the voltage of the light-emitting control signal can be adaptively adjusted, and the voltage adjustment of the compensation signal can be adaptively adjusted, which will not be repeated here.

[0068] Reference Figure 6 and Fig. 9 When the first capacitor Cx is used as the compensation unit 12, the capacitance value of the first capacitor Cx is C1, and the capacitance value of the parasitic capacitor is C0. The parasitic capacitance is a parasitic capacitance between the first node and a light emitting control signal line for transmitting a light emitting control signal.

[0069] Among them, the capacitance value of the parasitic capacitor can be calculated based on the distance and overlapping area of ​​the two plates constituting the parasitic capacitor, and the dielectric constant of the dielectric layer between the plates. The capacitance value of the first capacitor is calculated in the same way. Exemplarily, a compensation signal line for transmitting a compensation signal can be added to the display panel, and the overlapping portion of the compensation signal line and the first node constitutes the first capacitor. Exemplarily, the compensation signal line and the light-emitting control signal line can be set in the same layer or in different layers, and the embodiment of the present invention is not limited to this.

[0070] As described above, due to the existence of parasitic capacitance, the voltage jump of the light emitting control signal EMIT on the light emitting control signal line will cause the voltage change of the first node. Specifically, the voltage change value of the first node caused by the light emitting control signal EMIT is Wherein, C represents the total capacitance at the second node, ΔV0 represents the voltage jump amplitude of the first voltage jump J1, and according to the above description, ΔV0=|V1-V3|.

[0071] Furthermore, in this embodiment, the compensation unit 12 includes a first capacitor Cx, so that the voltage change of the compensation signal XP can be transmitted to the first node through the first capacitor Cx, so that the voltage of the first node changes. Specifically, the voltage change value of the first node caused by the compensation signal XP is Wherein, C represents the total capacitance at the second node, ΔV1 represents the voltage jump amplitude of the second voltage jump J2, and according to the above description, ΔV1=|V2-V4|.

[0072] Furthermore, since the voltage jump direction of the compensation signal XP is opposite to the voltage jump direction of the light emitting control signal, when ΔV E =ΔV X When , the influence of the voltage jump of the light emitting control signal EMIT on the voltage stability of the first node can be basically completely offset, so there is Right now

[0073]

[0074] In one embodiment, C0=C1 can be optionally designed. In this case, ΔV1=ΔV0, that is, |V1-V3|=|V2-V4|. Further, optionally, at any moment, the voltage of the compensation signal XP and the voltage of the light-emitting control signal EMIT are inverse numbers of each other, such as Figure 8 .

[0075] If C0≠C1, then ΔV1≠ΔV0 can be designed, and this is not limited in the embodiment of the present invention. Fig. 9 , Fig. 9 is with Figure 6Corresponding to another driving timing diagram, in another embodiment, ΔV1<ΔV0 can be selected, which is applicable to the case where C1>C0. Further, referring to the above description, when ΔV1<ΔV0, |V1-V3|-|V2-V4|≥-2V can be selected.

[0076] In addition, refer to Fig.10 , Fig.10 is with Figure 6 Corresponding to another driving timing diagram, in another embodiment, ΔV1>ΔV0 can be selected, which is applicable to the case where C1<C0. Further, referring to the above description, when ΔV1>ΔV0, |V1-V3|-|V2-V4|≤2V can be selected.

[0077] also, Fig.11 is with Figure 6 Another corresponding driving timing diagram is as follows: Fig.11 As shown, in one embodiment, optionally, within the fifth time period, the voltage of the compensation signal remains unchanged, for example, maintained at the fourth level; wherein the fifth time period overlaps with both the pre-stage and the first third time period T3 of the holding stage, and the end moment of the fifth time period coincides with the first second moment t2 in the holding stage.

[0078] Combination Figure 6 and Fig.11 After the pre-stage is over, the light emitting control signal EMIT undergoes a third voltage jump J3. Since the voltage of the first power signal terminal PVDD is written into the first node N1 at this time, the first node N1 is charged, thereby weakening or even eliminating the influence of the third voltage jump J3 of the light emitting control signal EMIT on the voltage of the first node N1 to a certain extent. Therefore, it is not necessary to offset it through the compensation signal. The compensation signal can be set to maintain a voltage unchanged in the fifth time period t5 corresponding to the first second moment t2 in the pre-stage to the holding stage, for example, maintaining the fourth level V4.

[0079] In other embodiments, reference Figure 7-10 , the optional compensation signal XP is maintained at the second level V2 in the pre-stage. At this time, each time the light-emitting control signal EMIT performs a voltage jump, the compensation signal XP performs a voltage jump in the opposite direction. Specifically, the light-emitting control signal performs a third voltage jump J3, the compensation signal XP performs a fourth voltage jump J4, the light-emitting control signal EMIT performs a first voltage jump J1, and the compensation signal XP performs a second voltage jump J2.

[0080] Figure 6 Based on the 8T1C (8 transistors and 1 storage capacitor) pixel circuit, a first capacitor Cx is added, and the first capacitor is connected between the first node N1 and the compensation signal terminal (XP). Figure 3In the 8T1C pixel circuit, a forward parasitic capacitor is formed between the first node N1 and the light emitting control signal line EM. By adopting the solution of the embodiment of the present invention, the influence of the parasitic capacitor on the voltage stability of the first node can be eliminated, thereby improving the visual uniformity.

[0081] Combine the following Figure 6 and Figure 7 , briefly describe the structure of the 8T1C pixel circuit and its working process in the pre-stage. Figure 6 and Figure 7 As shown, the pixel circuit also includes a data writing unit 13, a second light emitting control unit 14 and a bias adjustment unit 15, the data writing unit 13 includes a data writing transistor M2, the second light emitting control unit 14 includes a second light emitting control transistor M3, the bias adjustment unit 15 includes a bias adjustment transistor M7, and the pixel circuit also includes an initialization transistor M4, a threshold compensation transistor M5, a reset transistor M6 and a storage capacitor Cst. The first end of the first light-emitting control transistor M1 is electrically connected to the first power signal terminal (PVDD); the first end of the data writing transistor M2 is electrically connected to the data signal terminal (DATA); the first end of the bias adjustment transistor M7 is electrically connected to the bias adjustment signal terminal (DVH); the second end of the data writing transistor M2, the second end of the first light-emitting control transistor M1, the second end of the bias adjustment transistor M7 and the first end of the driving transistor M0 are connected to the first node N1; the first end of the initialization transistor M4 is electrically connected to the initialization signal terminal (VREF1); the first end of the threshold compensation transistor M5 is electrically connected to the second end of the driving transistor M0; the second end of the initialization transistor M4, the control terminal (gate) of the driving transistor M0 and the second end of the threshold compensation transistor M5 are connected to the second node N2; the second end of the second light-emitting control transistor M3 is electrically connected to the first node N1; the first end of the initialization transistor M4 is electrically connected to the initialization signal terminal (VREF1); the first end of the threshold compensation transistor M5 is electrically connected to the second end of the driving transistor M0; the second end of the initialization transistor M4, the control terminal (gate) of the driving transistor M0 and the second end of the threshold compensation transistor M5 are connected to the second node N2; The first end is electrically connected to the second end of the driving transistor M0, the second end of the second light-emitting control transistor M3 is electrically connected to the anode of the light-emitting element D, and the cathode of the light-emitting element D is electrically connected to the second power signal terminal (PVEE); the first end of the reset transistor M6 is electrically connected to the reset signal terminal VREF2, and the second end of the reset transistor M6 is electrically connected to the anode of the light-emitting element D; the control end of the initialization transistor M4 is electrically connected to the first scanning signal terminal (S1N), the control end of the threshold compensation transistor M5 is electrically connected to the second scanning signal terminal (S2N), the control end of the data writing transistor M2 is electrically connected to the third scanning signal terminal SP, and the control end of the reset transistor M6 and the control end of the bias adjustment transistor M7 are electrically connected to the fourth scanning signal terminal SP*; the storage capacitor Cst is connected between the first power signal terminal (PVDD) and the second node N2.

[0082] In the pre-stage, the light emitting control signal EMIT is an invalid pulse, and the first light emitting control transistor M1 and the second light emitting control transistor M3 are turned off under the action of the light emitting control signal EMIT, and the light emitting element D does not emit light.

[0083] In the pre-stage, when the first scanning signal S1N of the first scanning signal end is in the enabled state (high level), the initialization transistor M4 is turned on under the control of the first scanning signal S1N, and the initialization signal VREF1 of the initialization signal end is written to the gate of the driving transistor M0 (i.e., the second node N2), and the gate of the driving transistor M0 is initialized. When the second scanning signal S2N of the second scanning signal end is in the enabled state (high level), the threshold compensation transistor M5 is turned on under the control of the second scanning signal S2N, and the threshold compensation is performed on the driving transistor M0. When the third scanning signal SP of the third scanning signal end is in the enabled state (low level), the data writing transistor M2 is turned on under the control of the third scanning signal SP, and the data signal DATA is written to the gate of the driving transistor M0. When the fourth scanning signal SP* at the fourth scanning signal end is in the enabled state (low level), the reset transistor M6 is turned on under the control of the fourth scanning signal SP*, and the reset signal VREF2 is written to the anode of the light-emitting element D to reset the anode of the light-emitting element D. In addition, the bias adjustment transistor M7 is turned on under the control of the fourth scanning signal SP*, and the bias adjustment signal DVH is used to adjust the bias state of the driving transistor M0 to solve the problem of screen flickering caused by the threshold voltage offset of the driving transistor M0 in the low-frequency mode.

[0084] It should be noted that Figure 7 In the timing of the pre-stage shown, the order of the enabling states of the first scanning signal S1N, the second scanning signal S2N, the third scanning signal SP and the fourth scanning signal SP* is only for illustration and can be adjusted as required in other embodiments, which is not particularly limited in the embodiments of the present invention.

[0085] also, Fig.12 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention, Fig.13 is with Fig.12 A corresponding driving timing diagram, Fig.12 and Figure 6 The difference is that the bias adjustment transistor M7 is not provided. Fig.12On the basis of the 7T1C (7 transistors and 1 storage capacitor) pixel circuit, a first capacitor Cx is added, and the first capacitor is connected between the first node N1 and the compensation signal terminal (XP). The structure and working principle of the 7T1C pixel circuit are not described here. In the layout design of the 7T1C pixel circuit, the light-emitting control signal line and the active layer form a lateral parasitic capacitor. The solution of the embodiment of the present invention can eliminate the influence of the parasitic capacitor on the voltage stability of the first node, thereby improving the uniformity of visual effects.

[0086] It should be noted that Fig.13 This is only a schematic diagram of a design method for the compensation signal XP. Other implementations can refer to the above Figure 8-Figure 11 The description of the relevant content will not be repeated here.

[0087] Based on the same inventive concept, an embodiment of the present invention further provides a display panel. Fig.14 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention, such as Fig.14 As shown, the display panel 100 includes the pixel circuit 10 provided by any embodiment of the present invention, and thus has the same beneficial effects as the above-mentioned pixel circuit, which will not be described in detail herein.

[0088] Reference Fig.14 Optionally, the compensation signal terminal (XP) is electrically connected to the compensation signal line 102, the light-emitting control signal terminal (EMIT) is electrically connected to the light-emitting control signal line 101, and at least part of the compensation signal line is located on the side of the first node away from the light-emitting control signal line.

[0089] Referring to the above, by adding a compensation signal line for transmitting a compensation signal in the display panel, so that the compensation signal line overlaps with the first node, a first capacitor can be formed by the overlapping portion of the compensation signal line and the first node. The compensation signal line and the light-emitting control signal line can be arranged in the same layer or in different layers. In this embodiment, by arranging at least part of the compensation signal line to be located on the side of the first node away from the light-emitting control signal line, that is, at least part of the compensation signal line and the light-emitting control signal line are arranged in different layers (arranged on opposite sides of the first node), the difficulty of wiring arrangement can be reduced.

[0090] Reference Fig.14 Optionally, the compensation signal line 102 is electrically connected to the flexible circuit board 103. With this arrangement, the driver chip can flexibly adjust and control the compensation signal transmitted on the compensation signal line.

[0091] As a feasible implementation, the compensation signal line 102 may be directly electrically connected to the flexible circuit board 103 , and the driving chip sends the compensation signal to the compensation signal line 102 through the flexible circuit board 103 .

[0092] As another feasible implementation, the compensation signal line 102 may also be coupled to the flexible circuit board 103. Fig.14 Optionally, the display panel 100 further includes a compensation circuit module 20 for providing a compensation signal XP, the compensation signal line 102 is electrically connected to the compensation circuit module 20 , and the compensation circuit module 20 is electrically connected to the flexible circuit board 103 .

[0093] Reference Fig.14 The compensation circuit module 20 may include a plurality of compensation signal output ports. The compensation units in the plurality of pixel circuits 10 connected to the same light-emitting control signal line 101 may be electrically connected to the same compensation signal output port to receive the compensation signal. When the light-emitting control signal on the light-emitting control signal line jumps, the compensation circuit module outputs a compensation signal in the opposite direction of the jump to improve the uniformity of visual effects. In addition, by separately providing a compensation circuit module for providing the compensation signal XP in the display panel, the compensation signal line 102 is electrically connected to the flexible circuit board through the compensation circuit module 20, so that the flexibility of the output compensation signal can be guaranteed to meet different design requirements.

[0094] It should be noted that Fig.14 The example of the electrical connection between the pixel circuits in the same row and the same light-emitting control signal line 101 is used for illustration only. In other embodiments, multiple rows of pixel circuits may be electrically connected to the same light-emitting control signal line, which is not limited in the embodiment of the present invention.

[0095] Fig.15 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.15 As shown, optionally, the display panel further includes a light-emitting driving circuit 30 for providing a light-emitting control signal EMIT; the light-emitting driving circuit 30 is also multiplexed as a compensation circuit module 20 .

[0096] Reference Figure 8 In this embodiment, the compensation signal XP has a certain correlation with the light-emitting control signal EMIT. At any time, the absolute value of the voltage difference between the light-emitting control signal EMIT and the compensation signal XP is greater than the voltage value of the light-emitting control signal EMIT at that time. In simple terms, when the light-emitting control signal is at a high level, the compensation signal is at a low level, and when the light-emitting control signal is at a low level, the compensation signal is at a high level. When the voltage of the light-emitting control signal decreases, the voltage of the compensation signal increases, and when the voltage of the light-emitting control signal increases, the voltage of the compensation signal decreases. In this case, in this embodiment, the light-emitting driving circuit 30 is multiplexed as the compensation circuit module 20, so that it is used to provide the compensation signal while outputting the light-emitting control signal. This can ensure that the compensation signal and the light-emitting control signal have voltage jumps in opposite directions in the same time period, and can also simplify the structure of the display panel without the need to add other circuit modules specifically for providing the compensation signal.

[0097] like Fig.15 As shown, the light-emitting driving circuit 30 includes a plurality of cascaded light-emitting driving units 31; one light-emitting driving unit 31 is electrically connected to at least one row of pixel circuits 10, and is used to provide a light-emitting control signal EMIT and a compensation signal XP to these pixel circuits. The following is an exemplary description of the implementation method of multiplexing the light-emitting driving circuit as a compensation circuit module in combination with the specific structure of the light-emitting driving unit 31.

[0098] Fig.16 yes Fig.15 The structural diagram of the light-emitting driving unit is as follows: Fig.16 As shown, optionally, the light-emitting driving unit 31 includes a processing module 301, a first output module 302 and a second output module 303; the processing module 301 is electrically connected to the input terminal IN, the first clock signal terminal XCK, the second clock signal terminal CK, the first level signal terminal VGH, the second level signal terminal VGL, the third node N3 and the fourth node N4; the processing module 301 is used to respond to the first clock signal of the first clock signal terminal XCK and the second clock signal of the second clock signal terminal CK, and transmit a voltage signal to the third node N3 and the fourth node N4; the first output module 302 is electrically connected to the third node N3, the second level signal terminal VGL and the first output terminal O UT1; the first output module 301 is used to respond to the voltage signal of the third node N3, and transmit the second level signal of the second level signal terminal VGL to the first output terminal OUT1; the second output module 302 is electrically connected to the fourth node N4, the first level signal terminal VGH and the first output terminal OUT1; the second output module 302 is used to respond to the voltage signal of the fourth node N4, and transmit the first level signal of the first level signal terminal VGH to the first output terminal OUT1; the first output terminal OUT1 is electrically connected to the light emitting control signal line 101; the fourth node N4 is electrically connected to the second output terminal OUT2, and the second output terminal OUT2 is electrically connected to the compensation signal line 102.

[0099] like Fig.16 As shown, optionally, the processing module 301 includes a first processing unit 3011 electrically connected to the third node N3. The first processing unit 3011 is electrically connected to the input terminal IN, the second clock signal terminal CK and the third node N3. The first processing unit 3011 is used to provide the signal of the input terminal IN to the third node N3 in response to the signal of the second clock signal terminal CK.

[0100] like Fig.16As shown, the processing module 301 also includes a pull-down unit 3013 and a pull-up unit 3014. The pull-down unit 3013 is electrically connected to the first level signal terminal VGH, the fifth node N5, the first clock signal terminal XCK and the third node N3. The pull-down unit 3013 is used to provide the signal of the first level signal terminal VGH to the third node N3 in response to the signal of the first clock signal terminal XCK and the fifth node N5. The pull-up unit 3014 is electrically connected to the third node N3, the fourth node N4, the fifth node N5, the first level signal terminal VGH, the first clock signal terminal XCK and the second clock signal terminal CK, and is used to transmit a voltage signal to the fourth node N4 in response to the signal of the second clock signal terminal CK, the third node N3, the fifth node N5 and the first clock signal terminal XCK.

[0101] For example, Fig.16 As shown, the first processing unit 3011 includes a first transistor T1. A control electrode of the first transistor T1 is electrically connected to the second clock signal terminal CK, a first electrode of the first transistor T1 is electrically connected to the input terminal IN, and a second electrode of the first transistor T1 is electrically connected to the third node N3.

[0102] The pull-down unit 3013 includes a second transistor T2 and a third transistor T3. The control electrode of the second transistor T2 is electrically connected to the fifth node N5, the first electrode of the second transistor T2 is electrically connected to the first level signal terminal VGH, the second electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal XCK, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0103] The pull-up unit 3014 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8. The control electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CK, the first electrode of the fourth transistor T4 is electrically connected to the second level signal terminal VGL, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CK, and the second electrode of the fifth transistor T5 is electrically connected to the fifth node N5; the control electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and the first electrode of the sixth transistor T6 is electrically connected to the first clock signal terminal XCK; the control electrode of the seventh transistor T7 is electrically connected to the first clock signal terminal XCK, the first electrode of the seventh transistor T7 is electrically connected to the second electrode of the sixth transistor T6, that is, the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the control electrode of the eighth transistor T8 is electrically connected to the third node N3, the first electrode of the eighth transistor T8 is electrically connected to the first level signal terminal VGH, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4.

[0104] like Fig.16 As shown, the first output module 302 includes a ninth transistor T9, a control electrode of the ninth transistor T9 is electrically connected to the third node N3, a first electrode of the ninth transistor T9 is electrically connected to the second level signal terminal VGL, and a second electrode of the ninth transistor T9 is electrically connected to the first output terminal OUT1; the second output module 303 includes a tenth transistor T10, a control electrode of the tenth transistor T10 is electrically connected to the fourth node N4, a first electrode of the tenth transistor T10 is electrically connected to the first level signal terminal VGH, and a second electrode of the tenth transistor T10 is electrically connected to the first output terminal OUT1.

[0105] like Fig.16 As shown, the transmitting driving unit 10 also includes a second capacitor Cst2, a third capacitor Cst3 and a fourth capacitor Cst4. The first plate of the second capacitor Cst2 is electrically connected to the third node N3, and the second plate of the second capacitor Cst2 is electrically connected to the first clock signal terminal XCK. The first plate of the third capacitor Cst3 is electrically connected to the fifth node N5, and the second plate of the third capacitor Cst3 is electrically connected to the second electrode of the sixth transistor T6; the first plate of the fourth capacitor Cst4 is electrically connected to the first level signal terminal VGH, and the second plate of the fourth capacitor Cst4 is electrically connected to the fourth node N4.

[0106] Below Fig.16 The light emitting driving unit shown is a first-stage light emitting driving unit electrically connected to the start signal line STV as an example, and the working process of the light emitting driving unit is described. Fig.17 is with Fig.16 A corresponding working timing diagram of a light-emitting driving unit, combined with Fig.16 and Fig.17 As shown, the working process of the light driving unit 10 includes a first sub-period t21, a second sub-period t22, a third sub-period t23, a fourth sub-period t24, a fifth sub-period t25, a sixth sub-period t26, a seventh sub-period t27 and an eighth sub-period t28.

[0107] In the first sub-period t21, the second clock signal terminal CK provides a low level, the first clock signal terminal XCK provides a high level, and the start signal line STV provides a low level. The first transistor T1 and the fourth transistor T4 are turned on, and the low level signal provided by the start signal line STV writes the third node N3 low through the turned-on first transistor T1, and the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 are turned on. The high level signal provided by the first level signal terminal VGH writes the fourth node N4 high through the turned-on eighth transistor T8, and the tenth transistor T10 is turned off. The low level signal provided by the second level signal terminal VGL writes the first output terminal OUT1 low through the turned-on ninth transistor T9. The low level signal provided by the second clock signal terminal CK writes the fifth node N5 low through the turned-on fifth transistor T5, and the low level signal provided by the second level signal terminal VGL writes the fifth node N5 low through the turned-on fourth transistor T4, the second transistor T2 and the sixth transistor T6 are turned on, and the high level signal provided by the first clock signal terminal XCK writes the sixth node N6 high through the turned-on sixth transistor T6.

[0108] In the second sub-period t22, the second clock signal terminal CK provides a high level, the first clock signal terminal XCK provides a low level, and the start signal line STV provides a low level. The first transistor T1 and the fourth transistor T4 are turned off, the third node N3 maintains the low level of the first sub-period t21, the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 are turned on, the second clock signal terminal CK writes the fifth node N5 high through the turned-on fifth transistor T5, and the second transistor T2 and the sixth transistor T6 are turned off. The first level signal terminal VGH writes the fourth node N4 high through the turned-on eighth transistor T8. When the first clock signal terminal XCK jumps from a high level to a low level, the potential of the third node N3 changes from a low level to a third level smaller than the low level under the action of the second capacitor Cst2, and the ninth transistor T9 can be stably turned on to provide the low level signal of the second level signal terminal VGL to the first output terminal OUT1.

[0109] In the third sub-period t23, the second clock signal terminal CK provides a low level, the first clock signal terminal XCK provides a high level, and the start signal line STV provides a high level. The first transistor T1 and the fourth transistor T4 are turned on, and the high level signal provided by the start signal line STV writes the third node N3 high through the turned-on first transistor T1, and the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 are turned off. The low level signal provided by the second level signal terminal VGL writes the fifth node N5 low through the turned-on fourth transistor T4, and the second transistor T2 and the sixth transistor T6 are turned on. The high level signal provided by the first clock signal terminal XCK writes the sixth node N6 high through the turned-on sixth transistor T6. The seventh transistor T7 is turned off under the action of the first clock signal terminal XCK, the fourth node N4 maintains the high level of the second sub-period t2, the tenth transistor T10 is turned off, and the first output terminal OUT1 maintains the low level of the second sub-period t22.

[0110] In the fourth sub-period t24, the second clock signal terminal CK provides a high level, the first clock signal terminal XCK provides a low level, and the start signal line STV provides a high level. The first transistor T1 and the fourth transistor T4 are turned off, the third node N3 maintains the high level of the third sub-period t23, the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 are turned off, the fifth node N5 maintains the low level of the third sub-period t23, and the second transistor T2 and the sixth transistor T6 are turned on. When the first clock signal terminal XCK jumps from a high level to a low level, the low level signal provided by the first clock signal terminal XCK writes the sixth node N6 low through the turned-on sixth transistor T6. The fifth node N5 is pulled lower under the action of the third capacitor Cst3, so that the sixth transistor T6 stably maintains the turned-on state. Under the action of the low level provided by the first clock signal terminal XCK, the third transistor T3 and the seventh transistor T7 are turned on, and the high level signal provided by the first level signal terminal VGH writes the third node N3 high through the turned-on second transistor T2 and the third transistor T3. The low potential of the sixth node N6 writes the fourth node N4 low through the turned-on seventh transistor T7, and the tenth transistor T10 is turned on. The first level signal terminal VGH writes the first output terminal OUT1 high through the turned-on tenth transistor T10.

[0111] In the fifth sub-period t25, the second clock signal terminal CK provides a low level, the first clock signal terminal XCK provides a high level, and the start signal line STV provides a high level. The first transistor T1 and the fourth transistor T4 are turned on. The high level signal provided by the start signal line STV writes the third node N3 high through the first transistor T1, and the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 are turned off. The low level signal provided by the second level signal terminal VGL writes the fifth node N5 low through the turned-on fourth transistor T4, the second transistor T2 and the sixth transistor T6 are turned on, and the high level signal provided by the first clock signal terminal XCK writes the sixth node N6 high through the turned-on sixth transistor T6. The seventh transistor T7 is turned off. The fourth node N4 maintains the low level state of the fourth sub-period t4, and the tenth transistor T10 is turned on. The first level signal terminal VGH writes the first output terminal OUT1 high through the turned-on tenth transistor T10.

[0112] In the sixth sub-period t26, the second clock signal terminal CK provides a high level, the first clock signal terminal XCK provides a low level, and the start signal line STV provides a low level. The first transistor T1 and the fourth transistor T4 are turned off, the third node N3 maintains a high level in the fifth sub-period t25, and the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 are turned off. The fifth node N5 maintains a low level in the fifth sub-period t25, the second transistor T2 and the sixth transistor T6 are turned on, and the first level signal terminal VGH writes the third node N3 high through the turned-on second transistor T2 and the third transistor T3. When the first clock signal terminal XCK jumps from a high level to a low level, the low level writes the sixth node N6 low through the turned-on sixth transistor T6, and the potential of the fifth node N5 is further pulled down under the action of the fourth capacitor Cst4, and the sixth transistor T6 stably maintains the turned-on state. At the same time, the seventh transistor T7 is turned on, the low level signal of the sixth node N6 writes the fourth node N4 low through the turned-on seventh transistor T7, the tenth transistor T10 is turned on, and the high level signal provided by the first level signal terminal VGH writes the first output terminal OUT1 high through the turned-on tenth transistor T10.

[0113] In the seventh sub-period t27, the second clock signal terminal CK provides a low level, the first clock signal terminal XCK provides a high level, and the start signal line STV provides a low level. The first transistor T1 and the fourth transistor T4 are turned on. The low level signal provided by the start signal line STV writes the third node N3 low through the first transistor T1, and the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 are turned on. The low level signal provided by the second level signal terminal VGL writes the fifth node N5 low through the turned-on fourth transistor T4, the second transistor T2 and the sixth transistor T6 are turned on, and the high level signal provided by the first clock signal terminal XCK writes the sixth node N6 high through the turned-on sixth transistor T6. The seventh transistor T7 is turned off. The low level signal of the second level signal terminal VGL is provided to the first output terminal OUT1 through the turned-on ninth transistor T9. The high level signal provided by the first level signal terminal VGH writes the fourth node N4 high through the turned-on tenth transistor T10, and the tenth transistor T10 is turned off.

[0114] In the eighth sub-period t28, the second clock signal terminal CK provides a high level, the first clock signal terminal XCK provides a low level, and the start signal line STV provides a low level. The first transistor T1 and the fourth transistor T4 are turned off, the third node N3 maintains the low level of the seventh sub-period t27, the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 are turned on, the second clock signal terminal CK writes the fifth node N5 high through the turned-on fifth transistor T5, and the second transistor T2 and the sixth transistor T6 are turned off. The first level signal terminal VGH writes the fourth node N4 high through the turned-on eighth transistor T8. When the first clock signal terminal XCK jumps from a high level to a low level, the potential of the third node N3 changes from a low level to a third level smaller than the low level under the action of the second capacitor Cst2, and the ninth transistor T9 can be stably turned on to provide the low level signal of the second level signal terminal VGL to the first output terminal OUT1.

[0115] from Fig.17 It can be seen that the voltage of the fourth node N4 is opposite to the voltage of the first output terminal OUT1. Therefore, the fourth node N4 can be multiplexed as a compensation signal terminal, and the compensation signal line 102 is electrically connected to the fourth node N4 (the second output terminal OUT2) to provide a compensation signal through the light-emitting driving circuit to simplify the structure of the display panel.

[0116] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Fig.18 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig.18As shown, the display device 200 includes the display panel 100 provided in any of the above embodiments, and thus has the same beneficial effects as the above display panel. The same points can be found in the description of the above embodiments, which will not be repeated here. The display device 200 can be an OLED display device. In addition, the display device 200 provided in the embodiment of the present invention can be Fig.18 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0117] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A pixel circuit, characterized in that: include: A first light emitting control unit, a driving transistor and a compensation unit; The first end of the first light emitting control unit is electrically connected to the first power signal end; The second end of the first light emitting control unit, the first electrode of the driving transistor and the first end of the compensation unit are connected to a first node; the second end of the compensation unit is electrically connected to the compensation signal end; the control end of the first light emitting control unit is electrically connected to the light emitting control signal end; The light-emitting control signal at the light-emitting control signal end undergoes a first voltage jump at a first moment t1 and remains at a first level in a first time period, the compensation signal at the compensation signal end undergoes a second voltage jump at a second moment t2 and remains at a second level in a second time period, the first time period at least partially overlaps with the second time period, t1≤t2, and a jumping direction of the first voltage jump is opposite to a jumping direction of the second voltage jump.

2. The pixel circuit according to claim 1, characterized in that: The first level is a high level, the second level is a low level, the first time period is T1, the second time period is T2, and T1-T2≥0.

3. The pixel circuit according to claim 2, characterized in that: The light emitting control signal has a third level in a third time period, the third level is a low level, and the third time period is before the first time period. The compensation signal has a fourth level in a fourth time period, the fourth level is a high level, and the fourth time period is before the second time period. The fourth time period at least partially overlaps with the third time period.

4. The pixel circuit according to claim 2, characterized in that: T1=T2, t1=t2.

5. The pixel circuit according to claim 2, characterized in that: When t1<t2, T1-T2=t2-t1.

6. The pixel circuit according to claim 3, characterized in that: The absolute value of the difference between the first level V1 and the third level V3 |V1-V3| and the absolute value of the difference between the second level V2 and the fourth level V4 |V2-V4| satisfy: -2V≤|V1-V3|-|V2-V4|≤2V.

7. The pixel circuit according to claim 3, characterized in that: |V1-V3|=|V2-V4|.

8. The pixel circuit according to any one of claims 1 to 7, characterized in that: The compensation unit includes a first capacitor, a first plate of the first capacitor is electrically connected to the first node, and a second plate of the first capacitor is electrically connected to the compensation signal terminal.

9. The pixel circuit according to claim 8, characterized in that: The capacitance value of the first capacitor is C1, and the capacitance value of the parasitic capacitor is C0, wherein, The parasitic capacitance is a parasitic capacitance between the first node and a light emitting control signal line for transmitting the light emitting control signal.

10. A display panel, characterized in that: The pixel circuit comprises the pixel circuit described in any one of claims 1 to 9.

11. The display panel according to claim 10, characterized in that: The compensation signal terminal is electrically connected to the compensation signal line, the light-emitting control signal terminal is electrically connected to the light-emitting control signal line, and at least a portion of the compensation signal line is located on a side of the first node away from the light-emitting control signal line.

12. The display panel according to claim 11, characterized in that: The compensation signal line is electrically connected to the flexible circuit board.

13. The display panel according to claim 11, characterized in that: The display panel further includes a compensation circuit module for providing the compensation signal, and the compensation signal line is electrically connected to the compensation circuit module.

14. The display panel according to claim 13, characterized in that: The display panel further comprises a light-emitting driving circuit, which is used to provide the light-emitting control signal; The light-emitting driving circuit is also multiplexed as the compensation circuit module.

15. The display panel according to claim 14, characterized in that: The light-emitting driving circuit comprises a plurality of cascaded light-emitting driving units; the light-emitting driving unit comprises a processing module, a first output module and a second output module; The processing module is electrically connected to the input terminal, the first clock signal terminal, the second clock signal terminal, the first level signal terminal, the second level signal terminal, the third node and the fourth node; the processing module is used to respond to the first clock signal of the first clock signal terminal and the second clock signal of the second clock signal terminal, and transmit a voltage signal to the third node and the fourth node; The first output module is electrically connected to the third node, the second level signal terminal and the first output terminal; the first output module is used to respond to the voltage signal of the third node and transmit the second level signal of the second level signal terminal to the first output terminal; The second output module is electrically connected to the fourth node, the first level signal terminal and the first output terminal; The second output module is used for transmitting the first level signal of the first level signal end to the first output end in response to the voltage signal of the fourth node; The first output terminal is electrically connected to the light emitting control signal line; The fourth node is electrically connected to the compensation signal line.

16. A display device, characterized in that: A display panel comprising any one of claims 10-15.

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