Buffer chip, semiconductor package, and methods of operating same

Abstract

The invention relates to a buffer chip, a semiconductor package, and methods of operating the same. An operation method of a buffer chip may include: receiving a first control signal for setting a first memory chip; buffering the first control signal and transmitting the buffered signal to the first memory chip; storing a setting value of the first memory chip in response to the first control signal; receiving a second control signal for setting a second memory chip; buffering the second control signal and transmitting the buffered second control signal to the second memory chip; storing a setting value of the second memory chip in response to a second control signal; receiving a third control signal for applying the setting value of the first memory chip; buffering the third control signal and transmitting the buffered third control signal to the first memory chip; and applying the stored setting value of the first memory chip as a setting value of the buffer chip in response to a third control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0115962, filed on September 1, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor package including a buffer chip and a memory chip, and a memory module including the semiconductor package. Background Art

[0004] Recently, with the increase in application areas using artificial intelligence (AI) and big data, the amount of data to be processed is exploding. Many computer systems such as data centers, servers, etc. require a large amount of memory, and applications using computer systems require a larger amount of memory than the system capacity. However, due to the limitations of latency and bandwidth, it is difficult to add memory to a computer system. Various methods are being studied to increase the amount of memory in the system while maintaining low latency and high bandwidth. Summary of the invention

[0005] In one embodiment of the present disclosure, a method for operating a buffer chip may include: receiving a first control signal for setting a first memory chip; buffering the first control signal and transmitting the buffered first control signal to the first memory chip; storing a setting value for the first memory chip in response to the first control signal; receiving a second control signal for setting a second memory chip; buffering the second control signal and transmitting the buffered second control signal to the second memory chip; storing the setting value for the second memory chip in response to the second control signal; receiving a third control signal for applying the setting value for the first memory chip; buffering the third control signal and transmitting the buffered third control signal to the first memory chip; and applying the stored setting value for the first memory chip as the setting value of the buffer chip in response to the third control signal.

[0006] In one embodiment of the present disclosure, an operating method of a semiconductor package may include: receiving, by a buffer chip, a first control signal for setting a first memory chip; buffering, by the buffer chip, the first control signal and transmitting the buffered first control signal to the first memory chip; storing, by the buffer chip in response to the first control signal, a setting value for the first memory chip; storing, by the first memory chip in response to the first control signal, a setting value for the first memory chip; receiving, by the buffer chip, a second control signal for setting a second memory chip; buffering, by the buffer chip, the second control signal and transmitting the buffered second control signal to the second memory chip; and storing, by the buffer chip in response to the first control signal, a setting value for the first memory chip. A setting value for a second memory chip is stored in response to a second control signal; the second memory chip stores the setting value for the second memory chip in response to the second control signal; a buffer chip receives a third control signal for applying the setting value for the second memory chip; the buffer chip buffers the third control signal and transmits the buffered third control signal to the second memory chip; the buffer chip applies the stored setting value for the second memory chip as the setting value of the buffer chip in response to the third control signal; and the second memory chip applies the stored setting value for the second memory chip as the setting value for the second memory chip in response to the third control signal.

[0007] In one embodiment of the present disclosure, a buffer chip may include: a first command decoder, which is configured to decode a first chip selection signal and a command address signal; a second command decoder, which is configured to decode a second chip selection signal and a command address signal; a first setting circuit, which is configured to store a setting value for a first memory chip according to a decoding result of the first command decoder; a second setting circuit, which is configured to store a setting value for a second memory chip according to a decoding result of the second command decoder; and a buffer chip setting circuit, which is configured to: when application of setting values ​​for the first memory chip is indicated, receive one or more setting values ​​stored in the first setting circuit and store the received setting values ​​as buffer chip setting values; and when application of setting values ​​for the second memory chip is indicated, receive one or more setting values ​​stored in the second setting circuit and store the received setting values ​​as buffer chip setting values.

[0008] In one embodiment of the present disclosure, a semiconductor package may include: a buffer chip; a first memory chip configured to communicate with a memory controller through the buffer chip; and a second memory chip configured to communicate with the memory controller through the buffer chip, wherein the buffer chip includes: a first command decoder configured to decode a first chip selection signal and a command address signal; a second command decoder configured to decode a second chip selection signal and a command address signal; a first setting circuit configured to store a setting value for the first memory chip according to a decoding result of the first command decoder; a second setting circuit configured to store a setting value for the second memory chip according to a decoding result of the second command decoder; and a buffer chip setting circuit configured to: when application of setting values ​​for the first memory chip is indicated, receive one or more setting values ​​stored in the first setting circuit and store the received setting values ​​as buffer chip setting values, and when application of setting values ​​for the second memory chip is indicated, receive one or more setting values ​​stored in the second setting circuit and store the received setting values ​​as buffer chip setting values.

[0009] These and other features and advantages of the present invention will become apparent from the detailed description of the embodiments of the present disclosure and the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a configuration of a memory module according to one embodiment of the present disclosure.

[0011] Figure 2 is a diagram illustrating an embodiment according to the present disclosure Figure 1 A detailed configuration of a memory package is shown in FIG.

[0012] Figure 3 is a diagram illustrating an embodiment according to the present disclosure Figure 2 The detailed configuration of the buffer chip is shown in the figure.

[0013] Figure 4 is a diagram illustrating a method according to an embodiment of the present disclosure Figure 3 8 is a timing diagram of waveforms of the first clock to the fourth clock generated by the clock divider shown in FIG.

[0014] Figure 5 is a diagram illustrating an embodiment according to the present disclosure Figure 3 The detailed configuration of the control signal transmission circuit is shown in the diagram.

[0015] Figure 6 is a diagram illustrating an embodiment according to the present disclosure Figure 5A timing diagram of the operation of the control signal transmission circuit is shown in FIG.

[0016] Figure 7 is a diagram illustrating an embodiment according to the present disclosure Figure 5 The detailed configuration of the D flip-flop is shown in the diagram.

[0017] Figure 8 is a diagram illustrating an embodiment according to the present disclosure Figure 2 The detailed configuration of the buffer chip is shown in the figure.

[0018] Fig. 9 is a flowchart illustrating an operation according to an embodiment of the present disclosure, in which an Figure 8 The buffer chip shown in the figure sets the value immediately in the memory package.

[0019] Fig.10 is a flowchart illustrating an operation according to an embodiment of the present disclosure, in which an Figure 8 The buffer chip shown in the memory package is set with a set instruction setting value. DETAILED DESCRIPTION

[0020] Various embodiments of the present disclosure are directed to providing a technology for setting a buffer chip.

[0021] Embodiments of the present disclosure may set the buffer chip to an appropriate setting value.

[0022] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0023] Figure 1 is a diagram illustrating a configuration of a memory module 100 according to one embodiment of the present disclosure.

[0024] refer to Figure 1 , the memory module 100 may include a module controller 110 and a plurality of memory packages 120_0 to 120_19.

[0025] The module controller 110 may include a host interface 111, a memory controller logic 113, and a memory interface 115. The memory controller logic 113 and the memory interface 115 may also be referred to as a memory controller.

[0026] The host interface 111 may be used for communication between the module controller 110 and a host (e.g., a computer system). The host interface 111 may be a compute express link (CXL) interface. The CXL interface is an interface based on the peripheral component interconnect express (PCIe), and may be an interface through which a central processing unit (CPU), a graphics processing unit (GPU), and various types of accelerators use memory more efficiently. By connecting the memory module 100 to the host via the CXL interface, the memory capacity of a computer system such as a data center and a server may be increased, and various processors in the computer system may share memory.

[0027] The memory controller logic 113 may be logic for controlling the memory packages 120_0 to 120_19, and the memory interface 115 may be an interface for communicating with the memory packages 120_0 to 120_19. The memory interface 115 may include two channels CH0 and CH1. Ten memory packages (i.e., the first memory package group) 120_0 to 120_9 may be connected to the channel CH0 of the memory interface 115, and other memory packages 120_10 to 120_19 (i.e., the second memory package group) may be connected to the channel CH1.

[0028] The channel CH0 of the memory interface 115 may be connected to the first memory package group 120_0 to 120_9 through 40 data lines DQ<0:39>. Four different data lines may be connected to the first memory package group 120_0 to 120_9. For example, four data lines DQ<0:3> may be connected to the memory package 120_0, and four data lines DQ<4:7> may be connected to the memory package 120_1.

[0029] The channel CH0 of the memory interface 115 may be connected to the first memory package group 120_0 to 120_9 through the control signal transmission line CONTROL. The control signal transmission line CONTROL may include a plurality of lines and may be common to the first memory package group 120_0 to 120_9. For example, all control signal transmission lines CONTROL may be connected to the memory package 120_0 and may also be connected to the memory package 120_1. Although not illustrated in the drawings, lines for transmitting clock and data strobe signals may be further connected between the channel CH0 of the memory interface 115 and the first memory package group 120_0 to 120_9.

[0030] The channel CH1 of the memory interface 115 and the second memory package group 120_10 to 120_19 may be connected in the same manner as the channel CH0 and the first memory package group 120_0 to 120_9 .

[0031] Each memory package in the memory packages 120_0 to 120_19 may include one or more memory chips (e.g., DRAM chips). Because one of the important reasons for using the memory module 100 is to greatly increase the capacity of the memory, each memory package in the memory packages 120_0 to 120_19 generally includes a plurality of memory chips. As one of the methods for placing a plurality of memory chips in a memory package, methods such as 3-dimensional stacking (3DS) have been used. The 3DS method may use through-silicon vias (TSVs) for communication between memory chips in a memory package. However, when a memory package is manufactured in this manner, the price of the memory package may increase because a lot of time and cost are required in the package.

[0032] In the memory module 100, each of the memory packages 120_0 to 120_19 may include a buffer chip and a plurality of memory chips. The buffer chip may perform a buffer operation between the module controller 110 and the plurality of memory chips. The plurality of memory chips included in each of the memory packages 120_0 to 120_19 may be connected to the buffer chip by wiring bonding. The memory module 100 may increase the memory capacity by using a plurality of memory chips, and reduce the load caused by the increase of the memory by using the buffer chip.

[0033] However, the configuration of the memory packages 120_0 to 120_19 disclosed in the present disclosure is only an example and may not be limited thereto. For example, each memory package in the memory packages 120_0 to 120_19 may include different types of memory chips. For example, at least one memory package in the memory packages 120_0 to 120_19 may have a different configuration from other memory packages, and / or may be connected to the module controller 110 in a different manner. For example, a 3-dimensional stacking (3DS) method, a monolithic 3D (M3D) method, or the like may be used to integrate the memory chips included in at least one memory package in the memory packages 120_0 to 120_19. For example, by using through-silicon vias (TSVs) or vias having a smaller size and higher density than TSVs, the memory chips included in at least one memory package in the memory packages 120_0 to 120_19 may communicate with each other.

[0034] The form factor of the memory module 100 may have various forms, such as an add-in card (AIC) and an enterprise and data center SSD form factor (EDSFF).

[0035] Figure 2 is a diagram illustrating an embodiment according to the present disclosure Figure 1 Detailed configuration of the memory package 120 is shown in FIG.

[0036] refer to Figure 2 , the memory package 120 may include a package substrate 210 , a buffer chip 220 , and a plurality of memory chips 231 to 234 .

[0037] The package substrate 210 may include a plurality of package balls 211 and a plurality of bonding pads 213. The plurality of package balls 211 are used to connect to the memory interface 115 ( Figure 1 ) terminals for communication, and multiple bonding pads 213 are used for communication inside the memory package 120.

[0038] The buffer chip 220 may be disposed on the package substrate 210. The buffer chip 220 may be connected to the memory interface 115 ( Figure 1 The buffer chip 220 may further communicate with the memory chips 231 to 234 through the bonding pads 213 of the package substrate 210.

[0039] The memory chips 231 to 234 may be stacked on the buffer chip 220 and may communicate with the buffer chip 220 through the wiring 241 that connects the bonding pads 213 with the memory chips 231 to 234. The memory chips 231 to 234 may communicate with the memory interface 115 ( Figure 1 ) to communicate. From the memory interface 115 ( Figure 1 ) transmission control signal CONTROL( Figure 1 ) and data DQ<0:39>( Figure 1 ) can be transmitted to the buffer chip 220 through the package ball 211, buffered, and then transmitted from the buffer chip 220 to the memory chips 231 to 234 through the bonding pad 213. Data transmitted from the memory chips 231 to 234 can be transmitted to the buffer chip 220 through the bonding pad 213, buffered, and then transmitted to the memory interface 115 through the package ball 211 ( Figure 1 ).

[0040] Because only the buffer chip 220 among the chips of the memory package 120 can be connected to the memory interface 115 ( Figure 1 ), so the memory package 120 and the memory interface 115 ( Figure 1 ) between the buffer chip 220 and the memory chips 231 to 234 to enable high-speed operation. Since the buffer chip 220 and the memory chips 231 to 234 are connected by wiring instead of TSVs that consume a lot of cost in the manufacturing process, the manufacturing cost of the memory package 120 can be reduced.

[0041] Figure 3 is a diagram illustrating an embodiment according to the present disclosure Figure 2 A detailed configuration of the buffer chip 220 is shown in FIG.

[0042] refer to Figure 3 The buffer chip 220 may include an external control signal interface 310, an external data interface 320, an internal control signal interface 330, an internal data interface 340, a control signal transmission circuit 350, a delay control circuit 360, a command decoder 370, a setting circuit 380, a clock receiving circuit 390, a clock divider 393 and a clock transmission circuit 395.

[0043] The external control signal interface 310 can receive the control signal from the memory interface 115 ( Figure 1 ) transmission control signal CONTROL( Figure 1 ). Control signal CONTROL( Figure 1 ) may include a chip selection signal CS<0:3> and a command address signal CA<0:13>. The external control signal interface 310 may include a chip selection signal receiving circuit 311 and a command address receiving circuit 315.

[0044] The chip select signal CS<0:3> is used to distinguish the memory package 120 ( Figure 2 ) in memory chips 231 to 234 ( Figure 2 ), that is, used to distinguish ranks, and the number of chip selection signals CS<0:3> may be the same as the number of memory packages 120 ( Figure 2 ) in memory chips 231 to 234 ( Figure 2 ) are the same number. Figure 3 , since the number of chip selection signals CS<0:3> is illustrated as 4, the chip selection signal receiving circuit 311 may include four receiving buffers. The buffers of the chip selection signal receiving circuit 311 may receive the chip selection signal CS<0:3> by comparing the voltage levels of the chip selection reference voltage VREFCS and the chip selection signal CS<0:3> with each other.

[0045] The command address receiving circuit 315 may include the same number of receiving buffers as the number of command address signals CA<0:13>. Figure 3, since the number of command address signals CA<0:13> is illustrated as 14, the command address receiving circuit 315 may include 14 receiving buffers. The buffers of the command address receiving circuit 315 may receive the command address signal CA<0:13> by comparing the voltage levels of the command address reference voltage VREFCA and the command address signal CA<0:13> with each other.

[0046] The external data interface 320 can transmit the data DQ<k:k+3> Transmitted to the memory interface 115 ( Figure 1 ) / from memory interface 115( Figure 1 )Receive data DQ<k:k+3> , where k is an integer equal to or greater than 0. The external data interface 320 can not only transmit / receive data DQ<k:k+3> , and can transmit / receive strobe data DQ<k:k+3> The external data interface 320 may include an external data receiving circuit 321 , an external data transmission circuit 323 , an external data strobe receiving circuit 325 , and an external data strobe transmission circuit 327 .

[0047] The external data receiving circuit 321 may include a<k:k+3> The number of receive buffers is the same as the number of terminals that are input. Figure 3 Because each memory package 120 ( Figure 2 ) provides four data terminals, so the external data receiving circuit 321 may include four receiving buffers. The buffer of the external data receiving circuit 321 can be connected by the data reference voltage VREFDQ and the data DQ<k:k+3> The voltage levels are compared with each other to receive data DQ<k:k+3> .

[0048] The external data strobe receiving circuit 325 can receive the data DQ<k:k+3> Together from the memory interface 115 ( Figure 1 ) The data strobe signals DQS_t and DQS_c transmitted by the external data strobe receiving circuit 325 are differential type signals, so the external data strobe receiving circuit 325 may include a receiving buffer that compares the voltage levels of the data strobe signal DQS_t and the inverted data strobe signal DQS_c with each other and receives them.

[0049] The external data transmission circuit 323 can transmit data DQ<k:k+3> The external data transmission circuit 323 may include four transmission drivers.

[0050] The external data strobe transmission circuit 327 can transmit the data DQ used to select the data DQ transmitted by the external data transmission circuit 323.<k:k+3> The external data strobe transmission circuit 327 may include two transmission drivers.

[0051] The clock receiving circuit 390 can receive the clock from the memory interface 115 ( Figure 1 ) The clocks CLK_t and CLK_c transmitted by the clock receiving circuit 390. Since the clocks CLK_t and CLK_c are differential type signals, the clock receiving circuit 390 may include a receiving buffer that compares the voltage levels of the clock CLK_t and the inverted clock CLK_c and receives them.

[0052] The clock divider 393 may divide the clocks CLK_t and CLK_c received by the clock receiving circuit 390. The first to fourth clocks ICLK, QCLK, BCLK, and QBCLK generated by the clock divider 393 may each have a frequency half the frequency of each of the clocks CLK_t and CLK_c, and may have different phases. The clocks CLK_t and CLK_c received by the clock receiving circuit 390 and the first to fourth clocks ICLK, QCLK, BCLK, and QBCLK generated by the clock divider 393 may be used by various components inside the buffer chip 220.

[0053] The control signal transmission circuit 350 may buffer the control signal received through the external control signal interface 310 and transmit the buffered control signal to the internal control signal interface 330. The control signal transmission circuit 350 may include a setup and hold latch circuit 351 for ensuring a setup hold margin and a transmission control circuit 353 for performing a buffering operation.

[0054] The internal control signal interface 330 may transmit the control signals M_CS<0:3> and M_CA<0:13> transmitted through the control signal transmission circuit 350 to the memory chips 231 to 234 ( Figure 2 The command address signal M_CA<0:13> may be transmitted to the memory chips 231 to 234 in common ( Figure 2 ), and the chip selection signal M_CS<0:3> may be transmitted to the memory chips 231 to 234 in a one-to-one manner ( Figure 2 ). That is, the chip selection signal M_CS <0> can be transmitted to the memory chip 231 ( Figure 2 ), chip select signal M_CS <1> can be transmitted to the memory chip 232 ( Figure 2 ), chip select signal M_CS <2> can be transmitted to the memory chip 233 ( Figure 2 ), and the chip select signal M_CS <3> can be transmitted to the memory chip 234 ( Figure 2 ).

[0055] The internal control signal interface 330 may include a chip selection signal transmission circuit 331 and a command address transmission circuit 335. Since the number of chip selection signals M_CS<0:3> is 4, the chip selection signal transmission circuit 331 may include four transmission drivers. Also, since the number of command address signals M_CA<0:13> is 14, the command address transmission circuit 335 may include 14 transmission drivers.

[0056] The internal data interface 340 can transmit the data M_DQ<k:k+3> Transmitted to memory chips 231 to 234 ( Figure 2 ) / from memory chips 231 to 234 ( Figure 2 )Receive data M_DQ<k:k+3> . Data M_DQ<k:k+3> can be commonly connected to memory chips 231 to 234 ( Figure 2 ). When the data M_DQ<k:k+3> are transmitted to memory chips 231 to 234 during a write operation ( Figure 2 ), memory chips 231 to 234 ( Figure 2 ) among the memory chips selected to perform the write operation may receive the data M_DQ transmitted by the internal data interface 340.<k:k+3> During the read operation, the memory chip selected to perform the read operation among the memory chips 231 to 234 may store the data M_DQ<k:k+3> The internal data interface 340 can transmit the data M_DQ<k:k+3> Transmitted to memory chips 231 to 234 ( Figure 2 ) / from memory chips 231 to 234 ( Figure 2 )Receive data M_DQ<k:k+3> , and can be used to strobe data M_DQ<k:k+3> The data selection signals M_DQS_t and M_DQS_c are transmitted to the memory chips 231 to 234 ( Figure 2 ) / from memory chips 231 to 234 ( Figure 2 ) receives the M_DQ strobe data<k:k+3> The data selection signals M_DQS_t and M_DQS_c are as follows.

[0057] The internal data interface 340 may include an internal data transmission circuit 341, an internal data receiving circuit 343, an internal data strobe transmission circuit 345, and an internal data strobe receiving circuit 347. The internal data transmission circuit 341 may include four transmission drivers, and the internal data receiving circuit 343 may include four receiving buffers. The internal data strobe transmission circuit 345 may include two transmission drivers, and the internal data strobe receiving circuit 347 may include one receiving buffer.

[0058] The clock transmission circuit 395 can transmit the clocks M_CLK_t and M_CLK_c to the memory chips 231 to 234 ( Figure 2 The clocks M_CLK_t and M_CLK_c may be transmitted to the memory chips 231 to 234 in common ( Figure 2 ). The clock transmission circuit 395 may include two transmission drivers.

[0059] The command decoder 370 may decode the chip select signal CS<0:3> and the command address signal CA<0:13> received through the external control signal interface 310. The command decoder 370 may receive the control signal latched by the setup and hold latch circuit 351 after being received through the external control signal interface 310, and decode the control signal. The chip select signal CS<0:3> indicates the validity of the command address signal CA<0:13>, and when even one of the four chip select signals CS<0:3> is activated to a low level, the command decoder 370 of the buffer chip 220 may determine that the command address signal CA<0:13> is valid and decode the command address signal CA<0:13>.

[0060] The setting circuit 380 may perform a setting operation according to the decoding result of the command decoder 370. The setting items of the setting circuit 380 may include a read delay of the buffer chip 220, a write delay of the buffer chip 220, a level of a reference voltage used by the buffer chip 220, a terminal resistance value (also referred to as Rtt) of a buffer included in the buffer chip 220, a terminal resistance value (also referred to as Ron) of a driver included in the buffer chip 220, and the like.

[0061] The delay control circuit 360 can control whether to activate the external data interface 320 and the internal data interface 340. The delay control circuit 360 can activate the external data receiving circuit 321 and the internal data transmission circuit 341 so that from the time point when the write command is applied to the buffer chip 220, after the write delay set by the setting circuit 380, the memory interface 115 ( Figure 1) is transmitted to the data DQ of the buffer chip 220<k:k+3> can be received and transmitted to the memory chips 231 to 234 ( Figure 2 The delay control circuit 360 may further activate the internal data receiving circuit 343 and the external data transmission circuit 323 so that, starting from the time point when the read command is applied to the buffer chip 220, after the read delay set by the setting circuit 380, the data from the memory chips 231 to 234 ( Figure 2 ) received and then buffered data DQ<k:k+3> can be transmitted from the buffer chip 220 to the memory interface 115 ( Figure 1 The delay control circuit 360 can activate the external data strobe receiving circuit 325 and the internal data strobe transmission circuit 345 during a write operation, and activate the internal data strobe receiving circuit 347 and the external data strobe transmission circuit 327 during a read operation, so that the data strobe signals DQS_t and DQS_c can also be synchronized with the data DQ<k:k+3> The delay control circuit 360 may receive information indicating that the read command and the write command have been applied to the buffer chip 220 from the command decoder 370 , and receive information related to the read delay and the write delay from the setting circuit 380 .

[0062] Figure 4 is a diagram illustrating a method according to an embodiment of the present disclosure Figure 3 2 is a timing diagram of waveforms of the first to fourth clocks ICLK, QCLK, BCLK, and QBCLK generated by the clock divider 393 shown in FIG.

[0063] refer to Figure 4 , the first to fourth clocks ICLK, QCLK, BCLK and QBCLK generated by the clock divider 393 can each have a frequency half the frequency of each of the clocks CLK_t and CLK_c, and can have a phase difference of 90° between the first to fourth clocks ICLK, QCLK, BCLK and QBCLK.

[0064] Figure 5 It is a graphic Figure 3 FIG. 350 is a diagram showing a detailed configuration of the control signal transmission circuit 350, and Figure 6 is a timing diagram illustrating the operation of the control signal transmission circuit 350 according to one embodiment of the present disclosure. Figure 5 The control signal transmission circuit 350 is used to transmit the command address signal CA <0> The remaining control signals CA<1:13> and CS<0:3> can also be used with the command address signal CA <0> Transfer in the same way.

[0065] refer to Figure 5, the setup and hold latch circuit 351 of the control signal transmission circuit 350 may include D flip-flops 511 and 512. The input IN of the D flip-flops 511 and 512 may be Figure 3 The command address receiving circuit 315 receives the command address signal CA <0> The D flip-flop 511 can receive an input at the rising edge of the first clock ICLK, latch the received input, and output a signal FLA_A. <0> , and the D flip-flop 512 can receive an input at the rising edge of the third clock BCLK, latch the received input, and output a signal FLA_B <0> . Reference together Figure 6 , command address signal CA <0> The signal 1ST of the first cycle can be latched by the D flip-flop 511 and output as the signal FLA_A <0> , and the command address signal CA <0> The signal 2ND of the second cycle can be latched by the D flip-flop 512 and output as the signal FLA_B <0> .

[0066] The transmission control circuit 352 of the control signal transmission circuit 350 may include D flip-flops 521 to 524 , D latches 525 to 528 , inverters 529 to 536 and 541 to 544 , AND gates 537 to 540 and 545 to 548 , and an OR gate 549 .

[0067] The D flip-flop 521 may receive and latch the signal FLA_A at the rising edge of the first clock ICLK. <0> The output signal Q of the D flip-flop 521 is output by CA_QBCLK <0> The output Q0.5 of the D flip-flop 521 may be an output of a first stage of the D flip-flop 521 including two stages. Figure 7 The detailed configuration of the D flip-flop 521 is shown in the figure, and in addition to the configuration of a general D flip-flop, the D flip-flop 521 can further include an inverter 701 for outputting the output Q0.5 from the latch of the first stage. The D flip-flop 523 can receive and latch the output Q0.5 of the D flip-flop 521 at the rising edge of the second clock QCLK, and use the latched output as the signal CA_ICLK <0> Output. Reference Figure 6 , signal CA_QBCLK <0> and CA_ICLK <0> There may be a phase difference equal to that between the first clock ICLK and the second clock QCLK.

[0068] The D flip-flop 522 may receive and latch the signal FLA_B at the rising edge of the third clock BCLK. <0> The output signal Q of the D flip-flop 522 is output by CA_QCLK <0> The D flip-flop 524 can receive and latch the output Q0.5 of the D flip-flop 522 at the rising edge of the fourth clock QBCLK, and use the latched output as the signal CA_BCLK <0> Output. Reference Figure 6 , signal CA_QCLK <0> and CA_BCLK <0> may have a phase difference equal to that between the third clock BCLK and the fourth clock QBCLK.

[0069] When the fourth clock QBCLK is at a low level, the D latch 525 may latch and output the signal CA_QBCLK <0> The output of the D latch 525 may be inverted by the inverter 533, and the output of the inverter 533 and the fourth clock QBCLK may be input to the AND gate 537. The output of the AND gate 537 may be input to the AND gate 545 together with the first clock ICLK inverted by the inverter 541.

[0070] When the first clock ICLK is at a low level, the D latch 526 can latch and output the signal CA_ICLK <0> The output of the D latch 526 may be inverted by the inverter 534, and the output of the inverter 534 and the first clock ICLK may be input to the AND gate 538. The output of the AND gate 538 may be input to the AND gate 546 together with the second clock QCLK inverted by the inverter 542.

[0071] When the second clock QCLK is at a low level, the D latch 527 can latch and output the signal CA_QCLK <0> The output of the D latch 527 may be inverted by the inverter 535, and the output of the inverter 535 and the second clock QCLK may be input to the AND gate 539. The output of the AND gate 539 may be input to the AND gate 547 together with the third clock BCLK inverted by the inverter 543.

[0072] When the third clock BCLK is at a low level, the D latch 528 can latch and output the signal CA_BCLK <0> The output of the D latch 528 may be inverted by the inverter 536, and the output of the inverter 536 and the third clock BCLK may be input to the AND gate 540. The output of the AND gate 540 may be input to the AND gate 548 together with the fourth clock QBCLK inverted by the inverter 544.

[0073] The outputs of the AND gates 545 to 548 may be input to an OR gate 549, and the output OUT of the OR gate 549 may be Figure 3 The transmission command address signal M_CA of the command address transmission circuit 335 <0> of the drive input.

[0074] refer to Figure 6 , the command address receiving circuit 315 of the buffer chip 220 receives the command address from the memory interface 115 ( Figure 1) The received command address signal CA <0> It can be buffered by the control signal transmission circuit 350, delayed by 4 clock cycles based on the clocks CLK_t and CLK_c, and transmitted to the memory chips 231 to 234 by the command address transmission circuit 335 ( Figure 2 ).

[0075] Now go back to reference Figures 1 to 3 , Figure 3 The buffer chip 220 in the embodiment includes a command decoder 370 and a setting circuit 380. The command decoder 370 does not distinguish between the chip selection signals CS<0:3>, and when any one of the chip selection signals CS<0:3> is activated to a low level, determines that the command address signal CA<0:13> is valid. When the memory controllers 113 and 115 of the module controller 110 set different values ​​for each of the memory chips 231 to 234 distinguished by the chip selection signal CS<0:3> within the memory package 120, that is, for each level in the level, the operation of the buffer chip 220 and the memory package 120 may have problems.

[0076] Figure 8 is a diagram illustrating an embodiment according to the present disclosure Figure 2 The detailed configuration of the buffer chip 220 is shown in FIG. Figure 8 , an embodiment in which the buffer chip 220 performs a setting operation for each level individually will be described. Hereinafter, for ease of description, the number of chip selection signals CS<0:1> is two, that is, included in the memory package 120 ( Figure 2 ) in memory chips 231 and 232 ( Figure 2 ) is two, which indicates that the memory package 120 is configured by two levels, however other numbers of memory chips may also be used.

[0077] refer to Figure 8 The buffer chip 220 may include an external control signal interface 310, an external data interface 320, an internal control signal interface 330, an internal data interface 340, a control signal transmission circuit 350, a first delay control circuit 861, a second delay control circuit 863, a first command decoder 871, a second command decoder 873, a first setting circuit 881, a second setting circuit 883, a clock receiving circuit 390, a clock divider 393, a clock transmission circuit 395 and a buffer chip setting circuit 801.

[0078] The first command decoder 871 may decode the chip selection signal CS received through the external control signal interface 310. <0> Specifically, when the chip select signal CS <0> When activated to a low level, the first command decoder 871 can decode the command address signal CA<0:13>. That is, the first command decoder 871 can decode the level 0 command.

[0079] The second command decoder 873 may decode the chip selection signal CS received through the external control signal interface 310. <1> Specifically, when the chip select signal CS <1> When activated to a low level, the second command decoder 873 can decode the command address signal CA<0:13>. That is, the second command decoder 873 can decode the level 1 command.

[0080] According to the decoding result of the first command decoder 871, the first setting circuit 881 may store a setting value corresponding to level 0, that is, corresponding to the memory chip 231 ( Figure 2 ) The setting values ​​may include: read delay and write delay for the buffer operation of the buffer chip 220 for the memory chip 231, the level of reference voltages (e.g., VREFCA, VREFCS, and VREFDQ) used during the buffer operation of the buffer chip 220 for the memory chip 231, the terminal resistance value of the buffer used by the buffer chip 220 during the buffer operation for the memory chip 231, the terminal resistance value of the driver used by the buffer chip 220 during the buffer operation for the memory chip 231, etc.

[0081] According to the decoding result of the second command decoder 873, the second setting circuit 883 may store a setting value corresponding to level 1, that is, corresponding to the memory chip 232 ( Figure 2 ) The setting values ​​may include: a read delay and a write delay for the buffer operation of the buffer chip 220 for the memory chip 232, a level of a reference voltage used during the buffer operation of the buffer chip 220 for the memory chip 232, a terminal resistance value of a buffer used by the buffer chip 220 during the buffer operation for the memory chip 232, a terminal resistance value of a driver used by the buffer chip 220 during the buffer operation for the memory chip 232, and the like.

[0082] Some of the setting values ​​stored in the first setting circuit 881 and the second setting circuit 883 may be immediately applied once they are stored in the setting circuits 881 and 883. For example, when a setting value such as read delay and write delay is stored in the first setting circuit 881, the setting value may be immediately applied as a delay setting value of level 0, and when a setting value such as read delay and write delay is stored in the second setting circuit 883, the setting value may be immediately applied as a delay setting value of level 1. Hereinafter, setting values ​​that are immediately applied once they are stored in the setting circuits 881 and 883 will be referred to as immediate setting values.

[0083] Some of the setting values ​​stored in the first setting circuit 881 and the second setting circuit 883 may not be applied at the time point when they are stored in the setting circuits 881 and 883, but may be applied at the time point when the application of the setting value is indicated. For example, the level of the reference voltage and the setting value of the terminal resistance value stored in the first setting circuit 881 may not be applied at the time point when they are stored in the first setting circuit 881, but may be applied at the time point when the application of the setting value of level 0 is indicated. Similarly, the level of the reference voltage and the setting value of the terminal resistance value stored in the second setting circuit 883 may not be applied at the time point when they are stored in the second setting circuit 883, but may be applied at the time point when the application of the setting value of level 1 is indicated. In the following, the setting value applied at the time point when the application of the setting value is indicated will be referred to as the instruction setting value.

[0084] The buffer chip setting circuit 801 may be a circuit for storing an instruction setting value, for which the setting value application is indicated. When indicating the application of the setting value of level 0 (that is, the memory chip 231), the instruction setting value stored in the first setting circuit 881 may be applied to the buffer chip setting circuit 801 and stored in the buffer chip setting circuit 801. The instruction setting values ​​of level 0 may be applied to the buffer chip 220 at the time point when they are stored in the buffer chip setting circuit 801. For example, the level of the reference voltage used by the buffer chip 220 and the terminal resistance value may be set (that is, stored) as the instruction setting value of level 0 stored in the buffer chip setting circuit 801. When indicating the application of the setting value of level 1 (that is, the memory chip 232), the instruction setting value stored in the second setting circuit 883 may be applied to the buffer chip setting circuit 801 and stored in the buffer chip setting circuit 801. The instruction setting values ​​of level 1 may be applied to the buffer chip 220 at the time point when they are stored in the buffer chip setting circuit 801. For example, the level of the reference voltage and the terminal resistance value used by the buffer chip 220 may be set (ie, stored) as instruction setting values ​​of level 1 stored in the buffer chip setting circuit 801 .

[0085] The first delay control circuit 861 may control whether to activate the external data interface 320 and the internal data interface 340. The first delay control circuit 861 may activate the external data receiving circuit 321 and the internal data transmission circuit 341 so that, starting from the time point when the write command corresponding to level 0 is applied to the buffer chip 220, after the write delay set by the first setting circuit 881, the external data receiving circuit 321 and the internal data transmission circuit 341 are activated. Figure 1 ) is transmitted to the data DQ of the buffer chip 220<k:k+3> can be received and transmitted to the memory chip 231 of level 0. The first delay control circuit 861 can further activate the internal data receiving circuit 343 and the external data transmission circuit 323 so that, starting from the time point when the read command corresponding to level 0 is applied to the buffer chip 220, after the read delay set by the first setting circuit 881, the data DQ received from the memory chip 231 and then buffered is<k:k+3> can be transmitted from the buffer chip 220 to the memory interface 115 ( Figure 1The first delay control circuit 861 can activate the external data strobe receiving circuit 325 and the internal data strobe transmission circuit 345 during the write operation of level 0, and activate the internal data strobe receiving circuit 347 and the external data strobe transmission circuit 327 during the read operation of level 0, so that the data strobe signals DQS_t and DQS_c can also be synchronized with the data DQ<k:k+3> The first delay control circuit 861 may receive information indicating that the read command and write command of level 0 have been applied to the buffer chip 220 from the first command decoder 871 , and receive information related to the read delay and write delay of level 0 from the first setting circuit 881 .

[0086] The second delay control circuit 863 may control whether to activate the external data interface 320 and the internal data interface 340. The second delay control circuit 863 may activate the external data receiving circuit 321 and the internal data transmission circuit 341 so that, starting from the time point when the write command corresponding to level 1 is applied to the buffer chip 220, after the write delay set by the second setting circuit 883, the external data receiving circuit 321 and the internal data transmission circuit 341 are received from the memory interface 115 ( Figure 1 ) is transmitted to the data DQ of the buffer chip 220<k:k+3> can be received and transmitted to the memory chip 232 of level 1. The second delay control circuit 863 can further activate the internal data receiving circuit 343 and the external data transmission circuit 323 so that, starting from the time point when the read command corresponding to level 1 is applied to the buffer chip 220, after the read delay set by the second setting circuit 883, the data DQ received from the memory chip 232 and then buffered is<k:k+3> can be transmitted from the buffer chip 220 to the memory interface 115 ( Figure 1 The second delay control circuit 863 can activate the external data strobe receiving circuit 325 and the internal data strobe transmission circuit 345 during the write operation of level 1, and activate the internal data strobe receiving circuit 347 and the external data strobe transmission circuit 327 during the read operation of level 1, so that the data strobe signals DQS_t and DQS_c can also be synchronized with the data DQ<k:k+3> The second delay control circuit 863 may receive information indicating that the read command and write command of level 1 have been applied to the buffer chip 220 from the second command decoder 873 , and receive information related to the read delay and write delay of level 1 from the second setting circuit 883 .

[0087] Fig. 9 is a flowchart illustrating an operation according to an embodiment of the present disclosure, in which an Figure 8 An immediate setting value is set in the memory package 120 of the buffer chip 220 shown in FIG.

[0088] refer to Fig. 9 , the external control signal interface 310 of the buffer chip 220 may receive a control signal CS for setting an immediate setting value of level 0 <0> and CA<0:13> (at operation 901). The control signal for setting the immediate setting value of level 0 may include a chip selection signal CS <0> and command address signals CA<0:13>.

[0089] The first command decoder 871 of the buffer chip 220 can decode the chip selection signal CS <0> The command address signal CA<0:13> is decoded, and as a result, the first setting circuit 881 may store an immediate setting value (at operation 903). For example, the read delay RL of level 0 may be stored in the first setting circuit 881. Once the immediate setting value is stored in the first setting circuit 881, it may be immediately applied as a setting value.

[0090] Subsequently, the buffer chip 220 may buffer the control signal CS received in operation 901. <0> and CA<0:13>, and transmits the buffered signal to the memory chip 231 (at operation 905). The memory chip 231 may control the control signal M_CS <0> and M_CA<0:13> are decoded, and as a result, an immediate setting value (eg, read latency) of the memory chip 231 may be set (ie, stored) (at operation 907 ).

[0091] The external control signal interface 310 of the buffer chip 220 may receive a control signal CS for setting an immediate setting value of level 1. <1> and CA<0:13> (at operation 909). The control signal for setting the immediate setting value of level 1 may include a chip selection signal CS <1> and command address signals CA<0:13>.

[0092] The second command decoder 873 of the buffer chip 220 can decode the chip selection signal CS <1> The command address signal CA<0:13> is decoded, and as a result, the second setting circuit 883 may store an immediate setting value (at operation 911). For example, the write latency WL of level 1 may be stored in the second setting circuit 883. Once the immediate setting value is stored in the second setting circuit 883, it may be immediately applied as a setting value.

[0093] Subsequently, the buffer chip 220 may buffer the control signal CS received in operation 909. <1> and CA<0:13>, and transmits the buffered signal to the memory chip 232 (at operation 913). The memory chip 232 may control the control signal M_CS <1> and M_CA<0:13> are decoded, and as a result, the immediate setting value of the memory chip 232 may be set (ie, stored) (at operation 915).

[0094] As from Fig. 9 It can be seen that when the buffer chip 220 receives the control signal CS for setting the immediate setting value of level 0 <0> and CA<0:13>, the immediate setting value of the level 0 of the buffer chip 220 may be set, and when the memory chip 231 of the level 0 receives the control signal M_CS buffered by the buffer chip 220 <0> and M_CA<0:13>, the immediate setting value of the memory chip 231 can be set. In addition, when the buffer chip 220 receives the control signal CS for setting the immediate setting value of level 1 <1> and CA<0:13>, the immediate setting value of the level 1 of the buffer chip 220 may be set, and when the memory chip 232 of the level 1 receives the control signal M_CS buffered by the buffer chip 220 <1> and M_CA<0:13>, the immediate setting value of the memory chip 232 can be set.

[0095] Fig.10 is a flowchart illustrating an operation according to an embodiment of the present disclosure, in which an Figure 8 The buffer chip 220 shown in FIG. 1 sets the instruction setting value in the memory package 120 .

[0096] refer to Fig.10 , the external control signal interface 310 of the buffer chip 220 can receive the control signal CS for setting the instruction setting value of level 0 <0> and CA<0:13> (at operation 1001). The control signal for setting the instruction setting value of level 0 may include a chip selection signal CS <0> and command address signals CA<0:13>.

[0097] The first command decoder 871 of the buffer chip 220 can decode the chip selection signal CS <0> The command address signal CA<0:13> is decoded, and as a result, the first setting circuit 881 may store the instruction setting value (at operation 1003). For example, the value of the reference voltage VREF_CS of level 0 may be stored. In this case, the instruction setting value is only stored in the first setting circuit 881 and may not have been applied yet.

[0098] Subsequently, the buffer chip 220 may buffer the control signal CS received in operation 1001. <0> and CA<0:13>, and transmits the buffered signal to the memory chip 231 (at operation 1005). The memory chip 231 may control the control signal M_CS <0> and M_CA<0:13> are decoded, and as a result, the instruction setting value (eg, the value of VREF_CS) of the memory chip 231 may be stored (at operation 1007). In this case, the instruction setting value is only stored in the memory chip 231 and may not have been applied yet.

[0099] The external control signal interface 310 of the buffer chip 220 may receive a control signal CS for setting a command setting value of level 1. <1> and CA<0:13> (at operation 1009). The control signal for setting the instruction setting value of level 1 may include a chip selection signal CS <1> and command address signals CA<0:13>.

[0100] The second command decoder 873 of the buffer chip 220 can decode the chip selection signal CS <1> The command address signal CA<0:13> is decoded, and as a result, the second setting circuit 883 may store the instruction setting value (at operation 1011). For example, the value of the reference voltage VREF_CS of level 1 may be stored. In this case, the instruction setting value is only stored in the second setting circuit 883 and may not have been applied yet.

[0101] Subsequently, the buffer chip 220 may buffer the control signal CS received in operation 1009. <1> and CA<0:13>, and transmits the buffered signal to the memory chip 232 (at operation 1013). As a result, the instruction setting value of the memory chip 232 may be stored (at operation 1015). In this case, the instruction setting value is only stored in the memory chip 232 and may not have been applied yet.

[0102] The external control signal interface 310 of the buffer chip 220 may receive a control signal CS for setting a value of application level 0. <0> and CA<0:13> (at operation 1017).

[0103] The first command decoder 871 of the buffer chip 220 can decode the chip selection signal CS <0> The first command decoder 871 decodes the command address signal and determines that the application of the setting value of level 0 has been indicated. Under the control of the first command decoder 871, the instruction setting value stored in the first setting circuit 881 may be applied to the buffer chip setting circuit 801 and stored in the buffer chip setting circuit 801 (at operation 1019). When the instruction setting value is stored in the buffer chip setting circuit 801, the setting value may be applied as the setting value of the buffer chip 220. For example, when the value of the reference voltage VREF_CS of level 0 is stored in the buffer chip setting circuit 801, the buffer chip 220 uses the reference voltage VREF_CS of level 0 as a reference voltage for receiving the chip selection signal CS<0:1>.

[0104] Subsequently, the buffer chip 220 may buffer the control signal CS received in operation 1017. <0> and CA<0:13>, and transmits the buffered signal to the memory chip 231 (at operation 1021). As a result, the memory chip 231 may apply the instruction setting value stored in operation 1007 as the setting value of the memory chip 231 (at operation 1023). For example, the memory chip 231 may apply the value of the reference voltage VREF_CS stored in operation 1007 to the level of the reference voltage VREF_CS used by the memory chip 231.

[0105] The external control signal interface 310 of the buffer chip 220 may receive a control signal CS for setting a value of application level 1. <1> and CA<0:13> (at operation 1025).

[0106] The second command decoder 873 of the buffer chip 220 can decode the chip selection signal CS <1> The command address signal CA<0:13> is decoded and it is determined that the application of the setting value of level 1 has been indicated. Under the control of the second command decoder 873, the instruction setting value stored in the second setting circuit 883 may be applied to the buffer chip setting circuit 801 and stored in the buffer chip setting circuit 801 (at operation 1027). The instruction setting value of the first setting circuit 881 stored in operation 1019 may be replaced with the instruction setting value of the second setting circuit 883. When the instruction setting value of level 1 stored in the second setting circuit 883 is stored in the buffer chip setting circuit 801, the setting value may be applied as the setting value of the buffer chip 220. For example, when the value of the reference voltage VREF_CS of level 1 is stored in the buffer chip setting circuit 801, the buffer chip 220 uses the reference voltage VREF_CS of level 1 as a reference voltage for receiving the chip selection signal CS<0:1>.

[0107] Subsequently, the buffer chip 220 may buffer the control signal CS received in operation 1025. <1> and CA<0:13>, and transmits the buffered signal to the memory chip 232 (at operation 1029). As a result, the memory chip 232 may apply the instruction setting value stored in operation 1015 as the setting value of the memory chip 232 (at operation 1031). For example, the memory chip 232 may apply the value of the reference voltage VREF_CS stored in operation 1015 to the level of the reference voltage VREF_CS used by the memory chip 232.

[0108] As from Fig.10 It can be seen that when the buffer chip 220 receives the control signal CS for setting the instruction setting value of level 0 <0> and CA<0:13>, the command setting value of level 0 may be stored in the buffer chip 220, and when the memory chip 231 of level 0 receives the control signal M_CS buffered by the buffer chip 220 <0> and M_CA<0:13>, the memory chip 231 can store the instruction setting value. In addition, when the buffer chip 220 receives the control signal CS for setting the instruction setting value of level 1 <1> and CA<0:13>, the command setting value of level 1 may be stored in the buffer chip 220, and when the memory chip 232 of level 1 receives the control signal M_CS buffered by the buffer chip 220 <1> When M_CA<0:13> is indicated, the memory chip 232 may store the instruction setting value. Subsequently, when the application of the instruction setting value of level 0 is indicated, the instruction setting value of level 0 may be applied to the buffer chip 220 and the memory chip 231, and when the application of the instruction setting value of level 1 is indicated, the instruction setting value of level 1 may be applied to the buffer chip 220 and the memory chip 232.

[0109] Although the embodiments according to the technical aspects of the present disclosure have been described above with reference to the accompanying drawings, this is only used to describe the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the technical aspects of the present disclosure defined in the attached claims, a person skilled in the art of the present disclosure may make various types of replacements, modifications and changes to the embodiments, and it should be understood that these replacements, modifications and changes belong to the scope of the present disclosure. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A method for operating a buffer chip, the method comprising: receiving a first control signal for setting a first memory chip; buffering the first control signal and transmitting the buffered first control signal to the first memory chip; storing a setting value for the first memory chip in response to the first control signal; receiving a second control signal for setting a second memory chip; buffering the second control signal and transmitting the buffered second control signal to the second memory chip; storing a setting value for the second memory chip in response to the second control signal; receiving a third control signal for applying the setting value for the first memory chip; buffering the third control signal and transmitting the buffered third control signal to the first memory chip; as well as The stored setting value for the first memory chip is applied as a setting value for the buffer chip in response to the third control signal.

2. The operating method according to claim 1, further comprising: receiving a fourth control signal for applying the setting value for the second memory chip; buffering the fourth control signal and transmitting the buffered fourth control signal to the second memory chip; as well as The stored setting value for the second memory chip is applied as the setting value for the buffer chip in response to the fourth control signal. 3 . The operating method according to claim 1 , wherein the setting value includes at least one of a level of a reference voltage and a terminal resistance value.

4. A method for operating a semiconductor package, the method comprising: receiving, by the buffer chip, a first control signal for setting the first memory chip; buffering the first control signal by the buffer chip and transmitting the buffered first control signal to the first memory chip; storing, by the buffer chip in response to the first control signal, a setting value for the first memory chip; storing, by the first memory chip in response to the first control signal, the setting value for the first memory chip; The buffer chip receives a second control signal for setting a second memory chip; buffering the second control signal by the buffer chip and transmitting the buffered second control signal to the second memory chip; storing, by the buffer chip in response to the second control signal, a setting value for the second memory chip; storing, by the second memory chip in response to the second control signal, the setting value for the second memory chip; receiving, by the buffer chip, a third control signal for applying the setting value for the second memory chip; buffering the third control signal by the buffer chip and transmitting the buffered third control signal to the second memory chip; applying, by the buffer chip in response to the third control signal, the stored setting value for the second memory chip as a setting value for the buffer chip; as well as The stored setting value for the second memory chip is applied by the second memory chip as the setting value for the second memory chip in response to the third control signal.

5. The operating method according to claim 4, further comprising: receiving, by the buffer chip, a fourth control signal for applying the setting value for the first memory chip; buffering the fourth control signal by the buffer chip and transmitting the buffered fourth control signal to the first memory chip; applying, by the buffer chip in response to the fourth control signal, the stored setting value for the first memory chip as the setting value for the buffer chip; as well as The stored setting value for the first memory chip is applied by the first memory chip as a setting value for the first memory chip in response to the fourth control signal. 6 . The operating method according to claim 4 , wherein the setting value includes at least one of a level of a reference voltage and a terminal resistance value.

7. A buffer chip, comprising: a first command decoder configured to decode a first chip selection signal and a command address signal; a second command decoder configured to decode a second chip selection signal and the command address signal; a first setting circuit configured to store a setting value for a first memory chip according to a decoding result of the first command decoder; a second setting circuit configured to store a setting value for a second memory chip according to a decoding result of the second command decoder; as well as The buffer chip sets the circuit, which is configured as follows: when application of the setting values ​​for the first memory chip is indicated, receiving one or more setting values ​​among the setting values ​​stored in the first setting circuit and storing the received setting values ​​as buffer chip setting values; as well as When application of the setting values ​​for the second memory chip is instructed, one or more setting values ​​among the setting values ​​stored in the second setting circuit are received and the received setting values ​​are stored as the buffer chip setting values.

8. The buffer chip according to claim 7, further comprising: a command address receiving circuit configured to receive the command address signal transmitted from the memory controller; a first chip select signal buffer configured to receive the first chip select signal from the memory controller; a second chip select signal buffer configured to receive the second chip select signal from the memory controller; a command address transmission circuit configured to transmit the command address signal to the first memory chip and the second memory chip; a first chip selection signal driver configured to transmit the first chip selection signal to the first memory chip; as well as A second chip selection signal driver is configured to transmit the second chip selection signal to the second memory chip.

9. The buffer chip according to claim 8, further comprising: an external data interface configured to transmit data to and receive data from the memory controller; an internal data interface configured to transmit data to the first memory chip and the second memory chip, and receive data from the first memory chip and the second memory chip; a first delay control circuit configured to control whether to activate the external data interface and the internal data interface by using a delay setting value among the setting values ​​of the first setting circuit during a read operation and a write operation of the first memory chip; as well as A second delay control circuit is configured to control whether to activate the external data interface and the internal data interface by using a delay setting value among the setting values ​​of the second setting circuit during a read operation and a write operation of the second memory chip. 10 . The buffer chip according to claim 7 , wherein the one or more setting values ​​stored in the buffer chip setting circuit include at least one of a level of a reference voltage and a terminal resistance value.

11. The buffer chip according to claim 7, wherein when the application of the setting value for the first memory chip is indicated, the buffer chip setting circuit is configured to receive one or more setting values ​​among the setting values ​​stored in the first setting circuit and store the received setting values ​​as the buffer chip setting values, and When the application of the setting values ​​for the second memory chip is indicated, the buffer chip setting circuit is configured to receive one or more of the setting values ​​stored in the second setting circuit and change the buffer chip setting values.

12. A buffer chip according to claim 7, wherein when the application of the setting value for the first memory chip and the application of the setting value for the second memory chip are indicated at the same time, the buffer chip setting circuit is configured to receive one or more setting values ​​among the setting values ​​stored in predetermined setting circuits in the first setting circuit and the second setting circuit, and store the received setting values ​​as the buffer chip setting values.

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