Method for manufacturing semiconductor device
By using the double-layer structure of silicon oxide and silicon nitride and multi-layer hard masking technology in semiconductor device manufacturing, the problem of sidewall damage in the active area of the array is solved, and higher manufacturing accuracy and functional stability are achieved.
Patent Information
- Application Number
- CN202410252514.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-03
- Filing Date
- 2024-03-06
- Publication Date
- 2025-03-04
AI Technical Summary
In semiconductor device manufacturing, as the device size decreases, sidewall damage to the active region of the array becomes a major problem, resulting in worse leakage of bit-bit lines on the word line, slowing down reading operations and causing functional failure.
A two-layer structure containing silicon oxide and silicon nitride is adopted, and a mask stacking technique that forms a multi-layer hard mask and anti-reflective coating, combined with the patterning and etching process of photoresist, control the shape of the active region of the array and reduce side wall damage.
Through this method, the sidewall damage in the active region of the array is effectively reduced, the tip-to-tip depth and the side-to-side depth are improved, and the manufacturing accuracy and functional stability of the semiconductor device are improved.
Smart Images
Figure CN119560374A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a method for manufacturing a semiconductor device. Background Art
[0002] In the manufacture of semiconductor devices, with the development of new device generations and processes, the critical dimensions of the devices (i.e., the size of the devices) become smaller and smaller. Therefore, as the device dimensions shrink, sidewall damage in the active area of the array becomes a major problem. This damage will cause worse bit line-to-bit line leakage on the word line, slowing down the read operation of the device and causing functional failures. Summary of the invention
[0003] One aspect of the present disclosure provides a method for manufacturing a semiconductor device.
[0004] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: depositing a first double-layer structure above a substrate, wherein the first double-layer structure includes a silicon oxide layer and a silicon nitride layer located above the silicon oxide layer; forming a first carbon hard mask on the first double-layer structure; forming a second double-layer structure on the first carbon hard mask; forming a mask stack of alternating multiple anti-reflecting coating (ARC) hard masks and multiple second carbon hard masks on the second double-layer structure; and coating a photoresist on the mask stack.
[0005] In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further comprises: patterning a photoresist; etching a mask stack; removing the photoresist; etching the second double-layer structure; and removing the mask stack.
[0006] In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further comprises: etching the first carbon hard mask; removing the second double-layer structure; etching the first double-layer structure; removing the first carbon hard mask; etching the substrate; and removing the first double-layer structure.
[0007] In some embodiments of the present disclosure, the first carbon hard mask includes a diamond-like carbon hard mask.
[0008] In some embodiments of the present disclosure, the second double-layer structure includes an α-silicon layer and a silicon oxide layer located above the α-silicon layer.
[0009] In some embodiments of the present disclosure, the layer of the mask stack that contacts the second bi-layer structure is a second carbon hard mask.
[0010] In some embodiments of the present disclosure, a mask stack of alternating anti-reflecting coating (ARC) hard masks and second carbon hard masks is formed on a second double-layer structure, including: forming a second carbon hard mask on the second double-layer structure; forming a first ARC hard mask on the second carbon hard mask; forming a third carbon hard mask on the first ARC hard mask; and forming a second ARC hard mask on the third carbon hard mask.
[0011] In some embodiments of the present disclosure, depositing the first double-layer structure includes: depositing an oxide layer on the substrate; and depositing a nitride layer over the oxide layer.
[0012] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device.
[0013] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming an oxide layer on a substrate; depositing a first double-layer structure above the oxide layer, wherein the first double-layer structure includes a silicon oxide layer and a silicon nitride layer located above the silicon oxide layer; forming a first carbon hard mask on the first double-layer structure; forming a second double-layer structure on the first carbon hard mask, wherein the second double-layer structure includes an α silicon layer and a silicon oxide layer located above the α silicon layer; and forming an alternating stack of multiple anti-reflecting coating (ARC) hard masks and multiple second carbon hard masks on the second double-layer structure.
[0014] In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further comprises: etching a mask stack; etching the second double-layer structure; and removing the mask stack.
[0015] In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further comprises: etching the first carbon hard mask; removing the second double-layer structure; etching the first double-layer structure; removing the first carbon hard mask; etching the substrate; and removing the first double-layer structure.
[0016] In some embodiments of the present disclosure, the first carbon hard mask includes a diamond-like carbon hard mask.
[0017] In some embodiments of the present disclosure, the layer of the mask stack that contacts the second bi-layer structure is a second carbon hard mask.
[0018] In some embodiments of the present disclosure, a mask stack of alternating anti-reflecting coating (ARC) hard masks and second carbon hard masks is formed on a second double-layer structure, including: forming a second carbon hard mask on the second double-layer structure; forming a first ARC hard mask on the second carbon hard mask; forming a third carbon hard mask on the first ARC hard mask; and forming a second ARC hard mask on the third carbon hard mask.
[0019] In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further comprises: etching an oxide layer; and removing the oxide layer after etching the substrate.
[0020] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device.
[0021] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: depositing a first double-layer structure above a substrate, wherein the first double-layer structure includes a silicon oxide layer and a silicon nitride layer located above the silicon oxide layer; depositing a second double-layer structure above the first double-layer structure, wherein the second double-layer structure includes an α-silicon layer and a silicon oxide layer located above the α-silicon layer; and depositing a hard mask stack of alternating multiple ARC hard masks and multiple carbon hard masks on the second double-layer structure.
[0022] In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further comprises: patterning a hard mask stack; patterning a second double-layer structure; and removing the hard mask stack.
[0023] In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes: patterning the first double-layer structure; removing the second double-layer structure; and patterning the substrate.
[0024] In some embodiments of the present disclosure, patterning the first double-layer structure further includes: patterning the silicon nitride layer; and patterning the silicon oxide layer.
[0025] In some embodiments of the present disclosure, patterning the second double-layer structure further includes: patterning the silicon oxide layer; and patterning the α-silicon layer.
[0026] In the aforementioned embodiments of the present disclosure, since a first double-layer structure comprising silicon nitride and silicon oxide is used in the method for manufacturing a semiconductor device, the etching selectivity of oxide to nitride can help control the shape of the active region of the array, and thereby reduce sidewall damage and improve tip-to-tip depth and side-to-side depth. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.
[0028] Figures 1 to 19 is a cross-sectional view of a semiconductor device in an intermediate step of a manufacturing method according to one embodiment of the present disclosure.
[0029] Fig. 20 for Fig.19 A top view of a semiconductor device. DETAILED DESCRIPTION
[0030] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The specific examples of components and configurations described below are for the purpose of simplifying the disclosure. Of course, these are only examples and are not intended to be limiting. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.
[0031] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
[0032] Figures 1 to 19 is a cross-sectional view of a semiconductor device in an intermediate step of a manufacturing method according to one embodiment of the present disclosure. Figure 1 and Figure 2 , the method for manufacturing a semiconductor device includes: preparing a substrate 110. The material of the substrate 110 includes silicon or other suitable materials. Thereafter, an oxide layer 120 is formed on the substrate 110. The oxide layer 120 is generally referred to as a pad oxide layer and can be formed using a suitable deposition method.
[0033] refer to Figure 3, thereafter, a first double-layer structure 130 is deposited on the oxide layer 120, wherein the first double-layer structure 130 includes a silicon oxide layer 132 and a silicon nitride layer 134. In some embodiments, depositing the first double-layer structure 130 includes: depositing the silicon oxide layer 132 on the substrate 110; and depositing the silicon nitride layer 134 over the silicon oxide layer 132. The first double-layer structure 130 is generally referred to as an "oxide in-situ nitride (OSIN)" double-layer structure. It is formed by first depositing the silicon oxide layer 132 in a chamber using any suitable deposition method (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like), and then depositing the silicon nitride layer 134 in the same chamber using any suitable deposition method (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like). The two different kinds of materials of the first double-layer structure 130 may help to further control the etching process using the etching selectivity between silicon nitride and silicon oxide, which will be discussed herein.
[0034] refer to Figure 4 and Figure 5 , thereafter, a first carbonaceous hard mask 140 is formed on the first double-layer structure 130. Thereafter, a second double-layer structure 150 is formed on the first carbonaceous hard mask 140. The first carbonaceous hard mask 140 includes a diamond like carbonaceous (DLC) hard mask. The second double-layer structure 150 includes an α silicon layer 152 and a silicon oxide layer 154. The second double-layer structure 150 is generally referred to as an "α silicon in-situ oxide" double-layer structure. It is formed by first depositing the α silicon layer 152 in a chamber using any suitable deposition method (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like), and then depositing the silicon oxide layer 154 in the same chamber using any suitable deposition method (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like).
[0035] refer to Figure 6 and Figure 7, thereafter, a stack 160 of alternating anti-reflecting coating (ARC) hard masks 164, 168 and a second carbon hard mask 162 and a third carbon hard mask 166 is formed on the second double-layer structure 150. This step includes: forming the second carbon hard mask 162 on the second double-layer structure 150; forming the first ARC hard mask 164 on the second carbon hard mask 162; forming the third carbon hard mask 166 on the first ARC hard mask 164; and forming the second ARC hard mask 168 on the third carbon hard mask 166. In other words, the layer of the mask stack 160 that contacts the second double-layer structure 150 is the second carbon hard mask 162. Thereafter, a photoresist 170 is coated on the mask stack 160. In other words, the photoresist directly contacts the second ARC hard mask 168 of the mask stack 160.
[0036] refer to Figures 8 to 10 , after which the photoresist 170 is patterned. Here, the term "patterning" may refer to steps such as exposure, development, and etching. Thereafter, the mask stack 160 is patterned using the photoresist 170. Here, each layer of the mask stack 160 is not patterned at the same time, but is patterned using the upper layer as a mask so that one layer is patterned at a time. Fig.11 The patterning of the mask stack 160 will be discussed in . Thereafter, the photoresist 170 is removed.
[0037] refer to Fig.11 , after which the mask stack 160 is patterned layer by layer. As an example, in Fig.10 After patterning the second ARC hard mask 168 in the array, the second ARC hard mask 168 will be used as a mask to pattern the third carbon hard mask 166. After patterning the third carbon hard mask 166, the second ARC hard mask 168 will be removed. The process continues until the last layer of the mask stack 160 (which is the second carbon hard mask 162) is left. This process has two specific purposes: aligning the array active area and reducing the critical dimension. During the repeated patterning process, the line width of the device can be smaller and smaller in each step, but the present disclosure is not limited to this. The second carbon hard mask 162 will be used as a hard mask in a later process. The removal of the second ARC hard mask 168, the third carbon hard mask 166, the first ARC hard mask 164 (and the second carbon hard mask 162 later) can be performed via a chemical-mechanical polishing (CMP) method, a dry etching method or a wet etching method or other suitable methods.
[0038] refer to Fig.12, thereafter, the silicon oxide layer 154 of the second double-layer structure 150 is etched using the second carbon hard mask 162 as a hard mask. This process can be completed using a dry etching method, a reactive ion etching method, or other suitable methods. Thereafter, in some embodiments, the second carbon hard mask 162 is removed. In other embodiments, it acts as a hard mask for subsequent patterning processes.
[0039] refer to Fig.13 , thereafter, the α silicon layer 152 is patterned using the silicon oxide layer 154 (or the second carbon hard mask 162) as a mask. In this particular step, the second double-layer structure 150 having two different kinds of materials can control the area to be patterned using the etching selectivity of the two materials of an etchant (such as a wet etchant). In this case, the etching process may be a wet etching process, a dry etching process, or any other suitable method.
[0040] refer to Fig.14 , thereafter, the first carbon hard mask 140 is etched using the second double-layer structure 150 as a mask. This step can further reduce the critical dimension of the device and align the array active area. After this step, the second double-layer structure 150 is removed. The removal process can be a CMP process, a dry etching process, a wet etching process, or any suitable method.
[0041] refer to Fig.15 and Fig.16 , thereafter, the silicon nitride layer 134 of the first double-layer structure 130 is patterned using the first carbon hard mask 140 as a mask. Thereafter, the silicon oxide layer 132 of the first double-layer structure 130 is patterned using the silicon nitride layer 134 of the first double-layer structure 130 as a mask. The two patterning processes may use different etching methods, such as dry etching for etching the silicon nitride layer 134 and wet etching for etching the silicon oxide layer 132. Since there is a large difference in etching rate between silicon nitride and silicon oxide, when etching the silicon oxide layer 132, the etchant will not etch the silicon nitride layer 134 too much, thereby causing the opening of the silicon nitride layer 134 to further expand and damage the sidewall of the array active area.
[0042] Since the first double-layer structure 130 including silicon nitride and silicon oxide is used in the semiconductor device manufacturing method, the etching selectivity of oxide to nitride can help control the shape of the array active area and thus reduce sidewall damage and improve tip-to-tip depth and side-to-side depth.
[0043] refer to Fig.17, thereafter, the oxide layer 120 is etched using the first double-layer structure 130 as a mask. This step can further reduce the critical dimension of the semiconductor device. After this step, the first double-layer structure 130 is removed. The removal process can be a CMP process, a dry etching process, a wet etching process, or any suitable method.
[0044] refer to Fig.18 , Fig.19 and Fig. 20 Thereafter, the substrate 110 is patterned to form an active region AA (see Fig. 20 ). After this step, the oxide layer 120 is removed, leaving the patterned substrate 110. Fig. 20 for Fig.19 A top view of a semiconductor device. Fig. 20 The active area AA after patterning is shown. In some embodiments, the tip width W1 of the active area AA is 17.1 nanometers, and the width W2 of the active area AA is 23.56 nanometers, but the disclosure is not limited to this scope.
[0045] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.
[0046]
Explanation of symbols
[0047] 110:Substrate
[0048] 120: Oxide layer
[0049] 130: First double-layer structure
[0050] 132, 154: Silicon oxide layer
[0051] 134: Silicon nitride layer
[0052] 140:First Carbon Hard Mask
[0053] 150: Second double-layer structure
[0054] 152: α silicon layer
[0055] 160: Stack
[0056] 162: Second carbon hard mask
[0057] 164: First ARC Hard Mask
[0058] 166: Third carbon hard mask
[0059] 168: Second ARC Hard Mask
[0060] 170: Photoresist
[0061] AA: Active Area
[0062] W1: Tip width
[0063] W2: width.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Depositing a first double-layer structure on the substrate, wherein the first double-layer structure includes a silicon oxide layer and a silicon nitride layer located on the silicon oxide layer; forming a first carbon hard mask on the first bi-layer structure; forming a second double-layer structure on the first carbon hard mask; forming a mask stack of a plurality of alternating anti-reflective coating hard masks and a plurality of second carbon hard masks on the second bi-layer structure; and A photoresist is coated over the mask stack.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: Further comprising the steps of: patterning the photoresist; etching the mask stack; removing the photoresist; etching the second double-layer structure; and Removes the mask stack.
3. The method for manufacturing a semiconductor device according to claim 2, wherein: Further comprising the steps of: etching the first carbon hard mask; removing the second double-layer structure; etching the first double-layer structure; removing the first carbon hard mask; etching the substrate; and The first double-layer structure is removed.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The first carbon hard mask includes a diamond-like carbon hard mask.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The second double-layer structure includes an α-silicon layer and a silicon oxide layer located above the α-silicon layer.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: A layer of the mask stack that contacts the second double-layer structure is a second carbon hard mask.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the mask stack of the plurality of alternating anti-reflective coating hard masks and the plurality of second carbon hard masks on the second bi-layer structure comprises the following steps: forming a second carbon hard mask on the second bi-layer structure; forming a first antireflective coating hard mask on the second carbon hard mask; forming a third carbon hard mask on the first anti-reflective coating hard mask; and A second antireflective coating hard mask is formed on the third carbon hard mask.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of depositing the first double-layer structure comprises the following steps: depositing an oxide layer on the substrate; and A nitride layer is deposited over the oxide layer.
9. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: forming an oxide layer on the substrate; Depositing a first double-layer structure on the oxide layer, wherein the first double-layer structure includes a silicon oxide layer and a silicon nitride layer located on the silicon oxide layer; forming a first carbon hard mask on the first bi-layer structure; forming a second double-layer structure on the first carbon hard mask, wherein the second double-layer structure comprises an α-silicon layer and a silicon oxide layer located above the α-silicon layer; and A mask stack of a plurality of alternating anti-reflective coating hard masks and a plurality of second carbon hard masks is formed on the second bi-layer structure.
10. The method for manufacturing a semiconductor device according to claim 9, wherein: Further comprising the steps of: etching the mask stack; etching the second double-layer structure; and Removes the mask stack.
11. The method for manufacturing a semiconductor device according to claim 10, wherein: Further comprising the steps of: etching the first carbon hard mask; removing the second double-layer structure; etching the first double-layer structure; removing the first carbon hard mask; etching the substrate; and The first double-layer structure is removed.
12. The method for manufacturing a semiconductor device according to claim 9, wherein: The first carbon hard mask includes a diamond-like carbon hard mask.
13. The method for manufacturing a semiconductor device according to claim 9, wherein: A layer of the mask stack that contacts the second double-layer structure is a second carbon hard mask.
14. The method for manufacturing a semiconductor device according to claim 9, wherein: The step of forming the mask stack of the plurality of alternating anti-reflective coating hard masks and the plurality of second carbon hard masks on the second bi-layer structure comprises the following steps: forming a second carbon hard mask on the second bi-layer structure; forming a first antireflective coating hard mask on the second carbon hard mask; forming a third carbon hard mask on the first anti-reflective coating hard mask; and A second antireflective coating hard mask is formed on the third carbon hard mask.
15. The method for manufacturing a semiconductor device according to claim 9, wherein: Further comprising the steps of: etching the oxide layer; and The oxide layer is removed after etching the substrate.
16. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Depositing a first double-layer structure on the substrate, wherein the first double-layer structure includes a silicon oxide layer and a silicon nitride layer located on the silicon oxide layer; Depositing a second double-layer structure on the first double-layer structure, wherein the second double-layer structure comprises an α-silicon layer and a silicon oxide layer located on the α-silicon layer; and A hard mask stack of a plurality of alternating anti-reflective coating hard masks and a plurality of carbon hard masks is deposited on the second bi-layer structure.
17. The method for manufacturing a semiconductor device according to claim 16, wherein: Further comprising the steps of: patterning the hard mask stack; patterning the second bilayer structure; and Remove the hard mask stack.
18. The method for manufacturing a semiconductor device according to claim 17, wherein: Further comprising the steps of: patterning the first bilayer structure; removing the second double-layer structure; and The substrate is patterned.
19. The method for manufacturing a semiconductor device according to claim 18, wherein: The step of patterning the first double-layer structure further comprises the following steps: patterning the silicon nitride layer; and The silicon oxide layer is patterned.
20. The method for manufacturing a semiconductor device according to claim 18, wherein: The step of patterning the second double-layer structure further comprises the following steps: patterning the silicon oxide layer; and The alpha silicon layer is patterned.