A method for manufacturing a chip package structure

Abstract

The application relates to a preparation method of a chip packaging structure. The preparation method of the chip packaging structure comprises the following steps: forming a plurality of holes extending to the inside of a silicon wafer on one side surface of the silicon wafer; filling the holes with conductive material to form a plurality of metal columns; removing part of the height of the silicon wafer, exposing part of the metal columns as target metal columns, and not exposing part of the metal columns as internal metal columns; attaching a silicon bridge structure to the surface of the silicon wafer between the plurality of target metal columns; forming a first redistribution layer on the side of the silicon bridge structure away from the silicon wafer and the side of the target metal columns away from the silicon wafer; the first redistribution layer connects the silicon bridge structure and the target metal columns; and flip-chip setting a plurality of chips on the side of the first redistribution layer away from the silicon wafer. The preparation method of the chip packaging structure provided by the application can prepare metal columns and target metal columns with a higher height-to-diameter ratio and higher stability, realize high-density interconnection between the chips and the target metal columns, and improve the chip packaging yield and the integration of the chip packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to a method for fabricating a chip packaging structure. Background Technology

[0002] As the semiconductor industry's demand for higher-performance, more integrated chips continues to increase, traditional packaging technologies are gradually becoming insufficient to meet these needs. CoWoS-L (Chip-on-Wafer-on-Substrate with Logic) is an advanced integrated circuit packaging technology. CoWoS-L technology is primarily used to integrate logic chips with other functional chips (such as memory or RF chips) in the same package, providing higher performance and lower power consumption.

[0003] The existing CoWoS-L process includes: fabricating a metal interconnect layer on a glass substrate, creating copper pillars (mega pillars), attaching silicon bridges, thinning the substrate through molding, continuing to create metal interconnects, attaching the chip to the front side, thinning again through molding, removing the back glass, and creating back solder balls to complete the process. However, the process of fabricating copper pillars on a glass substrate has certain drawbacks: ① The bonding stability between the copper pillars and the glass substrate is not high, which may cause the copper pillars to detach in subsequent processes; ② The copper pillars formed by applying dry film and etching have low density and height, and a low height-to-diameter ratio, generally only reaching 3:1 or 4:1, which cannot form copper pillars with a high height-to-diameter ratio, resulting in low-density interconnects and low integration of the chip package structure; ③ The glass substrate still needs to be removed by debonding in subsequent processes, which is more complex and may cause surface damage and increased warpage of the package structure during debonding.

[0004] Therefore, a method for fabricating chip packaging structures is needed that can produce copper pillars with a high height-to-diameter ratio, while ensuring the stability of the copper pillars during the packaging process, reducing damage to the chip packaging structure, and lowering the warpage of the chip packaging structure. Summary of the Invention

[0005] Therefore, the present invention provides a method for fabricating a chip packaging structure to solve the problems in the prior art where the copper pillars have low density, low height-to-diameter ratio, poor stability and easy detachment, resulting in the inability to achieve high-density interconnection of chips and low integration of the chip packaging structure.

[0006] This invention provides a method for fabricating a chip packaging structure, comprising the following steps:

[0007] Silicon wafers are supplied;

[0008] Multiple holes are formed on one side surface of the silicon wafer, extending into the interior of the silicon wafer;

[0009] filling the holes with conductive material to form a plurality of metal columns;

[0010] removing part of the height of the silicon wafer to expose part of the height of the metal columns to the surface of the remaining silicon wafer; the exposed part being a target metal column and the unexposed part being an internal metal column;

[0011] attaching a silicon bridge structure to the surface of the silicon wafer between the plurality of target metal columns;

[0012] forming a first redistribution layer on the side of the silicon bridge structure facing away from the silicon wafer and on the side of the target metal columns facing away from the silicon wafer; the first redistribution layer connecting the silicon bridge structure and the target metal columns;

[0013] flip-chip mounting a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer.

[0014] Optionally, the ratio of the height to the diameter of the metal columns is greater than or equal to 10:1.

[0015] Optionally, the target metal columns comprise a plurality of target metal column groups; the distance between adjacent target metal columns in each target metal column group is less than 40 μm.

[0016] Optionally, the step of removing part of the height of the silicon wafer to expose part of the height of the metal columns to the surface of the remaining silicon wafer comprises:

[0017] removing part of the height of the silicon wafer from the side of the opening of the hole to expose part of the height of the metal columns to the surface of the remaining silicon wafer;

[0018] Optionally, the step of flip-chip mounting a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer further comprises:

[0019] thinning the side of the silicon wafer facing away from the target metal columns until the silicon wafer and the internal metal columns are removed;

[0020] forming a second redistribution layer on the side of the target metal columns facing away from the first redistribution layer; the second redistribution layer connecting the silicon bridge structure and the target metal columns.

[0021] Optionally, the silicon bridge structure comprises a silicon bridge body and a silicon bridge metal column.

[0022] Optionally, the step of attaching a silicon bridge structure to the surface of the silicon wafer between the plurality of target metal columns comprises:

[0023] Optionally, the step of forming a first redistribution layer on the side of the silicon bridge structure facing away from the silicon wafer and on the side of the target metal columns facing away from the silicon wafer comprises:

[0024] forming a first redistribution layer on the side of the silicon bridge metal column facing away from the silicon wafer and on the side of the target metal columns facing away from the silicon wafer; the first redistribution layer connecting the silicon bridge metal column and the target metal columns.

[0025] Optionally, the step of thinning the silicon wafer from the side opposite to the target metal pillars until the silicon wafer and the internal metal pillars are removed further comprises:

[0026] Thinning the target metal pillars and the silicon bridge body.

[0027] Optionally, after the step of attaching the silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars, before the step of forming the first redistribution layer on the side of the silicon bridge structure opposite to the silicon wafer and on the side of the target metal pillars opposite to the silicon wafer, further comprising:

[0028] Forming a first encapsulation layer on the surface of the side of the silicon wafer, the first encapsulation layer covering the target metal pillars and the silicon bridge structure;

[0029] Thinning the first encapsulation layer until the target metal pillars and the silicon bridge metal pillars are exposed;

[0030] The first redistribution layer is formed on the side of the first encapsulation layer opposite to the silicon wafer.

[0031] Optionally, in the step of flip-chip mounting a plurality of chips on the side of the first redistribution layer opposite to the silicon wafer, comprising:

[0032] Forming a first pad on the side of the first redistribution layer opposite to the silicon wafer; the first pad connecting the silicon bridge metal pillars and the target metal pillars through the first redistribution layer;

[0033] Flip-chip mounting a plurality of chips on the side of the first pad opposite to the first redistribution layer; the chip pins of the chips are connected to the first pad.

[0034] Optionally, after the step of flip-chip mounting a plurality of chips on the side of the first redistribution layer opposite to the silicon wafer, before the step of thinning the silicon wafer from the side opposite to the target metal pillars until the silicon wafer and the internal metal pillars are removed, further comprising:

[0035] Forming a second encapsulation layer on the surface of the side of the first redistribution layer opposite to the silicon wafer, the second encapsulation layer covering the plurality of chips and the first pad;

[0036] Thinning the second encapsulation layer.

[0037] Optionally, in the step of attaching the silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars, comprising:

[0038] Attaching the silicon bridge structure on the surface of the silicon wafer between two adjacent target metal pillar groups.

[0039] Optionally, in the step of removing part of the height of the silicon wafer to expose part of the height of the metal pillars to the remaining surface of the silicon wafer, comprising:

[0040] Part of the height of the silicon wafer is removed by using a wet etching process or a dry etching process, so that part of the height of the metal column is exposed to the surface of the remaining silicon wafer.

[0041] Optionally, the conductive material is copper; and the metal column is a copper column.

[0042] The chip is an HBM chip and an SOC chip.

[0043] The material of the first plastic sealing layer is epoxy resin.

[0044] The technical scheme of the present application has the following advantages:

[0045] (1) The preparation method of the chip packaging structure provided by the present application can form metal columns with a high height-to-diameter ratio and high density, thereby realizing high-density interconnection between the chip and the copper column, improving the integration of the chip packaging structure, and further reducing the volume of the chip packaging structure.

[0046] (2) In the preparation method of the chip packaging structure provided by the present application, the height-to-diameter ratio of the metal column is greater than or equal to 10:1; the target metal column includes a plurality of target metal column groups; and the distance between adjacent target metal columns in each target metal column group is less than 40 microns.

[0047] (3) The chip packaging structure preparation method provided by the application, after the step of flip-chip setting the plurality of chips, the silicon wafer is thinned on the side opposite to the target metal column until the silicon wafer and the internal metal column are removed, so that the silicon wafer and the internal metal column are removed without the need of removing the silicon wafer and the internal metal column through an additional process, the silicon wafer and the internal metal column are removed while the back of the chip packaging structure is thinned, the process flow is simplified, and the problem of damage and increased warping of the packaging structure caused by the debonding process of the glass carrier is avoided. Therefore, the chip packaging structure preparation method provided by the application can simplify the process flow, reduce the damage to the chip packaging structure, and reduce the warping degree of the chip packaging structure by removing the silicon wafer and the internal metal column through thinning.

[0048] (4) In the chip packaging structure preparation method provided by the application, in the step of attaching the silicon bridge structure to the surface of the silicon wafer between the plurality of target metal columns, the silicon bridge body is located on the surface of the silicon wafer, and since the silicon bridge body and the silicon wafer are both made of silicon, the stability of the attached silicon bridge structure can be improved, and the stability and yield of the chip packaging structure can be improved.

[0049] (5) In the chip packaging structure preparation method provided by the application, after the step of attaching the silicon bridge structure, before the step of forming the first redistribution layer, a first plastic encapsulation layer is formed on one side surface of the silicon wafer and is thinned until the target metal column and the silicon bridge metal column are exposed, so that the target metal column and the silicon bridge metal column are at the same height, thereby ensuring that the first redistribution layer formed subsequently simultaneously connects the silicon bridge structure and the target metal column, in addition, the first plastic encapsulation layer can improve the stability of the target metal column and the silicon bridge structure, reduce electromagnetic interference, protect the target metal column and the silicon bridge structure from being damaged, thereby improving the reliability and yield of the chip packaging structure.

[0050] (6) In the chip packaging structure preparation method provided by the application, after the step of flip-chip setting the plurality of chips, before the step of thinning the silicon wafer, a second plastic encapsulation layer is formed on the side surface of the first redistribution layer opposite to the silicon wafer and is thinned, so that the chip, the first redistribution layer, the first pad and other structures in the chip packaging structure are completely covered before the silicon wafer and the internal metal column are removed by thinning, the damage to the chip packaging structure can be reduced, in addition, the second redistribution layer can improve the stability of the chip, the first redistribution layer, the first pad and other structures, reduce electromagnetic interference, protect the chip, the first redistribution layer, the first pad and other structures from being damaged, thereby improving the reliability and yield of the chip packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to make the technical solutions in the specific embodiments or prior art of the present application more clearly understood, the drawings needed in the specific embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0052] Figure 1 A structural schematic diagram of a preparation method of a copper pillar in a chip packaging structure of the prior art;

[0053] Figure 2 A flowchart of a preparation method of a chip packaging structure of an embodiment of the present application;

[0054] Figure 3 A specific flowchart of a preparation method of a chip packaging structure of an embodiment of the present application.

[0055] Figures 4-14 A structural schematic diagram of each step in the specific flowchart of the preparation method of a chip packaging structure of an embodiment of the present application.

[0056] Legend of reference signs:

[0057] 100-silicon wafer; 200-glass wafer; 10-copper pillar; 11-target copper pillar; 12-internal copper pillar; 20-silicon bridge structure; 21-silicon bridge main body; 22-silicon bridge copper pillar; 30-first plastic sealing layer; 40-first redistribution layer; 50-first pad; 60-chip; 61-HBM1 chip; 62-SOC chip; 63-HBM2 chip; 70-second plastic sealing layer; 80-second redistribution layer; 90-pin. EMBODIMENT

[0058] The method for making a copper pillar in the existing CoWoS-L process is as follows Figure 1As shown, copper pillars 10 are fabricated by depositing a copper layer, applying a dry film, and etching on a glass substrate 200. Chip packaging processes continue on the formed copper pillars 10, such as: attaching silicon bridges, thinning after molding, continuing metal interconnects, attaching the chip to the front side, thinning again after molding, removing the back glass, and adding back solder balls. However, the process of fabricating copper pillars 10 on the glass substrate 200 has certain drawbacks: ① The bonding stability between the copper pillars and the glass substrate is not high, which may cause the copper pillars to detach in subsequent processes; ② The copper pillars fabricated by applying a dry film and etching have a pitch greater than 80μm, resulting in low density; the height-to-diameter ratio of the copper pillars is low, generally only reaching 3:1 or 4:1, making it impossible to form copper pillars with a high height-to-diameter ratio, resulting in the inability to achieve high-density interconnects and low integration of the chip packaging structure; ③ The glass substrate needs to be removed by debonding in subsequent processes, which is more complex and may cause surface damage and increased warpage of the packaging structure during debonding.

[0059] To address the problems of low density, low height-to-diameter ratio, poor stability, and easy detachment of copper pillars in existing technologies, which prevent high-density interconnection and result in low integration of chip packaging structures, this invention provides a method for fabricating a chip packaging structure, comprising: providing a silicon wafer; forming multiple holes on one side surface of the silicon wafer, the holes extending into the interior of the silicon wafer; filling the holes with a conductive material to form multiple metal pillars; removing a portion of the silicon wafer, exposing a portion of the metal pillars on the remaining silicon wafer surface; the exposed portion serving as target metal pillars, and the unexposed portion serving as internal metal pillars; mounting silicon bridge structures on the silicon wafer surface between the multiple target metal pillars; forming a first super-wiring layer on the side of the silicon bridge structure facing away from the silicon wafer and on the side of the target metal pillars facing away from the silicon wafer; the first super-wiring layer connecting the silicon bridge structure and the target metal pillars; and flip-chip mounting multiple chips on the side of the first super-wiring layer facing away from the silicon wafer.

[0060] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0061] Example 1

[0062] like Figure 2 As shown, this embodiment provides a method for fabricating a chip packaging structure, including:

[0063] S101 provides silicon wafers.

[0064] S102, forming a plurality of holes on one side surface of the silicon wafer, the holes extending to the inside of the silicon wafer.

[0065] In specific implementation, the plurality of holes can be formed by laser drilling, dry etching or wet etching, and the present embodiment does not limit the forming method. The plurality of holes are perpendicular to the surface of the silicon wafer, and the ratio of the height to the diameter of the holes is high, and the density of the holes is also high.

[0066] S103, filling the holes with conductive material to form a plurality of metal columns.

[0067] In specific implementation, the conductive material can be a metal material, such as copper, silver, tin, etc., and the metal column can be a copper column, a silver column, a tin column, etc.

[0068] S104, removing part of the height of the silicon wafer to expose part of the height of the metal column to the surface of the remaining silicon wafer; the exposed part is a target metal column, and the unexposed part is an internal metal column.

[0069] In specific implementation, the target metal column is part of the final chip packaging structure. According to the actual needs of the chip packaging structure, part of the height of the silicon wafer is removed to expose the target metal column.

[0070] S105, attaching a silicon bridge structure to the surface of the silicon wafer between the plurality of target metal columns.

[0071] In specific implementation, the silicon bridge structure can be attached by using a DAF film or other adhesive film material.

[0072] S106, forming a first redistribution layer on the side of the silicon bridge structure away from the silicon wafer and the side of the target metal column away from the silicon wafer; the first redistribution layer connects the silicon bridge structure and the target metal column.

[0073] S107, flip-chip setting a plurality of chips on the side of the first redistribution layer away from the silicon wafer.

[0074] In specific implementation, the plurality of chips can be the same chip or different chips.

[0075] The preparation method of the chip packaging structure provided in the embodiment can form metal columns with a high height-to-diameter ratio and a high density, thereby realizing high-density interconnection between the chip and the target metal columns, improving the integration of the chip packaging structure, and further reducing the volume of the chip packaging structure.

[0076] Further, in some embodiments, the height-to-diameter ratio of the metal column is greater than or equal to 10:1.

[0077] The target metal columns include a plurality of target metal column groups, and the spacing between adjacent target metal columns in each target metal column group is less than 40 μm.

[0078] In specific implementation, the height of the target metal column and the internal metal column can be set according to requirements. In some embodiments, the height of the internal metal column is small, for example, the height of the internal metal column is equal to the diameter D of the metal column, and in this case, the height-to-diameter ratio of the target metal column is greater than or equal to 9:1. In other embodiments, the height of the internal metal column can be set to other multiples of the diameter D of the metal column according to requirements, which is not limited in the embodiment.

[0079] In the preparation method of the chip packaging structure provided in the embodiment, the height-to-diameter ratio of the metal column is greater than or equal to 10:1, the target metal columns include a plurality of target metal column groups, and the spacing between adjacent target metal columns in each target metal column group is less than 40 μm. By preparing metal columns with a high height-to-diameter ratio and a high density, target metal columns with a high height-to-diameter ratio and a high density can be obtained, high-density interconnection between the chip and the target metal columns can be realized, the integration of the chip packaging structure can be improved, and the volume of the chip packaging structure can be further reduced.

[0080] Further, in some embodiments, the step of removing part of the height of the silicon wafer to expose part of the height of the metal column to the surface of the remaining silicon wafer includes:

[0081] Part of the height of the silicon wafer is removed from the side of the opening position of the hole to expose part of the height of the metal column to the surface of the remaining silicon wafer.

[0082] After the step of flip-chip setting the plurality of chips on the side of the first redistribution layer facing away from the silicon wafer, further comprising:

[0083] Thinning the silicon wafer on the side facing away from the target metal pillars until the silicon wafer and the internal metal pillars are removed.

[0084] Forming a second redistribution layer on the side of the target metal pillars facing away from the first redistribution layer; the second redistribution layer connects the silicon bridge structure and the target metal pillars.

[0085] In the method for manufacturing the chip packaging structure provided by the embodiment, after the step of flip-chip setting the plurality of chips, the silicon wafer is thinned on the side facing away from the target metal pillars until the silicon wafer and the internal metal pillars are removed. Therefore, the silicon wafer and the internal metal pillars do not need to be removed through an additional process. The silicon wafer and the internal metal pillars are removed while the back of the chip packaging structure is thinned, which simplifies the process flow and avoids the problem of increased damage and warping of the packaging structure caused by the debonding process of the glass carrier wafer. Therefore, the method for manufacturing the chip packaging structure provided by the present application can simplify the process flow, reduce damage to the chip packaging structure, and reduce the warping degree of the chip packaging structure by removing the silicon wafer and the internal metal pillars through thinning.

[0086] Further, in some embodiments, the silicon bridge structure includes a silicon bridge body and a silicon bridge metal pillar.

[0087] In the step of attaching the silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars, the silicon bridge body is located on the surface of the silicon wafer, and the silicon bridge metal pillar is located on the side of the silicon bridge structure facing away from the silicon wafer.

[0088] In the step of forming the first redistribution layer on the side of the silicon bridge metal pillar facing away from the silicon wafer and the side of the target metal pillar facing away from the silicon wafer, comprising:

[0089] Forming the first redistribution layer on the side of the silicon bridge metal pillar facing away from the silicon wafer and the side of the target metal pillar facing away from the silicon wafer; the first redistribution layer connects the silicon bridge metal pillar and the target metal pillar.

[0090] In the method for manufacturing the chip packaging structure provided by the embodiment, in the step of attaching the silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars, the silicon bridge body is located on the surface of the silicon wafer. Since the materials of the silicon bridge body and the silicon wafer are both silicon, the stability of the attached silicon bridge structure can be improved, and thus the stability and yield of the chip packaging structure can be improved.

[0091] Further, in some embodiments, the step of thinning the silicon wafer on the side facing away from the target metal pillars until the silicon wafer and the internal metal pillars are removed further comprises:

[0092] Thinning part of the target metal pillars and part of the silicon bridge body.

[0093] Further, in some embodiments, after the step of attaching the silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars, and before the step of forming the first redistribution layer on the side of the silicon bridge structure and the side of the target metal pillars away from the silicon wafer, further comprising:

[0094] forming a first encapsulation layer on the side of the silicon wafer, the first encapsulation layer covering the target metal pillars and the silicon bridge structure;

[0095] thinning the first encapsulation layer until the target metal pillars and the silicon bridge metal pillars are exposed;

[0096] the first redistribution layer is formed on the side of the first encapsulation layer away from the silicon wafer.

[0097] The preparation method of the chip packaging structure provided by the embodiment forms a first encapsulation layer on the side of the silicon wafer after the step of attaching the silicon bridge structure, and before the step of forming the first redistribution layer, and thins the first encapsulation layer until the target metal pillars and the silicon bridge metal pillars are exposed, so that the target metal pillars and the silicon bridge metal pillars are at the same height, thereby ensuring that the subsequently formed first redistribution layer simultaneously connects the silicon bridge structure and the target metal pillars, in addition, the first encapsulation layer can also improve the stability of the target metal pillars and the silicon bridge structure, reduce electromagnetic interference, protect the target metal pillars and the silicon bridge structure from damage, thereby improving the reliability and yield of the chip packaging structure.

[0098] Further, in some embodiments, in the step of flip-chip setting a plurality of chips on the side of the first redistribution layer away from the silicon wafer, comprising:

[0099] forming a first pad on the side of the first redistribution layer away from the silicon wafer; the first pad connects the silicon bridge metal pillars and the target metal pillars through the first redistribution layer;

[0100] flip-chip setting a plurality of chips on the side of the first pad away from the first redistribution layer; the chip pins of the chips are connected with the first pad.

[0101] Further, in some embodiments, after the step of flip-chip setting a plurality of chips on the side of the first redistribution layer away from the silicon wafer, and before the step of thinning the side of the silicon wafer away from the target metal pillars until the silicon wafer and the internal metal pillars are removed, further comprising:

[0102] forming a second encapsulation layer on the side of the first redistribution layer away from the silicon wafer, the second encapsulation layer covering the plurality of chips and the first pad;

[0103] thinning the second encapsulation layer.

[0104] The preparation method of the chip packaging structure provided by the embodiment includes the following steps: forming a first plastic encapsulation layer on the surface of the silicon wafer opposite to the first redistribution layer; and thinning the silicon wafer. The second plastic encapsulation layer is formed on the surface of the first redistribution layer opposite to the silicon wafer after the step of inversely arranging the plurality of chips, and before the step of thinning the silicon wafer. The second plastic encapsulation layer can completely encapsulate the chips, the first redistribution layer, the first pads and other structures in the chip packaging structure before the silicon wafer and the internal metal pillars are removed by thinning, so that the damage to the chip packaging structure is reduced. In addition, the second redistribution layer can also improve the stability of the chips, the first redistribution layer, the first pads and other structures, reduce electromagnetic interference, and protect the chips, the first redistribution layer, the first pads and other structures from being damaged, thereby improving the reliability and yield of the chip packaging structure.

[0105] Further, in some embodiments, after the step of forming the second redistribution layer on the side of the target metal pillar opposite to the first redistribution layer, the method further includes:

[0106] forming a pin on the side of the second redistribution layer opposite to the target metal pillar.

[0107] Further, in some embodiments, in the step of mounting the silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars, the method includes:

[0108] mounting the silicon bridge structure on the surface of the silicon wafer between the two adjacent target metal pillar groups.

[0109] Further, in some embodiments, in the step of removing part of the height of the silicon wafer to expose part of the height of the metal pillar to the remaining surface of the silicon wafer, the method includes:

[0110] using a wet etching process or a dry etching process to remove part of the height of the silicon wafer to expose part of the height of the metal pillar to the remaining surface of the silicon wafer.

[0111] Further, in some embodiments, the conductive material is copper; and the metal pillar is a copper pillar.

[0112] The chip is an HBM chip and an SOC chip.

[0113] The material of the first plastic encapsulation layer is epoxy resin.

[0114] The material of the second plastic encapsulation layer is epoxy resin.

[0115] In specific implementation, the chip can be an HBM1 chip, an HBM2 chip and an SOC chip. The number of each chip can be set according to actual requirements.

[0116] Embodiment 2

[0117] Reference Figure 3 The embodiment provides a specific process of a preparation method of a chip packaging structure, including steps S201-S213.

[0118] S201 provides 100 silicon wafers.

[0119] S202, multiple holes are formed on one side surface of silicon wafer 100, and the holes extend into the interior of silicon wafer 100.

[0120] S203, fill the holes with copper to form multiple copper pillars 10, such as Figure 4 As shown, the ratio of the height to the diameter of the copper column 10 is greater than or equal to 10:1.

[0121] S204, a portion of the silicon wafer 100 is removed from one side of the opening position of the hole, exposing part of the height of the copper pillar 10 to the remaining surface of the silicon wafer 100; the exposed portion serves as the target copper pillar 11, and the unexposed portion serves as the internal copper pillar 12, as shown below. Figure 5 As shown, the target copper pillar 11 includes two groups of target copper pillars; the ratio of the height to the diameter of the target copper pillar 11 is greater than or equal to 9:1.

[0122] S205, a silicon bridge structure 20 is mounted on the surface of the silicon wafer 100 between the two target copper pillar groups. The silicon bridge structure 20 includes a silicon bridge body 21 and silicon bridge copper pillars 22. The silicon bridge body 21 is located on the surface of the silicon wafer 100, and the silicon bridge copper pillars 22 are located on the side of the silicon bridge structure 20 facing away from the silicon wafer 100. Figure 6 As shown.

[0123] S206, a first molding compound 30 is formed on one side surface of the silicon wafer 100. The first molding compound 30 covers the target copper pillar 11 and the silicon bridge structure 20, as shown below. Figure 7 As shown;

[0124] S207, thin the first molding layer 30 until the target copper pillar 11 and silicon bridge copper pillar 22 are exposed, as shown. Figure 8 As shown;

[0125] S208, a first redistribution layer 40 is formed on the side of the first molding compound 30 facing away from the silicon wafer 100; the first redistribution layer 40 connects the silicon bridge copper pillar 22 and the target copper pillar 11, as shown in the figure. Figure 9 As shown;

[0126] S209, a first pad 50 is formed on the side of the first redistribution layer 40 facing away from the silicon wafer 100; the first pad 50 connects the silicon bridge copper pillar 22 and the target copper pillar 11 through the first redistribution layer 40, such as Figure 10 As shown;

[0127] S210, on the side of the first pad 50 facing away from the first redistribution layer 40, HBM1 chip 61, SOC chip 62, SOC chip 63 and HBM2 chip 63 are sequentially flip-chip mounted; the chip pins of the chips are connected to the first pad 50, such as... Figure 11 As shown.

[0128] S211, forming a second plastic sealing layer 70 on the side surface of the first redistribution layer 40 away from the silicon wafer 100, the second plastic sealing layer 70 covering the plurality of chips 60 and the first pads 50; thinning the second plastic sealing layer 70, as shown in Figure 12

[0129] S212, thinning the silicon wafer 100 away from the target copper pillar 11 until the silicon wafer 100 and the internal copper pillar 12 are removed, as shown in Figure 13

[0130] S213, sequentially forming a second redistribution layer 80 and a pin 90 on the side of the target copper pillar 11 away from the first redistribution layer 40; the pin 90 connects the silicon bridge structure 20 and the target copper pillar 11 through the second redistribution layer 80, as shown in Figure 14

[0131] The preparation method of the chip packaging structure provided by the present application can form a copper pillar with a high height-to-diameter ratio and high density, thereby realizing high-density interconnection between the chip and the target copper pillar, improving the integration of the chip packaging structure, and further reducing the volume of the chip packaging structure. After removing part of the height of the silicon wafer, the stability of the target copper pillar is improved due to the presence of the internal copper pillar in the silicon wafer, which can ensure that the target copper pillar will not fall off or deviate in subsequent steps, thereby improving the yield of the chip packaging structure. The silicon wafer and the internal copper pillar are removed at the same time as the back of the chip packaging structure is thinned, which simplifies the process flow and avoids the problem of increased damage and warping of the packaging structure caused by the debonding process of the glass carrier. Therefore, the preparation method of the chip packaging structure provided by the present application can prepare a copper pillar and a target copper pillar with a high height-to-diameter ratio, high density, and high stability, thereby realizing high-density interconnection between the chip and the target copper pillar, improving the yield of the chip packaging structure and the integration of the chip packaging structure, and further reducing the volume of the chip packaging structure. In addition, the process flow can be simplified, the damage to the chip packaging structure can be reduced, and the warping degree of the chip packaging structure can be reduced.

[0132] Obviously, the above embodiments are only examples for clearly illustrating the present application, and are not intended to limit the present application. Based on the above description, those skilled in the art can make other different forms of changes or modifications. Here, all the embodiments are not required to be exhausted, and the obvious changes or modifications derived therefrom are still within the protection scope of the present application.​​​

Claims

1. A method for fabricating a chip packaging structure, characterized in that, The method comprises the following steps: providing a silicon wafer; forming a plurality of holes on one side of the silicon wafer, the holes extending into the interior of the silicon wafer; filling the holes with a conductive material to form a plurality of metal pillars; removing part of the height of the silicon wafer to expose part of the height of the metal pillars to the surface of the remaining silicon wafer; the exposed part is a target metal pillar, and the unexposed part is an internal metal pillar; attaching a silicon bridge structure to the surface of the silicon wafer between the plurality of target metal pillars; forming a first redistribution layer on the side of the silicon bridge structure facing away from the silicon wafer and the side of the target metal pillars facing away from the silicon wafer; the first redistribution layer connects the silicon bridge structure and the target metal pillars; flip-chip mounting a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer.

2. The method of claim 1, wherein: the ratio of the height to the diameter of the metal pillars is greater than or equal to 10:1; the target metal pillars include a plurality of target metal pillar groups; the distance between adjacent target metal pillars in each target metal pillar group is less than 40 μm.

3. The method of claim 1, wherein: in the step of removing part of the height of the silicon wafer to expose part of the height of the metal pillars to the surface of the remaining silicon wafer, the step comprises: removing part of the height of the silicon wafer from the side of the opening of the hole to expose part of the height of the metal pillars to the surface of the remaining silicon wafer; after the step of flip-chip mounting a plurality of chips on the side of the first redistribution layer facing away from the silicon wafer, the method further comprises: thinning the side of the silicon wafer facing away from the target metal pillars until the silicon wafer and the internal metal pillars are removed; forming a second redistribution layer on the side of the target metal pillars facing away from the first redistribution layer; the second redistribution layer connects the silicon bridge structure and the target metal pillars.

4. The method of claim 3, wherein: the silicon bridge structure includes a silicon bridge body and a silicon bridge metal pillar; in the step of attaching a silicon bridge structure to the surface of the silicon wafer between the plurality of target metal pillars, the silicon bridge body is located on the surface of the silicon wafer, and the silicon bridge metal pillar is located on the side of the silicon bridge structure facing away from the silicon wafer; in the step of forming a first redistribution layer on the side of the silicon bridge structure facing away from the silicon wafer and the side of the target metal pillars facing away from the silicon wafer, the step comprises: forming the first redistribution layer on the side of the silicon bridge metal pillar facing away from the silicon wafer and the side of the target metal pillars facing away from the silicon wafer; the first redistribution layer connects the silicon bridge metal pillar and the target metal pillars.

5. The method of claim 4, wherein: in the step of thinning the side of the silicon wafer facing away from the target metal pillars until the silicon wafer and the internal metal pillars are removed, the step further comprises: thinning part of the target metal pillars and part of the silicon bridge body.

6. The method of claim 4, wherein: After the step of attaching the silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars, and before the step of forming the first redistribution layer on the side of the silicon bridge structure and the side of the target metal pillars away from the silicon wafer, the method further comprises: forming a first encapsulation layer on the side of the silicon wafer, the first encapsulation layer covering the target metal pillars and the silicon bridge structure; thinning the first encapsulation layer until the target metal pillars and the silicon bridge metal pillars are exposed; forming the first redistribution layer on the side of the first encapsulation layer away from the silicon wafer.

7. The method of claim 6, wherein the step of flip-chip mounting a plurality of chips on the side of the first redistribution layer away from the silicon wafer comprises: forming a first pad on the side of the first redistribution layer away from the silicon wafer, the first pad being connected to the silicon bridge metal pillars and the target metal pillars through the first redistribution layer; flip-chip mounting a plurality of the chips on the side of the first pad away from the first redistribution layer, the chip pins of the chips being connected to the first pad.

8. The method of claim 7, wherein after the step of flip-chip mounting a plurality of chips on the side of the first redistribution layer away from the silicon wafer, and before the step of thinning the silicon wafer on the side away from the target metal pillars until the silicon wafer and the internal metal pillars are removed, the method further comprises: forming a second encapsulation layer on the side of the first redistribution layer away from the silicon wafer, the second encapsulation layer covering the plurality of chips and the first pad; thinning the second encapsulation layer.

9. The method of claim 2, wherein the step of attaching the silicon bridge structure on the surface of the silicon wafer between the plurality of target metal pillars comprises: attaching the silicon bridge structure on the surface of the silicon wafer between two adjacent target metal pillar groups.

10. The method of claim 1, wherein the step of removing part of the height of the silicon wafer to expose part of the height of the metal pillars to the remaining surface of the silicon wafer comprises: using a wet etching process or a dry etching process to remove part of the height of the silicon wafer to expose part of the height of the metal pillars to the remaining surface of the silicon wafer.

11. The method of claim 6, wherein the conductive material is copper; the metal pillars are copper pillars; the chips are HBM chips and SOC chips; the material of the first encapsulation layer is epoxy resin. ​ ​ ​ ​ ​

Images