Packaging method and packaging structure of wafer-level large chip

Abstract

The invention provides a wafer-level large chip packaging method and packaging structure, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining a wafer-level large chip; the wafer-level large chip is a chip structure formed by combining a plurality of different types of core particles or a plurality of single type of core particles; preparing a plurality of metal columns on the first surface of the wafer-level large chip according to the bonding point positions of the wafer-level large chip and the substrate; a glass adapter plate is prepared, the glass adapter plate comprises a plurality of glass through holes, and the positions of the glass through holes are in one-to-one correspondence with the positions of the metal columns; the metal columns on the first surface of the wafer-level large chip are inserted into the glass through holes of the glass adapter plate, so that the first surface of the wafer-level large chip is bonded with the first surface of the glass adapter plate; and bonding the second surface of the glass adapter plate with the substrate to obtain the packaging structure of the wafer-level large chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a packaging method and packaging structure for a wafer-level large chip. Background Art

[0002] With the continuous increase in chip size and the improvement of functional integration, the packaging technology of large wafer-level chips faces increasingly complex manufacturing processes and severe cost control challenges.

[0003] Specifically, traditional packaging processes require multiple alignment and connection steps to achieve multi-layer interconnect structures and high-density solder joints, which can easily lead to process errors and packaging defects. This is especially true for large chip packaging, where the alignment and connection steps between the chip and the substrate are complex and require even higher alignment precision. Any slight alignment error can lead to interconnect defects, impacting the overall performance and reliability of the package. Summary of the Invention

[0004] In view of the above problems, embodiments of the present application provide a packaging method and packaging structure for a wafer-level large chip, so as to overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect of an embodiment of the present application, a method for packaging a large wafer-level chip is provided, the method comprising: Obtaining a large wafer-level chip; the large wafer-level chip refers to a chip structure composed of multiple different types of core particles or multiple single-type core particles; According to the bonding points between the wafer-level large chip and the substrate, a plurality of metal pillars are prepared on the first surface of the wafer-level large chip; Prepare a glass transfer plate, wherein the glass transfer plate includes a plurality of through-glass holes, and positions of the through-glass holes correspond one-to-one to positions of the plurality of metal pillars; Inserting the metal pillars on the first surface of the wafer-level large chip into the through-glass holes of the glass transfer plate to bond the first surface of the wafer-level large chip to the first surface of the glass transfer plate; The second surface of the glass transfer plate is bonded to the substrate to obtain the packaging structure of the wafer-level large chip.

[0006] In one possible implementation, the step of preparing the glass transfer plate includes: obtaining a glass substrate; Preparing the through-glass vias on the glass substrate according to the bonding points between the wafer-level large chip and the substrate; A first seed layer is prepared on the sidewall of the through-glass hole by magnetron sputtering or evaporation process, and the metal material used in the first seed layer is the same as the metal material used in the metal column.

[0007] In a possible implementation, the step of preparing the through-glass via on the glass substrate includes: The through-glass hole is prepared on the glass substrate by laser induced etching, and the diameter of the through-glass hole is greater than 300 μm.

[0008] In one possible implementation, bonding the first surface of the wafer-level large chip to the first surface of the glass transfer plate includes: On the second surface of the glass adapter plate, driving solder balls into each of the through-glass holes; The solder balls are melted by a thermal reflow process and then fill the gap between the through glass via and the metal column.

[0009] In a possible implementation, after obtaining the wafer-level large chip, the method further includes: preparing a dielectric layer of the wafer-level large chip; A redistribution layer (RDL) of the wafer-level large chip is prepared, wherein the RDL interconnection layer is used to realize interconnection between the plurality of core particles within the wafer-level large chip.

[0010] In one possible implementation, preparing a plurality of metal pillars on the first surface of the wafer-level large chip includes: sputtering a second seed layer on the first surface of the wafer-level large chip, wherein the metal material used in the second seed layer is the same as the metal material used in the metal pillar; The second seed layer is photolithographically processed to obtain a plurality of metal pads according to the bonding points between the wafer-level large chip and the substrate; The plurality of metal pads are electroplated to obtain the plurality of metal pillars, wherein the height of the metal pillars is greater than or equal to 2 / 3 of the depth of the through-glass hole, and the diameter of the metal pillars is smaller than the diameter of the through-glass hole.

[0011] In a possible implementation manner, the metal material used for the metal column is copper.

[0012] In a possible implementation, bonding the second surface of the glass transfer plate to the substrate includes: A ball planting process is adopted on the second surface of the glass transfer plate to perform flip-chip bonding on the second surface of the glass transfer plate and the substrate to obtain the packaging structure of the wafer-level large chip.

[0013] A second aspect of the embodiment of the present application further provides a packaging structure of a wafer-level large chip, wherein the packaging structure of the wafer-level large chip is prepared by the packaging method of the wafer-level large chip described in the first aspect; The packaging structure includes: Wafer-level large chip; the wafer-level large chip refers to a chip structure composed of multiple different types of core particles or multiple single-type core particles; The first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate; The glass transfer plate includes multiple glass through holes, each of which includes a metal column, one end of which is connected to the bonding point on the first surface of the wafer-level large chip, and the other end of which is connected to the bonding point on the substrate through a solder ball.

[0014] In a possible implementation, the height of the metal column is greater than or equal to 2 / 3 of the depth of the through-glass via, and less than or equal to the depth of the through-glass via.

[0015] An embodiment of the present application provides a packaging method for a wafer-level large chip, the method comprising: obtaining a wafer-level large chip; the wafer-level large chip refers to a chip structure composed of a plurality of different types of core particles or a plurality of single core particles; preparing a plurality of metal pillars on the first surface of the wafer-level large chip according to the bonding points between the wafer-level large chip and the substrate; preparing a glass transfer plate, the glass transfer plate comprising a plurality of glass through holes, the positions of the glass through holes corresponding one-to-one to the positions of the plurality of metal pillars; inserting the metal pillars on the first surface of the wafer-level large chip into the glass through holes of the glass transfer plate, so that the first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate; bonding the second surface of the glass transfer plate to the substrate to obtain the packaging structure of the wafer-level large chip.

[0016] The packaging method for wafer-level large chips provided in the present application prepares multiple metal pillars on the wafer-level large chip, inserts the metal pillars into the glass through-holes on the glass transfer plate, completes the bonding between the wafer-level large chip and the glass transfer plate, and then completes the bonding between the wafer-level large chip and the substrate by implanting solder balls, thereby simplifying the packaging process between the large chip and the substrate (especially the alignment and connection steps) and achieving high-precision alignment between the large chip and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 This is a flowchart of the steps of a wafer-level large chip packaging method provided in an embodiment of the present application; Figure 2 is a schematic structural diagram of a metal pillar formed in a packaging method provided in an embodiment of the present application; Figure 3 is a structural schematic diagram of a glass transfer plate formed in a packaging method provided in an embodiment of the present application; Figure 4 This is a schematic diagram of a process for preparing a glass transfer plate formed in a packaging method provided in an embodiment of the present application; Figure 5 This is a schematic diagram of the structure of a large wafer-level chip and a glass transfer plate after alignment, provided by an embodiment of the present application; Figure 6 This is a schematic diagram of the structure of a wafer-level large chip bonded to a glass transfer plate formed by a packaging method provided in an embodiment of the present application; Figure 7 This is a structural diagram of a glass transfer board formed by a packaging method provided in an embodiment of the present application after ball planting; Figure 8 This is a schematic diagram of a wafer-level large chip packaging structure provided in an embodiment of the present application; Description of the drawings: wafer-level large chip 100, metal pillar 101; Glass transfer plate 200, through-glass via 201, first seed layer 202, and material 203 after solder balls melt; Substrate 300, solder balls 301. DETAILED DESCRIPTION

[0019] The exemplary embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings in the embodiments of the present application. Although the accompanying drawings show exemplary embodiments of the present application, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0020] Existing wafer-level packaging technologies primarily include flip chip packaging, wafer-level ball grid array (WLBGA), and wafer-level system-in-package (WL-SiP). These technologies have addressed packaging density and performance issues to a certain extent, but they still have numerous shortcomings when it comes to packaging large chips.

[0021] Flip-chip packaging is widely used for high-performance chip packaging due to its high solder joint density and excellent electrical performance. However, as chip size increases, flip-chip packaging faces new challenges in terms of interconnect density and thermal management. First, as the number and density of solder joints increase, the complexity of the manufacturing process increases significantly, placing higher demands on the uniformity and reliability of solder joints. Any minor solder joint defect can cause package failure and affect the reliability of the entire system. Furthermore, flip-chip packaging has limited thermal management capabilities at high power densities, making it difficult to effectively and quickly transfer the heat generated by the chip to the external heat dissipation structure, causing the chip temperature to rise, thereby affecting its performance and lifespan.

[0022] Wafer-level ball grid array (WLBGA) packaging, as a mature wafer-level packaging technology, achieves high-density interconnection and excellent heat dissipation performance by directly forming a ball grid array at the wafer level. However, WLBGA still faces challenges in material selection and thermal stress control when handling large chip packaging. Traditional BGA packaging materials have limitations in thermal conductivity and thermal expansion coefficient, making it difficult to achieve uniform heat conduction under high power density and large chip area. This leads to uneven thermal stress within the package, which in turn causes warping and microcracks between the chip and the substrate. In addition, the WLBGA packaging process is relatively complex, requiring multiple soldering and alignment steps, which increases manufacturing difficulty and cost, limiting its application in large-scale production.

[0023] Wafer-level system-in-package (WL-SiP), a technology that integrates multiple chips and electronic components into a single package, can achieve high integration and multifunctionality to a certain extent. However, the application of WL-SiP packaging in large chip packages also faces the challenges of interconnect complexity and thermal management difficulties. Multi-chip integration leads to more complex interconnect lines within the package, increasing signal transmission delays and crosstalk risks, affecting the system's signal integrity and stability. Furthermore, the high power density of multiple chips significantly increases the overall heat dissipation requirements of the package. Traditional heat dissipation solutions struggle to meet the requirements for efficient heat conduction, resulting in uneven temperatures within the package and affecting chip performance and reliability.

[0024] The above-mentioned wafer-level packaging technology has the following main problems when dealing with large chip packaging: 1) Complex and difficult-to-control manufacturing processes: Traditional processes, particularly for high-density interconnects and multi-layer structures, involve numerous steps and demand extremely high equipment precision and process control, significantly increasing manufacturing difficulty and costs. Large chip packaging requires handling more solder joints and interconnects. Any slight process error can lead to packaging defects, reducing packaging yield and reliability.

[0025] 2) Inadequate thermal management capabilities: The limitations of traditional packaging materials in terms of thermal conductivity and thermal expansion coefficient make it difficult to achieve efficient heat conduction and uniform heat dissipation, resulting in elevated temperatures and concentrated thermal stress within the package. This is particularly true in large chip packages, where high power density and large surface areas lead to uneven heat distribution, which traditional heat dissipation solutions struggle to effectively address. This can lead to warping and microcracks between the chip and substrate, compromising the mechanical stability and service life of the package.

[0026] 3) Material Selection and Processing Limitations: Existing packaging technologies struggle to balance electrical conductivity, thermal conductivity, and mechanical strength in material selection, limiting further improvements in packaging performance. High-performance packaging materials are typically expensive and require stringent processing conditions, further increasing manufacturing costs. Furthermore, the mismatch in thermal expansion coefficients between the material and the substrate can easily induce mechanical stress and microcracks within the package, impacting its reliability and lifespan.

[0027] 4) Complex alignment and connection steps: Traditional packaging processes require multiple alignment and connection steps to achieve multi-layer interconnect structures and high-density solder joints, which can easily lead to process errors and packaging defects. Especially in large chip packaging, the alignment accuracy between the chip and the substrate must be even higher. Any slight alignment error can lead to interconnect defects, affecting the overall performance and reliability of the package.

[0028] The existence of these problems is mainly due to the inherent limitations of existing wafer-level packaging technology when dealing with large chip packaging. First, with the increase in chip size and power density, traditional packaging processes are stretched in achieving high-density interconnection and multi-layer structures, and it is difficult to meet the requirements of high precision and high reliability. Secondly, traditional packaging materials have insufficient performance in thermal management and cannot effectively cope with the high power density and complex heat flow paths in large chip packaging, resulting in thermal management becoming a bottleneck restricting packaging performance and reliability. In addition, the unreasonable process flow and material selection of existing packaging technology have led to a complex and costly manufacturing process, making it difficult to achieve large-scale commercial production. Finally, the multiple operations in the alignment and connection steps of the traditional packaging process are prone to process errors and packaging defects, affecting the overall quality and reliability of the package.

[0029] In view of the above-mentioned problems, the present invention proposes a large wafer-level chip packaging method and packaging structure. This method simplifies the packaging process (particularly the alignment and connection steps) when preparing the packaging structure between the large wafer-level chip and the substrate, thereby achieving high-precision alignment between the large chip and the substrate. The following, in conjunction with the accompanying drawings, describes in detail a large wafer-level chip packaging method provided by the present invention through several embodiments and their application scenarios.

[0030] The first aspect of the present application provides a method for packaging a large wafer-level chip, referring to Figure 1, Figure 1 A flowchart of a wafer-level large chip packaging method provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method includes: Step S101 , obtaining a wafer-level large chip; the wafer-level large chip refers to a chip structure composed of a plurality of different types of core particles or a plurality of single-type core particles.

[0031] Specifically, a wafer preparation process is first performed, and then a large wafer-level chip is selected based on the packaging requirements of the actual application. This large wafer-level chip includes multiple cores of the same type, which are integrated from the multiple cores. The multiple cores can be different types or multiple cores of the same type. It should be noted that in this embodiment, the large chip refers to a type of chip formed by integrating multiple cores, and does not limit the chip size to a specific data range. A large chip refers to a chip with an area larger than the maximum exposure area of ​​current lithography machines. Large chips have two characteristics: First, their large area breaks the area limitations of stepper lithography machines, allowing a large number of transistors to be integrated into a single chip, exceeding the number of transistors integrated on a single chip using current manufacturing technology. Second, large chips are composed of multiple functional bare dies (i.e., cores), and prefabricated bare dies are integrated into the large chip using several emerging semiconductor manufacturing technologies.

[0032] In this embodiment, the specific structure of the large wafer-level chip is not limited. The large wafer-level chip can be a wafer-level chip obtained from a tapeout field, and the size ranges from 2 to 12 inches.

[0033] In a possible implementation, after obtaining the wafer-level large chip, the method further includes: preparing a dielectric layer of the wafer-level large chip; A redistribution layer (RDL) of the wafer-level large chip is prepared, wherein the RDL interconnection layer is used to realize interconnection between the plurality of core particles within the wafer-level large chip.

[0034] In this embodiment, for the obtained wafer-level large chip, since it includes multiple core particles (equivalent to sub-chips with the same function), it is necessary to connect the multiple core particles through a certain process. Specifically, a dielectric layer can be prepared on the surface of the wafer-level large chip first, and then an RDL interconnection layer can be prepared. The RDL interconnection layer includes a metal interconnection structure, and the corresponding core particles are connected through the metal interconnection structure to achieve interconnection between multiple core particles. In this embodiment, since the internal structure of the wafer-level large chip is not limited, the structure of the prepared RDL interconnection layer is not limited accordingly, and can be set according to actual application requirements. In this embodiment, the wafer-level large chip and the related dielectric layer and RDL interconnection layer are regarded as a whole (the structure of the dielectric layer and the RDL interconnection layer is not described in the accompanying drawings), and subsequent steps are performed to complete the packaging of the wafer-level large chip and the substrate.

[0035] Step S102 : preparing a plurality of metal pillars on the first surface of the wafer-level large chip according to the bonding points between the wafer-level large chip and the substrate.

[0036] Reference Figure 2 , Figure 2 A schematic diagram of the structure of a metal column formed in a packaging method is shown. Figure 2 As shown, the upper and lower surfaces of the wafer-level large chip 100 are the first surface and the second surface respectively. In the subsequent process of preparing the packaging structure, the surface where the wafer-level large chip 100 is bonded to the substrate is used as the first surface of the wafer-level large chip.

[0037] There are multiple bonding points between the wafer-level large chip 100 and the substrate. The connection between the wafer-level large chip and the substrate is achieved through multiple bonding points. The positions of the bonding points on the first surface of the wafer-level large chip can be predetermined, so that multiple metal pillars 101 can be prepared at the positions of the bonding points to achieve subsequent bonding with the substrate through the metal pillars. The embodiment of the present application adopts a modular design concept, using a complex multi-layer interconnect structure (i.e., a wafer-level large chip composed of multiple cores) as a standardized module. This not only reduces the process steps and alignment difficulty, but also improves the flexibility and scalability of the process, allowing the packaging process to better adapt to changes in different chip sizes and functional requirements.

[0038] In a possible implementation manner, the metal material used for the metal column is copper.

[0039] In this embodiment, the position of the metal pillar 101 (ie, the position of the bonding point) can be determined according to actual process requirements, and the metal material used for the metal pillar can be copper with conductive properties.

[0040] In a possible implementation, the step S102 of preparing a plurality of metal pillars on the first surface of the wafer-level large chip includes: Step S1021 , sputtering a second seed layer on the first surface of the wafer-level large chip, wherein the metal material used in the second seed layer is the same as the metal material used in the metal pillars.

[0041] In step S1022 , a plurality of metal pads are prepared on the second seed layer by photolithography according to the bonding points between the wafer-level large chip and the substrate.

[0042] Step S1023 , electroplating the plurality of metal pads to obtain the plurality of metal pillars, wherein the height of the metal pillars is greater than or equal to 2 / 3 of the depth of the through-glass hole, and the diameter of the metal pillars is smaller than the diameter of the through-glass hole.

[0043] The metal material used for the second seed layer can be copper. The height of the metal pillar is greater than or equal to two-thirds of the depth of the through-glass via (TGL) and less than or equal to the TGL depth. The diameter (i.e., width) of the metal pillar should be smaller than the diameter of the TGL to facilitate subsequent insertion of the metal pillar into the TGL after alignment.

[0044] Step S103 : preparing a glass transfer plate, wherein the glass transfer plate comprises a plurality of through-glass holes, and positions of the through-glass holes correspond one-to-one to positions of the plurality of metal pillars.

[0045] Among them, reference Figure 3 , Figure 3 A schematic structural diagram of a glass transfer plate formed in a packaging method is shown. Figure 3 As shown, multiple glass through holes 201 are prepared in the glass transfer plate 200, so that the positions of the glass through holes 201 are the same as the positions of the metal pillars 101, that is, the same as the positions of the bonding points. The thickness of the glass transfer plate can be set according to the actual process requirements. Among them, a seed layer can also be set on the side wall of the glass through hole (at Figure 3 (not shown) so that it can be bonded to a large wafer-level chip later.

[0046] When packaging large chips, related packaging processes face the problem of a mismatch in thermal expansion coefficients between the materials (i.e., wafer-level large chips) and the substrate. This can easily cause mechanical stress and microcracks within the package, impacting its reliability and lifespan. Specifically, in the wafer-level system-on-chip packaging process, thermal management is a key factor in ensuring stable chip operation and extending its lifespan. With the increasing functionality and operating frequency of chips, the heat generated by chips during operation increases significantly, leading to elevated temperatures within the package. When faced with high power density and large chip areas, related packaging processes often struggle to achieve efficient heat conduction and dissipation, leading to a series of thermal stress issues, the most notable of which is warping between the chip and substrate. Warping is structural deformation caused by mechanical stress generated by the mismatch in thermal expansion coefficients between the chip and substrate during temperature changes. Different materials expand and contract at different rates during heating and cooling, and this mismatch in thermal expansion coefficients is particularly pronounced in high-power density and large chip packages. Warping not only affects the physical connection between the chip and the substrate, causing stress concentration and fracture in the interconnect structure, but may also cause microcracks and structural failures within the package, seriously affecting the reliability and service life of the package. Traditional solutions mainly rely on thermal interface materials (TIM) and heat sinks for heat conduction and heat dissipation. However, these methods have many limitations in large chip packaging. First, as the chip area increases, the problem of uneven heat distribution becomes more prominent, and traditional heat dissipation solutions are difficult to meet the needs of global thermal management. Second, the thermal conductivity of the thermal interface material is limited, making it difficult to achieve efficient heat transfer, resulting in difficulty in effectively dissipating chip hot spots. In addition, due to thermal expansion matching issues during the packaging process, it is still difficult to completely eliminate the warping phenomenon between the chip and the substrate, affecting the mechanical stability and reliability of the package.

[0047] In order to solve the above-mentioned heat conduction and heat dissipation problems, this embodiment uses a glass transfer plate to isolate the wafer-level large chip and the substrate, so that the two can be bonded and connected through the glass through-holes in the glass transfer plate while achieving thermal isolation. Specifically, the embodiment of the present application uses silicon glass bonding technology to reduce the warping phenomenon caused by thermal stress mismatch between the chip and the substrate. Silicon glass bonding is an advanced packaging technology that achieves efficient heat conduction and mechanical connection between the chip and the substrate by introducing a silicon glass layer (i.e., a glass transfer plate) between the chip and the substrate. Silicon glass has excellent thermal conductivity and a low thermal expansion coefficient. It can maintain good structural stability under high temperature conditions and reduce thermal stress between the chip and the substrate. This embodiment effectively solves the warping problem caused by thermal stress mismatch during the large chip packaging process by adopting silicon glass bonding technology, thereby improving the mechanical stability and thermal management efficiency of the package. At the same time, the introduction of silicon glass bonding also provides the possibility for further optimization and innovation of the packaging process, and promotes the development of wafer-level system large chip packaging technology.

[0048] In a possible implementation, the step S103 of preparing the glass transfer plate includes: Step S1031, obtaining a glass substrate; Step S1032, preparing the through-glass vias on the glass substrate according to the bonding points between the wafer-level large chip and the substrate; In this embodiment, referring to Figure 4 , Figure 4 A schematic diagram of the preparation process of a glass transfer plate formed in a packaging method is shown, Figure 4 As shown, first Figure 4 As shown, a glass substrate 200 is obtained, which can be made of silicon glass. Then, glass through holes 201 are prepared according to the positions corresponding to the bonding points, so that the positions of the glass through holes correspond to the positions of the metal pillars. The metal pillars can be inserted into the glass through holes later.

[0049] In a possible implementation, the step of preparing the through-glass via on the glass substrate includes: The through-glass hole is prepared on the glass substrate by laser induced etching, and the diameter of the through-glass hole is greater than 300 μm.

[0050] In this embodiment, if Figure 4 As shown, a through-glass hole is formed by laser-induced etching or other glass-based processing technology. The aperture of the through-glass hole can be designed according to actual application needs. In order to facilitate the injection of solder balls in subsequent processes, the diameter of the through-glass hole 201 should generally be controlled to be greater than 300um, so that the depth of the through-glass hole 201 is consistent with the thickness of the glass adapter plate 200.

[0051] Step S1033 , preparing a first seed layer on the sidewall of the through-glass via by magnetron sputtering or evaporation process, wherein the metal material used in the first seed layer is the same as the metal material used in the metal pillar.

[0052] like Figure 4 As shown, considering that the metal pillars of the wafer-level large chip need to be inserted into the glass through-holes of the glass transfer plate for bonding in the future, it is also necessary to prepare a seed layer (first seed layer 202) on the side wall of the glass through-hole 201 by magnetron sputtering or evaporation process in advance. The metal material used in the first seed layer 202 can be metallic copper.

[0053] The selection and processing of packaging materials is also a major challenge in the packaging process. Large chip packaging needs to take into account multiple aspects of performance such as electrical conductivity, thermal conductivity and mechanical strength, which limits the diversity of materials and the flexibility of the process. High-performance packaging materials are usually expensive and have strict requirements on process conditions during processing, which further increases the manufacturing cost. The embodiment of the present application optimizes the selection of packaging materials (using glass adapter plates as packaging materials) and processing technology (adopting a method of pre-preparing glass through-holes in the glass adapter plates), adopts cost-effective and high-performance materials, reduces the cost of packaging materials and processing difficulty, and ensures the economy and sustainability of the packaging process. Through these innovative process improvements, the manufacturing cost of large chip packaging is significantly reduced, and the production efficiency and yield are improved.

[0054] The embodiment of the present application optimizes the heat conduction path between the chip and the substrate by introducing a silicon glass layer into the packaging structure, significantly improves the overall thermal conductivity, and ensures efficient heat dissipation of the chip at high power density. At the same time, the mechanical properties of silicon glass enable it to effectively alleviate the stress concentration caused by the mismatch of thermal expansion coefficients, reducing the warping and microcracks of the packaging structure. In addition, the silicon glass bonding process has high process compatibility and reliability, and can be seamlessly integrated with existing packaging processes, simplifying the overall manufacturing process and reducing process complexity and cost. Therefore, this embodiment successfully overcomes the thermal stress mismatch and warping problems faced by traditional packaging technology in large chip packaging through innovative packaging structure design and advanced silicon glass bonding process, significantly improves the performance and reliability of the packaging system, ensures the stable operation and long life of large chips at high power density, and provides a solid technical guarantee for the reliability and performance of high-end electronic products.

[0055] Step S104 : inserting the metal pillars on the first surface of the wafer-level large chip into the through-glass holes of the glass transfer plate to bond the first surface of the wafer-level large chip to the first surface of the glass transfer plate.

[0056] Specifically, an alignment device can be used to align the metal pillars of the large wafer-level chip with the through-glass holes on the glass transfer plate. The metal pillars are then inserted into the through-glass holes, bringing the first surface of the large wafer-level chip into contact with the first surface of the glass transfer plate. The alignment device used in this embodiment can be any device that performs alignment functions, and its type is not limited in this embodiment. Then, a ball placement process is performed to complete the bonding.

[0057] Silicon glass bonding technology can achieve high-precision alignment and connection between the chip and the substrate, reducing the multiple alignment and connection steps in the traditional packaging process. The present application adopts silicon glass bonding technology, which achieves high-precision alignment between the chip and the substrate through one-time bonding, significantly simplifying the preparation process of the interconnect structure. Not only does it reduce the process steps and equipment requirements, it also reduces the incidence of process errors and packaging defects, and improves the packaging yield. Therefore, the embodiment of the present application introduces high-precision wafer-level bonding equipment, improves the accuracy and consistency of the packaging process, and significantly improves the yield.

[0058] In a possible implementation, step S104, bonding the first surface of the wafer-level large chip to the first surface of the glass transfer plate, includes: Step S1041 : driving solder balls into each of the through-glass holes on the second surface of the glass adapter plate.

[0059] Step S1042 , melting the solder balls through a thermal reflow process to fill the gap between the through glass via and the metal pillar.

[0060] In this embodiment, referring to Figure 5 , Figure 5 A schematic diagram of the structure after alignment of a large wafer-level chip and a glass transfer plate is shown. Figure 5 As shown, first insert the metal pillars 101 of the wafer-level large chip into the glass through-holes 201 on the glass transfer board, so that the first surface of the wafer-level large chip contacts the first surface of the glass transfer board. Then, insert solder balls into each glass through-hole so that the solder balls contact the top of the metal pillars. Figure 6 , Figure 6 The schematic diagram of the structure after the wafer-level large chip formed by a packaging method is bonded to the glass transfer plate is shown as follows: Figure 6 As shown, through a thermal reflow process, the melted solder ball material 203 fills the gap between the metal pillar 101 and the through-glass via 201. Excess melted solder ball material is removed from the second surface of the glass transfer plate. The upper and lower surfaces of the glass transfer plate 200 are the first and second surfaces, respectively. The surface where the wafer-level large chip 100 is bonded to the glass transfer plate 200 serves as the first surface of the glass transfer plate 200. The surface where the glass transfer plate 200 is bonded to the substrate serves as the second surface of the glass transfer plate 200.

[0061] Step S105 , bonding the second surface of the glass transfer plate to the substrate to obtain the packaging structure of the wafer-level large chip.

[0062] In a possible implementation, step S105 of bonding the second surface of the glass transfer plate to the substrate includes: A ball planting process is adopted on the second surface of the glass transfer plate to perform flip-chip bonding on the second surface of the glass transfer plate and the substrate to obtain the packaging structure of the wafer-level large chip.

[0063] Specifically, refer to Figure 7 , Figure 7 A schematic diagram of the structure after ball planting on a glass transfer board formed by a packaging method is shown. Figure 7 As shown, after the wafer-level large chip is bonded to the glass transfer plate, a plurality of solder balls 301 are driven into each glass through-hole on the second surface of the glass transfer plate through a ball planting process. Then, a flip-chip bonding process is used to flip-chip bond the glass transfer plate after ball planting to the substrate (PCB board) to complete the packaging and obtain the packaging structure of the wafer-level large chip. Figure 8 , Figure 8 A schematic diagram of a wafer-level large chip packaging structure is shown. Figure 8 As shown, the wafer-level large chip 100 is inserted into the glass through-hole 201 of the glass transfer plate 200 through the metal pillar 101 on the first surface, so that the wafer-level large chip 100 is bonded to the glass transfer plate 200, and then bonded to the substrate 300 through the solder ball 301.

[0064] The wafer-level packaging process for large chips typically involves multiple complex steps, including chip dicing, interconnect layer stacking, material deposition, micromachining, and package integration. These steps are not only complex but also require extremely high equipment precision and process control, significantly increasing the difficulty and cost of the manufacturing process. Specifically, as chip size increases, the number of interconnect layers and interconnect density increase, the precision requirements for the packaging process also increase. The fabrication of multi-layer interconnects requires multiple steps such as exposure, development, and etching, each of which requires extremely high process control precision to ensure accurate inter-layer alignment. However, in actual production, any slight alignment error can cause interconnect defects, affecting the overall performance and reliability of the package. Furthermore, the complex inter-layer connection process not only increases the number of process steps, but also increases manufacturing difficulty, reduces production efficiency, and thus drives up packaging costs. Furthermore, the packaging process requires extremely high cleanliness and surface flatness. During the large chip packaging process, even the slightest contamination or surface unevenness can cause packaging defects and reduce the packaging yield. Achieving high cleanliness and surface flatness in the packaging process requires significant investment in production environment and equipment, such as high-cleanliness production workshops and sophisticated surface treatment equipment. These investments not only increase production costs but also limit the scalability and economic viability of the packaging process.

[0065] The embodiment of the present application proposes an innovative wafer-level large chip packaging method, which completes the bonding between the wafer and the substrate by preparing high copper pillars on the wafer-level large chip, bonding them to the glass through-holes, and then implanting solder balls. This simplifies the process flow and improves the overall performance and reliability of the package. By simplifying the process flow, introducing silicon glass temporary bonding technology, optimizing the manufacturing steps, and introducing advanced materials and process technologies, the problems of manufacturing process complexity, insufficient thermal management, and material performance limitations in the existing technology are solved, thereby achieving high efficiency and low cost of large chip packaging.

[0066] Secondly, silicon-glass bonding technology offers excellent thermal conductivity and mechanical stability, simplifying the process while ensuring efficient thermal management and mechanical reliability of the package. The silicon-glass layer (i.e., glass adapter plate) not only efficiently conducts heat, reducing temperature differences between the chip and substrate and preventing warping caused by thermal stress mismatch, but also provides a robust mechanical connection, enhancing the overall stability of the package structure. This eliminates the need for complex thermal interface materials and multi-layer heat dissipation structures in the packaging process, further simplifying the manufacturing process. Furthermore, silicon-glass bonding technology offers excellent process compatibility, enabling seamless integration with existing packaging processes and materials. Traditional packaging processes often require extensive process optimization and equipment modifications when introducing new materials and processes, increasing technical risks and costs. However, due to its process flexibility and compatibility, silicon-glass bonding technology can be adapted to existing packaging processes without requiring large-scale process adjustments or equipment investment, thus reducing packaging process complexity and costs. By applying silicon-glass bonding technology to wafer-level large-chip packaging structures, the present application successfully simplifies and optimizes the packaging process. Specifically, the embodiments of the present application use silicon glass bonding technology to replace traditional multi-layer interconnects and thermal interface materials, reducing the alignment and connection steps in the packaging process, reducing process complexity and manufacturing costs. At the same time, the efficient heat conduction and mechanical stability of silicon glass bonding technology ensure efficient thermal management and mechanical reliability of the package, and improve the overall performance and life of the packaging system. Through the above innovations, the present application not only solves the manufacturing process complexity and cost control problems faced in large chip packaging, but also simplifies and optimizes the packaging process through silicon glass bonding technology, significantly improving the production efficiency and yield of the package.

[0067] A second aspect of the embodiment of the present application further provides a packaging structure of a wafer-level large chip, wherein the packaging structure of the wafer-level large chip is prepared by the packaging method of the wafer-level large chip described in the first aspect; The packaging structure includes: Wafer-level large chip; the wafer-level large chip refers to a chip structure composed of multiple different types of core particles or multiple single-type core particles; The first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate; The glass transfer plate includes multiple glass through holes, each of which includes a metal column, one end of which is connected to the bonding point on the first surface of the wafer-level large chip, and the other end of which is connected to the bonding point on the substrate through a solder ball.

[0068] In a possible implementation, the height of the metal column is greater than or equal to 2 / 3 of the depth of the through-glass via, and less than or equal to the depth of the through-glass via.

[0069] In the embodiment of the present application, the packaging structure of the wafer-level large chip can be as follows: Figure 8 As shown, the package structure mainly includes three parts: a large wafer-level chip 100, a glass transfer plate 200, and a substrate 300. The first surface of the large wafer-level chip is bonded to the first surface of the glass transfer plate. The metal pillars 101 on the first surface of the large wafer-level chip are inserted into the through-glass holes 201 of the glass transfer plate. Solder balls are injected into the through-glass holes and melted using a thermal reflow process. The melted solder ball material fills the gap between the through-glass holes 201 and the metal pillars 101, completing the bonding.

[0070] In a possible implementation manner, the metal material used for the metal column is copper, and the metal column is a copper column.

[0071] like Figure 8 As shown, the second surface of the glass transfer plate 200 is bonded to the substrate 300. Specifically, a plurality of solder balls 301 are prepared on the second surface of the glass transfer plate using a ball planting process. The second surface of the glass transfer plate and the substrate are flip-chip bonded via the solder balls 301 to obtain the wafer-level large chip packaging structure.

[0072] In a possible implementation manner, a first seed layer is prepared on the sidewall of the through-glass via, and the metal material used in the first seed layer is the same as the metal material used in the metal column.

[0073] In a possible implementation manner, the diameter of the through-glass hole is greater than 300 um.

[0074] In a possible implementation, the wafer-level large chip includes: a dielectric layer and a redistribution layer (RDL) interconnection layer, and the RDL interconnection layer is used to realize interconnection between the plurality of core particles inside the wafer-level large chip.

[0075] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0076] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, apparatuses, electronic devices, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0077] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0079] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0080] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "includes," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements that are inherent to such process, method, article, or terminal device. In the absence of further restrictions, an element defined by the phrase "comprises a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0081] The above is a detailed introduction to the packaging method and packaging structure of a wafer-level large chip provided by this application. Specific examples are used in this article to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method of this application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on this application.

Claims

1. A packaging method for a large wafer-level chip, characterized in that: The method comprises: Obtaining a wafer-level large chip; the wafer-level large chip refers to a chip structure composed of a plurality of different types of core particles or a plurality of single core particles; According to the bonding points between the wafer-level large chip and the substrate, a plurality of metal pillars are prepared on the first surface of the wafer-level large chip; Prepare a glass transfer plate, wherein the glass transfer plate comprises a plurality of through-glass holes, and positions of the through-glass holes correspond one-to-one to positions of the plurality of metal pillars; Inserting the metal column on the first surface of the wafer-level large chip into the glass through hole of the glass transfer plate, so that the first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate; The second surface of the glass transfer plate is bonded to the substrate to obtain the packaging structure of the wafer-level large chip.

2. The packaging method according to claim 1, characterized in that: The method for preparing the glass transfer plate comprises: obtaining a glass substrate; According to the bonding points between the wafer-level large chip and the substrate, preparing the through-glass holes on the glass substrate; A first seed layer is prepared on the side wall of the through-glass hole by magnetron sputtering or evaporation process, and the metal material used in the first seed layer is the same as the metal material used in the metal column.

3. The packaging method according to claim 2, characterized in that: The step of preparing the through-glass hole on the glass substrate comprises: The through-glass hole is prepared on the glass substrate by laser induced etching, and the diameter of the through-glass hole is greater than 300 um.

4. The packaging method according to claim 1, characterized in that: Bonding the first surface of the wafer-level large chip to the first surface of the glass transfer plate comprises: On the second surface of the glass transfer plate, injecting solder balls into each of the through-glass holes; The solder balls are melted by a thermal reflow process to fill the gap between the through glass via and the metal column.

5. The packaging method according to claim 1, characterized in that: After obtaining the wafer-level large chip, the method further includes: Preparing a dielectric layer of the wafer-level large chip; A rewiring RDL interconnection layer of the wafer-level large chip is prepared, and the RDL interconnection layer is used to realize the interconnection between the multiple core particles inside the wafer-level large chip.

6. The packaging method according to claim 1, characterized in that: The step of preparing a plurality of metal pillars on the first surface of the wafer-level large chip comprises: sputtering a second seed layer on the first surface of the wafer-level large chip, wherein the metal material used in the second seed layer is the same as the metal material used in the metal column; The second seed layer is photolithographically processed to obtain a plurality of metal pads according to the bonding points between the wafer-level large chip and the substrate; The plurality of metal pads are electroplated to obtain the plurality of metal columns, wherein the height of the metal columns is greater than or equal to 2 / 3 of the depth of the through glass hole, and the diameter of the metal columns is smaller than the diameter of the through glass hole.

7. The packaging method according to claim 1, characterized in that: The metal material used for the metal column is copper.

8. The packaging method according to claim 1, characterized in that: The step of bonding the second surface of the glass transfer plate to the substrate comprises: A ball planting process is adopted on the second surface of the glass transfer plate to perform flip-chip bonding on the second surface of the glass transfer plate and the substrate to obtain the packaging structure of the wafer-level large chip.

9. A wafer-level large chip packaging structure, characterized in that: The wafer-level large chip packaging structure is prepared by the wafer-level large chip packaging method according to any one of claims 1 to 8; The packaging structure comprises: Wafer-level large chip; the wafer-level large chip refers to a chip structure composed of multiple different types of core particles or multiple single core particles; The first surface of the wafer-level large chip is bonded to the first surface of the glass transfer plate; The glass transfer plate includes a plurality of through-glass holes, each of which includes a metal column, one end of which is connected to a bonding point on the first surface of the wafer-level large chip, and the other end of which is connected to a bonding point on the substrate via a solder ball.

10. The packaging structure according to claim 9, characterized in that: The height of the metal column is greater than or equal to 2 / 3 of the depth of the through glass via, and less than or equal to the depth of the through glass via.

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