Semiconductor structure and method for manufacturing the same

Abstract

The present invention provides a semiconductor structure and a method for making the same. The method for making the semiconductor structure includes: providing a substrate, the substrate including a first region and a second region, and a dielectric layer formed on the substrate; performing an anisotropic first dry etching process, etching the dielectric layer and the substrate and stopping in the substrate to form a plurality of through holes in the first region; performing an anisotropic second dry etching process, etching the dielectric layer and the substrate in the second region to form a contact hole, and simultaneously etching the dielectric layer and the substrate on the side of the through hole to expand the through hole to form a marking groove. In this way, when etching the contact hole and the marking groove at the same time, the restricted diffusion effect occurring when etching the marking groove can be effectively suppressed, the boundary clarity of the marking groove can be improved, and the accuracy of the overlay precision measurement value can be improved. The semiconductor structure of the present invention is made using the method for making the semiconductor structure provided by the present invention.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the manufacture of semiconductor structures, it is necessary to form a mark groove on the substrate so that the mark groove can be used to measure the overlay accuracy (OVL) between the material layer formed on the substrate and the substrate. In the traditional process, the mark groove and the contact hole (Contact Hole) on the substrate are formed in the same etching step. Due to the inherent etching rate distribution (ETCH rate MAP) of the etching machine, while ensuring the normal contact hole pattern, the restricted diffusion effect is prone to occur when etching the mark groove. The restricted diffusion effect usually refers to the increase in the modulation probability due to the increase in the sheath voltage during the plasma etching process, which in turn affects the anisotropy of the etching profile. For the mark groove, due to the restricted diffusion effect, such as Figure 1 As shown, the center area of ​​the bottom surface of the mark groove 107 is raised relative to the edge area, so that when the mark groove is used to measure the overlay accuracy later, for example, when measuring the overlay accuracy between M1 and the substrate after forming the metal layer M1, as shown in FIG. Figure 2 As shown, the boundary of the mark groove 107 is not clear, which has a great impact on the measurement value of the overlay accuracy, reduces the accuracy of the overlay accuracy measurement value, affects engineers' judgment of the process level, increases the amount of rework and scrap, and wastes manufacturing (FAB) resource capacity. Summary of the invention

[0003] One of the purposes of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which can effectively suppress the restricted diffusion effect when etching the mark groove when etching the contact hole and the mark groove at the same time, improve the boundary clarity of the mark groove, and improve the accuracy of the overlay precision measurement value.

[0004] In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a semiconductor structure on one hand. The method for manufacturing a semiconductor structure comprises: providing a substrate, the substrate comprising a first region and a second region, and a dielectric layer formed on the substrate; performing an anisotropic first dry etching process, etching the dielectric layer and the substrate and stopping in the substrate, and forming a plurality of through holes in the first region; and performing an anisotropic second dry etching process, etching the dielectric layer and the substrate in the second region to form contact holes, and etching the dielectric layer and the substrate on the side of the through hole to expand the through hole to form a marking groove.

[0005] Optionally, the method of performing an anisotropic second dry etching process to etch the dielectric layer and the substrate in the second area to form a contact hole, and simultaneously etching the dielectric layer and the substrate on the side of the through hole to enlarge the through hole to form a marking groove includes: forming a graphic second mask layer on the substrate, the graphic second mask layer having a contact hole pattern and a marking groove pattern, one of the marking groove patterns corresponding to at least a portion of the through hole position and exposing the corresponding through hole; performing the second dry etching process under the mask of the graphic second mask layer to form the contact hole and the marking groove; and removing the graphic second mask layer.

[0006] Optionally, the method for forming a patterned second mask layer on the substrate includes: coating a photoresist on the substrate to form a photoresist layer, the photoresist layer covering the substrate and filling the multiple through holes; exposing the photoresist layer; and developing the photoresist layer to form the patterned second mask layer, wherein the photoresist layer is developed twice to remove the photoresist in the multiple through holes.

[0007] Optionally, in the step of performing the anisotropic second dry etching process, the dielectric layer and the substrate at the side of the through hole are etched so that more than two through holes are connected to form the marking groove.

[0008] Optionally, the first dry etching process and the second dry etching process are performed on the same machine.

[0009] Optionally, the method for manufacturing the semiconductor structure also includes: after performing an anisotropic second dry etching process, forming a barrier layer, the barrier layer covering the side walls of the contact hole and the side walls of the mark groove; forming a conductive material layer on the dielectric layer, the conductive material layer covering the dielectric layer and filling the contact hole and the mark groove; and grinding away the conductive material layer on the top surface of the dielectric layer to form a contact hole structure, the contact hole structure including the contact hole, the barrier layer in the contact hole, and the conductive material layer in the contact hole.

[0010] Optionally, the method for manufacturing the semiconductor structure also includes: after grinding and removing the conductive material layer on the top surface of the dielectric layer, forming a metal wiring layer on the dielectric layer, the metal wiring layer is electrically connected to the substrate through the contact hole structure, the metal wiring layer includes a marking pattern corresponding to the marking groove, and the marking groove and the marking pattern are used to measure the overlay accuracy between the metal wiring layer and the substrate.

[0011] Optionally, the base includes a substrate and an epitaxial layer located on the substrate, and the marking groove is located in the epitaxial layer.

[0012] Optionally, the first area is a cutting path area.

[0013] Another aspect of the present invention provides a semiconductor structure, which is manufactured using the above-mentioned method for manufacturing a semiconductor structure.

[0014] In the semiconductor structure and the manufacturing method thereof provided by the present invention, after forming a dielectric layer on a substrate, a first anisotropic dry etching process is first performed to etch the dielectric layer and the substrate and stop in the substrate to form a plurality of through holes in a first region, and then a second anisotropic dry etching process is performed to etch the dielectric layer and the substrate in the second region to form a contact hole, and at the same time, the dielectric layer and the substrate on the side of the through hole are etched to expand the through hole to form a marking groove. In this way, when etching the contact hole and the marking groove at the same time, the diffusion restriction effect occurring when etching the marking groove can be effectively suppressed while ensuring that the pattern and size of the contact hole are qualified. The bottom surface of the formed mark groove is relatively flat, thereby improving the boundary clarity of the mark groove. When the mark groove is used to measure the overlay accuracy in the subsequent process, the measurement interference caused by the unclear boundary of the mark groove can be reduced, and the accuracy of the overlay accuracy measurement value can be improved. In turn, the rework and scrap caused by the abnormal overlay accuracy measurement value caused by the unclear boundary of the mark groove can be reduced, which helps to save manufacturing resources and production capacity. In addition, since the bottom surface of the formed mark groove is relatively flat, the contact between the conductive material subsequently filled in the mark groove and the substrate can be more comprehensive, which helps to improve the stress of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a SEM cross-sectional image of an existing marking groove.

[0016] Figure 2 This is a SEM top view of the existing marking groove.

[0017] Figure 3 The present invention is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0018] Figures 4 to 15 A schematic diagram of a process of manufacturing a semiconductor structure provided by an embodiment of the present invention.

[0019] Fig.16 A SEM cross-sectional view of a marking trench of a semiconductor structure provided in accordance with an embodiment of the present invention.

[0020] Fig.17 A SEM top view of a marking trench of a semiconductor structure provided in accordance with an embodiment of the present invention.

[0021] Explanation of the reference numerals: 100-substrate; 100a-first region; 100b-second region; 101-substrate; 102-epitaxial layer; 103-dielectric layer; 104-patterned first mask layer; 105-through hole; 106-patterned second mask layer; 106a-marking groove pattern; 106b-contact hole pattern; 107-marking groove; 108-contact hole; 109-barrier layer; 110-conductive material layer; 111-metal wiring layer; 111a-marking pattern. DETAILED DESCRIPTION

[0022] The semiconductor structure and the method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0023] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0024] Figure 3 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention. Figure 3 As shown, the method for manufacturing the semiconductor structure provided by the present application includes:

[0025] Step S1, providing a substrate, the substrate comprising a first region and a second region, and a dielectric layer formed on the substrate;

[0026] Step S2, performing a first anisotropic dry etching process to etch the dielectric layer and the substrate and stop in the substrate, forming a plurality of through holes in the first region; and

[0027] Step S3, performing a second anisotropic dry etching process to etch the dielectric layer and substrate in the second region to form a contact hole, and at the same time, etching the dielectric layer and substrate on the side of the through hole to enlarge the through hole to form a marking groove.

[0028] Figures 4 to 15 A process diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention, wherein: Figure 6 , Figure 8 , Fig.11 and Fig.15 is a top view, and the rest are cross-sectional views. Figure 3 , Figures 4 to 15 The method for manufacturing the semiconductor structure of the present application is described.

[0029] In one embodiment of the present application, reference Figure 4 As shown, the base 100 includes a substrate 101 and an epitaxial layer 102 located on the substrate 101. The vias, contact holes and marking grooves formed subsequently may be located in the epitaxial layer 102. Exemplarily, the materials of the substrate 101 and the epitaxial layer 102 include but are not limited to silicon or germanium. In another embodiment of the present application, the base may only include the substrate.

[0030] refer to Figure 4 As shown, the substrate 100 includes a first region 100a and a second region 100b. Exemplarily, the first region 100a may be a cutting path region, and the marking groove may be formed in the cutting path region, which helps to improve the utilization rate of the wafer area; the second region 100b may be a device region for forming devices. This application only uses the first region and the second region to distinguish the formation regions of the contact holes and the marking grooves, and does not limit the specific regions and functions of the first region and the second region on the wafer.

[0031] In this embodiment, the substrate 100 may be a substrate that has completed any front-end process. For example, a variety of active and passive devices may be formed on the substrate 100. The active device may be, for example, a planar MOS transistor, whose structure includes a source, a drain, a gate oxide layer and a gate formed in sequence on the channel region between the source and the drain, and a sidewall located on the gate oxide layer and the sidewall of the gate. Metal silicide may also be formed on the source, drain, and gate of the MOS transistor to reduce contact resistance.

[0032] refer to Figure 4 As shown, a dielectric layer 103 is formed on the substrate 100, and the dielectric layer 103 can cover the top surface of the substrate 100. The material of the dielectric layer 103 can be silicon dioxide, but is not limited thereto.

[0033] Execute step S2, refer to Figure 5 and Figure 6As shown, a first anisotropic dry etching process is performed to etch the dielectric layer 103 and the substrate 100 and stop in the substrate 100, and a plurality of through holes 105 are formed in the first region 100a.

[0034] Specifically, step S2 may include: Figure 4 As shown, a patterned first mask layer 104 is formed on the dielectric layer 103, and the patterned first mask layer 104 defines the positions and opening patterns of a plurality of through holes 105; Figure 5 As shown, under the masking of the patterned first mask layer 104 , the first dry etching process is performed to form a plurality of through holes 105 ; and the patterned first mask layer 104 is removed.

[0035] Execute step S3, refer to Fig.10 and Fig.11 As shown, a second anisotropic dry etching process is performed to etch the dielectric layer 103 and the substrate 100 in the second region 100 b to form a contact hole 108 , and at the same time, the dielectric layer 103 and the substrate 100 on the side of the through hole 105 are etched to enlarge the through hole to form a marking groove 107 .

[0036] In this embodiment, the mark groove 107 is used to measure the overlay accuracy. In one embodiment of the present application, the opening size of the mark groove 107 and the opening size of the contact hole 108 can be different, for example, the opening width of the mark groove 107 is greater than the opening width of the contact hole 108, but it is not limited thereto. In the second dry etching process, when setting the etching conditions, firstly, it is necessary to ensure that the pattern size of the contact hole 108 is normal, and then consider the etching requirements of the mark groove 107.

[0037] Specifically, step S3 may include: Figure 7 and Figure 8 As shown, a patterned second mask layer 106 is formed on the substrate 100, wherein the patterned second mask layer 106 has a contact hole pattern 106b and a marking groove pattern 106a, wherein a marking groove pattern 106a corresponds to at least a portion of the through hole 105 and exposes the corresponding through hole 105; Fig. 9 As shown, under the masking of the patterned second mask layer 106, a second dry etching process is performed to form a contact hole 108 and a mark groove 107; Fig.10 and Fig.11 As shown, the patterned second mask layer 106 is removed.

[0038] In this embodiment, the method for forming a patterned second mask layer 106 on the substrate 100 may include: coating a photoresist on the substrate 100 to form a photoresist layer, the photoresist layer covering the substrate 100 and filling a plurality of through holes 105; exposing the photoresist layer; and developing the photoresist layer to form a patterned second mask layer 106.

[0039] It should be noted that since the photoresist fills the through hole 105, the photoresist layer at the through hole 105 is thicker. In this embodiment, the photoresist layer can be developed twice to completely remove the photoresist in the through hole 105, which helps to form a marking groove 107 of a set size.

[0040] In one embodiment of the present application, reference Figure 8 As shown, one marking groove pattern 106a may correspond to more than two through holes 105, and after performing the second dry etching process, more than two through holes 105 may be connected to form a marking groove 107. It should be noted that the number of through holes 105 corresponding to one marking groove pattern 106a may be selected as required, and in another embodiment of the present application, one marking groove pattern may also correspond to only one through hole.

[0041] For example, the patterned second mask layer 106 may have a plurality of marking groove patterns 106a, and one marking groove pattern 106a corresponds to a group of through holes 105. The plurality of through holes 105 in a group of through holes 105 may be arranged according to the opening area and opening shape of the marking groove 107 to be formed. For example, a group of through holes 105 may be arranged in a row (e.g., Figure 6 As shown in FIG. 1 ), a group of through holes 105 may also be arranged in multiple rows, and there may be dislocations between two adjacent rows of through holes 105, but the present invention is not limited thereto.

[0042] It should be noted that the opening shape of the through hole 105 can be rectangular or circular, etc., and the opening shape of the through hole 105 can be selected according to actual conditions. In this embodiment, the mark groove pattern 106a in the patterned second mask layer 106 exposes the corresponding through hole 105, and the opening size of the formed mark groove 107 is larger than the opening size of the through hole 105, and the opening size includes a length and a width that are perpendicular to each other. The opening width of the through hole 105 can also be smaller than the opening width of the contact hole 108. The opening width of the through hole 105 is, for example, 90nm~120nm, but is not limited thereto.

[0043] The depth of the through hole 105 is less than or equal to the depth of the mark groove 107, and the depth of the through hole 105 can be set according to the depth of the mark groove 107. Exemplarily, the depth of the through hole 105 can be greater than or equal to 4500Å and less than or equal to 5000Å, for example, 4800Å, but is not limited thereto.

[0044] Since different dry etching machines have different etching performances, in this embodiment, the first dry etching process and the second dry etching process are performed on the same machine, which can better suppress the restricted diffusion effect when etching the mark groove 107.

[0045] In this embodiment, after forming the patterned second mask layer 106, the overlay accuracy between the patterned second mask layer 106 and the substrate 100 and the critical dimension of the contact hole pattern 106b can be measured, so that when the overlay accuracy between the patterned second mask layer 106 and the substrate 100 is abnormal and / or the critical dimension of the contact hole pattern 106b is abnormal, it can be handled in time, which helps to ensure the alignment between the contact hole 108 and the substrate 100 and ensure the critical dimension of the obtained contact hole 108. After removing the patterned second mask layer 106, the critical dimension of the contact hole 108 can also be detected, so that when the critical dimension of the contact hole 108 is abnormal, it can be handled in time.

[0046] After removing the patterned second mask layer 106, refer to Fig.13 As shown, a barrier layer 109 may be formed, and the barrier layer 109 covers the sidewalls of the contact hole 108 and the sidewalls of the mark trench 107. Specifically, as Fig.12 As shown, a barrier layer 109 is formed on the dielectric layer 103, and the barrier layer 109 covers the top surface of the dielectric layer 103, the sidewalls and bottom surface of the marking groove 107, and the sidewalls and bottom surface of the contact hole 108; Fig.13 As shown, the barrier layer 109 on the bottom surfaces of the mark trench 107 and the contact hole 108 is removed, and at least the barrier layer 109 on the sidewalls of the contact hole 108 and the mark trench 107 is retained.

[0047] The barrier layer 109 can prevent the conductive material subsequently filled in the contact hole 108 from diffusing into the dielectric layer 103 to affect the conductive properties of the contact hole structure, and can also improve the adhesion between the conductive material and the substrate 100 .

[0048] The material of the barrier layer 109 includes, but is not limited to, tantalum, tantalum nitride, titanium or titanium nitride. Exemplarily, the barrier layer 109 may be a double-layer structure, for example, including a titanium layer and a titanium nitride layer stacked on the titanium layer, but is not limited thereto.

[0049] refer to Fig.14 As shown, a conductive material layer 110 is formed on the dielectric layer 103, the conductive material layer 110 covers the dielectric layer 103 and fills the contact hole 108 and the mark groove 107, wherein the conductive material layer 110 at least fills the contact hole 108; the conductive material layer 110 on the top surface of the dielectric layer 103 is removed by grinding to form a contact hole structure, the contact hole structure includes the contact hole 108, the barrier layer 109 in the contact hole 108 and the conductive material layer 110 in the contact hole 108. Exemplarily, the material of the conductive material layer 110 includes but is not limited to tungsten (W).

[0050] Next, refer to Fig.15As shown, a metal wiring layer 111 is formed on the dielectric layer 103 , and the metal wiring layer 111 is electrically connected to the substrate 100 via a contact hole structure.

[0051] refer to Fig.15 As shown, the metal wiring layer 111 includes a mark pattern 111a corresponding to the mark groove 107. The mark groove 107 and the mark pattern 111a can be used to measure the overlay accuracy between the metal wiring layer 111 and the substrate 100. The shape of the mark pattern 111a can be set according to the pattern of the mark groove 107.

[0052] Fig.16 This is a SEM cross-sectional view of a marking groove of a semiconductor structure provided by an embodiment of the present invention. Fig.16 As shown, the bottom surface of the mark groove 107 formed in the substrate 100 using the semiconductor structure manufacturing method provided by the present application is relatively flat, and there is no situation where the central area of ​​the bottom surface is raised relative to the edge area, which effectively suppresses the restricted diffusion effect when etching the mark groove 107.

[0053] Fig.17 FIG. 1 is a SEM top view of a marking groove of a semiconductor structure provided by an embodiment of the present invention. Fig.17 As shown, the outline of the mark groove 107 is clear and easy to identify, which helps to improve the accuracy of the overlay accuracy measurement value obtained by measuring the mark groove 107.

[0054] The present application also provides a semiconductor structure, which can be manufactured using the above-mentioned semiconductor structure manufacturing method.

[0055] Specifically, refer to Fig.14 and Fig.15 The semiconductor structure includes a substrate 100 and a dielectric layer 103 formed on the substrate 100, the substrate 100 includes a first area 100a and a second area 100b; a marking groove 107 is formed in the first area 100a, and a contact hole 108 is formed in the second area 100b, the marking groove 107 and the contact hole 108 both penetrate the dielectric layer 103 and the bottom surface is located in the substrate 100.

[0056] Exemplarily, the opening size of the mark groove 107 and the opening size of the contact hole 108 may be different, for example, the opening width of the mark groove 107 is greater than the opening width of the contact hole 108, but it is not limited thereto.

[0057] The semiconductor structure may further include a barrier layer 109 and a conductive material layer 110, wherein the barrier layer 109 covers the sidewalls of the contact hole 108 and the sidewalls of the marking groove 107, and the conductive material layer 110 fills the contact hole 108 and the marking groove 107, wherein the conductive material layer 110 may at least fill the contact hole 108 to form a contact hole structure, and the contact hole structure includes the contact hole 108, the barrier layer 109 in the contact hole 108, and the conductive material layer 110 in the contact hole 108.

[0058] refer to Fig.15 As shown, a metal wiring layer 111 may be formed on the dielectric layer 103, and the metal wiring layer 111 is electrically connected to the substrate 100 through a contact hole structure. The metal wiring layer 111 may also include a marking pattern 111a corresponding to the marking groove 107, and the overlay accuracy between the metal wiring layer 111 and the substrate 100 may be measured using the marking groove 107 and the marking pattern 111a. The shape of the marking pattern 111a may be set according to the pattern of the marking groove 107.

[0059] In the semiconductor structure and the manufacturing method thereof provided by the present invention, after the dielectric layer 103 is formed on the substrate 100, a first anisotropic dry etching process is first performed to etch the dielectric layer 103 and the substrate 100 and stop in the substrate 100 to form a plurality of through holes 105 in the first region 100a, and then a second anisotropic dry etching process is performed to etch the dielectric layer 103 and the substrate 100 in the second region 100b to form a contact hole 108, and at the same time, the dielectric layer 103 and the substrate 100 on the side of the through hole 105 are etched to enlarge the through hole 105 to form a marking groove 107. In this way, when the contact hole 108 and the marking groove 107 are etched at the same time, the pattern and size of the contact hole 108 are ensured to be consistent. In the case of a grid, the restricted diffusion effect that occurs when etching the mark groove 107 can be effectively suppressed, so that the bottom surface of the formed mark groove is relatively flat, thereby improving the boundary clarity of the mark groove, and subsequently using the mark groove to measure the overlay accuracy can reduce the measurement interference caused by the unclear boundary of the mark groove, improve the accuracy of the overlay accuracy measurement value, and further reduce the rework and scrap caused by the abnormal overlay accuracy measurement value caused by the unclear boundary of the mark groove, which helps to save manufacturing resources and production capacity; in addition, since the bottom surface of the formed mark groove is relatively flat, the contact between the conductive material subsequently filled in the mark groove and the substrate can be more comprehensive, which helps to improve the stress of the wafer.

[0060] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region, and a dielectric layer formed on the substrate; Performing an anisotropic first dry etching process to etch the dielectric layer and the substrate and stop in the substrate, forming a plurality of through holes in the first region; Forming a patterned second mask layer on the substrate, wherein the patterned second mask layer has a contact hole pattern and a marking groove pattern, wherein one of the marking groove patterns corresponds to at least a portion of the through hole position and exposes the corresponding through hole; Under the mask of the patterned second mask layer, performing an anisotropic second dry etching process to etch the dielectric layer and the substrate in the second region to form a contact hole, and at the same time etching the dielectric layer and the substrate at the side of the through hole to enlarge the through hole to form a marking groove; as well as The patterned second mask layer is removed.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method of forming a patterned second mask layer on the substrate comprises: Coating a photoresist on the substrate to form a photoresist layer, wherein the photoresist layer covers the substrate and fills the plurality of through holes; exposing the photoresist layer; and The photoresist layer is developed to form the patterned second mask layer, wherein the photoresist layer is developed twice to remove the photoresist in the plurality of through holes.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: In the step of performing the anisotropic second dry etching process, the dielectric layer and the substrate at the side of the through hole are etched so that more than two through holes are connected to form the marking groove.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first dry etching process and the second dry etching process are performed on the same machine.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: After performing an anisotropic second dry etching process, a barrier layer is formed, wherein the barrier layer covers the sidewalls of the contact hole and the sidewalls of the mark groove; forming a conductive material layer on the dielectric layer, wherein the conductive material layer covers the dielectric layer and fills the contact hole and the mark groove; The conductive material layer on the top surface of the dielectric layer is removed by grinding to form a contact hole structure, wherein the contact hole structure includes the contact hole, the barrier layer in the contact hole, and the conductive material layer in the contact hole.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: Also includes: After grinding and removing the conductive material layer on the top surface of the dielectric layer, a metal wiring layer is formed on the dielectric layer. The metal wiring layer is electrically connected to the substrate through the contact hole structure. The metal wiring layer includes a marking pattern corresponding to the marking groove. The marking groove and the marking pattern are used to measure the overlay accuracy between the metal wiring layer and the substrate.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The base comprises a substrate and an epitaxial layer located on the substrate, and the marking groove is located in the epitaxial layer.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first area is a scribe line area.

9. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing the semiconductor structure according to any one of claims 1 to 8.

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