Packaging structure and packaging method

Abstract

According to the packaging structure and the packaging method, when the packaging structure works, the temperature of the packaging structure rises, system chips in a chip-scale packaging assembly can be pulled by external stress and extruded by a heat dissipation cover, and due to the fact that a stress buffer groove is formed between every two adjacent system chips in the chip-scale packaging assembly, the system chips in the chip-scale packaging assembly cannot be damaged. The stress buffer groove can play a role in releasing stress and alleviate the pulling of external stress and the extrusion of the heat dissipation cover, so that different system chips in the chip-scale packaging assembly are not easy to crack due to external force, the possibility of warping of the chip-scale packaging assembly is reduced, and the reliability and the service life of the packaging structure are improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor packaging, and in particular to a packaging structure and a packaging method. Background Art

[0002] In the field of modern semiconductor manufacturing, as the functions of integrated circuits become increasingly complex, the traditional packaging method of a single chip can no longer meet the needs of high performance and high integration. To this end, chiplet technology has emerged. By integrating multiple chip modules with specific functions into chip-level packaging components using advanced wafer-level packaging (Chip on Wafer, CoW) technology, this integration method not only significantly improves the design flexibility and overall system performance, but also effectively reduces production costs and packaging size.

[0003] In specific applications, the chip-level package assembly contains multiple system chips, and each system chip includes multiple chips. As chip performance continues to improve, the integration of multiple system chips in large wafer-level packages will generate a lot of heat, and efficient heat dissipation solutions are urgently needed. VC (Vapor Chamber) heat sinks have become the preferred heat dissipation solution in wafer-level packaging due to their excellent thermal conductivity.

[0004] However, there is still room for further improvement in the reliability and service life of the packaging structure. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method to improve the reliability and service life of the packaging structure.

[0006] To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a packaging substrate; a chip-level packaging component located on the packaging substrate, the chip-level packaging component including a plurality of system chips, and the plurality of system chips are arranged at intervals in the plane on the packaging substrate; a stress buffer groove located between adjacent system chips and used to reduce the stress borne by the system chips; and a heat dissipation cover located on the chip-level packaging component, the heat dissipation cover being used to dissipate heat from the chip-level packaging component.

[0007] An embodiment of the present invention also provides a packaging method, comprising: providing a packaging substrate; providing a chip-level packaging component, the chip-level packaging component comprising a plurality of system chips, and the plurality of system chips are arranged at intervals in a plane, and stress buffer grooves are provided between adjacent system chips, the stress buffer grooves being used to reduce the stress borne by the system chips; mounting the side of the chip-level packaging component away from the stress buffer grooves on the packaging substrate; providing a heat dissipation cover, and forming the heat dissipation cover on the chip-level packaging component for dissipating heat from the chip-level packaging component.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] The packaging structure provided by the embodiment of the present invention includes: a packaging substrate; a chip-level packaging component, located on the packaging substrate, the chip-level packaging component includes a plurality of system chips, and the plurality of system chips are arranged at intervals in the plane on the packaging substrate; a stress buffer groove, the stress buffer groove is recessed and located between adjacent system chips, and is used to reduce the stress borne by the system chips; a heat dissipation cover, located on the chip-level packaging component, and the heat dissipation cover is used to dissipate heat from the chip-level packaging component. When the packaging structure provided by the embodiment of the present invention is working, the temperature of the packaging structure rises, and the system chips in the chip-level packaging component will be pulled by external stress and squeezed by the heat dissipation cover. Because there is a stress buffer groove between adjacent system chips, the stress buffer groove can play a role in stress release, relieve the pulling of external stress and the squeezing of the heat dissipation cover, so that different system chips in the chip-level packaging component are not easy to crack due to external force, reduce the possibility of warping of the chip-level packaging component, and help improve the reliability and service life of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 9 It is a structural schematic diagram corresponding to the key steps in the packaging method embodiment of the present invention. DETAILED DESCRIPTION

[0011] As known from the background technology, due to the different coefficients of expansion (CTE) between the chip-scale packaging component, the packaging substrate and the VC heat sink, when the package is heated, the chip-scale packaging component will be subjected to external stress, which reduces the reliability and service life of the packaging structure.

[0012] In order to solve the technical problem, the packaging structure provided by the embodiment of the present invention includes: a packaging substrate; a chip-level packaging component, located on the packaging substrate, the chip-level packaging component includes a plurality of system chips, and the plurality of system chips are arranged at intervals in the plane on the packaging substrate; a stress buffer groove, the stress buffer groove is recessed between adjacent system chips, and is used to reduce the stress borne by the system chip; a heat dissipation cover, located on the chip-level packaging component, and the heat dissipation cover is used to dissipate heat for the chip-level packaging component. When the packaging structure provided by the embodiment of the present invention is working, the temperature of the packaging structure rises, and the system chip in the chip-level packaging component will be pulled by external stress and squeezed by the heat dissipation cover. Because there is a stress buffer groove between adjacent system chips, the stress buffer groove can play a role in stress release, relieve the pulling of external stress and the squeezing of the heat dissipation cover, so that different system chips in the chip-level packaging component are not easy to crack due to external force, reduce the possibility of warping of the chip-level packaging component, and help improve the reliability and service life of the packaging structure.

[0013] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0014] Correspondingly, the present invention also provides a packaging method. Figures 1 to 9 It is a structural schematic diagram corresponding to the key steps in the first embodiment of the packaging method of the present invention.

[0015] refer to Figure 1 , providing a packaging substrate 100. The packaging substrate 100 provides a process platform for subsequently forming a chip-level packaging component.

[0016] In this embodiment, the packaging substrate 100 is a multi-layer printed circuit board (PCB), which is formed by alternately stacking multiple conductive layers and insulating layers. The material of the multi-layer printed circuit board can be an organic material or a glass material.

[0017] In this embodiment, the packaging substrate 100 includes a first surface 100A and a second surface 100B opposite to the first surface 100A. Electrical connection structures (for example, pads) are formed on the surfaces of the first surface 100A and the second surface 100B. An electrical channel is formed between the first surface 100A and the second surface 100B in the packaging substrate 100. The electrical channel is used to electrically connect the electrical connection structures of the first surface 100A and the second surface 100B in a subsequent packaging process.

[0018] refer to Figures 2 to 4 , providing a chip-scale package component 200, the chip-scale package component 200 includes a plurality of system chips 201 ( Figure 32 is a schematic diagram of a top view of a chip-level package component 200, showing a system chip 201A and a system chip 201B, wherein the plurality of system chips 201 are arranged at intervals in a plane, and a stress buffer groove 202 (such as Figure 4 As shown), the stress buffer groove 202 is used to reduce the stress borne by the system chip 201.

[0019] In the subsequent packaging process, the chip-level package component 200 will be mounted on the packaging substrate 100, and a heat dissipation cover will also be provided and formed on the chip-level package component 200 to dissipate heat for the chip-level package component 200. When the package structure provided by the embodiment of the present invention is working, the temperature of the package structure rises, and the system chip 201 in the chip-level package component 200 will be pulled by external stress and squeezed by the heat dissipation cover. Because there are recessed stress buffer grooves 202 between adjacent system chips 201 in the chip-level package component 200, the stress buffer grooves 202 can play a role in stress release, relieve the pulling of external stress and the squeezing of the heat dissipation cover, so that different system chips 201 in the chip-level package component 200 are not easy to crack due to external force, reduce the possibility of warping of the chip-level package component 200, and help improve the reliability and service life of the package structure.

[0020] In the step of providing the chip-scale package component 200 in this embodiment, the width D1 of the stress buffer groove 202 (eg Figure 4 20μm to 100μm). If the width D1 of the stress buffer groove 202 is too large, the interval between the corresponding system chips 201 is too large, which will lead to poor integration of the chip-level packaging component 200. If the width D1 of the stress buffer groove 202 is too small, the stress buffer groove 202 will be insufficient in releasing stress, and the stress borne by the chip-level packaging component 200 cannot be effectively dispersed, which will easily form a stress concentration point in the chip-level packaging component 200, increasing the risk of cracking of the chip-level packaging component 200; moreover, if the width D1 of the stress buffer groove 202 is too small, it will not be conducive to alleviating the warping of the chip-level packaging component 200, affecting the reliability of the subsequent packaging process.

[0021] It should be noted that, in the step of providing the chip-level package component 200, the stress buffer groove 202 is located in the middle position between adjacent system chips 201. When the chip-level package component 200 is subjected to thermal stress or mechanical stress, because the stress buffer groove 202 is located in the middle position between adjacent system chips 201, the stress buffer groove 202 is easily subjected to symmetrical stress, which avoids the stress from being concentrated on one side, and can effectively balance the stress distribution between adjacent system chips 201, thereby reducing the occurrence of cracks or warping between adjacent system chips 201.

[0022] Specifically, the steps of providing the chip-level packaging component 200 include: providing an adapter board 203; forming a plurality of system chips 201 spaced apart on the adapter board 203; forming a plastic encapsulation layer 204 between adjacent system chips 201; and etching the plastic encapsulation layer 204 between adjacent system chips 201 to form a stress buffer groove 202.

[0023] The interposer 203 serves as a base of the chip-scale package assembly 200 and provides a platform for structural support and electrical connection.

[0024] In this embodiment, the thermal expansion coefficient of the material of the adapter plate 203 should match that of the system chip 201 to reduce stress caused by thermal mismatch. For example, the material of the adapter plate 203 includes silicon.

[0025] It should be noted that the adapter board 203 has a third surface 203A and a fourth surface 203B opposite to the third surface 203A, and an electrical channel (TSV) is also formed between the third surface 203A and the fourth surface 203B in the adapter board 203, and the electrical channel is used for vertical electrical connection between the third surface 203A and the fourth surface 203B. TSV technology can reduce the interconnection length, reduce signal delay, reduce capacitance and inductance through vertical interconnection, realize low-power and high-speed communication between chips, and realize miniaturization of packaging structure.

[0026] In this embodiment, the third surface 203A of the adapter board 203 is used to set the system chip 201, and the fourth surface 203B is formed with first conductive bumps 211. In the subsequent packaging process, the first conductive bumps 211 on the fourth surface 203B are used to electrically connect the chip-level packaging component 200 with the packaging substrate 100.

[0027] Multiple system chips 201 (such as system chip 201A and system chip 201B) are spaced apart on the adapter board 203, so that adjacent system chips 201 are not easily in direct contact, which helps to evenly disperse the heat generated by the multiple system chips 201 in the chip-level packaging component 200 and avoid the formation of hot spots, thereby improving the heat dissipation efficiency of the chip-level packaging component 200; moreover, the spacing between the system chips 201 also provides space for stress release of the system chips 201, reducing stress concentration caused by differences in thermal expansion coefficients or external temperature changes.

[0028] In this embodiment, Figure 3 The chip-scale package assembly 200 only illustrates two system chips 201, namely, a system chip 201A and a system chip 201B. In other embodiments, the chip-scale package assembly may further include a plurality of system chips, and the plurality of system chips may be arranged in a matrix of multiple rows and columns.

[0029] In this embodiment, the system chip 201 includes multiple chips 201a. By integrating multiple chips 201a into the same system chip 201, the flexibility and scalability of the system chip 201 are improved, which is conducive to simplifying the integration process of the chip-level package component 200. In addition, integrating multiple chips 201a into the same system chip 201 helps to concentrate heat dissipation.

[0030] It should be noted that the multiple chips 201a in the system chip 201 can be divided into different types of chips according to the performance requirements of the packaging structure, such as memory chips and ASIC chips (Application-Specific Integrated Circuit).

[0031] In this embodiment, a flip-chip (FC) process is adopted to arrange a plurality of system chips 201 (eg, the system chip 201A and the system chip 201B) on the transfer board 203 at intervals.

[0032] The plastic encapsulation layer 204 is formed between adjacent system chips 201 and can provide stable mechanical support for the system chip 201. The material of the plastic encapsulation layer 204 is usually elastic and can effectively disperse and relieve internal or external stress. In addition, the plastic encapsulation layer 204 can effectively protect the system chip 201 from environmental factors (such as moisture, dust, etc.).

[0033] In this embodiment, the plastic packaging layer 204 is flush with the top of the system chip 201 , which is beneficial to the heat dissipation of the system chip 201 .

[0034] In this embodiment, the stress buffering groove 202 is spaced apart from the system chip 201. Because the stress buffering groove 202 is spaced apart from the system chip 201, in other words, the sidewall of the system chip 201 is still covered by the plastic packaging layer 204, which is beneficial to protect the sidewall of the system chip 201.

[0035] In this embodiment, the plastic packaging layer 204 is made of a packaging material with good fluidity and appropriate elasticity, such as epoxy molding compound.

[0036] It should be noted that in the step of providing the chip-level packaging component 200, the stress buffer groove 202 is recessed at the top between the adjacent system chips 201. The depth L of the stress buffer groove 202 (eg Figure 4As shown in the figure, the depth L of the stress buffer groove 202 is one-third to one-half of the thickness of the plastic layer 204. If the depth L of the stress buffer groove 202 is too large, the corresponding remaining thickness of the plastic layer 204 between adjacent system chips 201 is small, resulting in a weak mechanical strength of the plastic layer 204, and also making it easier for external moisture, impurities, etc. to enter the system chip 201. If the depth L of the stress buffer groove 202 is too small, when the packaging structure is working, the stress that the stress buffer groove 202 can relieve is limited, resulting in the chip-level packaging component 200 being prone to cracking or warping.

[0037] In this embodiment, a laser etching process is used to etch the plastic layer 204 between adjacent system chips 201 to form a stress buffer groove 202. The laser etching process can achieve nano-level fine processing, which is conducive to accurately controlling the size of the stress buffer groove 202, and the laser etching process is a non-contact etching process, which is conducive to reducing mechanical damage to the plastic layer 204.

[0038] Specifically, the step of etching the plastic packaging layer 204 between adjacent system chips 201 to form the stress buffer groove 202 includes: forming a second mask layer 205 (eg, Figure 4 As shown), the second mask layer 205 has a second opening 206 (as shown Figure 4 As shown), the second opening 206 corresponds to the position where the stress buffer groove 202 is to be formed; the plastic encapsulation layer 204 exposed by the second opening 206 is etched by a laser etching process to form the stress buffer groove 202.

[0039] The second mask layer 205 not only accurately controls the formation position of the stress buffer groove 202 , but also plays a role in protecting the system chip 201 .

[0040] In this embodiment, the material of the second mask layer 205 includes photoresist, and the second opening 206 is formed by exposure and development processes. Photoresist is easy to form and remove, which is conducive to simplifying the formation process of the second mask layer 205, and photoresist is not easy to damage other structures.

[0041] The step of providing the chip-scale packaging component 200 further includes: after forming the stress buffer groove 202 , removing the second mask layer 205 by an ashing process.

[0042] It should be noted that the method for forming the chip-scale package assembly 200 further includes: before forming the plastic encapsulation layer 204 between adjacent system chips 201 , forming a first bottom filling layer 207 between the bottom of the system chip 201 and the transfer board 203 .

[0043] The first bottom filling layer 207 is used to fix and protect the electrical connection between the system chip 201 and the third surface 203A of the transfer board 203 .

[0044] In this embodiment, the material of the first bottom filling layer 207 includes: epoxy resin. Epoxy resin has good adhesion and mechanical strength, and can be used to quickly fix the system chip 201 and provide electrical isolation.

[0045] It should also be noted that in the step of providing the chip-scale packaging component 200 , the plastic encapsulation layer 204 is formed after the first bottom filling layer 207 , and the corresponding plastic encapsulation layer 204 is formed on the first bottom filling layer 207 .

[0046] refer to Figure 5 , the side of the chip-scale package component 200 facing away from the stress buffer groove 202 is mounted on the package substrate 100 .

[0047] The side of the chip-level packaging component 200 facing away from the stress buffer groove 202 is mounted on the packaging substrate 100, and the system chip 201 in the corresponding chip-level packaging component 200 is arranged away from the packaging substrate 100, so that a heat dissipation cover can be formed on the system chip 201 later, so that the heat dissipation cover can dissipate heat for the system chip 201.

[0048] In this embodiment, a flip-chip (FC) process is used to mount the side of the chip-scale package component 200 away from the stress buffer groove 202 on the package substrate 100. Specifically, the first conductive bump 211 in the chip-scale package component 200 is electrically connected to the electrical connection structure on the first surface 100A of the package substrate 100.

[0049] In this embodiment, after the chip-scale package component 200 is mounted on the package substrate 100 at a side facing away from the stress buffer groove 202 , a second bottom filling layer 208 is formed between the first conductive bump 211 in the transfer board 203 and the package substrate 100 .

[0050] The second underfill layer 208 is used to fix and protect the electrical connection between the first conductive bump 211 and the package substrate 100 .

[0051] In this embodiment, the material of the second bottom filling layer 208 includes epoxy resin. The epoxy resin has good adhesion and mechanical strength, and can be used to quickly fix the chip-scale packaging component 200 and provide electrical isolation.

[0052] It should be noted that the method for forming the packaging structure further includes: before mounting the side of the chip-level packaging component 200 away from the stress buffer groove 202 on the packaging substrate 100 , mounting the passive device 213 on the packaging substrate 100 .

[0053] During the packaging process, passive components 213 (such as capacitors, inductors, resistors, etc.) are reasonably arranged on the packaging substrate 100 according to the performance requirements of the packaging structure to be formed, which is beneficial to optimizing the electrical performance of the packaging structure.

[0054] Specifically, the passive device 213 is mounted on the first surface 100A of the packaging substrate 100 .

[0055] like Figure 6 As shown, the method for forming the packaging structure further includes: after mounting the side of the chip-level packaging component 200 away from the stress buffer groove 202 on the packaging substrate 100 , a heat conducting layer 209 is formed on the system chip 201 .

[0056] In the subsequent packaging process, a heat dissipation cover is formed on the heat conductive layer 209. When the packaging structure is working, the heat conductive layer 209 acts as a heat conduction medium to effectively conduct the heat generated by the system chip 201 to the heat dissipation cover, and then discharges the heat through the heat dissipation cover, so that the system chip 201 is not easily degraded or failed due to overheating, thereby improving the reliability and service life of the packaging structure.

[0057] In this embodiment, the material of the thermal conductive layer 209 includes thermal conductive adhesive (Thermal Interface Material, TiM). The thermal conductive adhesive, as a heat conduction medium, not only has excellent thermal conductivity, but also has good mechanical elasticity. It can alleviate the mechanical stress caused by the difference in thermal expansion coefficient (CTE) and prevent the chip-level packaging component 200 from cracking, thereby improving the overall reliability and service life of the packaging structure.

[0058] It should be noted that the heat conducting layer 209 on each system chip 201 covers at least 90% of the area on the top of the corresponding system chip 201. If the area on the top of the corresponding system chip 201 covered by the heat conducting layer 209 is too small, the heat generated by the system chip 201 cannot be discharged in time, which reduces the performance of the system chip 201. In addition, if the temperature of the system chip 201 is too high, the stress inside the chip-level package component 200 will be relatively large, and the chip-level package component 200 will be prone to cracking or warping.

[0059] The method for forming the package structure further includes: mounting the side of the chip-level package component 200 away from the stress buffer groove 202 on the package substrate 100 , and forming an adhesive layer 210 (adhesive) on the package substrate 100 .

[0060] In the subsequent packaging process, the adhesive layer 210 is used to fix the heat dissipation cover and the packaging substrate 100 .

[0061] In this embodiment, the material of the adhesive layer 210 includes a silicone-based adhesive or a polyimide-based adhesive. The silicone-based adhesive or the polyimide-based adhesive has excellent mechanical properties and can meet high-temperature process requirements.

[0062] refer to Figure 7 , providing a heat dissipation cover 300 . In a subsequent packaging process, the heat dissipation cover 300 is formed on the chip-scale package component 200 to dissipate heat for the chip-scale package component 200 .

[0063] In this embodiment, in the step of providing the heat dissipation cover 300 , the heat dissipation cover 300 includes: a plurality of heat dissipation modules 301 arranged at intervals in a plane, and blind holes 302 are provided between adjacent heat dissipation modules 301 .

[0064] After the heat dissipation cover 300 is subsequently formed on the chip-level packaging component 200, the heat dissipation module 301 corresponds to the system chip 201 one by one, so that the heat dissipation module 301 can directly and efficiently receive and conduct heat from the corresponding system chip 201; in addition, the heat dissipation cover 300 will generate mechanical stress during thermal expansion and contraction, and the blind holes 302 between adjacent heat dissipation modules 301 can absorb part of the stress, so that the stress will not be directly transmitted to the chip-level packaging component 200, thereby reducing the squeezing and pulling of the system chip 201 in the chip-level packaging component 200, making the chip-level packaging component 200 less prone to warping and cracking.

[0065] In this embodiment, in the step of providing the heat dissipation cover 300 , the length of the blind hole 302 in the extending direction is greater than or equal to the length of the stress buffer groove 202 in the extending direction.

[0066] The length of the blind hole 302 in the extension direction is greater than or equal to the length of the stress buffer groove 202 in the extension direction. That is to say, the blind hole 302 in the extension direction is long enough. After the temperature of the heat dissipation cover 300 rises, the heat dissipation cover 300 has a large enough space for stress buffering, thereby reducing the stress caused by the heat dissipation cover 300 to the chip-level packaging component 200 and reducing the probability of warping and deformation of the chip-level packaging component 200.

[0067] In this embodiment, the step of providing the heat dissipation cover 300 includes: forming a first mask layer (not shown in the figure) covering the heat dissipation module 301, the first mask layer having a first opening (not shown in the figure) exposing the area between the heat dissipation modules 301; etching the heat dissipation cover 300 exposed by the first opening to form the blind hole 302.

[0068] In this embodiment, the heat dissipation cover 300 exposed by the first opening is etched by dry etching process to form the blind hole 302. The dry etching process has good etching profile, which is conducive to controlling the morphology of the blind hole 302.

[0069] Specifically, the heat dissipation cover 300 exposed by the first opening is etched by laser etching process to form the blind hole 302. The laser etching process can achieve nano-level fine processing, which is conducive to the precise control of the size of the blind hole 302, and the laser etching process is a non-contact etching process, which is conducive to reducing mechanical damage to the heat dissipation cover 300.

[0070] The first mask layer not only accurately controls the formation position of the blind hole 302 , but also plays a role in protecting the evaporation chamber 3013 in the heat dissipation cover 300 .

[0071] In this embodiment, the material of the first mask layer includes photoresist, and the first opening is formed by exposure and development processes. Photoresist is easy to form and remove, which is conducive to simplifying the formation process of the first mask layer, and photoresist is not easy to damage other structures.

[0072] The step of providing the heat dissipation cover 300 further includes: after forming the blind hole 302 , removing the first mask layer by an ashing process.

[0073] In this embodiment, the heat dissipation cover 300 is made of a material with good thermal conductivity, for example, the material of the heat dissipation cover 300 includes copper.

[0074] In this embodiment, in the step of providing the heat dissipation cover 300 , the heat dissipation module 301 includes: a stacked condensation chamber 3011 , a heat transfer pipe 3012 and an evaporation chamber 3013 , and the heat transfer pipe 3012 is connected to both the condensation chamber 3011 and the evaporation chamber 3013 .

[0075] In the subsequent packaging process, the evaporation chamber 3013 of the heat dissipation cover 300 is arranged close to the chip-level packaging component 200, and is used to directly absorb the heat generated by the system chip 201. The heat dissipation liquid in the evaporation chamber 3013 vaporizes after absorbing the heat, and the steam moves to the condensation chamber 3011 through the heat transfer pipe 3012. The condensation chamber 3011 receives the steam from the heat transfer pipe 3012. Because the condensation chamber 3011 is far away from the chip-level packaging component 200, the temperature of the condensation chamber 3011 is relatively low. The steam condenses in the condensation chamber 3011 to release heat, and the condensed liquid then flows back to the evaporation chamber 3013 through the heat transfer pipe 3012. This cycle continues, thereby achieving the effect of lowering the temperature of the system chip 201.

[0076] In this embodiment, in the step of providing the heat dissipation cover 300, the evaporation chamber 3013 is formed on the surface of the heat dissipation cover 300, that is, the evaporation chamber 3013 is exposed outside the heat dissipation cover 300. When the heat dissipation cover 300 is subsequently formed on the chip-level package component 200, the evaporation chamber 3013 can be in direct contact with the heat conductive layer 209, and can quickly absorb the heat of the evaporation chamber 3013. In other embodiments, in the step of providing the heat dissipation cover, the evaporation chamber can also be formed inside the heat dissipation cover, that is, the evaporation chamber is covered by the material of the heat dissipation cover, so that the evaporation chamber is not directly exposed to the surface of the heat dissipation cover, which is conducive to protecting the evaporation chamber.

[0077] In this embodiment, in the step of providing the heat dissipation cover 300, the condensation chamber 3011 is formed inside the heat dissipation cover 300, that is, the condensation chamber 3011 is covered by the material of the heat dissipation cover 300, so that the condensation chamber 3011 is not directly exposed to the surface of the heat dissipation cover 300, which is conducive to protecting the condensation chamber 3011. In other embodiments, in the step of providing the heat dissipation cover, the condensation chamber can also be formed on the surface of the heat dissipation cover, that is, the condensation chamber is exposed to the outside of the heat dissipation cover, which is conducive to the rapid condensation and heat dissipation of the steam in the condensation chamber.

[0078] It should be noted that there are multiple heat transfer pipes 3012 between the condensation chamber 3011 and the evaporation chamber 3013, which is conducive to rapid heat transfer between the evaporation chamber 3013 and the condensation chamber 3011.

[0079] It should also be noted that the evaporation chambers 3013 in the heat dissipation module 301 are interconnected, and the condensation chambers 3011 are interconnected.

[0080] In this embodiment, the heat dissipation cover 300 includes a central area and an edge area. The heat dissipation module 301 is located in the central area of ​​the heat dissipation cover 300. The edge area of ​​the heat dissipation cover 300 has a protruding fixing portion 303, which is used to be mounted and fixed with the adhesive layer 210 on the packaging substrate 100.

[0081] In the subsequent packaging process, when the heat dissipation cover 300 is mounted on the packaging substrate 100, the heat dissipation cover 300 surrounds the top and side walls of the chip-level packaging component 200, thereby protecting the chip-level packaging component 200, and the heat dissipation module 301 is located above the chip-level packaging component 200, and is used to dissipate heat for the system chip 201 in the chip-level packaging component 200.

[0082] It should be noted that the heat dissipation module 301 is formed in the central area of ​​the heat dissipation cover 300 , and the corresponding blind hole 302 is formed in the central area of ​​the heat dissipation cover 300 .

[0083] It should also be noted that the width of the heat dissipation cover 300 is greater than the width of the chip-scale package assembly 200. After the heat dissipation cover 300 is formed on the chip-scale package assembly 200, the fixing portion 303 is combined with the adhesive layer 210 on the package substrate 100 to form a cavity on the side of the chip-scale package assembly 200.

[0084] refer to Figure 8 A heat dissipation cover 300 is formed on the chip-scale package component 200 to dissipate heat for the chip-scale package component 200 .

[0085] In this embodiment, in the step of forming the heat dissipation cover 300 on the chip-level package component 200 , the side of the heat dissipation cover 300 having the blind hole 302 is close to the chip-level package component 200 , and the heat dissipation modules 301 are arranged one by one directly above the system chip 201 .

[0086] The heat dissipation cover 300 of the embodiment of the present invention includes a plurality of heat dissipation modules 301, which are arranged at intervals in a plane and are disposed one by one directly above the system chip 201 in the chip-level package assembly 200. Thus, the heat dissipation modules 301 can directly and efficiently receive and conduct heat from the corresponding system chip 201.

[0087] In this embodiment, in the step of forming the heat dissipation cover 300 on the chip-scale package component 200 , the blind hole 302 is connected to the stress buffer groove 202 .

[0088] When the packaging structure is working, the difference in coefficient of thermal expansion (CTE) between the chip-level packaging component 200, the packaging substrate 100 and the heat sink will cause mechanical stress. Since the blind hole 302 is connected to the stress buffer groove 202, the blind hole 302 can absorb part of the stress and reduce the possibility of cracking of the chip-level packaging component 200.

[0089] In this embodiment, in the step of forming the heat dissipation cover 300 on the chip-scale package component 200, the blind hole 302 is located directly above the stress buffering groove 202. The blind hole 302 is located directly above the stress buffering groove 202, so that after the heat dissipation cover 300 and the chip-scale package component 200 release stress at the same position, the stress between the chip-scale package component 200 and the heat dissipation cover 300 is reduced.

[0090] In the present embodiment, in the step of forming the heat dissipation cover 300 on the chip-scale package component 200, the width D2 of the blind hole 302 (eg Figure 8 ) is larger than the width D1 of the stress buffering groove 202 and smaller than the interval between the system chips 201 .

[0091] The width D2 of the blind hole 302 is greater than the width D1 of the stress buffer groove 202, and the corresponding contact area of ​​the plastic sealing layer 204 between the heat dissipation cover 300 and the system chip 201 is smaller, so that the extrusion force of the heat dissipation cover 300 on the plastic sealing layer 204 at the stress buffer groove 202 is smaller, making it difficult for the plastic sealing layer 204 to crack. At the same time, the width D2 of the blind hole 302 is smaller than the interval between adjacent system chips 201, so as to avoid the blind hole 302 being too wide, resulting in a reduction in the contact area between the heat dissipation cover 300 and the system chip 201, so that the system chip 201 and the heat dissipation cover 300 have a higher heat transfer efficiency.

[0092] It should be noted that in the step of forming the heat dissipation cover 300 on the chip-scale package component 200 , the evaporation chamber 3013 in the heat dissipation cover 300 is disposed close to the chip-scale package component 200 , and the condensation chamber 3011 is disposed away from the chip-scale package component 200 .

[0093] The evaporation chamber 3013 is close to the chip-scale package component 200, so that the heat generated by the chip-scale package component 200 is directly transferred to the heat dissipation liquid in the evaporation chamber 3013, causing the liquid to evaporate quickly. Since the evaporation process absorbs a large amount of heat, the temperature of the system chip 201 is effectively controlled. Subsequently, the gas generated by evaporation rises to the condensation chamber 3011 far away from the chip-scale package component 200 through the heat transfer pipe 3012. In the condensation chamber 3011, the gas releases heat and condenses into liquid, and the released heat is further conducted to the outside of the heat dissipation cover 300. The condensed liquid returns to the evaporation chamber 3013, and the cycle is repeated to achieve the purpose of lowering the temperature of the chip-scale package component 200.

[0094] In this embodiment, in the step of forming the heat dissipation cover 300 on the chip-scale package component 200 , the heat conduction layer 209 is formed between the heat dissipation cover 300 and the system chip 201 , and the heat conduction layer 209 exposes the blind hole 302 and the stress buffer groove 202 .

[0095] The heat conducting layer 209 exposes the blind holes 302 and the stress buffer grooves 202, so that stress concentration is not easy between the heat dissipation modules 301 and between the system chips 201, reducing the thermal stress and mechanical stress on the chip-level packaging component 200, preventing the chip-level packaging component 200 from cracking and the packaging structure from warping, and improving the reliability of the product.

[0096] It should be noted that, in the step of forming the heat dissipation cover 300 on the chip-level packaging component 200, the fixing portion 303 is used to be mounted and fixed to the adhesive layer 210 on the packaging substrate 100, and the heat dissipation cover 300 also forms a cavity 212 with the side wall of the chip-level packaging component 200, and the passive device 213 is located in the cavity 212.

[0097] The cavity 212 provides a closed protective space for the passive device 213, reducing the impact of the external environment on the passive device 213; in addition, the cavity 212 can also reduce stress concentration and buffer stress, which helps to improve the reliability and service life of the packaging structure.

[0098] In this embodiment, the cavity 212 surrounds the chip-scale packaging component 200, providing all-round protection for the entire chip-scale packaging component 200, and the surrounding design can make the stress more evenly distributed around the chip-scale packaging component 200, which helps to better relieve and disperse the stress.

[0099] In this embodiment, the blind hole 302, the stress buffer groove 202 and the cavity 212 are connected to avoid the popcorn effect caused by the concentration of thermal stress in the blind hole 302 and the stress buffer groove 202. Fig. 9 The packaging method further includes: forming a second conductive bump 103 on the second surface 100B of the packaging substrate 100. The second conductive bump 103 is used to electrically connect the packaging substrate 100 and the chip-scale packaging component 200 thereon with the outside.

[0100] In this embodiment, the second conductive bump 103 includes a solder ball, and the material of the solder ball includes tin or a tin alloy.

[0101] The embodiment of the present invention also provides a packaging structure, referring to Fig. 9 , which illustrates a schematic structural diagram of the packaging structure implemented in the present invention.

[0102] The packaging structure includes: a packaging substrate 100; a chip-level packaging component 200, which is located on the packaging substrate 100, and the chip-level packaging component 200 includes a plurality of system chips 201, and the plurality of system chips 201 are arranged in a plane on the packaging substrate 100; a stress buffer groove 202, which is located between adjacent system chips 201 and is used to reduce the stress on the system chip 201; a heat dissipation cover 300 (such as Figure 7 As shown), it is located on the chip-scale packaging component 200, and the heat dissipation cover 300 is used to dissipate heat for the chip-scale packaging component 200.

[0103] When the packaging structure provided by the embodiment of the present invention is working, the temperature of the packaging structure rises, and the system chip 201 in the chip-level packaging component 200 will be pulled by external stress and squeezed by the heat dissipation cover 300. Because there are stress buffer grooves 202 between adjacent system chips 201, the stress buffer grooves 202 can play a role in stress release, alleviate the pulling of external stress and the squeezing of the heat dissipation cover 300, so that different system chips 201 in the chip-level packaging component 200 are not easily cracked due to external force, and the possibility of warping of the chip-level packaging component 200 is reduced, which is beneficial to improving the reliability and service life of the packaging structure.

[0104] In this embodiment, the packaging substrate 100 is a multi-layer printed circuit board (PCB), which is formed by alternately stacking multiple conductive layers and insulating layers. The material of the multi-layer printed circuit board can be an organic material or a glass material.

[0105] In this embodiment, the packaging substrate 100 includes a first surface 100A and a second surface 100B opposite to the first surface 100A, and electrical connection structures (for example, pads) are formed on the surfaces of the first surface 100A and the second surface 100B. An electrical channel is formed in the packaging substrate 100 between the first surface 100A and the second surface 100B, and the electrical channel is used to vertically connect the electrical connection structures of the first surface 100A and the second surface 100B.

[0106] The chip-scale package assembly 200 includes a plurality of system chips 201 ( Figure 3 2 is a schematic diagram of a top view of a chip-level package component 200 , illustrating a system chip 201A and a system chip 201B, and a stress buffer groove 202 is provided between adjacent system chips 201 , and the stress buffer groove 202 is used to reduce the stress on the system chip 201 .

[0107] In this embodiment, the width D1 of the stress buffer groove 202 is 20 μm to 100 μm. If the width D1 of the stress buffer groove 202 is too large, the interval between the corresponding system chips 201 is too large, which will lead to poor integration of the chip-level package component 200. If the width D1 of the stress buffer groove 202 is too small, the stress buffer groove 202 will not be able to release stress effectively, and the stress borne by the chip-level package component 200 cannot be effectively dispersed, which is easy to form a stress concentration point in the chip-level package component 200, increasing the risk of cracking of the chip-level package component 200; moreover, if the width D1 of the stress buffer groove 202 is too small, it is not conducive to alleviating the warping of the chip-level package component 200.

[0108] It should be noted that the stress buffer groove 202 is located in the middle between adjacent system chips 201. When the chip-level package component 200 is subjected to thermal stress or mechanical stress, because the stress buffer groove 202 is located in the middle between adjacent system chips 201, the stress buffer groove 202 is easily subjected to symmetrical stress, avoiding the stress from being concentrated on one side, and can effectively balance the stress distribution between adjacent system chips 201, thereby reducing the occurrence of cracks or warping between adjacent system chips 201.

[0109] Specifically, the chip-level packaging component 200 includes: an adapter board 203; a plurality of system chips 201 spaced apart and located on the adapter board 203; a plastic encapsulation layer 204 located between adjacent system chips 201; and the stress buffer groove 202 located on the top of the plastic encapsulation layer 204 between adjacent system chips 201.

[0110] The interposer 203 serves as a base of the chip-scale package assembly 200 and provides a platform for structural support and electrical connection.

[0111] In this embodiment, the thermal expansion coefficient of the material of the adapter plate 203 should match that of the system chip 201 to reduce stress caused by thermal mismatch. For example, the material of the adapter plate 203 includes silicon.

[0112] It should be noted that the adapter board 203 has a third surface 203A and a fourth surface 203B opposite to the third surface 203A, and an electrical channel (TSV) is also formed between the third surface 203A and the fourth surface 203B in the adapter board 203, and the electrical channel is used for vertical electrical connection between the third surface 203A and the fourth surface 203B. TSV technology can reduce the interconnection length, reduce signal delay, reduce capacitance and inductance through vertical interconnection, realize low-power and high-speed communication between chips, and realize miniaturization of packaging structure.

[0113] In this embodiment, the third surface 203A of the transfer board 203 is used to place the system chip 201, and the fourth surface 203B is formed with first conductive bumps 211. The first conductive bumps 211 on the fourth surface 203B are used to electrically connect the chip-scale package component 200 with the package substrate 100.

[0114] Multiple system chips 201 (such as system chip 201A and system chip 201B) are spaced apart on the adapter board 203, so that adjacent system chips 201 are not easily in direct contact, which helps to evenly disperse the heat generated by the multiple system chips 201 in the chip-level packaging component 200 and avoid the formation of hot spots, thereby improving the heat dissipation efficiency of the chip-level packaging component 200; moreover, the spacing between the system chips 201 also provides space for stress release of the system chips 201, reducing stress concentration caused by differences in thermal expansion coefficients or external temperature changes.

[0115] In this embodiment, Figure 3 The chip-scale package assembly 200 only illustrates two system chips 201, namely, a system chip 201A and a system chip 201B. In other embodiments, the chip-scale package assembly may further include a plurality of system chips, and the plurality of system chips may be arranged in a matrix of multiple rows and columns.

[0116] In this embodiment, the system chip 201 includes a plurality of chips 201a (eg Figure 3By integrating multiple chips 201a into the same system chip 201, the flexibility and scalability of the system chip 201 are improved, which is conducive to simplifying the integration process of the chip-level package component 200. In addition, integrating multiple chips 201a into the same system chip 201 helps to concentrate the heat dissipation.

[0117] It should be noted that the multiple chips 201a in the system chip 201 can be different types of chips, such as memory chips and ASIC chips, according to the performance requirements of the packaging structure.

[0118] The plastic encapsulation layer 204 is located between adjacent system chips 201 and can provide stable mechanical support for the system chip 201. The material of the plastic encapsulation layer 204 is usually elastic and can effectively disperse and relieve internal or external stress. In addition, the plastic encapsulation layer 204 can effectively protect the system chip 201 from environmental factors (such as moisture, dust, etc.).

[0119] In this embodiment, in the step of providing the chip-level packaging component, the stress buffer groove 202 is spaced apart from the system chip 201. Because the stress buffer groove 202 is spaced apart from the system chip 201, in other words, the side wall of the system chip 201 is still covered by the plastic packaging layer 204, which is beneficial to protect the side wall of the system chip 201.

[0120] In this embodiment, the plastic packaging layer 204 is made of a packaging material with good fluidity and appropriate elasticity, such as epoxy molding compound.

[0121] It should be noted that the stress buffer groove 202 is recessed at the top between the adjacent system chips 201. The depth L of the stress buffer groove 202 is one-third to one-half of the thickness of the plastic encapsulation layer 204. If the depth L of the stress buffer groove 202 is too large, the corresponding remaining thickness of the plastic encapsulation layer 204 between the adjacent system chips 201 is small, resulting in a weaker mechanical strength of the plastic encapsulation layer 204, and also making it easier for external moisture, impurities, etc. to enter the system chip 201. If the depth L of the stress buffer groove 202 is too small, when the packaging structure is working, the stress that the stress buffer groove 202 can relieve is limited, resulting in the chip-level packaging component 200 being prone to cracking or warping.

[0122] It should be noted that the chip-scale package component 200 further includes: a first bottom filling layer 207, which is located between the bottom of the system chip 201 and the adapter board 203. The first bottom filling layer 207 is used to fix and protect the electrical connection between the system chip 201 and the third surface 203A of the adapter board 203. Correspondingly, the plastic encapsulation layer 204 in the chip-scale package component 200 is located on the first bottom filling layer 207.

[0123] In this embodiment, the material of the first bottom filling layer 207 includes epoxy resin. The epoxy resin has good adhesion and mechanical strength, and can be used to quickly fix the system chip 201 and provide electrical isolation.

[0124] In this embodiment, the side of the chip-level package component 200 away from the stress buffer groove 202 is located on the package substrate 100 , and the system chip 201 in the corresponding chip-level package component 200 is arranged away from the package substrate 100 , so that the heat dissipation cover 300 can dissipate heat for the system chip 201 .

[0125] In this embodiment, the side of the chip-scale package component 200 away from the stress buffer groove 202 is located on the package substrate 100. Specifically, the first conductive bump 211 in the chip-scale package component 200 is electrically connected to the electrical connection structure on the first surface 100A of the package substrate 100.

[0126] In this embodiment, the package structure further includes: a second bottom filling layer 208 located between the first conductive bump 211 and the package substrate 100. The second bottom filling layer 208 is used to fix and protect the electrical connection between the first conductive bump 211 and the package substrate 100.

[0127] In this embodiment, the material of the second bottom filling layer 208 includes epoxy resin. The epoxy resin has good adhesion and mechanical strength, and can be used to quickly fix the chip-scale packaging component 200 and provide electrical isolation.

[0128] It should be noted that the packaging structure further includes: a passive device 213 located on the packaging substrate 100 .

[0129] According to the performance requirements of the packaging structure, the passive components 213 (such as capacitors, inductors, resistors, etc.) are reasonably arranged on the packaging substrate 100, which is beneficial to optimizing the electrical performance of the packaging structure.

[0130] Specifically, the passive device 213 is mounted on the first surface 100A of the packaging substrate 100 .

[0131] The heat dissipation cover 300 is located on the chip-scale package component 200 and is used to dissipate heat for the chip-scale package component 200 .

[0132] In this embodiment, the heat dissipation cover 300 includes: a plurality of heat dissipation modules 301 arranged at intervals in a plane, and a blind hole 302 is provided between adjacent heat dissipation modules 301. The side of the heat dissipation cover 300 having the blind hole 302 is close to the chip-level packaging component 200, and the heat dissipation modules 301 are arranged one by one directly above the system chip 201.

[0133] The heat dissipation cover 300 of the embodiment of the present invention includes a plurality of heat dissipation modules 301, which are arranged at intervals in a plane and are arranged one by one directly above the system chip 201 in the chip-level package component 200. Therefore, the heat dissipation modules 301 can directly and efficiently receive and conduct heat from the corresponding system chip 201. In addition, the heat dissipation cover 300 will generate mechanical stress during thermal expansion and contraction, and the blind holes 302 between adjacent heat dissipation modules 301 can absorb part of the stress, so that the stress will not be directly transmitted to the chip-level package component 200, reducing the squeezing and pulling of the system chip 201 in the chip-level package component 200, so that the chip-level package component 200 is not easy to warp and crack.

[0134] In this embodiment, the blind hole 302 is connected to the stress buffer groove 202. When the packaging structure is working, the difference in thermal expansion coefficients between the chip-scale packaging component 200, the packaging substrate 100 and the heat sink will cause mechanical stress. Because the blind hole 302 is connected to the stress buffer groove 202, the blind hole 302 can absorb part of the stress, thereby reducing the possibility of cracking of the chip-scale packaging component 200.

[0135] In this embodiment, the blind hole 302 is located directly above the stress buffering groove 202. The blind hole 302 is located directly above the stress buffering groove 202, so that the heat dissipation cover 300 and the chip-scale package component 200 release stress at the same position, thereby reducing the stress between the chip-scale package component 200 and the heat dissipation cover 300.

[0136] In this embodiment, the width D2 of the blind hole 302 is greater than the width D1 of the stress buffering groove 202 and smaller than the interval between the system chips 201 . The blind hole 302 is located directly above the stress buffering groove 202 .

[0137] The width D2 of the blind hole 302 is greater than the width D1 of the stress buffer groove 202, and the corresponding contact area of ​​the plastic sealing layer 204 between the heat dissipation cover 300 and the system chip 201 is smaller, so that the extrusion force of the heat dissipation cover 300 on the plastic sealing layer 204 at the stress buffer groove 202 is smaller, making it difficult for the plastic sealing layer 204 to crack. At the same time, the width D2 of the blind hole 302 is smaller than the interval between adjacent system chips 201, so as to avoid the blind hole 302 being too wide, resulting in a reduction in the contact area between the heat dissipation cover 300 and the system chip 201, so that the system chip 201 and the heat dissipation cover 300 have a higher heat transfer efficiency.

[0138] In this embodiment, the heat dissipation module 301 includes: a stacked condensation chamber 3011, a heat transfer pipe 3012 and an evaporation chamber 3013, the heat transfer pipe 3012 is connected to the condensation chamber 3011 and the evaporation chamber 3013 at the same time, and the evaporation chamber 3013 in the heat dissipation cover 300 is arranged close to the chip-level packaging component 200, and the condensation chamber 3011 is far away from the chip-level packaging component 200.

[0139] The evaporation chamber 3013 is close to the chip-scale package component 200, so that the heat generated by the chip-scale package component 200 is directly transferred to the heat dissipation liquid in the evaporation chamber 3013, causing the liquid to evaporate quickly. Since the evaporation process absorbs a large amount of heat, the temperature of the system chip 201 is effectively controlled. Subsequently, the gas generated by evaporation rises to the condensation chamber 3011 far away from the chip-scale package component 200 through the heat transfer pipe 3012. In the condensation chamber 3011, the gas releases heat and condenses into liquid, and the released heat is further conducted to the outside of the heat dissipation cover 300. The condensed liquid returns to the evaporation chamber 3013, and the cycle is repeated to achieve the purpose of lowering the temperature of the chip-scale package component 200.

[0140] In this embodiment, in the step of providing the heat dissipation cover 300, the evaporation chamber 3013 is formed on the surface of the heat dissipation cover 300, that is, the evaporation chamber 3013 is exposed outside the heat dissipation cover 300. When the heat dissipation cover 300 is subsequently formed on the chip-level package component 200, the evaporation chamber 3013 can be in direct contact with the heat conductive layer 209, and can quickly absorb the heat of the evaporation chamber 3013. In other embodiments, in the step of providing the heat dissipation cover, the evaporation chamber can also be formed inside the heat dissipation cover, that is, the evaporation chamber is covered by the material of the heat dissipation cover, so that the evaporation chamber is not directly exposed to the surface of the heat dissipation cover, which is conducive to protecting the evaporation chamber.

[0141] In this embodiment, in the step of providing the heat dissipation cover 300, the condensation chamber 3011 is formed inside the heat dissipation cover 300, that is, the condensation chamber 3011 is covered by the material of the heat dissipation cover 300, so that the condensation chamber 3011 is not directly exposed to the surface of the heat dissipation cover 300, which is conducive to protecting the condensation chamber 3011. In other embodiments, in the step of providing the heat dissipation cover, the condensation chamber can also be formed on the surface of the heat dissipation cover, that is, the condensation chamber is exposed to the outside of the heat dissipation cover, which is conducive to the rapid condensation and heat dissipation of the steam in the condensation chamber.

[0142] It should be noted that there are multiple heat transfer pipes 3012 between the condensation chamber 3011 and the evaporation chamber 3013, which is conducive to rapid heat transfer between the evaporation chamber 3013 and the condensation chamber 3011.

[0143] It should also be noted that the evaporation chambers 3013 in the heat dissipation module 301 are interconnected, and the condensation chambers 3011 are interconnected.

[0144] In this embodiment, the length of the blind hole 302 in the extending direction is greater than or equal to the length of the stress buffering groove 202 in the extending direction.

[0145] The length of the blind hole 302 in the extension direction is greater than or equal to the length of the stress buffer groove 202 in the extension direction, that is, the blind hole 302 in the extension direction is long enough. After the temperature of the heat dissipation cover 300 rises, the blind hole 302 provides a large enough space for stress buffering, thereby reducing the stress caused by the heat dissipation cover 300 to the chip-level packaging component 200 and reducing the probability of warping and deformation of the chip-level packaging component 200.

[0146] In this embodiment, the heat dissipation cover 300 includes a central area and an edge area. The heat dissipation module 301 is located in the central area of ​​the heat dissipation cover 300. The edge area of ​​the heat dissipation cover 300 has a protruding fixing portion 303, and the fixing portion 303 is located on the adhesive layer 210 on the packaging substrate 100.

[0147] The adhesive layer 210 is used to fix the heat dissipation cover 300 and the packaging substrate 100 .

[0148] In this embodiment, the material of the adhesive layer 210 includes a silicone-based adhesive or a polyimide-based adhesive. The silicone-based adhesive or the polyimide-based adhesive has excellent mechanical properties and can meet high-temperature process requirements.

[0149] It should also be noted that the heat dissipation module 301 is located in the central area of ​​the heat dissipation cover 300 , and the corresponding blind hole 302 is located in the central area of ​​the heat dissipation cover 300 .

[0150] In this embodiment, the heat dissipation cover 300 surrounds the top and side walls of the chip-level packaging component 200 to protect the chip-level packaging component 200, and the heat dissipation module 301 is located above the chip-level packaging component 200 to dissipate heat for the system chip 201 in the chip-level packaging component 200.

[0151] In this embodiment, the heat dissipation cover 300 is made of a material with good thermal conductivity, for example, the material of the heat dissipation cover 300 includes copper.

[0152] It should be noted that the fixing portion 303 of the heat dissipation cover 300 is used to be mounted and fixed to the adhesive layer 210 on the packaging substrate 100 . The heat dissipation cover 300 also forms a cavity 212 with the side wall of the chip-level packaging component 200 . The passive device 213 is located in the cavity 212 .

[0153] The cavity 212 provides a closed protective space for the passive device 213, reducing the impact of the external environment on the passive device 213; in addition, the cavity 212 can also reduce stress concentration and buffer stress, which helps to improve the reliability and service life of the packaging structure.

[0154] In this embodiment, the cavity 212 surrounds the chip-scale packaging component 200, providing all-round protection for the entire chip-scale packaging component 200, and the surrounding design can make the stress more evenly distributed around the chip-scale packaging component 200, which helps to better relieve and disperse the stress.

[0155] In this embodiment, the packaging structure further includes: a heat conducting layer 209 located between the heat dissipation cover 300 and the system chip 201 , and the heat conducting layer 209 exposes the blind hole 302 and the stress buffer groove 202 .

[0156] When the packaging structure is working, the heat conducting layer 209 acts as a heat conducting medium to effectively conduct the heat generated by the system chip 201 to the heat dissipation cover 300, and then discharges the heat through the heat dissipation cover 300. The heat conducting layer 209 exposes the blind holes 302 and the stress buffer grooves 202, so that stress concentration is not easy between the heat dissipation modules 301 and between the system chips 201, reducing the thermal stress and mechanical stress on the chip-level packaging component 200, preventing the chip-level packaging component 200 from cracking and the packaging structure from warping, and improving the reliability of the product.

[0157] In this embodiment, the material of the heat conductive layer 209 includes thermal conductive adhesive. The thermal conductive adhesive, as a heat conduction medium, not only has excellent thermal conductivity, but also has good mechanical elasticity. It can alleviate the mechanical stress caused by the difference in thermal expansion coefficient and prevent the chip-level packaging component 200 from cracking, thereby improving the overall reliability and service life of the packaging structure.

[0158] It should be noted that the heat conducting layer 209 on each system chip 201 covers at least 90% of the area on the top of the corresponding system chip 201. If the area on the top of the corresponding system chip 201 covered by the heat conducting layer 209 is too small, the heat generated by the system chip 201 cannot be discharged in time, which reduces the performance of the system chip 201. In addition, if the temperature of the system chip 201 is too high, the stress inside the chip-level package component 200 will be relatively large, and the chip-level package component 200 will be prone to cracking or warping.

[0159] The packaging structure includes: a second conductive bump 103, which is located on the second surface 100B of the packaging substrate 100. The second conductive bump 103 is used to electrically connect the packaging substrate 100 and the chip-scale packaging component 200 thereon with the outside.

[0160] In this embodiment, the second conductive bump 103 includes a solder ball, and the material of the solder ball includes tin or a tin alloy.

[0161] The packaging structure can be formed by the forming method described in the above embodiment, or by other forming methods. For the specific description of the packaging structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0162] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: Package substrate; A chip-scale packaging component is located on the packaging substrate, the chip-scale packaging component includes a plurality of system chips, and the plurality of system chips are arranged at intervals in a plane on the packaging substrate; A stress buffer groove, located between adjacent system chips, for reducing the stress borne by the system chip; A heat dissipation cover is located on the chip-scale packaging component, and the heat dissipation cover is used to dissipate heat for the chip-scale packaging component.

2. The packaging structure according to claim 1, characterized in that: The heat dissipation cover comprises: A plurality of heat dissipation modules are arranged at intervals in a plane, and blind holes are provided between adjacent heat dissipation modules. The side of the heat dissipation cover having the blind holes is close to the chip-level packaging component, and the heat dissipation modules are arranged one by one directly above the system chip.

3. The packaging structure according to claim 2, characterized in that: The blind hole is communicated with the stress buffer groove.

4. The packaging structure according to claim 3, characterized in that: The blind hole is located directly above the stress buffer groove.

5. The packaging structure according to claim 2, characterized in that: The width of the blind hole is greater than the width of the stress buffer groove and smaller than the interval between adjacent system chips.

6. The packaging structure according to claim 2, characterized in that: The length of the blind hole in an extending direction is greater than or equal to the length of the stress buffer groove in an extending direction.

7. The packaging structure according to claim 2, characterized in that: The packaging structure further includes: The heat conducting layer is located between the heat dissipation cover and the system chip, and the blind hole and the stress buffer groove are exposed on the heat conducting layer.

8. The packaging structure according to claim 1, characterized in that: The stress buffering groove is located at a middle position between adjacent system chips, and the stress buffering groove is spaced apart from the system chip.

9. The packaging structure according to claim 1, characterized in that: The chip-scale packaging assembly further includes: an adapter plate; A plurality of the system chips distributed at intervals are located on the adapter board; A plastic sealing layer, located between adjacent system chips; The stress buffer groove is located on the top of the plastic packaging layer between adjacent system chips.

10. The packaging structure according to claim 1, wherein: The heat dissipation module includes: a stacked condensation chamber, a heat transfer pipe and an evaporation chamber, the heat transfer pipe is connected to the condensation chamber and the evaporation chamber at the same time, and the evaporation chamber in the heat dissipation cover is arranged close to the chip-level packaging component, and the condensation chamber is far away from the chip-level packaging component.

11. A packaging method, characterized in that: include: Providing a packaging substrate; A chip-scale packaging component is provided, wherein the chip-scale packaging component includes a plurality of system chips, and the plurality of system chips are arranged at intervals in a plane, and a stress buffer groove is provided between adjacent system chips, and the stress buffer groove is used to reduce the stress borne by the system chip; Mounting the chip-scale packaging component on the packaging substrate at a side facing away from the stress buffer groove; A heat dissipation cover is provided and formed on the chip-scale packaging component to dissipate heat for the chip-scale packaging component.

12. The packaging method according to claim 11, characterized in that: In the step of providing a heat dissipation cover, the heat dissipation cover comprises: a plurality of heat dissipation modules arranged at intervals in a plane, and blind holes are provided between adjacent heat dissipation modules; In the step of forming the heat dissipation cover on the chip-scale packaging component, the side of the heat dissipation cover having the blind hole is placed close to the chip-scale packaging component, and the heat dissipation modules are arranged one by one directly above the system chip.

13. The packaging method according to claim 12, characterized in that: In the step of forming the heat dissipation cover on the chip-scale packaging component, the blind hole is communicated with the stress buffer groove.

14. The packaging method according to claim 13, characterized in that: In the step of forming the heat dissipation cover on the chip-scale packaging component, the blind hole is located directly above the stress buffer groove.

15. The packaging method according to claim 12, characterized in that: The steps of providing a heat dissipation cover include: forming a first mask layer covering the heat dissipation modules, wherein the first mask layer has a first opening exposing the area between the heat dissipation modules; The heat dissipation cover exposed by the first opening is etched to form the blind hole.

16. The packaging method according to claim 12, characterized in that: In the step of forming the heat dissipation cover on the chip-scale packaging component, the width of the blind hole is greater than the width of the stress buffer groove and smaller than the interval between the system chips.

17. The packaging method according to claim 11, characterized in that: In the step of providing the chip-level packaging component, the stress buffer groove is located at a middle position between adjacent system chips, and the stress buffer groove is spaced apart from the system chip.

18. The packaging method according to claim 12, characterized in that: In the step of providing the heat dissipation cover, the length of the blind hole in an extending direction is greater than or equal to the length of the stress buffer groove in an extending direction.

19. The packaging method according to claim 11, characterized in that: The steps of providing the chip-scale packaging assembly include: Provide adapter plate; Forming a plurality of the system chips distributed at intervals on the adapter board; forming a plastic encapsulation layer between adjacent system chips; The plastic packaging layer between adjacent system chips is etched to form the stress buffer groove.

20. The packaging method according to claim 19, characterized in that: The plastic packaging layer between adjacent system chips is etched using a laser etching process to form the stress buffer groove.

21. The packaging method according to claim 19, characterized in that: The step of forming the stress buffer groove includes: forming a second mask layer on the chip-scale packaging component, wherein the second mask layer has a second opening; The plastic packaging layer exposed by the second opening is etched by a laser etching process to form the stress buffer groove.

22. The packaging method according to claim 12, characterized in that: After mounting the side of the chip-scale packaging component away from the stress buffer groove on the packaging substrate, a heat conducting layer is formed on the system chip; In the step of forming the heat dissipation cover on the chip-scale packaging component, a heat conduction layer is formed between the heat dissipation cover and the system chip, and the heat conduction layer exposes the blind hole and the stress buffer groove.

23. The packaging method according to claim 11, characterized in that: In the step of providing a heat dissipation cover, the heat dissipation module comprises: a stacked condensation chamber, a heat transfer pipe and an evaporation chamber, wherein the heat transfer pipe is connected to the condensation chamber and the evaporation chamber at the same time; In the step of forming the heat dissipation cover on the chip-scale package component, the evaporation chamber in the heat dissipation cover is arranged close to the chip-scale package component, and the condensation chamber is arranged far away from the chip-scale package component.

Images