Mask arranged in staggered direction for counteracting stress of IGBT (Insulated Gate Bipolar Translator) wafer

Abstract

The invention provides a staggered-direction-arranged mask plate for counteracting stress of IGBT (Insulated Gate Bipolar Translator) wafers, and relates to the field of semiconductor power devices. The mask plate comprises a plurality of IGBT chips; the IGBT chips are arranged in a staggered mode, one part of the IGBT chips are arranged in the 0-degree direction, and the other part of the IGBT chips are arranged after rotating by 90 degrees. The IGBT chips arranged in the 0-degree direction are diagonally distributed on a mask plate in a staggered arrangement mode; and the IGBT chips which are distributed at two sides in a 90-degree direction are filled and then are alternately arranged, so that mutual counteraction of stress in a local area is realized, and the warping of the wafer is reduced. Through the design of the masks arranged in the staggered direction, the warping problem of the IGBT wafer is reduced, the yield is remarkably improved, the production cost is reduced, the overall stability of the chip is enhanced, and an innovative solution is provided for efficient and stable production of the IGBT chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor power devices, and in particular to a mask plate arranged in staggered directions to offset the stress of an IGBT (insulated gate bipolar transistor) wafer. Background Art

[0002] The manufacturing process of IGBT (Insulate Gate Bipolar Transistor) chips involves forming strip trench gate structures on a silicon substrate. The depth of these strip trench gates can range from a few microns to tens of microns, depending on the specific design and application. In the prior art, IGBT chips are usually arranged on a wafer according to the same positioning surface, which means that all the strip trench gates extend in the same direction. This consistent directional arrangement will cause greater internal stress in the direction of the trench gate extension, thereby causing the wafer to warp.

[0003] When a wafer warps, it will cause a series of problems, such as lithography alignment deviation, pattern deformation, potential stress defects, chip failure and yield reduction. Especially for large-sized wafers (such as 12 inches), the warping problem is more serious and may even cause the wafer to break. Although the existing technology attempts to reduce warping by improving heat treatment and wet etching, these methods have limited effects and cannot completely solve the fundamental problem. Summary of the invention

[0004] In view of this, the purpose of the present invention is to propose a mask plate arranged in a staggered direction to offset the stress of the IGBT wafer, improve the IGBT wafer warping by optimizing the mask plate layout design, reduce wafer breakage and chip yield loss problems, and do not increase manufacturing costs.

[0005] To achieve the above object, the present invention provides the following technical solutions: Based on the above purpose, in a first aspect, the present invention provides a mask plate arranged in a staggered direction to offset the stress of an IGBT wafer, wherein the mask plate includes a plurality of IGBT chips; The IGBT chips are arranged in a staggered manner, with some IGBT chips arranged in a 0° direction and other IGBT chips arranged after being rotated 90°; The staggered arrangement is formed by distributing the IGBT chips arranged at 0° diagonally on the mask plate; filling the IGBT chips arranged at 90° on both sides and arranging them alternately to achieve mutual offset of stress in local areas, thereby reducing the warping of the wafer.

[0006] As a further solution of the present invention, the 0° arrangement refers to that the strip-shaped groove gate of the IGBT chip extends in the left-right direction, and the 90° arrangement refers to that the strip-shaped groove gate of the IGBT chip extends in the up-down direction.

[0007] As a further solution of the present invention, all the IGBT chips on the mask have the same specifications and are arranged alternately in different arrangement directions.

[0008] As a further solution of the present invention, the IGBT chip consists of a cell region and a terminal region. The terminal region surrounds the outside of the cell region, and a composite structure of a field plate and a field limiting ring is arranged on the surface of the terminal region. A strip-shaped groove gate is opened in the silicon substrate on the front side of the cell region, and an IGBT gate is also arranged on the IGBT chip. The position of the IGBT gate is set at the center of the IGBT chip to meet the design requirements of staggered arrangement of the chip direction.

[0009] As a further solution of the present invention, the mask is a square structure and 16 IGBT chips are arranged on the mask.

[0010] As a further solution of the present invention, the IGBT chips on the mask are arranged in the form of 4 rows and 4 columns, that is, arranged in a 4×4 manner.

[0011] As a further solution of the present invention, the IGBT chips in each row and each column on the mask plate include IGBT chips arranged in a 0° direction and in a 90° rotated direction, so as to achieve a staggered arrangement.

[0012] As a further solution of the present invention, on a mask having IGBT chips arranged in 4 rows and 4 columns, the IGBT chips arranged in a 90° direction are distributed in an L shape on both sides of the IGBT chips arranged in a diagonal 0° direction.

[0013] As a further solution of the present invention, the mask plate transfers the IGBT chip to a silicon substrate wafer through a photolithography machine, so that the IGBT chips arranged in the 0° direction and the 90° direction form a local area stress on the wafer to offset each other, thereby significantly improving the warping problem of the wafer.

[0014] As a further solution of the present invention, the IGBT chips transferred to the silicon substrate wafer by a photolithography machine are arranged in sequence, and between the IGBT chips of adjacent mask plates, an inclined extension line I of the IGBT chips in the 0° direction and an inclined extension line II of the IGBT chips in the 90° direction are formed, which are inclined 45° clockwise and arranged alternately in sequence.

[0015] Compared with the prior art, the present invention proposes a mask plate arranged in staggered directions to offset the stress of the IGBT wafer, which has the following beneficial effects: 1. Effectively reduces wafer warpage. The present invention arranges the strip-shaped trench gates of the IGBT chip in a staggered arrangement (i.e., alternately arranged in the 0° and 90° directions). This layout can effectively balance the stress generated on the wafer during the chip production process, avoiding the internal stress accumulation caused by the consistent direction of the trench gates in the traditional design, thereby significantly reducing the warpage of the wafer.

[0016] 2. Improved yield and reduced manufacturing costs. The present invention reduces wafer warping, avoids lithography alignment deviation, pattern deformation and potential stress defects caused by warping, reduces defective product rate, and significantly improves chip yield. In addition, since the integrity of the wafer is improved, chip damage or breakage is less likely to occur during the manufacturing process, further improving production efficiency and product qualification rate. The present invention optimizes the mask design (staggered IGBT chips) to make the processing process more stable, reducing processing difficulties and cost increases caused by warping. Therefore, the final production cost is reduced.

[0017] 3. Strong adaptability, and the chip layout is optimized. The present invention is not only suitable for large-sized wafers such as 12 inches through a staggered arrangement design, but can also be flexibly applied to silicon wafers of different sizes, and has strong adaptability. Even in the production of IGBT chips of different sizes and types, a good stress compensation effect can still be exerted. In the design of the present invention on the mask, the chip layouts arranged in the 0° and 90° directions are alternately distributed, and the chips arranged in the 90° direction are L-shaped and distributed on both sides of the chips arranged in the 0° direction along the diagonal distribution. This layout allows the stresses in the local areas where the chips are arranged on the wafer to offset each other, further optimizes the stress distribution during the production process, and avoids the risk of damage caused by concentrated stress.

[0018] 4. The overall stability of the wafer is improved, and the production operation is convenient. In the photolithography process, after using the mask of the present invention, the stress distribution on the wafer is more uniform, the overall stress concentration is reduced, and the stress of the wafer and the cracking or cracking problems that may occur during the heat treatment process are reduced, thereby ensuring the stability and safety of the wafer. Due to the staggered arrangement of the IGBT chips on the mask, the alignment error and pattern alignment difficulty caused by the warping of the wafer can be reduced, thereby simplifying the subsequent manufacturing operations, improving the automation of the production line, and reducing the possibility of manual intervention and errors.

[0019] In summary, the present invention reduces the warping problem of IGBT wafers through the design of mask plates arranged in staggered directions, significantly improves the yield, reduces production costs, and enhances the overall stability of the chip, providing an innovative solution for the efficient and stable production of IGBT chips.

[0020] These and other aspects of the present application will be more concise and understandable in the following description of the embodiments. It should be understood that the above general description and the following detailed description are only exemplary and explanatory and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the following briefly introduces the drawings required for use in the exemplary embodiments or related technical descriptions. The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In the drawings: Figure 1 The diagram is a schematic diagram of the arrangement of IGBT chips in a mask plate arranged in staggered directions to offset the stress of the IGBT wafer according to an embodiment of the present invention.

[0022] Figure 2 The schematic diagram of the top view of the structure of the IGBT chips in the mask plate arranged in staggered directions to offset the stress of the IGBT wafer according to an embodiment of the present invention.

[0023] Figure 3 The schematic diagram of the top view of the structure of an IGBT chip placed at 0° in a mask plate arranged in a staggered direction to offset the stress of the IGBT wafer according to an embodiment of the present invention.

[0024] Figure 4 The schematic diagram of the top view of the structure of an IGBT chip placed at 90° in a mask plate arranged in a staggered direction to offset the stress of the IGBT wafer according to an embodiment of the present invention.

[0025] Figure 5 The present invention is a schematic diagram of the arrangement and placement of IGBT chips on a wafer in a mask plate arranged in staggered directions to offset the stress of the IGBT wafer according to an embodiment of the present invention. Description of the drawings: 1-IGBT chip, 11-terminal region, 12-cell region, 13-strip trench gate, 14-IGBT gate, 2-mask, 3-wafer, 4-inclined extension line I, 5-inclined extension line II. DETAILED DESCRIPTION

[0027] Below, the present application is further described in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of no conflict, the various embodiments or technical features described below can be arbitrarily combined to form a new embodiment.

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0029] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product or device that includes a series of steps or units.

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0032] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0033] All the strip-shaped groove gates extend in the same direction. The consistent direction arrangement will cause a large internal stress in the groove gate extension direction, thereby causing the problem of wafer warping. The present invention proposes a mask plate that is arranged in a staggered direction to offset the stress of the IGBT wafer. The strip-shaped groove gates of the IGBT chip are arranged in a staggered manner. The mask plate layout design is optimized to improve the IGBT wafer warping, reduce the wafer breakage and chip yield loss problems, and do not increase the manufacturing cost.

[0034] See also Figure 1As shown, an embodiment of the present invention provides a mask plate for offsetting the stress of IGBT wafers by staggered arrangement. The mask plate 2 includes multiple IGBT chips 1; the IGBT chips 1 are staggered, with some IGBT chips 1 arranged in a 0° direction and other IGBT chips 1 rotated 90° and arranged. All the IGBT chips 1 on the mask plate 2 have the same specifications and are arranged alternately in different arrangement directions, see Figure 2 As shown, the IGBT chip 1 on the mask 2 is square, and the length and width of each IGBT chip 1 are the same. The IGBT chip 1 consists of a cell region 12 and a terminal region 11. The terminal region 11 surrounds the outside of the cell region 12, and a composite structure of a field plate and a field limiting ring is arranged on the surface of the terminal region 11; a strip-shaped trench gate 13 is opened in the silicon substrate on the front of the cell region 12, and an IGBT gate 14 is also arranged on the IGBT chip 1; the position of the IGBT gate 14 is set at the center of the IGBT chip 1 to meet the design requirements of staggered arrangement of the chip direction.

[0035] See also Figure 3 As shown, the 0° direction arrangement means that the strip-shaped trench gate 13 of the IGBT chip 1 extends in the left-right direction, see Figure 4 As shown, the 90° arrangement means that the strip-shaped trench gate 13 of the IGBT chip 1 extends in the up-down direction. Figure 3 and Figure 4 The arrow in shows that the stress direction of the cell region 12 is consistent with the extending direction of the strip trench gate 13 .

[0036] In this embodiment, see Figure 1 As shown, the staggered arrangement is achieved by diagonally distributing the IGBT chips 1 arranged at 0° on the mask plate 2; filling the IGBT chips 1 arranged at 90° on both sides and arranging them alternately to achieve mutual offset of stress in local areas, thereby reducing the warping of the wafer 3.

[0037] See also Figures 1 to 4 As shown, the mask plate 2 is a square structure and 16 IGBT chips 1 are arranged on the mask plate 2. The IGBT chips 1 on the mask plate 2 are arranged in the form of 4 rows and 4 columns, that is, in a 4×4 arrangement.

[0038] Among them, see Figure 1 As shown, the IGBT chips 1 in each row and column on the mask 2 include IGBT chips 1 arranged in the 0° direction and in the 90° direction, so as to achieve a staggered arrangement. On the mask 2 with 4 rows and 4 columns of IGBT chips 1 arranged, the IGBT chips 1 arranged in the 90° direction are L-shaped and arranged on both sides of the IGBT chips 1 arranged in the 0° direction along the diagonal distribution.

[0039] In this embodiment, see Figure 1 and Figure 5 As shown, the mask 2 transfers the IGBT chip 1 onto the wafer 3 of the silicon substrate through a photolithography machine, so that the IGBT chips 1 arranged in the 0° direction and the 90° direction form a local area stress on the wafer 3 to offset each other, thereby significantly improving the warping problem of the wafer 3.

[0040] The present invention arranges the strip-shaped trench gates 13 of the IGBT chip 1 in a staggered arrangement, that is, alternately arranged in the 0° and 90° directions. This layout can effectively balance the stress generated on the wafer 3 during the chip production process, avoids the internal stress accumulation caused by the consistent direction of the trench gates in the traditional design, and thus significantly reduces the warping of the wafer 3.

[0041] Among them, see Figure 5 As shown, the IGBT chips 1 transferred to the wafer 3 of the silicon substrate by the photolithography machine are arranged in sequence, and the IGBT chips 1 of adjacent mask plates 2 form an inclined extension line Ⅰ4 of the IGBT chip 1 in the 0° direction and an inclined extension line Ⅱ5 of the IGBT chip 1 in the 90° direction, which are inclined 45° clockwise and arranged alternately in sequence.

[0042] In the photolithography process, after using the mask 2 of the present invention, the stress distribution on the wafer 3 is more uniform, the overall stress concentration is reduced, and the stress of the wafer 3 and the cracking or cracking problems that may occur during the heat treatment process are reduced, thereby ensuring the stability and safety of the wafer 3. Due to the staggered arrangement design of the IGBT chips 1 on the mask 2, the alignment error and pattern alignment difficulty caused by the warping of the wafer 3 can be reduced, thereby simplifying the subsequent manufacturing operations, improving the automation level of the production line, and reducing the possibility of manual intervention and errors.

[0043] The present invention reduces the warping of the wafer 3, avoids the lithography alignment deviation, pattern deformation and potential stress defects caused by the warping, reduces the defective rate, and significantly improves the yield rate of the chip. In addition, since the integrity of the wafer 3 is improved, there are fewer chip damage or breakage problems during the manufacturing process, further improving production efficiency and product qualification rate. The present invention optimizes the mask plate 2 to design an interlaced arrangement of the IGBT chip 1, so that the processing process can be more stable, reducing the processing difficulties and cost increases caused by warping. Therefore, the final production cost is reduced.

[0044] The present invention is not only suitable for large-sized wafers 3 such as 12 inches, but can also be flexibly applied to silicon wafers 3 of different sizes through a staggered arrangement design, and has strong adaptability. Even in the production of IGBT chips 1 of different sizes and types, a good stress offset effect can still be exerted. In the design of the present invention on the mask plate 2, the chip layouts arranged in the 0° and 90° directions are alternately distributed, and the chips arranged in the 90° direction are L-shaped and distributed on both sides of the chips arranged in the 0° direction along the diagonal distribution. This layout allows the stresses in the local areas where the chips are arranged on the wafer 3 to offset each other, further optimizes the stress distribution during the production process, and avoids the risk of damage caused by concentrated stress.

[0045] In summary, the present invention reduces the warping problem of the IGBT wafer 3 by designing the mask plates 2 arranged in staggered directions, significantly improves the yield, reduces production costs, and enhances the overall stability of the chip, providing an innovative solution for the efficient and stable production of the IGBT chip 1.

[0046] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0047] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments.

[0048] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A mask plate arranged in staggered directions to offset the stress of IGBT wafers, characterized in that: The mask plate includes a plurality of IGBT chips; The IGBT chips are arranged in a staggered manner, with some IGBT chips arranged in a 0° direction and other IGBT chips arranged after being rotated 90°; The staggered arrangement is formed by distributing the IGBT chips arranged in the 0° direction diagonally on the mask plate; and filling the IGBT chips arranged in the 90° direction on both sides and arranging them alternately.

2. The mask plate arranged in staggered directions to offset the stress of the IGBT wafer as claimed in claim 1, characterized in that: The 0° arrangement means that the strip-shaped trench gates of the IGBT chip extend in the left-right direction, and the 90° arrangement means that the strip-shaped trench gates of the IGBT chip extend in the up-down direction.

3. The mask plate arranged in staggered directions to offset the stress of the IGBT wafer as claimed in claim 2, characterized in that: All the IGBT chips on the mask have the same specifications and are arranged alternately in different arrangement directions.

4. The mask plate arranged in staggered directions to offset the stress of the IGBT wafer as claimed in claim 3, characterized in that: The IGBT chip consists of a cell region and a terminal region. The terminal region surrounds the outside of the cell region, and a composite structure of a field plate and a field limiting ring is arranged on the surface of the terminal region. A strip-shaped groove gate is opened in the silicon substrate on the front side of the cell region, and an IGBT gate is also arranged on the IGBT chip. The position of the IGBT gate is arranged at the center of the IGBT chip.

5. The mask plate arranged in staggered directions to offset the stress of the IGBT wafer as claimed in claim 4, characterized in that: The mask has a square structure and 16 IGBT chips are arranged on the mask.

6. The mask plate arranged in staggered directions to offset the stress of the IGBT wafer as claimed in claim 5, characterized in that: The IGBT chips on the mask are arranged in the form of 4 rows and 4 columns.

7. The mask plate arranged in staggered directions to offset the stress of the IGBT wafer as claimed in claim 6, characterized in that: The IGBT chips in each row and each column on the mask plate include IGBT chips arranged in a 0° direction and in a 90° rotated direction, so as to achieve a staggered arrangement.

8. The mask plate arranged in staggered directions to offset the stress of the IGBT wafer as claimed in claim 7, characterized in that: The IGBT chips arranged in the 90° direction on the mask are distributed in an L shape on both sides of the IGBT chips arranged in the 0° direction along the diagonal distribution.

9. The mask plate arranged in staggered directions to offset the stress of IGBT wafer as claimed in claim 1, characterized in that: The mask plate transfers the IGBT chip to a wafer of a silicon substrate through a photolithography machine, and the IGBT chips arranged in the 0° direction and the IGBT chips arranged in the 90° direction form a mutual offset of stress in a local area on the wafer.

10. The mask plate arranged in staggered directions to offset the stress of the IGBT wafer as claimed in claim 9, characterized in that: The IGBT chips transferred to the silicon substrate wafer by the photolithography machine are arranged in sequence, and the IGBT chips on adjacent mask plates form an inclined extension line I of the 0° direction IGBT chip and an inclined extension line II of the 90° direction IGBT chip, which are inclined 45° clockwise and arranged alternately in sequence.

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