Packaging structure and manufacturing method thereof

Abstract

The present disclosure provides a packaging structure and a manufacturing method thereof, wherein the packaging structure includes: a substrate; an interposer located on the substrate; the interposer including a first surface and a second surface opposite to each other; the second surface facing the substrate; at least one chip located on the first surface; a first heat dissipation structure located in the interposer and exposed from the second surface; and a first heat-conducting structure located in the interposer and connecting the chip and the first heat dissipation structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a packaging structure and a manufacturing method thereof. Background Art

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid growth. Semiconductor packaging devices typically undergo two processing steps: chip manufacturing and chip packaging. Therefore, the chip's inherent characteristics and the quality of the packaging structure directly determine the ultimate performance of the semiconductor packaging device product. As Moore's Law slows and transistor miniaturization approaches physical limits, advanced packaging, which integrates multiple chips onto a single large chip through wafer manufacturing processes, has become a key development direction for improving chip computing power and performance. Among these, 2.5D advanced packaging technology, which uses an interposer to integrate different chips, has seen particularly strong development and has been widely applied in high-performance computing chips, graphics chips, and other fields.

[0003] However, while 2.5D advanced packaging achieves a high degree of integration and good functional scalability, it also brings the problem of poor heat dissipation. Due to the close interconnection and stacking between the small chips, the heat inside the integrated chip cannot be dissipated efficiently and quickly, resulting in a decrease in the overall computing performance of the chip, and even causing the chip to be damaged due to overheating. Therefore, the heat dissipation performance of the existing 2.5D advanced packaging still needs to be strengthened. Summary of the Invention

[0004] The present disclosure provides a packaging structure and a manufacturing method thereof.

[0005] In a first aspect, the present disclosure provides a packaging structure, including: a substrate;

[0006] an interposer located on the substrate; the interposer comprising a first surface and a second surface opposite to each other; the second surface facing the substrate;

[0007] at least one chip located on the first surface;

[0008] a first heat dissipation structure located in the interposer and exposed from the second surface;

[0009] A first heat-conducting structure is located in the intermediary layer and connects the chip and the first heat dissipation structure.

[0010] In some embodiments, the interposer includes a central region and a peripheral region surrounding the central region; and the package structure further includes:

[0011] an interconnect structure located in the interposer and in the central region; the interconnect structure is used to transmit signals between the plurality of chips, and / or the interconnect structure is used to transmit signals between the chip and the substrate;

[0012] The first heat dissipation structure is located in the peripheral area.

[0013] In some embodiments, the first heat dissipation structure surrounds the central area.

[0014] In some embodiments, the packaging structure further includes:

[0015] a second heat dissipation structure, located on the first surface and in the peripheral area;

[0016] The second heat-conducting structure is located in the intermediate layer and connects the first heat dissipation structure and the second heat dissipation structure.

[0017] In some embodiments, the second heat dissipation structure surrounds the central area.

[0018] In some embodiments, the chip includes a circuit structure and a third heat-conducting structure located at an edge of the circuit structure; the third heat-conducting structure is connected to the first heat-conducting structure.

[0019] In a second aspect, the present disclosure provides a method for manufacturing a package structure, the method comprising:

[0020] Providing an interposer; the interposer comprising a first surface and a second surface opposite to each other;

[0021] A first heat dissipation structure and a first heat conductive structure are formed in the interposer; wherein the first heat dissipation structure is exposed from the second surface, and the first heat conductive structure is connected to the first heat dissipation structure and is exposed from the first surface;

[0022] fixing at least one chip on the first surface; the chip is connected to the first heat conducting structure;

[0023] A substrate is provided, and the intermediary layer is fixed on the substrate; the second surface faces the substrate.

[0024] In some embodiments, the interposer includes a central region and a peripheral region surrounding the central region; and the manufacturing method further includes:

[0025] forming an interconnect structure in the interposer within the central region; the interconnect structure being used to transmit signals between the plurality of chips, and / or the interconnect structure being used to transmit signals between the chip and the substrate;

[0026] The forming of a first heat dissipation structure in the interposer includes:

[0027] The first heat dissipation structure is formed in the interposer in the peripheral area; the first heat dissipation structure surrounds the central area.

[0028] In some embodiments, the manufacturing method further comprises:

[0029] forming a second heat dissipation structure on the first surface in the peripheral area; the second heat dissipation structure surrounds the central area;

[0030] A second heat-conducting structure is formed in the intermediary layer; the second heat-conducting structure connects the first heat dissipation structure and the second heat dissipation structure.

[0031] In some embodiments, the manufacturing method further comprises:

[0032] forming a third heat conducting structure at an edge of the circuit structure of the chip;

[0033] The step of fixing at least one chip on the first surface further comprises:

[0034] At least one chip is fixed on the first surface, and the third heat-conducting structure is connected to the first heat-conducting structure.

[0035] In the disclosed embodiment, the chip is located on the first surface of the interposer, the first heat dissipation structure is connected to the chip via the first thermally conductive structure, and the first heat dissipation structure is exposed from the second surface. This facilitates heat dissipation from the chip, thereby improving the reliability of the package. Furthermore, since both the first thermally conductive structure and the first heat dissipation structure are located within the interposer, the package is compact, which improves its integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of a packaging structure provided by the present disclosure;

[0037] Figure 2 A schematic diagram of another packaging structure provided by the present disclosure;

[0038] Figure 3a and Figure 3b A schematic diagram of a first heat dissipation structure in another packaging structure provided by the present disclosure;

[0039] Figure 4a and Figure 4b A schematic diagram of a second heat dissipation structure in another packaging structure provided by the present disclosure;

[0040] Figure 5 A flowchart of a method for manufacturing a packaging structure provided by the present disclosure;

[0041] Figures 6a to 6f A schematic diagram of a process for forming a packaging structure provided by the present disclosure. DETAILED DESCRIPTION

[0042] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0043] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0044] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0045] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions of the present disclosure. Preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementations. It should be understood that in order to clearly illustrate each structure in the drawings, the dimensional ratios of each structure may not conform to the actual structure.

[0047] With the development of integrated circuit technology, the arrangement of electronic devices on integrated circuit boards (such as packaging substrates) has become increasingly dense, and more and more chips are used on integrated circuit boards. Some existing integrated circuit boards are provided with stacked chips, that is, multiple chips are arranged in a stacked arrangement in a direction perpendicular to the packaging substrate. At present, most chips are connected to the packaging substrate through bumps after 2.5D and 3D packaging. On the one hand, the chip realizes signal transmission with the packaging substrate through the bumps. On the other hand, the heat generated by the chip is also conducted through the bumps and then dissipated to the environment through the packaging substrate, realizing the heat dissipation of the chip.

[0048] However, because the bumps on the chip are very small, the heat generated by the bumps and the chip relies solely on the bumps to conduct heat to the package substrate, resulting in inefficient heat dissipation. Heat generated by the chip often cannot be dissipated in a timely manner. For chips that generate a lot of heat, such as those that require high-frequency switching or power chips, simply dissipating heat to the package substrate through the bumps is insufficient to meet the chip's heat dissipation needs. If the heat generated by the chip cannot be dissipated in a timely manner, it may cause damage to the chip and shorten the service life of the electronic device.

[0049] like Figure 1The present disclosure shows a package structure 100, comprising: a substrate 110; an interposer 120 located on the substrate 110; and at least one chip 130 located on the interposer 120. The chips 130 include, but are not limited to, logic chips, memory chips, sensor chips, and system-on-chip (SoC) chips. For example, the interposer 120 may have a logic chip and a high-bandwidth memory (HBM) chip arranged in parallel. The chips 130 may be connected to the interposer 120 via bumps, microbumps, hybrid bonding, or the like, and the interposer 120 may have an interconnect structure 121, such as a metal wiring layer or through-silicon vias (TSVs), to enable signal transmission between the multiple chips 130 and between the chips 130 and the substrate 110. However, since the package structure 100 integrates multiple chips 130, if the chips 130 generate a large amount of heat, the heat generated cannot be effectively dissipated, thereby affecting the reliability of the package structure 100.

[0050] like Figure 2 As shown, the present disclosure provides a packaging structure 200, including: a substrate 210; an interposer 220, located on the substrate 210; the interposer 220 includes a first surface 220a and a second surface 220b opposite to each other; the second surface 220b faces the substrate 210; at least one chip 230, located on the first surface 220a; a first heat dissipation structure 241, located in the interposer 220 and exposed from the second surface 220b; a first heat conducting structure 251, located in the interposer 220 and connecting the chip 230 and the first heat dissipation structure 241.

[0051] In the disclosed embodiment, substrate 210 may be a packaging substrate. Substrate 210 includes, but is not limited to, organic substrates, ceramic substrates, and silicon substrates. Substrate 210 provides electrical connection, protection, support, heat dissipation, and integration for the chip, thereby achieving multiple pins, reducing the size of the packaged product, improving electrical performance and heat dissipation, and multi-chip modularization. For example, substrate 210 may be a printed circuit board (PCB).

[0052] The interposer 220 is located above the substrate 210 and can be connected to the substrate 210 through bumps. The interposer 220 can be a single-layer structure or a multi-layer structure. The interposer 220 can carry multiple chips and is used to achieve communication between multiple chips, or communication between the chips and the outside world. The interposer 220 includes any suitable dielectric material, which can be a non-organic dielectric material, such as silicon, silicon oxide or silicon nitride, or an organic dielectric material, such as an organic polymer, including polyimide (PI), benzocyclobutene (BCB) or polybenzobisoxazole (PBO). Exemplarily, the interposer 220 is a silicon interposer. The interposer 220 includes a first surface 220a and a second surface 220b relative to each other, wherein the second surface 220b faces the substrate 210. It is understandable that, since the interposer 220 is connected to the substrate 210 through bumps or the like, there is a gap between the second surface 220 b of the interposer 220 and the upper surface of the substrate 210 .

[0053] At least one chip 230 is disposed on the interposer 220. Chips 230 include, but are not limited to, logic chips, memory chips, sensor chips, and system-on-chip chips. A first heat dissipation structure 241 and a first thermally conductive structure 251 are disposed within the interposer 230. The materials of the first heat dissipation structure 241 and the first thermally conductive structure 251 can be copper, gold, cobalt, graphene, or any other material with excellent thermal conductivity. For example, the first heat dissipation structure 241 can be a heat sink, and the first thermally conductive structure 251 can be a metal wire, TSV, or the like.

[0054] The first heat dissipation structure 241 is located within the interposer 220 and is exposed from the second surface 220b. The first heat dissipation structure 241 is connected to the chip 230 via the first thermally conductive structure 251. As such, heat generated by the chip 230 can be transferred to the first heat dissipation structure 241 via the first thermally conductive structure 251, and then dissipated to the external environment through the first heat dissipation structure 241, thereby meeting the heat dissipation requirements of the chip 230. Furthermore, the first heat dissipation structure 241 can dissipate heat from the second surface 220b of the interposer 220, thereby reducing the impact of heat dissipated by the first heat dissipation structure 241 on the chip 230 located on the first surface 220a, further improving the reliability of the package structure 200.

[0055] It can be understood that, on the one hand, the heat dissipation path jointly formed by the first thermal conductive structure 251 and the first heat dissipation structure 241 is beneficial to the heat dissipation of the chip 230, so as to improve the reliability of the packaging structure 200; on the other hand, the first thermal conductive structure 251 and the first heat dissipation structure 241 are both located in the intermediate layer 220, and the volume of the packaging structure 200 is relatively small, which is beneficial to improving the integration of the packaging structure 200.

[0056] In some embodiments, the first heat dissipation structure 241 may be disposed on the second surface 220 b of the interposer 220 .

[0057] In some embodiments, as Figure 3a and Figure 3b As shown, the interposer 220 includes a central area A1 and a peripheral area A2 surrounding the central area A1; the package structure 200 further includes: an interconnection structure 221 located in the interposer 220 and within the central area A1; the interconnection structure 221 is used to transmit signals between the plurality of chips 230, and / or, the interconnection structure 221 is used to transmit signals between the chips 230 and the substrate 210; the first heat dissipation structure 241 is located within the peripheral area A2. Figure 3a is a front view of the packaging structure 200, Figure 3b Then Figure 3a Schematic diagram of the A-A' section.

[0058] In the disclosed embodiment, the peripheral region A2 of the interposer 220 surrounds the central region A1. The interposer 220 also includes an interconnect structure 221, which includes but is not limited to metal wiring layers and through-silicon vias (TSVs). This facilitates signal transmission between the multiple chips 230 and between the chips 230 and the substrate 210. The interconnect structure 221 is located within the central region A1, while the first heat dissipation structure 241 is located within the peripheral region A2. This ensures that the first heat dissipation structure 241 and the interconnect structure 221 do not interfere with each other, effectively utilizing the internal space of the interposer 220.

[0059] In some embodiments, the interposer 220 may be provided with multiple first heat dissipation structures 241, distributed within the peripheral area A2. In other embodiments, the interposer 220 may be provided with only one first heat dissipation structure 241. When viewed from above, the first heat dissipation structure 241 may be in any shape, such as a strip, L-shape, or ring, to suit the peripheral area A2.

[0060] In some embodiments, the first heat dissipation structure 241 surrounds the central area A1.

[0061] In the embodiments of the present disclosure, reference Figure 3b The first heat dissipation structure 241 may be annular and surround the central area A1. In this way, the area of ​​the first heat dissipation structure 241 is large, further improving the heat dissipation performance of the package structure 200.

[0062] In some embodiments, as Figure 4a and Figure 4bAs shown, the package structure 200 further includes: a second heat dissipation structure 242 located on the first surface 220a and within the peripheral area A2; a second heat conducting structure 252 located in the interposer 220 and connecting the first heat dissipation structure 241 and the second heat dissipation structure 242. Figure 4a is a front view of the packaging structure 200, Figure 4b Then Figure 4a Schematic diagram of the BB' section.

[0063] In the disclosed embodiment, the package structure 200 further includes a second heat dissipation structure 242 and a second thermally conductive structure 252. The second heat dissipation structure 242 and the second thermally conductive structure 252 can be made of copper, gold, cobalt, graphene, or any other material with excellent thermal conductivity. For example, the second heat dissipation structure 242 can be a heat sink, and the second thermally conductive structure 252 can be a metal wire, TSV, or the like. Furthermore, the second heat dissipation structure 242 can also be a fluid heat dissipation structure, such as a liquid cooling device.

[0064] The second heat dissipation structure 242 is disposed on the first surface 220a and is located within the peripheral area A2. The second heat dissipation structure 242 does not contact the chip 230. The first heat dissipation structure 241 is connected to the second heat dissipation structure 242 via the second heat conductive structure 252. In this way, heat generated by the chip 230 can be transferred to the first heat dissipation structure 241 via the first heat conductive structure 251. The first heat dissipation structure 241 can dissipate a portion of the heat into the external environment, while another portion of the heat continues to be transferred to the second heat dissipation structure 242 via the second heat conductive structure 252. The second heat dissipation structure 242 dissipates the remaining heat into the external environment, thereby further improving the heat dissipation performance of the package structure 200.

[0065] It can be understood that since the heat in the chip 230 is first transferred to the first heat dissipation structure 241 and then transferred to the second heat dissipation structure 242 located on the first surface 220a, the heat dissipated by the second heat dissipation structure 242 is less than the heat dissipated by the first heat dissipation structure 241, and the heat dissipated by the second heat dissipation structure 242 has less impact on the chip 230.

[0066] In some embodiments, the second heat dissipation structure 242 may also be disposed in the interposer 220 and exposed from the first surface 220 a .

[0067] In some embodiments, the second heat dissipation structure 242 surrounds the central area A1.

[0068] In the embodiments of the present disclosure, reference Figure 4bThe second heat dissipation structure 242 may be annular and surround the central area A1. In this way, the area of ​​the second heat dissipation structure 242 is larger, further improving the heat dissipation performance of the package structure 200.

[0069] In some embodiments, the second heat dissipation structure 242 may also be located in the spacing region S between the plurality of chips 230 , and the spacing region S at least partially overlaps with the central region A1 .

[0070] It should be noted that the positions of the multiple chips 230 shown in the drawings of this disclosure are only used as examples to facilitate understanding. The number and position of the chips 230 in actual products can be adjusted according to actual needs, and this disclosure does not impose too many restrictions.

[0071] In some embodiments, as Figure 4a and Figure 4b As shown, the chip 230 includes a circuit structure 231 and a third heat-conducting structure 253 located at the edge of the circuit structure 231 ; the third heat-conducting structure 253 is connected to the first heat-conducting structure 251 .

[0072] In the disclosed embodiment, a third heat-conducting structure 253 that does not touch the circuit structure 231 can also be formed at the edge of the chip 230 to assist in transferring heat from the chip 230 to the first heat-conducting structure 251 and the first heat dissipation structure 241. The circuit structure 231 includes, but is not limited to, active devices, passive devices, and metal layers in the chip 230. The third heat-conducting structure 253 can be a metal wire, TSV, or the like. The chip 230 can be secured to the interposer 220 via hybrid bonding or micro-bump connections, while simultaneously connecting the third heat-conducting structure 253 to the first heat-conducting structure 251.

[0073] It can be understood that in the packaging structure 200 provided by the present disclosure, the heat dissipation path jointly formed by the first heat-conducting structure 251, the first heat dissipation structure 241, the second heat-conducting structure 252, the second heat dissipation structure 242, and the third heat-conducting structure 253 can enable the heat of the chip 230 to dissipate from the first surface 220a and the second surface 220b of the interposer 220 to the external environment, thereby improving the reliability of the packaging structure 200.

[0074] like Figure 5 As shown, the present disclosure provides a method for manufacturing a packaging structure, the manufacturing method comprising the following steps:

[0075] Step S10: providing an interposer; the interposer comprises a first surface and a second surface opposite to each other;

[0076] Step S20, forming a first heat dissipation structure and a first heat conductive structure in the interposer; wherein the first heat dissipation structure is exposed from the second surface, and the first heat conductive structure is connected to the first heat dissipation structure and is exposed from the first surface;

[0077] Step S30: fixing at least one chip on the first surface; the chip is connected to the first heat-conducting structure;

[0078] Step S40: providing a substrate, and fixing the interposer on the substrate; the second surface faces the substrate.

[0079] It should be understood that Figure 5 The steps shown in the embodiment are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown. For example, the execution order of step S30 and step S40 may be interchanged. Figures 6a to 6f The manufacturing process of the packaging structure shown is described in detail with the corresponding process diagram.

[0080] like Figure 6a As shown, an interposer 220 is provided, which can be a single-layer structure or a multi-layer structure. The interposer 220 can carry multiple chips and is used to realize communication between multiple chips, or communication between the chips and the outside world. The interposer 220 includes any suitable dielectric material, which can be a non-organic dielectric material, such as silicon, silicon oxide or silicon nitride, or an organic dielectric material, such as an organic polymer, including polyimide, benzocyclobutene or polybenzobisoxazole. Exemplarily, the interposer 220 is a silicon interposer. The interposer 220 includes a first surface 220a and a second surface 220b opposite to each other.

[0081] like Figure 6b As shown, a first heat dissipation structure 241 and a first thermally conductive structure 251 can be formed in the interposer 220 using processes such as deposition, photolithography, etching, and damascene. The first heat dissipation structure 241 is exposed from the second surface 220b, and the first thermally conductive structure 251 is connected to the first heat dissipation structure 241 and is exposed from the first surface 220a. For example, the material of the first heat dissipation structure 241 and the first thermally conductive structure 251 can be copper, and copper is patterned in the interposer 220 using a damascene process to form the first heat dissipation structure 241 and the first thermally conductive structure 251. In other embodiments, the first heat dissipation structure 241 can be a prefabricated heat sink that is pre-embedded in the interposer 220.

[0082] In some embodiments, the interconnection structure 221 and the second heat conducting structure 252 can be formed in the interposer 220 using the same process as that used to form the first heat dissipation structure 241 and the first heat conducting structure 251 (see FIG. Figure 4a and Figure 4b The interconnect structure 221 is used to transmit signals between multiple chips and / or between a chip and a substrate. The second thermally conductive structure 252 is used to connect to a second heat dissipation structure subsequently formed on the first surface 220a. The interconnect structure 221 can be formed in the central region A1 of the interposer 220, while the first thermally conductive structure 251 and the second thermally conductive structure 252 are formed in the peripheral region A2 of the interposer 220, with the peripheral region A2 surrounding the central region A1.

[0083] In some embodiments, the first heat conducting structure 251 and / or the second heat conducting structure 252 may be ring-shaped, and the first heat conducting structure 251 and / or the second heat conducting structure 252 surrounds the central area A1 .

[0084] like Figure 6c As shown, a second heat dissipation structure 242 can be formed on the first surface 220a within the peripheral area A2. The second heat dissipation structure 242 is connected to the first heat dissipation structure 241 via a second thermally conductive structure 252. The second heat dissipation structure 242 can be made of copper, gold, cobalt, graphene, or any other material with excellent thermal conductivity. For example, the second heat dissipation structure 242 can be a heat sink or a fluid heat dissipation structure, such as a liquid cooling device.

[0085] like Figure 6d As shown, a third heat-conducting structure 253 is formed at the edge of the circuit structure 231 of the chip 230. The third heat-conducting structure 253 does not touch the circuit structure 231. Here, the circuit structure 231 includes, but is not limited to, active devices, passive devices, metal layers, etc. in the chip 230. The third heat-conducting structure 253 can be a metal line, TSV, etc., and can be formed through deposition, photolithography, etching, damascene, etc. processes. For example, the third heat-conducting structure 253 can be formed together with the circuit structure 231 in the chip 230.

[0086] like Figure 6e As shown, the chip 230 is fixed on the interposer 220 by hybrid bonding, micro-bump connection, etc., and the third heat conducting structure 253 and the first heat conducting structure 251 are connected at the same time.

[0087] like Figure 6f As shown, the interposer 220 is fixed on the substrate 210 by bump connection (solder balls) or the like, and the second surface 220 b of the interposer 220 faces the substrate 210 .

[0088] It should be noted that Figures 6a to 6fThe process of first securing the chip 230 to the first surface 220a of the interposer 220 and then securing the interposer 220 with the chip 230 to the substrate 210 is shown for exemplary purposes only. In actual manufacturing of the package structure, the interposer 220 may also be secured to the substrate 210 first and then the chip 230 may be secured to the first surface 220a of the interposer 220, and this disclosure does not impose any particular limitations thereon.

[0089] In some embodiments, the interposer includes a central area and a peripheral area surrounding the central area; the manufacturing method further includes: forming an interconnection structure in the interposer within the central area; the interconnection structure is used to transmit signals between multiple chips, and / or, the interconnection structure is used to transmit signals between the chip and the substrate; forming a first heat dissipation structure in the interposer includes: forming the first heat dissipation structure in the interposer within the peripheral area; the first heat dissipation structure surrounds the central area.

[0090] In some embodiments, the manufacturing method further includes: forming a second heat dissipation structure on the first surface within the peripheral area; the second heat dissipation structure surrounds the central area; forming a second heat conductive structure in the intermediate layer; and the second heat conductive structure connects the first heat dissipation structure and the second heat dissipation structure.

[0091] In some embodiments, the manufacturing method further includes: forming a third heat-conducting structure at the edge of the circuit structure of the chip; fixing at least one chip on the first surface further includes: fixing at least one chip on the first surface and connecting the third heat-conducting structure with the first heat-conducting structure.

[0092] The present disclosure also provides an electronic device, comprising the packaging structure according to any one of the above embodiments.

[0093] The packaging structures disclosed herein can be used in various electronic devices, including but not limited to mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, and any other suitable electronic devices.

[0094] The packaging structure and manufacturing method provided by the present disclosure can effectively improve the heat dissipation efficiency of chips in 2.5D and 3D packaging, reduce chip heat accumulation, improve chip performance, and extend chip life.

[0095] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0096] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made based on the contents of the present disclosure and the drawings, or direct / indirect applications in other related technical fields, are included in the patent protection scope of the present disclosure.

Claims

1. A packaging structure, characterized in that: include: substrate; an interposer located on the substrate; the interposer comprising a first surface and a second surface opposite to each other; the second surface facing the substrate; the interposer comprising a central region and a peripheral region surrounding the central region; At least one chip is located on the first surface; the chip includes a circuit structure and a third heat-conducting structure located at an edge of the circuit structure; the third heat-conducting structure extends in a direction perpendicular to the first surface; a first heat dissipation structure, located in the interposer and exposed from the second surface; the first heat dissipation structure is located in the peripheral area, and the first heat dissipation structure surrounds the central area; A first heat-conducting structure is located in the intermediary layer and connects the chip and the first heat dissipation structure.

2. The packaging structure according to claim 1, wherein: The packaging structure further includes: An interconnection structure is located in the interposer and in the central area; the interconnection structure is used to transmit signals between the plurality of chips, and / or the interconnection structure is used to transmit signals between the chip and the substrate.

3. The packaging structure according to claim 2, wherein: The packaging structure further includes: a second heat dissipation structure, located on the first surface and in the peripheral area; The second heat-conducting structure is located in the intermediate layer and connects the first heat dissipation structure and the second heat dissipation structure.

4. The packaging structure according to claim 3, wherein: The second heat dissipation structure surrounds the central area.

5. The packaging structure according to claim 1, wherein: The third heat-conducting structure is connected to the first heat-conducting structure.

6. A method for manufacturing a packaging structure, characterized in that: The manufacturing method comprises: Providing an interposer; the interposer comprising a first surface and a second surface opposite to each other; the interposer comprising a central region and a peripheral region surrounding the central region; A first heat dissipation structure and a first heat conductive structure are formed in the interposer; wherein the first heat dissipation structure is exposed from the second surface, and the first heat conductive structure is connected to the first heat dissipation structure and is exposed from the first surface; the first heat dissipation structure is located in the peripheral area, and the first heat dissipation structure surrounds the central area; At least one chip is fixed on the first surface; the chip is connected to the first heat-conducting structure; the chip includes a circuit structure and a third heat-conducting structure located at an edge of the circuit structure; the third heat-conducting structure extends in a direction perpendicular to the first surface; A substrate is provided, and the intermediary layer is fixed on the substrate; the second surface faces the substrate.

7. The manufacturing method according to claim 6, characterized in that The manufacturing method further comprises: An interconnection structure is formed in the interposer in the central area; the interconnection structure is used to transmit signals between the plurality of chips, and / or the interconnection structure is used to transmit signals between the chip and the substrate.

8. The manufacturing method according to claim 7, characterized in that The manufacturing method further comprises: forming a second heat dissipation structure on the first surface in the peripheral area; the second heat dissipation structure surrounds the central area; A second heat-conducting structure is formed in the intermediary layer; the second heat-conducting structure connects the first heat dissipation structure and the second heat dissipation structure.

9. The manufacturing method according to claim 6, characterized in that The step of fixing at least one chip on the first surface further comprises: At least one chip is fixed on the first surface, and the third heat-conducting structure is connected to the first heat-conducting structure.

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